3,5c3,5
< sim_seconds 0.206025 # Number of seconds simulated
< sim_ticks 206024606500 # Number of ticks simulated
< final_tick 206024606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.206007 # Number of seconds simulated
> sim_ticks 206006891000 # Number of ticks simulated
> final_tick 206006891000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,77c7,77
< host_inst_rate 152686 # Simulator instruction rate (inst/s)
< host_op_rate 172002 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 61807337 # Simulator tick rate (ticks/s)
< host_mem_usage 303988 # Number of bytes of host memory used
< host_seconds 3333.34 # Real time elapsed on the host
< sim_insts 508955238 # Number of instructions simulated
< sim_ops 573341798 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9266560 # Number of bytes read from this memory
< system.physmem.bytes_read::total 9483840 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6249216 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6249216 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 144790 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 148185 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 97644 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 97644 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1054631 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 44977928 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 46032560 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1054631 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1054631 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 30332377 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 30332377 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 30332377 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1054631 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 44977928 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 76364937 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 148186 # Total number of read requests seen
< system.physmem.writeReqs 97644 # Total number of write requests seen
< system.physmem.cpureqs 245841 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 9483840 # Total number of bytes read from memory
< system.physmem.bytesWritten 6249216 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 9483840 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 6249216 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 83 # Number of read reqs serviced by write Q
< system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 9219 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 9199 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 9344 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 8811 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 9228 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 8973 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 9239 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 9440 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 9127 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 10272 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 9693 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 9714 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 9129 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 8954 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 8756 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 5972 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 6125 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 5945 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 6129 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 5951 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 6023 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 6373 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 5964 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 6647 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 6322 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 6045 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 6065 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 5899 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 5778 # Track writes on a per bank basis
---
> host_inst_rate 48397 # Simulator instruction rate (inst/s)
> host_op_rate 54519 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 19589283 # Simulator tick rate (ticks/s)
> host_mem_usage 261836 # Number of bytes of host memory used
> host_seconds 10516.31 # Real time elapsed on the host
> sim_insts 508955198 # Number of instructions simulated
> sim_ops 573341758 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu.inst 216256 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9272640 # Number of bytes read from this memory
> system.physmem.bytes_read::total 9488896 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 216256 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 216256 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6250240 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6250240 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3379 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 144885 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 148264 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 97660 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 97660 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1049751 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 45011310 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 46061061 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1049751 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1049751 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 30339956 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 30339956 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 30339956 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1049751 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 45011310 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 76401017 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 148265 # Total number of read requests seen
> system.physmem.writeReqs 97660 # Total number of write requests seen
> system.physmem.cpureqs 245934 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 9488896 # Total number of bytes read from memory
> system.physmem.bytesWritten 6250240 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 9488896 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 6250240 # bytesWritten derated as per pkt->getSize()
> system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q
> system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 9228 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 9341 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 8794 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 9227 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 8981 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 9254 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 9466 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 9155 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 10302 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 9694 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 9707 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 9134 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 8959 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 9019 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 8746 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 5978 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 6111 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::2 6105 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::3 5940 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 6130 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 5961 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 6031 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 6368 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 6669 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 6289 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 6316 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 6051 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 6056 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 5913 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 5774 # Track writes on a per bank basis
80c80
< system.physmem.totGap 206024585500 # Total gap between requests
---
> system.physmem.totGap 206006873500 # Total gap between requests
87c87
< system.physmem.readPktSize::6 148186 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 148265 # Categorize read packet sizes
96c96
< system.physmem.writePktSize::6 97644 # categorize write packet sizes
---
> system.physmem.writePktSize::6 97660 # categorize write packet sizes
105c105
< system.physmem.neitherpktsize::6 11 # categorize neither packet sizes
---
> system.physmem.neitherpktsize::6 9 # categorize neither packet sizes
108,113c108,113
< system.physmem.rdQLenPdf::0 138148 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 9303 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 576 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 138270 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 9286 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
141,142c141,142
< system.physmem.wrQLenPdf::0 4240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 4246 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 4241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 4247 # What write queue length does an incoming req see
150,163c150,163
< system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see
174,179c174,179
< system.physmem.totQLat 1634901672 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 4710633672 # Sum of mem lat for all requests
< system.physmem.totBusLat 592412000 # Total cycles spent in databus access
< system.physmem.totBankLat 2483320000 # Total cycles spent in bank access
< system.physmem.avgQLat 11038.95 # Average queueing delay per request
< system.physmem.avgBankLat 16767.52 # Average bank access latency per request
---
> system.physmem.totQLat 1631933240 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 4708845240 # Sum of mem lat for all requests
> system.physmem.totBusLat 592780000 # Total cycles spent in databus access
> system.physmem.totBankLat 2484132000 # Total cycles spent in bank access
> system.physmem.avgQLat 11012.07 # Average queueing delay per request
> system.physmem.avgBankLat 16762.59 # Average bank access latency per request
181,185c181,185
< system.physmem.avgMemAccLat 31806.47 # Average memory access latency
< system.physmem.avgRdBW 46.03 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 30.33 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 46.03 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 30.33 # Average consumed write bandwidth in MB/s
---
> system.physmem.avgMemAccLat 31774.66 # Average memory access latency
> system.physmem.avgRdBW 46.06 # Average achieved read bandwidth in MB/s
> system.physmem.avgWrBW 30.34 # Average achieved write bandwidth in MB/s
> system.physmem.avgConsumedRdBW 46.06 # Average consumed read bandwidth in MB/s
> system.physmem.avgConsumedWrBW 30.34 # Average consumed write bandwidth in MB/s
189,194c189,194
< system.physmem.avgWrQLen 8.63 # Average write queue length over time
< system.physmem.readRowHits 128528 # Number of row buffer hits during reads
< system.physmem.writeRowHits 35061 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 86.78 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 35.91 # Row buffer hit rate for writes
< system.physmem.avgGap 838077.47 # Average gap between requests
---
> system.physmem.avgWrQLen 8.58 # Average write queue length over time
> system.physmem.readRowHits 128622 # Number of row buffer hits during reads
> system.physmem.writeRowHits 35037 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 86.79 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 35.88 # Row buffer hit rate for writes
> system.physmem.avgGap 837681.71 # Average gap between requests
238c238
< system.cpu.numCycles 412049214 # number of cpu cycles simulated
---
> system.cpu.numCycles 412013783 # number of cpu cycles simulated
241,245c241,245
< system.cpu.BPredUnit.lookups 182068030 # Number of BP lookups
< system.cpu.BPredUnit.condPredicted 142371650 # Number of conditional branches predicted
< system.cpu.BPredUnit.condIncorrect 7270692 # Number of conditional branches incorrect
< system.cpu.BPredUnit.BTBLookups 93491623 # Number of BTB lookups
< system.cpu.BPredUnit.BTBHits 88706856 # Number of BTB hits
---
> system.cpu.BPredUnit.lookups 182073557 # Number of BP lookups
> system.cpu.BPredUnit.condPredicted 142374329 # Number of conditional branches predicted
> system.cpu.BPredUnit.condIncorrect 7271583 # Number of conditional branches incorrect
> system.cpu.BPredUnit.BTBLookups 93640941 # Number of BTB lookups
> system.cpu.BPredUnit.BTBHits 88714986 # Number of BTB hits
247,263c247,263
< system.cpu.BPredUnit.usedRAS 12684721 # Number of times the RAS was used to get a target.
< system.cpu.BPredUnit.RASInCorrect 116337 # Number of incorrect RAS predictions.
< system.cpu.fetch.icacheStallCycles 117167260 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 763059580 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 182068030 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 101391577 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 170902348 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 35691223 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 89206735 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 447 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 113060023 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 2443326 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 404896941 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.113484 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.961332 # Number of instructions fetched each cycle (Total)
---
> system.cpu.BPredUnit.usedRAS 12682930 # Number of times the RAS was used to get a target.
> system.cpu.BPredUnit.RASInCorrect 115717 # Number of incorrect RAS predictions.
> system.cpu.fetch.icacheStallCycles 117168420 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 763090504 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 182073557 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 101397916 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 170904146 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 35690489 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 89173012 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 387 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 113064693 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 2443926 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 404864320 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.113664 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.961425 # Number of instructions fetched each cycle (Total)
265,273c265,273
< system.cpu.fetch.rateDist::0 234007224 57.79% 57.79% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 14183787 3.50% 61.30% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 22898202 5.66% 66.95% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 22746913 5.62% 72.57% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 20897614 5.16% 77.73% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 13086335 3.23% 80.96% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 13059349 3.23% 84.19% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 11995905 2.96% 87.15% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 52021612 12.85% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 233972788 57.79% 57.79% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 14182494 3.50% 61.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 22907477 5.66% 66.95% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 22746192 5.62% 72.57% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 20892499 5.16% 77.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 13088798 3.23% 80.96% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 13051042 3.22% 84.19% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 11993527 2.96% 87.15% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 52029503 12.85% 100.00% # Number of instructions fetched each cycle (Total)
277,322c277,322
< system.cpu.fetch.rateDist::total 404896941 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.441860 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.851865 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 127568061 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 83247236 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 161078099 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 5457696 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 27545849 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 26128375 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 76880 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 833033782 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 297363 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 27545849 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 135637511 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 9603466 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 58001862 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 158291644 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 15816609 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 804360707 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 1150 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 3056892 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 8825253 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 274 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 960209661 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 3520079656 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 3520077996 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 672200315 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 288009346 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 3037560 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 3037556 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 48985402 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 170961044 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 74192431 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 27929541 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 15655992 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 757955551 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 4467760 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 669035735 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 1391656 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 187243555 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 479554620 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 746625 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 404896941 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.652361 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.728633 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 404864320 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.441911 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.852099 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 127567795 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 83214346 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 161081773 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 5456100 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 27544306 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 26131693 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 76746 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 833046476 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 293832 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 27544306 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 135636368 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 9592122 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 57998215 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 158294561 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 15798748 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 804356889 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 3056071 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 8809517 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 236 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 960228219 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 3520047664 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 3520046036 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 1628 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 672200251 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 288027968 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 3037400 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 3037395 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 48984020 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 170948465 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 74181775 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 27930048 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 15662241 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 757938362 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 4467556 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 669004170 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 1390745 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 187223839 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 479595431 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 746429 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 404864320 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.652416 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.728625 # Number of insts issued each cycle
324,332c324,332
< system.cpu.iq.issued_per_cycle::0 145342748 35.90% 35.90% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 75751868 18.71% 54.61% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 69103679 17.07% 71.67% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 53697004 13.26% 84.93% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 30880919 7.63% 92.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 16180758 4.00% 96.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 9302044 2.30% 98.85% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 3357601 0.83% 99.68% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 1280320 0.32% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 145294997 35.89% 35.89% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 75803785 18.72% 54.61% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 69074812 17.06% 71.67% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 53696610 13.26% 84.93% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 30882442 7.63% 92.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 16155264 3.99% 96.55% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 9314791 2.30% 98.85% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 3366855 0.83% 99.69% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 1274764 0.31% 100.00% # Number of insts issued each cycle
336c336
< system.cpu.iq.issued_per_cycle::total 404896941 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 404864320 # Number of insts issued each cycle
338c338
< system.cpu.iq.fu_full::IntAlu 478504 4.99% 4.99% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 478550 4.99% 4.99% # attempts to use FU when none available
367,368c367,368
< system.cpu.iq.fu_full::MemRead 6546722 68.33% 73.32% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 2556023 26.68% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 6548662 68.24% 73.23% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 2569141 26.77% 100.00% # attempts to use FU when none available
372,402c372,402
< system.cpu.iq.FU_type_0::IntAlu 449967918 67.26% 67.26% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 383484 0.06% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.31% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 154140670 23.04% 90.35% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 64543544 9.65% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 449957502 67.26% 67.26% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 383513 0.06% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 114 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 154129801 23.04% 90.35% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 64533237 9.65% 100.00% # Type of FU issued
405,413c405,413
< system.cpu.iq.FU_type_0::total 669035735 # Type of FU issued
< system.cpu.iq.rate 1.623679 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 9581249 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.014321 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 1753941049 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 950473417 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 649676758 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes
---
> system.cpu.iq.FU_type_0::total 669004170 # Type of FU issued
> system.cpu.iq.rate 1.623742 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 9596353 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.014344 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 1753859495 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 950436200 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 649651296 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 358 # Number of floating instruction queue writes
415,417c415,417
< system.cpu.iq.int_alu_accesses 678616849 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 8574736 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.int_alu_accesses 678600390 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 8560025 # Number of loads that had data forwarded from stores
419,422c419,422
< system.cpu.iew.lsq.thread0.squashedLoads 44187986 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 40720 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 810577 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 16588451 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 44175415 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 40342 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 810510 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 16577803 # Number of stores squashed
425,426c425,426
< system.cpu.iew.lsq.thread0.rescheduledLoads 19568 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 4004 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 19533 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 4184 # Number of times an access to memory failed due to the cache being blocked
428,444c428,444
< system.cpu.iew.iewSquashCycles 27545849 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 4988149 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 372803 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 763982304 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 1114436 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 170961044 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 74192431 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 2979014 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 218503 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 11510 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 810577 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 4341639 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 4005453 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 8347092 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 659537182 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 150855099 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 9498553 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 27544306 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 4979953 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 372702 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 763965600 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 1116680 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 170948465 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 74181775 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 2978814 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 218949 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 11431 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 810510 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 4004049 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 8346983 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 659511571 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 150841037 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 9492599 # Number of squashed instructions skipped in execute
446,454c446,454
< system.cpu.iew.exec_nop 1558993 # number of nop insts executed
< system.cpu.iew.exec_refs 214102413 # number of memory reference insts executed
< system.cpu.iew.exec_branches 139198797 # Number of branches executed
< system.cpu.iew.exec_stores 63247314 # Number of stores executed
< system.cpu.iew.exec_rate 1.600627 # Inst execution rate
< system.cpu.iew.wb_sent 654653382 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 649676774 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 375457821 # num instructions producing a value
< system.cpu.iew.wb_consumers 646369335 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 1559682 # number of nop insts executed
> system.cpu.iew.exec_refs 214084743 # number of memory reference insts executed
> system.cpu.iew.exec_branches 139192858 # Number of branches executed
> system.cpu.iew.exec_stores 63243706 # Number of stores executed
> system.cpu.iew.exec_rate 1.600703 # Inst execution rate
> system.cpu.iew.wb_sent 654626894 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 649651312 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 375421754 # num instructions producing a value
> system.cpu.iew.wb_consumers 646280118 # num instructions consuming a value
456,457c456,457
< system.cpu.iew.wb_rate 1.576697 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.580872 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.576771 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.580896 # average fanout of values written-back
459,464c459,464
< system.cpu.commit.commitSquashedInsts 189322511 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 3721135 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 7196542 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 377351093 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.522947 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.207142 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 189306245 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 3721127 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 7197604 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 377320014 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.523072 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.207570 # Number of insts commited each cycle
466,474c466,474
< system.cpu.commit.committed_per_cycle::0 165639440 43.90% 43.90% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 102355544 27.12% 71.02% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 34004026 9.01% 80.03% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 18854456 5.00% 85.03% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 16118319 4.27% 89.30% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 7599031 2.01% 91.31% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 6941679 1.84% 93.15% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 3068571 0.81% 93.97% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 22770027 6.03% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 165631141 43.90% 43.90% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 102377769 27.13% 71.03% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 33965417 9.00% 80.03% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 18834681 4.99% 85.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 16120892 4.27% 89.30% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 7588494 2.01% 91.31% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 6947007 1.84% 93.15% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 3071988 0.81% 93.96% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 22782625 6.04% 100.00% # Number of insts commited each cycle
478,480c478,480
< system.cpu.commit.committed_per_cycle::total 377351093 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 510299122 # Number of instructions committed
< system.cpu.commit.committedOps 574685682 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 377320014 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 510299082 # Number of instructions committed
> system.cpu.commit.committedOps 574685642 # Number of ops (including micro ops) committed
482,483c482,483
< system.cpu.commit.refs 184377038 # Number of memory references committed
< system.cpu.commit.loads 126773058 # Number of loads committed
---
> system.cpu.commit.refs 184377022 # Number of memory references committed
> system.cpu.commit.loads 126773050 # Number of loads committed
485c485
< system.cpu.commit.branches 122291804 # Number of branches committed
---
> system.cpu.commit.branches 122291796 # Number of branches committed
487c487
< system.cpu.commit.int_insts 473701705 # Number of committed integer instructions.
---
> system.cpu.commit.int_insts 473701673 # Number of committed integer instructions.
489c489
< system.cpu.commit.bw_lim_events 22770027 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 22782625 # number cycles where commit BW limit reached
491,503c491,503
< system.cpu.rob.rob_reads 1118582121 # The number of ROB reads
< system.cpu.rob.rob_writes 1555682986 # The number of ROB writes
< system.cpu.timesIdled 306922 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 7152273 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.committedInsts 508955238 # Number of Instructions Simulated
< system.cpu.committedOps 573341798 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 508955238 # Number of Instructions Simulated
< system.cpu.cpi 0.809598 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.809598 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.235181 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.235181 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 3078487600 # number of integer regfile reads
< system.cpu.int_regfile_writes 757812476 # number of integer regfile writes
---
> system.cpu.rob.rob_reads 1118522138 # The number of ROB reads
> system.cpu.rob.rob_writes 1555649058 # The number of ROB writes
> system.cpu.timesIdled 306506 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 7149463 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.committedInsts 508955198 # Number of Instructions Simulated
> system.cpu.committedOps 573341758 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 508955198 # Number of Instructions Simulated
> system.cpu.cpi 0.809529 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.809529 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.235287 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.235287 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 3078340491 # number of integer regfile reads
> system.cpu.int_regfile_writes 757780607 # number of integer regfile writes
505,511c505,511
< system.cpu.misc_regfile_reads 213834943 # number of misc regfile reads
< system.cpu.misc_regfile_writes 4464090 # number of misc regfile writes
< system.cpu.icache.replacements 14939 # number of replacements
< system.cpu.icache.tagsinuse 1085.691077 # Cycle average of tags in use
< system.cpu.icache.total_refs 113039002 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 16794 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 6730.915922 # Average number of references to valid blocks.
---
> system.cpu.misc_regfile_reads 213817535 # number of misc regfile reads
> system.cpu.misc_regfile_writes 4464074 # number of misc regfile writes
> system.cpu.icache.replacements 15034 # number of replacements
> system.cpu.icache.tagsinuse 1084.596639 # Cycle average of tags in use
> system.cpu.icache.total_refs 113043631 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 16888 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 6693.725189 # Average number of references to valid blocks.
513,539c513,539
< system.cpu.icache.occ_blocks::cpu.inst 1085.691077 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.530123 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.530123 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 113039002 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 113039002 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 113039002 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 113039002 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 113039002 # number of overall hits
< system.cpu.icache.overall_hits::total 113039002 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 21020 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 21020 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 21020 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 21020 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 21020 # number of overall misses
< system.cpu.icache.overall_misses::total 21020 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 467898499 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 467898499 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 467898499 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 467898499 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 467898499 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 467898499 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 113060022 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 113060022 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 113060022 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 113060022 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 113060022 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 113060022 # number of overall (read+write) accesses
---
> system.cpu.icache.occ_blocks::cpu.inst 1084.596639 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.529588 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.529588 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 113043631 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 113043631 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 113043631 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 113043631 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 113043631 # number of overall hits
> system.cpu.icache.overall_hits::total 113043631 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 21062 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 21062 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 21062 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 21062 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 21062 # number of overall misses
> system.cpu.icache.overall_misses::total 21062 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 460496000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 460496000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 460496000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 460496000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 460496000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 460496000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 113064693 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 113064693 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 113064693 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 113064693 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 113064693 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 113064693 # number of overall (read+write) accesses
546,552c546,552
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22259.681208 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 22259.681208 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 22259.681208 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 22259.681208 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 22259.681208 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 22259.681208 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21863.830595 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 21863.830595 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 21863.830595 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 21863.830595 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 1088 # number of cycles access was blocked
554c554
< system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
556c556
< system.cpu.icache.avg_blocked_cycles::no_mshrs 44.071429 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 90.666667 # average number of cycles each access was blocked
560,589c560,589
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4142 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 4142 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 4142 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 4142 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 4142 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 4142 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16878 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 16878 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 16878 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 16878 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 16878 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 16878 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 345467499 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 345467499 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 345467499 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 345467499 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 345467499 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 345467499 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20468.509243 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20468.509243 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20468.509243 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 20468.509243 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20468.509243 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 20468.509243 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4099 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 4099 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 4099 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 4099 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 4099 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 4099 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16963 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 16963 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 16963 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 16963 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 16963 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 16963 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340828000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 340828000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340828000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 340828000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340828000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 340828000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000150 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000150 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000150 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20092.436479 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20092.436479 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency
591,807c591,681
< system.cpu.dcache.replacements 1192636 # number of replacements
< system.cpu.dcache.tagsinuse 4054.758730 # Cycle average of tags in use
< system.cpu.dcache.total_refs 191679858 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1196732 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 160.169410 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4054.758730 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.989931 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.989931 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 136223332 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 136223332 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 50991136 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 50991136 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233077 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 2233077 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 2232044 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 2232044 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 187214468 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 187214468 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 187214468 # number of overall hits
< system.cpu.dcache.overall_hits::total 187214468 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1695528 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1695528 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3248170 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3248170 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 4943698 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4943698 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4943698 # number of overall misses
< system.cpu.dcache.overall_misses::total 4943698 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 25996744000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 25996744000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 58872632949 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 58872632949 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 602000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 602000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 84869376949 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 84869376949 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 84869376949 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 84869376949 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 137918860 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 137918860 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233117 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 2233117 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232044 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 2232044 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 192158166 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 192158166 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 192158166 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 192158166 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012294 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.012294 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059886 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.059886 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.025727 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.025727 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.025727 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.025727 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15332.535942 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15332.535942 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18124.861984 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 18124.861984 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15050 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15050 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 17167.184757 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 17167.184757 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 14786 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 14311 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 1668 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 602 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.864508 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 23.772425 # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 1110847 # number of writebacks
< system.cpu.dcache.writebacks::total 1110847 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847136 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 847136 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899743 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2899743 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 3746879 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3746879 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3746879 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3746879 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848392 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 848392 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348427 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 348427 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1196819 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1196819 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1196819 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1196819 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11475027500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 11475027500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8270144996 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8270144996 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19745172496 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 19745172496 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19745172496 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 19745172496 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13525.619643 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13525.619643 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23735.660543 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23735.660543 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16498.043978 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 16498.043978 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16498.043978 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 16498.043978 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.l2cache.replacements 115436 # number of replacements
< system.cpu.l2cache.tagsinuse 26914.677594 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 1781438 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 146695 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 12.143822 # Average number of references to valid blocks.
< system.cpu.l2cache.warmup_cycle 106786835500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 22885.911087 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 362.909713 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 3665.856794 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.698423 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.inst 0.011075 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.111873 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.821371 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 13377 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 804311 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 817688 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1110847 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1110847 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 76 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 76 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 247608 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 247608 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 13377 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1051919 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1065296 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 13377 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1051919 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1065296 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 3401 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 43520 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 46921 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 3401 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 144813 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 148214 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3401 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 144813 # number of overall misses
< system.cpu.l2cache.overall_misses::total 148214 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 194270000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2545313000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2739583000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5395902500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5395902500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 194270000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7941215500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 8135485500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 194270000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7941215500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 8135485500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 16778 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 847831 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 864609 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1110847 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1110847 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 87 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 87 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 348901 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 348901 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 16778 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1196732 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1213510 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 16778 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1196732 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1213510 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.202706 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051331 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.054268 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.126437 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.126437 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290320 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.290320 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.202706 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.121007 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.122137 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.202706 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.121007 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.122137 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57121.434872 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58486.052390 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 58387.140087 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53270.240787 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53270.240787 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57121.434872 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54837.725204 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 54890.128463 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57121.434872 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54837.725204 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 54890.128463 # average overall miss latency
---
> system.cpu.l2cache.replacements 115524 # number of replacements
> system.cpu.l2cache.tagsinuse 26913.844111 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 1781016 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 146770 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 12.134741 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 106794042500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 22881.724629 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 362.646179 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 3669.473303 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.698295 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.011067 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.111983 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.821345 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 13496 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 804094 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 817590 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1110621 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1110621 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 66 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 66 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 247478 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 247478 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 13496 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1051572 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1065068 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 13496 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1051572 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1065068 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 3384 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 43623 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 47007 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 101285 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 101285 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 3384 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 144908 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 148292 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3384 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 144908 # number of overall misses
> system.cpu.l2cache.overall_misses::total 148292 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188319500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2550766500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2739086000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5396872000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5396872000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 188319500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7947638500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8135958000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 188319500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7947638500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8135958000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 16880 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 847717 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 864597 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1110621 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1110621 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 75 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 348763 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 348763 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 16880 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1196480 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1213360 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 16880 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1196480 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1213360 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200474 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051459 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.054369 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.120000 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.120000 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290412 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.290412 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200474 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.121112 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.122216 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200474 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.121112 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.122216 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55649.970449 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58472.972973 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 58269.747059 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53284.020339 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53284.020339 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55649.970449 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54846.098904 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 54864.443126 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55649.970449 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54846.098904 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 54864.443126 # average overall miss latency
816,817c690,691
< system.cpu.l2cache.writebacks::writebacks 97644 # number of writebacks
< system.cpu.l2cache.writebacks::total 97644 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 97660 # number of writebacks
> system.cpu.l2cache.writebacks::total 97660 # number of writebacks
819,820c693,694
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
822,823c696,697
< system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
825,868c699,742
< system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3396 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43497 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 46893 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3396 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 144790 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 148186 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3396 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 144790 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 148186 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 150961260 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1989439233 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2140400493 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 110011 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 110011 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4107848419 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4107848419 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 150961260 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6097287652 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6248248912 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 150961260 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6097287652 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 6248248912 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051304 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.126437 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.126437 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290320 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290320 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120988 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.122114 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120988 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.122114 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44452.667845 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45737.389544 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45644.349754 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3379 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43601 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 46980 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101285 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 101285 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3379 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 144886 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 148265 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3379 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 144886 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 148265 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 144900235 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1993232927 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2138133162 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4109014892 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4109014892 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 144900235 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6102247819 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6247148054 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 144900235 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6102247819 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6247148054 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051433 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054337 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.120000 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.120000 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290412 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290412 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121094 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.122194 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121094 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.122194 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42882.579165 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45715.303021 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45511.561558 # average ReadReq mshr miss latency
871,878c745,752
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40554.119426 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40554.119426 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40568.839335 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40568.839335 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42882.579165 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42117.580850 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42135.015371 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42882.579165 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42117.580850 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42135.015371 # average overall mshr miss latency
879a754,879
> system.cpu.dcache.replacements 1192383 # number of replacements
> system.cpu.dcache.tagsinuse 4054.755183 # Cycle average of tags in use
> system.cpu.dcache.total_refs 191684453 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1196479 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 160.207119 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4054.755183 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.989930 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.989930 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 136225611 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 136225611 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 50993519 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 50993519 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233068 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 2233068 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 2232036 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 2232036 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 187219130 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 187219130 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 187219130 # number of overall hits
> system.cpu.dcache.overall_hits::total 187219130 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1694816 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1694816 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3245787 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3245787 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 4940603 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4940603 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4940603 # number of overall misses
> system.cpu.dcache.overall_misses::total 4940603 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 25904626000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 25904626000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 58849421949 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 58849421949 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 574000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 574000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 84754047949 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 84754047949 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 84754047949 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 84754047949 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 137920427 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 137920427 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233106 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 2233106 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232036 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 2232036 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 192159733 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 192159733 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 192159733 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 192159733 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012288 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.012288 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059842 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.059842 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000017 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000017 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.025711 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.025711 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.025711 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.025711 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15284.624408 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15284.624408 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18131.017824 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 18131.017824 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15105.263158 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15105.263158 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 17154.595896 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 17154.595896 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 17154.595896 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 17154.595896 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 17486 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 15854 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 1635 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 605 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.694801 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 26.204959 # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 1110621 # number of writebacks
> system.cpu.dcache.writebacks::total 1110621 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 846554 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 846554 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2897494 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2897494 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 3744048 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3744048 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3744048 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3744048 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848262 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 848262 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348293 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 348293 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1196555 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1196555 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1196555 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1196555 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11478175000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 11478175000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269727997 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269727997 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19747902997 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 19747902997 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19747902997 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 19747902997 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13531.403033 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13531.403033 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23743.595183 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23743.595183 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate