7,11c7,11
< host_inst_rate 104599 # Simulator instruction rate (inst/s)
< host_op_rate 117832 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 47897344 # Simulator tick rate (ticks/s)
< host_mem_usage 237516 # Number of bytes of host memory used
< host_seconds 4865.77 # Real time elapsed on the host
---
> host_inst_rate 102553 # Simulator instruction rate (inst/s)
> host_op_rate 115527 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 46960535 # Simulator tick rate (ticks/s)
> host_mem_usage 237172 # Number of bytes of host memory used
> host_seconds 4962.84 # Real time elapsed on the host
14,23c14,36
< system.physmem.bytes_read 15214144 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 10947904 # Number of bytes written to this memory
< system.physmem.num_reads 237721 # Number of read requests responded to by this memory
< system.physmem.num_writes 171061 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 246208 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 14967936 # Number of bytes read from this memory
> system.physmem.bytes_read::total 15214144 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 246208 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 246208 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 10947904 # Number of bytes written to this memory
> system.physmem.bytes_written::total 10947904 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3847 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 233874 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 237721 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 171061 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 171061 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1056426 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 64224208 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 65280633 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1056426 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1056426 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 46975111 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 46975111 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 46975111 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1056426 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 64224208 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 112255745 # Total bandwidth to/from this memory (bytes/s)
370a384
> system.cpu.icache.ReadReq_miss_rate::total 0.000157 # miss rate for ReadReq accesses
371a386
> system.cpu.icache.demand_miss_rate::total 0.000157 # miss rate for demand accesses
372a388
> system.cpu.icache.overall_miss_rate::total 0.000157 # miss rate for overall accesses
373a390
> system.cpu.icache.ReadReq_avg_miss_latency::total 13468.126288 # average ReadReq miss latency
374a392
> system.cpu.icache.demand_avg_miss_latency::total 13468.126288 # average overall miss latency
375a394
> system.cpu.icache.overall_avg_miss_latency::total 13468.126288 # average overall miss latency
404a424
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000143 # mshr miss rate for ReadReq accesses
405a426
> system.cpu.icache.demand_mshr_miss_rate::total 0.000143 # mshr miss rate for demand accesses
406a428
> system.cpu.icache.overall_mshr_miss_rate::total 0.000143 # mshr miss rate for overall accesses
407a430
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9466.164792 # average ReadReq mshr miss latency
408a432
> system.cpu.icache.demand_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency
409a434
> system.cpu.icache.overall_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency
464a490
> system.cpu.dcache.ReadReq_miss_rate::total 0.009328 # miss rate for ReadReq accesses
465a492
> system.cpu.dcache.WriteReq_miss_rate::total 0.026850 # miss rate for WriteReq accesses
466a494
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000035 # miss rate for LoadLockedReq accesses
467a496
> system.cpu.dcache.demand_miss_rate::total 0.014186 # miss rate for demand accesses
468a498
> system.cpu.dcache.overall_miss_rate::total 0.014186 # miss rate for overall accesses
469a500
> system.cpu.dcache.ReadReq_avg_miss_latency::total 11591.851869 # average ReadReq miss latency
470a502
> system.cpu.dcache.WriteReq_avg_miss_latency::total 17278.996354 # average WriteReq miss latency
471a504
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10839.743590 # average LoadLockedReq miss latency
472a506
> system.cpu.dcache.demand_avg_miss_latency::total 14576.321503 # average overall miss latency
473a508
> system.cpu.dcache.overall_avg_miss_latency::total 14576.321503 # average overall miss latency
510a546
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006138 # mshr miss rate for ReadReq accesses
511a548
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006292 # mshr miss rate for WriteReq accesses
512a550
> system.cpu.dcache.demand_mshr_miss_rate::total 0.006181 # mshr miss rate for demand accesses
513a552
> system.cpu.dcache.overall_mshr_miss_rate::total 0.006181 # mshr miss rate for overall accesses
514a554
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7154.602287 # average ReadReq mshr miss latency
515a556
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12837.889185 # average WriteReq mshr miss latency
516a558
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency
517a560
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency
589a633
> system.cpu.l2cache.ReadReq_miss_rate::total 0.145145 # miss rate for ReadReq accesses
590a635
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.230769 # miss rate for UpgradeReq accesses
591a637
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.319698 # miss rate for ReadExReq accesses
593a640
> system.cpu.l2cache.demand_miss_rate::total 0.193778 # miss rate for demand accesses
595a643
> system.cpu.l2cache.overall_miss_rate::total 0.193778 # miss rate for overall accesses
597a646
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34200.768309 # average ReadReq miss latency
598a648
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6212.121212 # average UpgradeReq miss latency
599a650
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34242.649952 # average ReadExReq miss latency
601a653
> system.cpu.l2cache.demand_avg_miss_latency::total 34220.019853 # average overall miss latency
603a656
> system.cpu.l2cache.overall_avg_miss_latency::total 34220.019853 # average overall miss latency
650a704
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.145114 # mshr miss rate for ReadReq accesses
651a706
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for UpgradeReq accesses
652a708
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.319698 # mshr miss rate for ReadExReq accesses
654a711
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.193756 # mshr miss rate for demand accesses
656a714
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.193756 # mshr miss rate for overall accesses
658a717
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31038.310611 # average ReadReq mshr miss latency
659a719
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31045.454545 # average UpgradeReq mshr miss latency
660a721
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.610514 # average ReadExReq mshr miss latency
662a724
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency
664a727
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency
< host_inst_rate 104599 # Simulator instruction rate (inst/s)
< host_op_rate 117832 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 47897344 # Simulator tick rate (ticks/s)
< host_mem_usage 237516 # Number of bytes of host memory used
< host_seconds 4865.77 # Real time elapsed on the host
---
> host_inst_rate 102553 # Simulator instruction rate (inst/s)
> host_op_rate 115527 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 46960535 # Simulator tick rate (ticks/s)
> host_mem_usage 237172 # Number of bytes of host memory used
> host_seconds 4962.84 # Real time elapsed on the host
14,23c14,36
< system.physmem.bytes_read 15214144 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 10947904 # Number of bytes written to this memory
< system.physmem.num_reads 237721 # Number of read requests responded to by this memory
< system.physmem.num_writes 171061 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 246208 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 14967936 # Number of bytes read from this memory
> system.physmem.bytes_read::total 15214144 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 246208 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 246208 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 10947904 # Number of bytes written to this memory
> system.physmem.bytes_written::total 10947904 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3847 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 233874 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 237721 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 171061 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 171061 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1056426 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 64224208 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 65280633 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1056426 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1056426 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 46975111 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 46975111 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 46975111 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1056426 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 64224208 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 112255745 # Total bandwidth to/from this memory (bytes/s)
370a384
> system.cpu.icache.ReadReq_miss_rate::total 0.000157 # miss rate for ReadReq accesses
371a386
> system.cpu.icache.demand_miss_rate::total 0.000157 # miss rate for demand accesses
372a388
> system.cpu.icache.overall_miss_rate::total 0.000157 # miss rate for overall accesses
373a390
> system.cpu.icache.ReadReq_avg_miss_latency::total 13468.126288 # average ReadReq miss latency
374a392
> system.cpu.icache.demand_avg_miss_latency::total 13468.126288 # average overall miss latency
375a394
> system.cpu.icache.overall_avg_miss_latency::total 13468.126288 # average overall miss latency
404a424
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000143 # mshr miss rate for ReadReq accesses
405a426
> system.cpu.icache.demand_mshr_miss_rate::total 0.000143 # mshr miss rate for demand accesses
406a428
> system.cpu.icache.overall_mshr_miss_rate::total 0.000143 # mshr miss rate for overall accesses
407a430
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9466.164792 # average ReadReq mshr miss latency
408a432
> system.cpu.icache.demand_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency
409a434
> system.cpu.icache.overall_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency
464a490
> system.cpu.dcache.ReadReq_miss_rate::total 0.009328 # miss rate for ReadReq accesses
465a492
> system.cpu.dcache.WriteReq_miss_rate::total 0.026850 # miss rate for WriteReq accesses
466a494
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000035 # miss rate for LoadLockedReq accesses
467a496
> system.cpu.dcache.demand_miss_rate::total 0.014186 # miss rate for demand accesses
468a498
> system.cpu.dcache.overall_miss_rate::total 0.014186 # miss rate for overall accesses
469a500
> system.cpu.dcache.ReadReq_avg_miss_latency::total 11591.851869 # average ReadReq miss latency
470a502
> system.cpu.dcache.WriteReq_avg_miss_latency::total 17278.996354 # average WriteReq miss latency
471a504
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10839.743590 # average LoadLockedReq miss latency
472a506
> system.cpu.dcache.demand_avg_miss_latency::total 14576.321503 # average overall miss latency
473a508
> system.cpu.dcache.overall_avg_miss_latency::total 14576.321503 # average overall miss latency
510a546
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006138 # mshr miss rate for ReadReq accesses
511a548
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006292 # mshr miss rate for WriteReq accesses
512a550
> system.cpu.dcache.demand_mshr_miss_rate::total 0.006181 # mshr miss rate for demand accesses
513a552
> system.cpu.dcache.overall_mshr_miss_rate::total 0.006181 # mshr miss rate for overall accesses
514a554
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7154.602287 # average ReadReq mshr miss latency
515a556
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12837.889185 # average WriteReq mshr miss latency
516a558
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency
517a560
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency
589a633
> system.cpu.l2cache.ReadReq_miss_rate::total 0.145145 # miss rate for ReadReq accesses
590a635
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.230769 # miss rate for UpgradeReq accesses
591a637
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.319698 # miss rate for ReadExReq accesses
593a640
> system.cpu.l2cache.demand_miss_rate::total 0.193778 # miss rate for demand accesses
595a643
> system.cpu.l2cache.overall_miss_rate::total 0.193778 # miss rate for overall accesses
597a646
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34200.768309 # average ReadReq miss latency
598a648
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6212.121212 # average UpgradeReq miss latency
599a650
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34242.649952 # average ReadExReq miss latency
601a653
> system.cpu.l2cache.demand_avg_miss_latency::total 34220.019853 # average overall miss latency
603a656
> system.cpu.l2cache.overall_avg_miss_latency::total 34220.019853 # average overall miss latency
650a704
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.145114 # mshr miss rate for ReadReq accesses
651a706
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for UpgradeReq accesses
652a708
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.319698 # mshr miss rate for ReadExReq accesses
654a711
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.193756 # mshr miss rate for demand accesses
656a714
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.193756 # mshr miss rate for overall accesses
658a717
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31038.310611 # average ReadReq mshr miss latency
659a719
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31045.454545 # average UpgradeReq mshr miss latency
660a721
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.610514 # average ReadExReq mshr miss latency
662a724
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency
664a727
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency