3,5c3,5
< sim_seconds 0.236034 # Number of seconds simulated
< sim_ticks 236034256000 # Number of ticks simulated
< final_tick 236034256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.236024 # Number of seconds simulated
> sim_ticks 236023688000 # Number of ticks simulated
> final_tick 236023688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 253188 # Simulator instruction rate (inst/s)
< host_op_rate 274292 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 118283576 # Simulator tick rate (ticks/s)
< host_mem_usage 302048 # Number of bytes of host memory used
< host_seconds 1995.49 # Real time elapsed on the host
---
> host_inst_rate 256452 # Simulator instruction rate (inst/s)
> host_op_rate 277829 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 119803336 # Simulator tick rate (ticks/s)
> host_mem_usage 301968 # Number of bytes of host memory used
> host_seconds 1970.09 # Real time elapsed on the host
16,54c16,54
< system.physmem.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 637184 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10497472 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 16389440 # Number of bytes read from this memory
< system.physmem.bytes_read::total 27524096 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 637184 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 637184 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 18641536 # Number of bytes written to this memory
< system.physmem.bytes_written::total 18641536 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 9956 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 164023 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 256085 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 430064 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 291274 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 291274 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 2699540 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 44474358 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 69436701 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 116610599 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 2699540 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 2699540 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 78978095 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 78978095 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 78978095 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 2699540 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 44474358 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 69436701 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 195588695 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 430064 # Number of read requests accepted
< system.physmem.writeReqs 291274 # Number of write requests accepted
< system.physmem.readBursts 430064 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 291274 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 27360896 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 163200 # Total number of bytes read from write queue
< system.physmem.bytesWritten 18638848 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 27524096 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 18641536 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 2550 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 640832 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10509760 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 16394496 # Number of bytes read from this memory
> system.physmem.bytes_read::total 27545088 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 640832 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 640832 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 18630208 # Number of bytes written to this memory
> system.physmem.bytes_written::total 18630208 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 10013 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 164215 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 256164 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 430392 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 291097 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 291097 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 2715117 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 44528412 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 69461231 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 116704761 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 2715117 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 2715117 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 78933637 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 78933637 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 78933637 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2715117 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 44528412 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 69461231 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 195638397 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 430392 # Number of read requests accepted
> system.physmem.writeReqs 291097 # Number of write requests accepted
> system.physmem.readBursts 430392 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 291097 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 27379648 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 165440 # Total number of bytes read from write queue
> system.physmem.bytesWritten 18628032 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 27545088 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 18630208 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 2585 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one
56,87c56,87
< system.physmem.perBankRdBursts::0 27217 # Per bank write bursts
< system.physmem.perBankRdBursts::1 26580 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25459 # Per bank write bursts
< system.physmem.perBankRdBursts::3 32933 # Per bank write bursts
< system.physmem.perBankRdBursts::4 28005 # Per bank write bursts
< system.physmem.perBankRdBursts::5 30095 # Per bank write bursts
< system.physmem.perBankRdBursts::6 25324 # Per bank write bursts
< system.physmem.perBankRdBursts::7 24336 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25637 # Per bank write bursts
< system.physmem.perBankRdBursts::9 25661 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25768 # Per bank write bursts
< system.physmem.perBankRdBursts::11 26242 # Per bank write bursts
< system.physmem.perBankRdBursts::12 27581 # Per bank write bursts
< system.physmem.perBankRdBursts::13 26014 # Per bank write bursts
< system.physmem.perBankRdBursts::14 24864 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25798 # Per bank write bursts
< system.physmem.perBankWrBursts::0 18651 # Per bank write bursts
< system.physmem.perBankWrBursts::1 18268 # Per bank write bursts
< system.physmem.perBankWrBursts::2 17926 # Per bank write bursts
< system.physmem.perBankWrBursts::3 17983 # Per bank write bursts
< system.physmem.perBankWrBursts::4 18558 # Per bank write bursts
< system.physmem.perBankWrBursts::5 18375 # Per bank write bursts
< system.physmem.perBankWrBursts::6 17786 # Per bank write bursts
< system.physmem.perBankWrBursts::7 17681 # Per bank write bursts
< system.physmem.perBankWrBursts::8 18027 # Per bank write bursts
< system.physmem.perBankWrBursts::9 17737 # Per bank write bursts
< system.physmem.perBankWrBursts::10 18114 # Per bank write bursts
< system.physmem.perBankWrBursts::11 18781 # Per bank write bursts
< system.physmem.perBankWrBursts::12 18716 # Per bank write bursts
< system.physmem.perBankWrBursts::13 18163 # Per bank write bursts
< system.physmem.perBankWrBursts::14 18303 # Per bank write bursts
< system.physmem.perBankWrBursts::15 18163 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 27300 # Per bank write bursts
> system.physmem.perBankRdBursts::1 26589 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25489 # Per bank write bursts
> system.physmem.perBankRdBursts::3 32817 # Per bank write bursts
> system.physmem.perBankRdBursts::4 28238 # Per bank write bursts
> system.physmem.perBankRdBursts::5 30052 # Per bank write bursts
> system.physmem.perBankRdBursts::6 25322 # Per bank write bursts
> system.physmem.perBankRdBursts::7 24428 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25638 # Per bank write bursts
> system.physmem.perBankRdBursts::9 25508 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25695 # Per bank write bursts
> system.physmem.perBankRdBursts::11 26146 # Per bank write bursts
> system.physmem.perBankRdBursts::12 27543 # Per bank write bursts
> system.physmem.perBankRdBursts::13 26122 # Per bank write bursts
> system.physmem.perBankRdBursts::14 24924 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25996 # Per bank write bursts
> system.physmem.perBankWrBursts::0 18688 # Per bank write bursts
> system.physmem.perBankWrBursts::1 18252 # Per bank write bursts
> system.physmem.perBankWrBursts::2 17892 # Per bank write bursts
> system.physmem.perBankWrBursts::3 17877 # Per bank write bursts
> system.physmem.perBankWrBursts::4 18635 # Per bank write bursts
> system.physmem.perBankWrBursts::5 18189 # Per bank write bursts
> system.physmem.perBankWrBursts::6 17877 # Per bank write bursts
> system.physmem.perBankWrBursts::7 17743 # Per bank write bursts
> system.physmem.perBankWrBursts::8 17943 # Per bank write bursts
> system.physmem.perBankWrBursts::9 17697 # Per bank write bursts
> system.physmem.perBankWrBursts::10 18014 # Per bank write bursts
> system.physmem.perBankWrBursts::11 18785 # Per bank write bursts
> system.physmem.perBankWrBursts::12 18684 # Per bank write bursts
> system.physmem.perBankWrBursts::13 18184 # Per bank write bursts
> system.physmem.perBankWrBursts::14 18324 # Per bank write bursts
> system.physmem.perBankWrBursts::15 18279 # Per bank write bursts
90c90
< system.physmem.totGap 236034203500 # Total gap between requests
---
> system.physmem.totGap 236023635500 # Total gap between requests
97c97
< system.physmem.readPktSize::6 430064 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 430392 # Read request sizes (log2)
104,116c104,116
< system.physmem.writePktSize::6 291274 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 318869 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 60281 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 13267 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 8983 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 7229 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 6032 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 5148 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 4295 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3299 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 63 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 23 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 291097 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 318668 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 60537 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 13344 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 8917 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 7275 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 6198 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 5201 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 4287 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3249 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 78 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see
118c118
< system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see
152,182c152,182
< system.physmem.wrQLenPdf::15 6756 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 7242 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 12113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 14851 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 16256 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 16916 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 17294 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 17615 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 17892 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 18128 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 18323 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 18440 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 18551 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 18644 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 18821 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 18548 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 17432 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 17189 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 6733 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 7233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 12073 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 14859 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 16212 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 16884 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 17281 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 17602 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 17833 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 18085 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 18311 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 18465 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 18518 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 18609 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 18833 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 18532 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 17483 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 17245 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 140 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
201,218c201,218
< system.physmem.bytesPerActivate::samples 329061 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 139.787432 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 98.478985 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 178.644390 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 210353 63.93% 63.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 79320 24.10% 88.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 14852 4.51% 92.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7229 2.20% 94.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4899 1.49% 96.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2483 0.75% 96.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1823 0.55% 97.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1564 0.48% 98.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 6538 1.99% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 329061 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 17032 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 25.095820 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 145.258821 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 17030 99.99% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 328591 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 140.009775 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 98.675291 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 178.430270 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 209431 63.74% 63.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 79588 24.22% 87.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 14900 4.53% 92.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7308 2.22% 94.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4939 1.50% 96.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2586 0.79% 97.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1820 0.55% 97.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1543 0.47% 98.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 6476 1.97% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 328591 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 17028 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 25.118628 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 145.022717 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 17026 99.99% 99.99% # Reads before turning the bus around for writes
221,239c221,241
< system.physmem.rdPerTurnAround::total 17032 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 17032 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.099108 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.028520 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.818567 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-17 10039 58.94% 58.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18-19 6203 36.42% 95.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-21 545 3.20% 98.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22-23 139 0.82% 99.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-25 59 0.35% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26-27 18 0.11% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-29 9 0.05% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::30-31 2 0.01% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-33 2 0.01% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::34-35 2 0.01% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-37 3 0.02% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::38-39 5 0.03% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-41 2 0.01% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-61 2 0.01% 99.99% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 17028 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 17028 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.093199 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.022957 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.821852 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-17 10045 58.99% 58.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18-19 6192 36.36% 95.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-21 538 3.16% 98.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22-23 158 0.93% 99.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-25 50 0.29% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26-27 18 0.11% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-29 8 0.05% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::30-31 3 0.02% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-33 4 0.02% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::34-35 3 0.02% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::38-39 1 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-45 1 0.01% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-53 1 0.01% 99.98% # Writes before turning the bus around for reads
241,246c243,249
< system.physmem.wrPerTurnAround::104-105 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 17032 # Writes before turning the bus around for reads
< system.physmem.totQLat 14213030846 # Total ticks spent queuing
< system.physmem.totMemAccLat 22228918346 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2137570000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 33245.77 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::90-91 1 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-93 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 17028 # Writes before turning the bus around for reads
> system.physmem.totQLat 14230918095 # Total ticks spent queuing
> system.physmem.totMemAccLat 22252299345 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2139035000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 33264.81 # Average queueing delay per DRAM burst
248,252c251,255
< system.physmem.avgMemAccLat 51995.77 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 115.92 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 78.97 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 116.61 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 78.98 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 52014.81 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 78.92 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 116.70 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 78.93 # Average system write bandwidth in MiByte/s
257,308c260,311
< system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 21.65 # Average write queue length when enqueuing
< system.physmem.readRowHits 307655 # Number of row buffer hits during reads
< system.physmem.writeRowHits 82023 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 71.96 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 28.16 # Row buffer hit rate for writes
< system.physmem.avgGap 327217.20 # Average gap between requests
< system.physmem.pageHitRate 54.21 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 1196014260 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 635677680 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1570435860 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 758090160 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 15730481520.000004 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 13398551100 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 618704160 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 46181225010 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 17503538880 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 15597346500 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 113194744170 # Total energy per rank (pJ)
< system.physmem_0.averagePower 479.569128 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 205028158054 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 920292705 # Time in different power states
< system.physmem_0.memoryStateTime::REF 6672444000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 58173065750 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 45581110454 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 23413245991 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 101274097100 # Time in different power states
< system.physmem_1.actEnergy 1153531260 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 613108815 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1482014100 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 762140880 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 15061753200.000004 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 13366111830 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 607264320 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 42525061470 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 17168834400 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 17794675410 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 110539948695 # Total energy per rank (pJ)
< system.physmem_1.averagePower 468.321620 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 205130134268 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 923619714 # Time in different power states
< system.physmem_1.memoryStateTime::REF 6390116000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 67161872750 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 44710479181 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 23590386018 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 93257782337 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 174591760 # Number of BP lookups
< system.cpu.branchPred.condPredicted 131058406 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 7233420 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 90376052 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 79001018 # Number of BTB hits
---
> system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing
> system.physmem.readRowHits 308090 # Number of row buffer hits during reads
> system.physmem.writeRowHits 82180 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 72.02 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 28.23 # Row buffer hit rate for writes
> system.physmem.avgGap 327134.07 # Average gap between requests
> system.physmem.pageHitRate 54.29 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 1195143180 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 635214690 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1572477900 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 757698660 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 15717574080.000004 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 13455213090 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 610838880 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 46153778370 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 17481507840 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 15586959435 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 113172096165 # Total energy per rank (pJ)
> system.physmem_0.averagePower 479.494648 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 204913310074 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 902504711 # Time in different power states
> system.physmem_0.memoryStateTime::REF 6666906000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 58174043250 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 45524259021 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 23540851965 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 101215123053 # Time in different power states
> system.physmem_1.actEnergy 1151060820 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 611788155 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1482064080 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 761650200 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 15007050240.000004 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 13420176330 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 597461760 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 42655727700 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 16961144160 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 17790500985 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 110444200560 # Total energy per rank (pJ)
> system.physmem_1.averagePower 467.936931 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 205025277615 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 898721445 # Time in different power states
> system.physmem_1.memoryStateTime::REF 6366412000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 67312288506 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 44168958563 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 23733276940 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 93544030546 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 174594111 # Number of BP lookups
> system.cpu.branchPred.condPredicted 131059017 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 7233933 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 90232346 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 78999638 # Number of BTB hits
310,316c313,319
< system.cpu.branchPred.BTBHitPct 87.413664 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 12105632 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 104483 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 4688252 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 4674256 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 13996 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 53921 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 87.551351 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 12106114 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 104453 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 4688512 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 4673325 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 15187 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 53879 # Number of mispredicted indirect branches.
318c321
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
348c351
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
378c381
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
408c411
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
439,440c442,443
< system.cpu.pwrStateResidencyTicks::ON 236034256000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 472068513 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 236023688000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 472047377 # number of cpu cycles simulated
443,456c446,459
< system.cpu.fetch.icacheStallCycles 7651832 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 727514898 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 174591760 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 95780906 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 456008633 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 14520873 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 8018 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 72 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 15159 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 235276766 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 36821 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 470944150 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.672513 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.189889 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 7665841 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 727531021 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 174594111 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 95779077 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 455980909 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 14521279 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 6370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 74 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 14846 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 235277273 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 36996 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 470928679 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.672614 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.189870 # Number of instructions fetched each cycle (Total)
458,461c461,464
< system.cpu.fetch.rateDist::0 101233581 21.50% 21.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 132057346 28.04% 49.54% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 57356975 12.18% 61.72% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 180296248 38.28% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 101212688 21.49% 21.49% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 132055507 28.04% 49.53% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 57355152 12.18% 61.71% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 180305332 38.29% 100.00% # Number of instructions fetched each cycle (Total)
465,492c468,495
< system.cpu.fetch.rateDist::total 470944150 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.369844 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.541121 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 32549558 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 125926098 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 282874913 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 22821432 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 6772149 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 23855969 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 495947 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 710956468 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 29088219 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 6772149 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 63367796 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 61282237 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 40473434 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 273481495 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 25567039 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 682687004 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 12847672 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 10037372 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 2522908 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1816731 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 2323927 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 827475029 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 3000364097 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 718606364 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 112 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 470928679 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.369866 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.541225 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 32549304 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 125870927 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 282926168 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 22809881 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 6772399 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 23857268 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 495900 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 710989368 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 29087460 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 6772399 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 63357486 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 61253040 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 40466365 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 273530421 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 25548968 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 682720764 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 12849971 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 10025216 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 2519363 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1823930 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 2318589 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 827514324 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 3000521547 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 718647704 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
494,511c497,514
< system.cpu.rename.UndoneMaps 173379355 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1545861 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 1536327 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 43857094 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 142358041 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 67520451 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 12908238 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 11335045 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 664745436 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2979378 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 608905066 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 5749480 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 120376659 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 306522000 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1746 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 470944150 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.292945 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.104492 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 173418650 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1545803 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 1536177 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 43812625 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 142363196 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 67528532 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 12884136 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 11268568 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 664776091 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2979332 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 608934070 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 5749195 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 120407268 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 306545068 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1700 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 470928679 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.293049 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.104484 # Number of insts issued each cycle
513,518c516,521
< system.cpu.iq.issued_per_cycle::0 154541552 32.82% 32.82% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 100868277 21.42% 54.23% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 145535828 30.90% 85.14% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 63029448 13.38% 98.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 6968436 1.48% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 609 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 154505965 32.81% 32.81% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 100895056 21.42% 54.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 145511490 30.90% 85.13% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 63049261 13.39% 98.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 6966284 1.48% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 623 0.00% 100.00% # Number of insts issued each cycle
525c528
< system.cpu.iq.issued_per_cycle::total 470944150 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 470928679 # Number of insts issued each cycle
527,560c530,563
< system.cpu.iq.fu_full::IntAlu 71902487 53.13% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 30 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 44305802 32.74% 85.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 19132129 14.14% 100.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 12 0.00% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 71893204 53.11% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 30 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 44308845 32.73% 85.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 19163928 14.16% 100.00% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 14 0.00% 100.00% # attempts to use FU when none available
565,598c568,601
< system.cpu.iq.FU_type_0::IntAlu 412584657 67.76% 67.76% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 352207 0.06% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 133573188 21.94% 89.75% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 62394973 10.25% 100.00% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemRead 22 0.00% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 412595854 67.76% 67.76% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 352107 0.06% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 133581364 21.94% 89.75% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 62404700 10.25% 100.00% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemRead 26 0.00% 100.00% # Type of FU issued
602,610c605,613
< system.cpu.iq.FU_type_0::total 608905066 # Type of FU issued
< system.cpu.iq.rate 1.289866 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 135340482 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.222269 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 1829844132 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 788130713 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 594185364 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 112 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 88 # Number of floating instruction queue writes
---
> system.cpu.iq.FU_type_0::total 608934070 # Type of FU issued
> system.cpu.iq.rate 1.289985 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 135366043 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.222300 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 1829911935 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 788191546 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 594211471 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 100 # Number of floating instruction queue writes
612,614c615,617
< system.cpu.iq.int_alu_accesses 744245476 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 7285563 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.int_alu_accesses 744300035 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 78 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 7286788 # Number of loads that had data forwarded from stores
616,619c619,622
< system.cpu.iew.lsq.thread0.squashedLoads 26474758 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 24641 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 29761 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 10660231 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 26479913 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 24891 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 29414 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 10668312 # Number of stores squashed
622,623c625,626
< system.cpu.iew.lsq.thread0.rescheduledLoads 224867 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 23122 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 225406 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 23080 # Number of times an access to memory failed due to the cache being blocked
625,628c628,631
< system.cpu.iew.iewSquashCycles 6772149 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 23809987 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 977416 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 669217601 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 6772399 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 23806628 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 967662 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 669248404 # Number of instructions dispatched to IQ
630,641c633,644
< system.cpu.iew.iewDispLoadInsts 142358041 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 67520451 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1490836 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 256647 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 583506 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 29761 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 3591077 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3742851 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 7333928 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 598406414 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 129080217 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 10498652 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 142363196 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 67528532 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1490790 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 256473 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 573815 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 29414 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 3591193 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3742987 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 7334180 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 598436406 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 129089013 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 10497664 # Number of squashed instructions skipped in execute
643,654c646,657
< system.cpu.iew.exec_nop 1492787 # number of nop insts executed
< system.cpu.iew.exec_refs 189993781 # number of memory reference insts executed
< system.cpu.iew.exec_branches 131261458 # Number of branches executed
< system.cpu.iew.exec_stores 60913564 # Number of stores executed
< system.cpu.iew.exec_rate 1.267626 # Inst execution rate
< system.cpu.iew.wb_sent 595430710 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 594185380 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 349559163 # num instructions producing a value
< system.cpu.iew.wb_consumers 571371780 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.258685 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.611789 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 107108792 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 1492981 # number of nop insts executed
> system.cpu.iew.exec_refs 190011710 # number of memory reference insts executed
> system.cpu.iew.exec_branches 131264327 # Number of branches executed
> system.cpu.iew.exec_stores 60922697 # Number of stores executed
> system.cpu.iew.exec_rate 1.267746 # Inst execution rate
> system.cpu.iew.wb_sent 595457934 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 594211487 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 349573647 # num instructions producing a value
> system.cpu.iew.wb_consumers 571370339 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.258796 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.611816 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 107140247 # The number of squashed insts skipped by commit
656,659c659,662
< system.cpu.commit.branchMispredicts 6745133 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 454284606 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.207816 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.884395 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 6745693 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 454265599 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.207866 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.884244 # Number of insts commited each cycle
661,669c664,672
< system.cpu.commit.committed_per_cycle::0 225505384 49.64% 49.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 116384460 25.62% 75.26% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 43472433 9.57% 84.83% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 23172184 5.10% 89.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 11521266 2.54% 92.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 7756423 1.71% 94.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 8277792 1.82% 95.99% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 4245082 0.93% 96.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 13949582 3.07% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 225450125 49.63% 49.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 116407668 25.63% 75.26% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 43488632 9.57% 84.83% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 23202465 5.11% 89.94% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 11495162 2.53% 92.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 7755603 1.71% 94.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 8270201 1.82% 95.99% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 4246101 0.93% 96.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 13949642 3.07% 100.00% # Number of insts commited each cycle
673c676
< system.cpu.commit.committed_per_cycle::total 454284606 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 454265599 # Number of insts commited each cycle
723,727c726,730
< system.cpu.commit.bw_lim_events 13949582 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 1096128717 # The number of ROB reads
< system.cpu.rob.rob_writes 1328290478 # The number of ROB writes
< system.cpu.timesIdled 14613 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 1124363 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 13949642 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 1096141105 # The number of ROB reads
> system.cpu.rob.rob_writes 1328357052 # The number of ROB writes
> system.cpu.timesIdled 14656 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 1118698 # Total number of cycles that the CPU has spent unscheduled due to idling
730,735c733,738
< system.cpu.cpi 0.934354 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.934354 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.070258 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.070258 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 610109745 # number of integer regfile reads
< system.cpu.int_regfile_writes 327329948 # number of integer regfile writes
---
> system.cpu.cpi 0.934313 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.934313 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.070306 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.070306 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 610147261 # number of integer regfile reads
> system.cpu.int_regfile_writes 327343686 # number of integer regfile writes
737,739c740,742
< system.cpu.cc_regfile_reads 2166188285 # number of cc regfile reads
< system.cpu.cc_regfile_writes 376531340 # number of cc regfile writes
< system.cpu.misc_regfile_reads 217592371 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 2166295309 # number of cc regfile reads
> system.cpu.cc_regfile_writes 376541599 # number of cc regfile writes
> system.cpu.misc_regfile_reads 217608578 # number of misc regfile reads
741,748c744,751
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 2817297 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.628265 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168862807 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 2817809 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 59.926988 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 504720000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.628265 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 2817163 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.628180 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168869146 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 2817675 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 59.932088 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 504794000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.628180 # Average occupied blocks per requestor
752,753c755,756
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id
756,766c759,769
< system.cpu.dcache.tags.tag_accesses 355255813 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 355255813 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 114160281 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 114160281 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 51722579 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 51722579 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 2790 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 2790 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 355269881 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 355269881 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 114167630 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 114167630 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 51721570 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 51721570 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits
769,778c772,781
< system.cpu.dcache.demand_hits::cpu.data 165882860 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 165882860 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 165885650 # number of overall hits
< system.cpu.dcache.overall_hits::total 165885650 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 4839703 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 4839703 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 2516470 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2516470 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 165889200 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 165889200 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 165891987 # number of overall hits
> system.cpu.dcache.overall_hits::total 165891987 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 4839460 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 4839460 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 2517479 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2517479 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses
781,796c784,799
< system.cpu.dcache.demand_misses::cpu.data 7356173 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 7356173 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 7356185 # number of overall misses
< system.cpu.dcache.overall_misses::total 7356185 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 63969719500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 63969719500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 19897650428 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 19897650428 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1356500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 1356500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 83867369928 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 83867369928 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 83867369928 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 83867369928 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 118999984 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 118999984 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 7356939 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 7356939 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 7356950 # number of overall misses
> system.cpu.dcache.overall_misses::total 7356950 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 63959252000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 63959252000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 19900951428 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 19900951428 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1024000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 1024000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 83860203428 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 83860203428 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 83860203428 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 83860203428 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 119007090 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 119007090 # number of ReadReq accesses(hits+misses)
799,802c802,805
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 2802 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 2802 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2798 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2798 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses)
805,814c808,817
< system.cpu.dcache.demand_accesses::cpu.data 173239033 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 173239033 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 173241835 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 173241835 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040670 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046396 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.046396 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004283 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.004283 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 173246139 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 173246139 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 173248937 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 173248937 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040665 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.040665 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046415 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.046415 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003931 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.003931 # miss rate for SoftPFReq accesses
817,832c820,835
< system.cpu.dcache.demand_miss_rate::cpu.data 0.042463 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.042463 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.042462 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.042462 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13217.695280 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13217.695280 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7906.969059 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 7906.969059 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20553.030303 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20553.030303 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 11400.951273 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 11400.951273 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 11400.932675 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 11400.932675 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 1093581 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.042465 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.042465 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.042465 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.042465 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13216.196022 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13216.196022 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7905.111196 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 7905.111196 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15515.151515 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15515.151515 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 11398.790098 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 11398.790098 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 11398.773055 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 11398.773055 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 1096029 # number of cycles access was blocked
834,842c837,845
< system.cpu.dcache.blocked::no_targets 221181 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.333333 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 4.944281 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 2817297 # number of writebacks
< system.cpu.dcache.writebacks::total 2817297 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541719 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2541719 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996628 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1996628 # number of WriteReq MSHR hits
---
> system.cpu.dcache.blocked::no_targets 221098 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 4.957209 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 2817163 # number of writebacks
> system.cpu.dcache.writebacks::total 2817163 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541567 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 2541567 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1997678 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1997678 # number of WriteReq MSHR hits
845,852c848,855
< system.cpu.dcache.demand_mshr_hits::cpu.data 4538347 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 4538347 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 4538347 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 4538347 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297984 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 2297984 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519842 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 519842 # number of WriteReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 4539245 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 4539245 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 4539245 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 4539245 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297893 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 2297893 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519801 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 519801 # number of WriteReq MSHR misses
855,870c858,873
< system.cpu.dcache.demand_mshr_misses::cpu.data 2817826 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2817826 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2817836 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2817836 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32775846000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 32775846000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786094494 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786094494 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1244000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1244000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37561940494 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 37561940494 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563184494 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 37563184494 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019311 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 2817694 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2817694 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2817704 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2817704 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32776399000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 32776399000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786328496 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786328496 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1261500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1261500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37562727496 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 37562727496 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563988996 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 37563988996 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses
873,898c876,901
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003569 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016266 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016266 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.016265 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14262.869541 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14262.869541 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9206.825332 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9206.825332 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 124400 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 124400 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13330.113532 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 13330.113532 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13330.507700 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 13330.507700 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 76619 # number of replacements
< system.cpu.icache.tags.tagsinuse 466.071602 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 235190778 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 77131 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 3049.238024 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 116612189500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 466.071602 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.910296 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.910296 # Average percentage of cache occupancy
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003574 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003574 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14263.675028 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14263.675028 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9208.001708 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9208.001708 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 126150 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 126150 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13331.017313 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 13331.017313 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13331.417706 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 13331.417706 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 76621 # number of replacements
> system.cpu.icache.tags.tagsinuse 466.068009 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 235191085 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 77133 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 3049.162939 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 116620130500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 466.068009 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.910289 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.910289 # Average percentage of cache occupancy
900,901c903,904
< system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
906,970c909,973
< system.cpu.icache.tags.tag_accesses 470630395 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 470630395 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 235190778 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 235190778 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 235190778 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 235190778 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 235190778 # number of overall hits
< system.cpu.icache.overall_hits::total 235190778 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 85841 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 85841 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 85841 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 85841 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 85841 # number of overall misses
< system.cpu.icache.overall_misses::total 85841 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 1941915678 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 1941915678 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 1941915678 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 1941915678 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 1941915678 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 1941915678 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 235276619 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 235276619 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 235276619 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 235276619 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 235276619 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 235276619 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000365 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000365 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000365 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000365 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000365 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000365 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22622.239699 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 22622.239699 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 22622.239699 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 22622.239699 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 206659 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 2170 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 7236 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 28.559840 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 197.272727 # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 76619 # number of writebacks
< system.cpu.icache.writebacks::total 76619 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8683 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 8683 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 8683 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 8683 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 8683 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 8683 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77158 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 77158 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 77158 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 77158 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 77158 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 77158 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1536678279 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 1536678279 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1536678279 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 1536678279 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1536678279 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 1536678279 # number of overall MSHR miss cycles
---
> system.cpu.icache.tags.tag_accesses 470631453 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 470631453 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 235191085 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 235191085 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 235191085 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 235191085 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 235191085 # number of overall hits
> system.cpu.icache.overall_hits::total 235191085 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 86061 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 86061 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 86061 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 86061 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 86061 # number of overall misses
> system.cpu.icache.overall_misses::total 86061 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 1945774184 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 1945774184 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 1945774184 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 1945774184 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 1945774184 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 1945774184 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 235277146 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 235277146 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 235277146 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 235277146 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 235277146 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 235277146 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22609.244420 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 22609.244420 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 22609.244420 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 22609.244420 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 22609.244420 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 22609.244420 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 200857 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 1531 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 7099 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 28.293703 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 191.375000 # average number of cycles each access was blocked
> system.cpu.icache.writebacks::writebacks 76621 # number of writebacks
> system.cpu.icache.writebacks::total 76621 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8898 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 8898 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 8898 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 8898 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 8898 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 8898 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77163 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 77163 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 77163 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 77163 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 77163 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 77163 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1533201777 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 1533201777 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1533201777 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 1533201777 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1533201777 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 1533201777 # number of overall MSHR miss cycles
977,986c980,989
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19915.994181 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19915.994181 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19915.994181 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 19915.994181 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19915.994181 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 19915.994181 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 8510000 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 8511429 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 428 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19869.649664 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19869.649664 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 8513489 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 8514918 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 429 # number of redundant prefetches already in prefetch queue
989,995c992,998
< system.cpu.l2cache.prefetcher.pfSpanPage 743291 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 389594 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 15007.037789 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2698812 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 405195 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.660526 # Average number of references to valid blocks.
---
> system.cpu.l2cache.prefetcher.pfSpanPage 744218 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 389920 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 15006.987953 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2697445 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 405523 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.651768 # Average number of references to valid blocks.
997,1079c1000,1083
< system.cpu.l2cache.tags.occ_blocks::writebacks 14932.547255 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.490534 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.911410 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004547 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.915957 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 98 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15503 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 41 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 672 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5433 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6587 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2565 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.005981 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946228 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 95366335 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 95366335 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 2351800 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 2351800 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 518252 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 518252 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 516857 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 516857 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67161 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 67161 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130903 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 2130903 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 67161 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 2647760 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2714921 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 67161 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 2647760 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2714921 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 27 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 5168 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 5168 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9964 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 9964 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164881 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 164881 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 9964 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 170049 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 180013 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 9964 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 170049 # number of overall misses
< system.cpu.l2cache.overall_misses::total 180013 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 20500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 20500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 668599000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 668599000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1018287500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1018287500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15371092500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 15371092500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1018287500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 16039691500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 17057979000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1018287500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 16039691500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 17057979000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 2351800 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 2351800 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 518252 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 518252 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 27 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 522025 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 522025 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77125 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 77125 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295784 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 2295784 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 77125 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 2817809 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2894934 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 77125 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 2817809 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2894934 # number of overall (read+write) accesses
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 14934.817227 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 72.170726 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.911549 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004405 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.915954 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 103 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15500 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 49 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 35 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 665 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5454 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6553 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2579 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006287 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946045 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 95362177 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 95362177 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 2356317 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 2356317 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 513605 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 513605 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 516771 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 516771 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67113 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 67113 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130678 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 2130678 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 67113 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 2647449 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2714562 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 67113 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 2647449 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2714562 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 29 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 29 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 5213 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 5213 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10017 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 10017 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 165013 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 165013 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 10017 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 170226 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 180243 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 10017 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 170226 # number of overall misses
> system.cpu.l2cache.overall_misses::total 180243 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 21500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 669742000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 669742000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1015207000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 1015207000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15371129000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 15371129000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1015207000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 16040871000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 17056078000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1015207000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 16040871000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 17056078000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 2356317 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 2356317 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 513605 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 513605 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 29 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 29 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 521984 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 521984 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77130 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 77130 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295691 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 2295691 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 77130 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 2817675 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2894805 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 77130 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 2817675 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2894805 # number of overall (read+write) accesses
1082,1107c1086,1111
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009900 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.009900 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.129193 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.129193 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071819 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071819 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.129193 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.060348 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.062182 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.129193 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.060348 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.062182 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 759.259259 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 759.259259 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129372.871517 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129372.871517 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102196.657969 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102196.657969 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93225.371632 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93225.371632 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102196.657969 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94323.938982 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 94759.706243 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102196.657969 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94323.938982 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 94759.706243 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009987 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.009987 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.129872 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.129872 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071879 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071879 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.129872 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.060414 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.062264 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.129872 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.060414 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.062264 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 741.379310 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 741.379310 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128475.350086 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128475.350086 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101348.407707 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101348.407707 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93151.018405 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93151.018405 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101348.407707 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94232.790526 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 94628.240764 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101348.407707 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94232.790526 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 94628.240764 # average overall miss latency
1114,1162c1118,1166
< system.cpu.l2cache.unused_prefetches 2063 # number of HardPF blocks evicted w/o reference
< system.cpu.l2cache.writebacks::writebacks 291274 # number of writebacks
< system.cpu.l2cache.writebacks::total 291274 # number of writebacks
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1581 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 1581 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 8 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4441 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4441 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 6022 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 6030 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 6022 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 6030 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 355324 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 355324 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3587 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 3587 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9956 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9956 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160440 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160440 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 9956 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 164027 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 173983 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 9956 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 164027 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 355324 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 529307 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21295211595 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21295211595 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 417500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 417500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 461178500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 461178500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 956729500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 956729500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14002333000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14002333000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 956729500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14463511500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 15420241000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 956729500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14463511500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21295211595 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 36715452595 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.unused_prefetches 2009 # number of HardPF blocks evicted w/o reference
> system.cpu.l2cache.writebacks::writebacks 291097 # number of writebacks
> system.cpu.l2cache.writebacks::total 291097 # number of writebacks
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1528 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 1528 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4483 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4483 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 6011 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 6015 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 6011 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 6015 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 355832 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 355832 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 29 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3685 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 3685 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10013 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10013 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160530 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160530 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 10013 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 164215 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 174228 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 10013 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 164215 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 355832 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 530060 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21330424894 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21330424894 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 451500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 451500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 469308000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 469308000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 954360500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 954360500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13996060500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13996060500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 954360500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14465368500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 15419729000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 954360500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14465368500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21330424894 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 36750153894 # number of overall MSHR miss cycles
1167,1177c1171,1181
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006871 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006871 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129089 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069885 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069885 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.060099 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007060 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007060 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129820 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069927 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069927 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.060186 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for overall accesses
1179,1208c1183,1212
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.182839 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59931.813204 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15462.962963 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15462.962963 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128569.417340 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128569.417340 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96095.771394 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96095.771394 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87274.576166 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87274.576166 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88630.734037 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69365.137047 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 5788910 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893955 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23897 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 99240 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99239 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 2372941 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 2643074 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 542116 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 98320 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 402261 # Transaction distribution
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.183107 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59945.212612 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15568.965517 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15568.965517 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 127356.309362 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 127356.309362 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95312.144213 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95312.144213 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87186.572603 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87186.572603 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88503.162523 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69332.064095 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 5788651 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893810 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 99788 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99240 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 548 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 2372852 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 2647414 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 537467 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 98823 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 402669 # Transaction distribution
1210,1226c1214,1230
< system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 522025 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 522025 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 77158 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295784 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230901 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452970 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8683871 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839552 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360646848 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 370486400 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 791889 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 18643712 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 3686849 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.033410 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.179705 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 29 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 521984 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 521984 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 77163 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295691 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230912 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452572 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8683484 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839936 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360629696 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 370469632 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 792623 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 18632384 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 3687456 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.034433 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.183151 # Request fanout histogram
1228,1230c1232,1234
< system.cpu.toL2Bus.snoop_fanout::0 3563674 96.66% 96.66% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 123174 3.34% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 3561035 96.57% 96.57% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 125873 3.41% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 548 0.01% 100.00% # Request fanout histogram
1234,1235c1238,1239
< system.cpu.toL2Bus.snoop_fanout::total 3686849 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 5788371005 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3687456 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 5788109505 # Layer occupancy (ticks)
1239c1243
< system.cpu.toL2Bus.respLayer0.occupancy 115765939 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 115773436 # Layer occupancy (ticks)
1241c1245
< system.cpu.toL2Bus.respLayer1.occupancy 4226743467 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 4226542968 # Layer occupancy (ticks)
1243,1244c1247,1248
< system.membus.snoop_filter.tot_requests 819690 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 413483 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.membus.snoop_filter.tot_requests 820344 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 413808 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1249,1252c1253,1256
< system.membus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 426481 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 291274 # Transaction distribution
< system.membus.trans_dist::CleanEvict 98320 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 426709 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 291097 # Transaction distribution
> system.membus.trans_dist::CleanEvict 98823 # Transaction distribution
1254,1260c1258,1264
< system.membus.trans_dist::ReadExReq 3582 # Transaction distribution
< system.membus.trans_dist::ReadExResp 3582 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 426482 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1249753 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1249753 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46165568 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 46165568 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadExReq 3682 # Transaction distribution
> system.membus.trans_dist::ReadExResp 3682 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 426710 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1250735 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1250735 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46175232 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 46175232 # Cumulative packet size per connected master and slave (bytes)
1263c1267
< system.membus.snoop_fanout::samples 430096 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 430424 # Request fanout histogram
1267c1271
< system.membus.snoop_fanout::0 430096 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 430424 100.00% 100.00% # Request fanout histogram
1272,1273c1276,1277
< system.membus.snoop_fanout::total 430096 # Request fanout histogram
< system.membus.reqLayer0.occupancy 2210866206 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 430424 # Request fanout histogram
> system.membus.reqLayer0.occupancy 2210945378 # Layer occupancy (ticks)
1275c1279
< system.membus.respLayer1.occupancy 2276438586 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2277916539 # Layer occupancy (ticks)