3,5c3,5
< sim_seconds 0.233363 # Number of seconds simulated
< sim_ticks 233363457000 # Number of ticks simulated
< final_tick 233363457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.236034 # Number of seconds simulated
> sim_ticks 236034256000 # Number of ticks simulated
> final_tick 236034256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 153279 # Simulator instruction rate (inst/s)
< host_op_rate 166055 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 70798116 # Simulator tick rate (ticks/s)
< host_mem_usage 302508 # Number of bytes of host memory used
< host_seconds 3296.18 # Real time elapsed on the host
---
> host_inst_rate 147811 # Simulator instruction rate (inst/s)
> host_op_rate 160132 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 69053974 # Simulator tick rate (ticks/s)
> host_mem_usage 301356 # Number of bytes of host memory used
> host_seconds 3418.11 # Real time elapsed on the host
16,54c16,54
< system.physmem.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 641792 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10513600 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 16409344 # Number of bytes read from this memory
< system.physmem.bytes_read::total 27564736 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 641792 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 641792 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 18651328 # Number of bytes written to this memory
< system.physmem.bytes_written::total 18651328 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 10028 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 164275 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 256396 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 430699 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 291427 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 291427 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 2750182 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 45052469 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 70316682 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 118119333 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 2750182 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 2750182 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 79923945 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 79923945 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 79923945 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 2750182 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 45052469 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 70316682 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 198043278 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 430699 # Number of read requests accepted
< system.physmem.writeReqs 291427 # Number of write requests accepted
< system.physmem.readBursts 430699 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 291427 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 27407296 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 157440 # Total number of bytes read from write queue
< system.physmem.bytesWritten 18649728 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 27564736 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 18651328 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 2460 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 637184 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10497472 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 16389440 # Number of bytes read from this memory
> system.physmem.bytes_read::total 27524096 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 637184 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 637184 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 18641536 # Number of bytes written to this memory
> system.physmem.bytes_written::total 18641536 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 9956 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 164023 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 256085 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 430064 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 291274 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 291274 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 2699540 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 44474358 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 69436701 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 116610599 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 2699540 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 2699540 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 78978095 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 78978095 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 78978095 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2699540 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 44474358 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 69436701 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 195588695 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 430064 # Number of read requests accepted
> system.physmem.writeReqs 291274 # Number of write requests accepted
> system.physmem.readBursts 430064 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 291274 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 27360896 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 163200 # Total number of bytes read from write queue
> system.physmem.bytesWritten 18638848 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 27524096 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 18641536 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 2550 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one
56,87c56,87
< system.physmem.perBankRdBursts::0 27205 # Per bank write bursts
< system.physmem.perBankRdBursts::1 26463 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25602 # Per bank write bursts
< system.physmem.perBankRdBursts::3 32969 # Per bank write bursts
< system.physmem.perBankRdBursts::4 28037 # Per bank write bursts
< system.physmem.perBankRdBursts::5 29890 # Per bank write bursts
< system.physmem.perBankRdBursts::6 25340 # Per bank write bursts
< system.physmem.perBankRdBursts::7 24398 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25649 # Per bank write bursts
< system.physmem.perBankRdBursts::9 25581 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25884 # Per bank write bursts
< system.physmem.perBankRdBursts::11 26303 # Per bank write bursts
< system.physmem.perBankRdBursts::12 27555 # Per bank write bursts
< system.physmem.perBankRdBursts::13 26148 # Per bank write bursts
< system.physmem.perBankRdBursts::14 24908 # Per bank write bursts
< system.physmem.perBankRdBursts::15 26307 # Per bank write bursts
< system.physmem.perBankWrBursts::0 18644 # Per bank write bursts
< system.physmem.perBankWrBursts::1 18139 # Per bank write bursts
< system.physmem.perBankWrBursts::2 17950 # Per bank write bursts
< system.physmem.perBankWrBursts::3 17944 # Per bank write bursts
< system.physmem.perBankWrBursts::4 18581 # Per bank write bursts
< system.physmem.perBankWrBursts::5 18235 # Per bank write bursts
< system.physmem.perBankWrBursts::6 17841 # Per bank write bursts
< system.physmem.perBankWrBursts::7 17708 # Per bank write bursts
< system.physmem.perBankWrBursts::8 18005 # Per bank write bursts
< system.physmem.perBankWrBursts::9 17734 # Per bank write bursts
< system.physmem.perBankWrBursts::10 18244 # Per bank write bursts
< system.physmem.perBankWrBursts::11 18783 # Per bank write bursts
< system.physmem.perBankWrBursts::12 18680 # Per bank write bursts
< system.physmem.perBankWrBursts::13 18156 # Per bank write bursts
< system.physmem.perBankWrBursts::14 18369 # Per bank write bursts
< system.physmem.perBankWrBursts::15 18389 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 27217 # Per bank write bursts
> system.physmem.perBankRdBursts::1 26580 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25459 # Per bank write bursts
> system.physmem.perBankRdBursts::3 32933 # Per bank write bursts
> system.physmem.perBankRdBursts::4 28005 # Per bank write bursts
> system.physmem.perBankRdBursts::5 30095 # Per bank write bursts
> system.physmem.perBankRdBursts::6 25324 # Per bank write bursts
> system.physmem.perBankRdBursts::7 24336 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25637 # Per bank write bursts
> system.physmem.perBankRdBursts::9 25661 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25768 # Per bank write bursts
> system.physmem.perBankRdBursts::11 26242 # Per bank write bursts
> system.physmem.perBankRdBursts::12 27581 # Per bank write bursts
> system.physmem.perBankRdBursts::13 26014 # Per bank write bursts
> system.physmem.perBankRdBursts::14 24864 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25798 # Per bank write bursts
> system.physmem.perBankWrBursts::0 18651 # Per bank write bursts
> system.physmem.perBankWrBursts::1 18268 # Per bank write bursts
> system.physmem.perBankWrBursts::2 17926 # Per bank write bursts
> system.physmem.perBankWrBursts::3 17983 # Per bank write bursts
> system.physmem.perBankWrBursts::4 18558 # Per bank write bursts
> system.physmem.perBankWrBursts::5 18375 # Per bank write bursts
> system.physmem.perBankWrBursts::6 17786 # Per bank write bursts
> system.physmem.perBankWrBursts::7 17681 # Per bank write bursts
> system.physmem.perBankWrBursts::8 18027 # Per bank write bursts
> system.physmem.perBankWrBursts::9 17737 # Per bank write bursts
> system.physmem.perBankWrBursts::10 18114 # Per bank write bursts
> system.physmem.perBankWrBursts::11 18781 # Per bank write bursts
> system.physmem.perBankWrBursts::12 18716 # Per bank write bursts
> system.physmem.perBankWrBursts::13 18163 # Per bank write bursts
> system.physmem.perBankWrBursts::14 18303 # Per bank write bursts
> system.physmem.perBankWrBursts::15 18163 # Per bank write bursts
90c90
< system.physmem.totGap 233363404500 # Total gap between requests
---
> system.physmem.totGap 236034203500 # Total gap between requests
97c97
< system.physmem.readPktSize::6 430699 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 430064 # Read request sizes (log2)
104,118c104,118
< system.physmem.writePktSize::6 291427 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 330391 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 50226 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 12856 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 8880 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 7122 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 6027 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 5118 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 4235 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3274 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 16 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 9 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 291274 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 318869 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 60281 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 13267 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 8983 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 7229 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 6032 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 5148 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 4295 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3299 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 63 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 23 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see
152,171c152,171
< system.physmem.wrQLenPdf::15 7280 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 7756 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 12492 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 15016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 16255 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 16901 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 17254 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 17654 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 17875 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 18074 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 18193 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 18541 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 18646 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 18700 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 18837 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 17505 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 17142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 17030 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 51 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 6756 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 7242 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 12113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 14851 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 16256 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 16916 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 17294 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 17615 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 17892 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 18128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 18323 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 18440 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 18551 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 18644 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 18821 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 18548 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 17432 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 17189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see
173,186c173,186
< system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
201,218c201,218
< system.physmem.bytesPerActivate::samples 328347 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 140.266048 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 98.833830 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 178.808988 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 208753 63.58% 63.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 80037 24.38% 87.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 14980 4.56% 92.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7256 2.21% 94.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4857 1.48% 96.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2521 0.77% 96.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1858 0.57% 97.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1524 0.46% 98.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 6561 2.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 328347 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 16970 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 25.230642 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 145.328941 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 16968 99.99% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 329061 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 139.787432 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 98.478985 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 178.644390 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 210353 63.93% 63.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 79320 24.10% 88.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 14852 4.51% 92.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7229 2.20% 94.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4899 1.49% 96.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2483 0.75% 96.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1823 0.55% 97.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1564 0.48% 98.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 6538 1.99% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 329061 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 17032 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 25.095820 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 145.258821 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 17030 99.99% 99.99% # Reads before turning the bus around for writes
221,249c221,246
< system.physmem.rdPerTurnAround::total 16970 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 16970 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.171597 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.099419 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.840930 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-17 9436 55.60% 55.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18-19 6694 39.45% 95.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-21 588 3.46% 98.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22-23 150 0.88% 99.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-25 55 0.32% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26-27 20 0.12% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-29 4 0.02% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::30-31 8 0.05% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-33 2 0.01% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::34-35 4 0.02% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-45 1 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-49 1 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::62-63 1 0.01% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-73 1 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-77 1 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::94-95 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 16970 # Writes before turning the bus around for reads
< system.physmem.totQLat 8687632010 # Total ticks spent queuing
< system.physmem.totMemAccLat 16717113260 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2141195000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 20286.88 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 17032 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 17032 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.099108 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.028520 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.818567 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-17 10039 58.94% 58.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18-19 6203 36.42% 95.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-21 545 3.20% 98.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22-23 139 0.82% 99.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-25 59 0.35% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26-27 18 0.11% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-29 9 0.05% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::30-31 2 0.01% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-33 2 0.01% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::34-35 2 0.01% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-37 3 0.02% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::38-39 5 0.03% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-41 2 0.01% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-61 2 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::70-71 1 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-105 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 17032 # Writes before turning the bus around for reads
> system.physmem.totQLat 14213030846 # Total ticks spent queuing
> system.physmem.totMemAccLat 22228918346 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2137570000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 33245.77 # Average queueing delay per DRAM burst
251,255c248,252
< system.physmem.avgMemAccLat 39036.88 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 117.44 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 79.92 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 118.12 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 79.92 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 51995.77 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 115.92 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 78.97 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 116.61 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 78.98 # Average system write bandwidth in MiByte/s
257,258c254,255
< system.physmem.busUtil 1.54 # Data bus utilization in percentage
< system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 1.52 # Data bus utilization in percentage
> system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads
261,301c258,308
< system.physmem.avgWrQLen 21.52 # Average write queue length when enqueuing
< system.physmem.readRowHits 308039 # Number of row buffer hits during reads
< system.physmem.writeRowHits 83248 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 71.93 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 28.57 # Row buffer hit rate for writes
< system.physmem.avgGap 323161.62 # Average gap between requests
< system.physmem.pageHitRate 54.37 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 1261242360 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 688177875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1715142000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 939872160 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 86511761685 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 64129665000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 170487912840 # Total energy per rank (pJ)
< system.physmem_0.averagePower 730.572857 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 106127593352 # Time in different power states
< system.physmem_0.memoryStateTime::REF 7792460000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 119441919148 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 1221045840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 666245250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1624857000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 948412800 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 81485025165 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 68539083000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 169726720815 # Total energy per rank (pJ)
< system.physmem_1.averagePower 727.311005 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 113492657633 # Time in different power states
< system.physmem_1.memoryStateTime::REF 7792460000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 112077139867 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 174594135 # Number of BP lookups
< system.cpu.branchPred.condPredicted 131061438 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 7233022 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 90315091 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 79002409 # Number of BTB hits
---
> system.physmem.avgWrQLen 21.65 # Average write queue length when enqueuing
> system.physmem.readRowHits 307655 # Number of row buffer hits during reads
> system.physmem.writeRowHits 82023 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 71.96 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 28.16 # Row buffer hit rate for writes
> system.physmem.avgGap 327217.20 # Average gap between requests
> system.physmem.pageHitRate 54.21 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 1196014260 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 635677680 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1570435860 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 758090160 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 15730481520.000004 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 13398551100 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 618704160 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 46181225010 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 17503538880 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 15597346500 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 113194744170 # Total energy per rank (pJ)
> system.physmem_0.averagePower 479.569128 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 205028158054 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 920292705 # Time in different power states
> system.physmem_0.memoryStateTime::REF 6672444000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 58173065750 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 45581110454 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 23413245991 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 101274097100 # Time in different power states
> system.physmem_1.actEnergy 1153531260 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 613108815 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1482014100 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 762140880 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 15061753200.000004 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 13366111830 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 607264320 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 42525061470 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 17168834400 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 17794675410 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 110539948695 # Total energy per rank (pJ)
> system.physmem_1.averagePower 468.321620 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 205130134268 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 923619714 # Time in different power states
> system.physmem_1.memoryStateTime::REF 6390116000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 67161872750 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 44710479181 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 23590386018 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 93257782337 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 174591760 # Number of BP lookups
> system.cpu.branchPred.condPredicted 131058406 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 7233420 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 90376052 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 79001018 # Number of BTB hits
303,309c310,316
< system.cpu.branchPred.BTBHitPct 87.474206 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 12105110 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 104499 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 4687937 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 4674274 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 13663 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 53871 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 87.413664 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 12105632 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 104483 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 4688252 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 4674256 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 13996 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 53921 # Number of mispredicted indirect branches.
311c318
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
341c348
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
371c378
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
401c408
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
432,433c439,440
< system.cpu.pwrStateResidencyTicks::ON 233363457000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 466726915 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 236034256000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 472068513 # number of cpu cycles simulated
436,449c443,456
< system.cpu.fetch.icacheStallCycles 7649319 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 727510991 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 174594135 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 95781793 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 451018276 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 14520177 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 5415 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 13360 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 235275678 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 36827 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 465946604 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.690437 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.183518 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 7651832 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 727514898 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 174591760 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 95780906 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 456008633 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 14520873 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 8018 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 72 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 15159 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 235276766 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 36821 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 470944150 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.672513 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.189889 # Number of instructions fetched each cycle (Total)
451,454c458,461
< system.cpu.fetch.rateDist::0 96241342 20.66% 20.66% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 132050994 28.34% 49.00% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 57360477 12.31% 61.31% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 180293791 38.69% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 101233581 21.50% 21.50% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 132057346 28.04% 49.54% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 57356975 12.18% 61.72% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 180296248 38.28% 100.00% # Number of instructions fetched each cycle (Total)
458,485c465,492
< system.cpu.fetch.rateDist::total 465946604 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.374082 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.558751 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 32536552 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 120918293 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 282902203 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 22817634 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 6771922 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 23855471 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 495849 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 710960604 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 29091371 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 6771922 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 63349282 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 56784032 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 40401553 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 273510163 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 25129652 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 682692967 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 12844145 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 9945202 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 2511648 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1805093 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 1905777 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 827472920 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 3000392013 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 718609980 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 470944150 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.369844 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.541121 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 32549558 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 125926098 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 282874913 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 22821432 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 6772149 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 23855969 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 495947 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 710956468 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 29088219 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 6772149 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 63367796 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 61282237 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 40473434 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 273481495 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 25567039 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 682687004 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 12847672 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 10037372 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 2522908 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1816731 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 2323927 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 827475029 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 3000364097 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 718606364 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 112 # Number of floating rename lookups
487,504c494,511
< system.cpu.rename.UndoneMaps 173377246 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1545812 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 1536134 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 43839802 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 142358029 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 67522859 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 12902461 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 11335768 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 664750936 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2979334 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 608926553 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 5748894 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 120382115 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 306467952 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1702 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 465946604 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.306859 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.102130 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 173379355 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1545861 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 1536327 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 43857094 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 142358041 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 67520451 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 12908238 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 11335045 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 664745436 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2979378 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 608905066 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 5749480 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 120376659 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 306522000 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1746 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 470944150 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.292945 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.104492 # Number of insts issued each cycle
506,511c513,518
< system.cpu.iq.issued_per_cycle::0 149520607 32.09% 32.09% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 100880237 21.65% 53.74% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 145552540 31.24% 84.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 63032249 13.53% 98.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 6960366 1.49% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 605 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 154541552 32.82% 32.82% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 100868277 21.42% 54.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 145535828 30.90% 85.14% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 63029448 13.38% 98.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 6968436 1.48% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 609 0.00% 100.00% # Number of insts issued each cycle
518c525
< system.cpu.iq.issued_per_cycle::total 465946604 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 470944150 # Number of insts issued each cycle
520,550c527,557
< system.cpu.iq.fu_full::IntAlu 71896734 53.12% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 30 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.12% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 44291867 32.73% 85.85% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 19147796 14.15% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 71902487 53.13% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 30 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 44305814 32.74% 85.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 19132145 14.14% 100.00% # attempts to use FU when none available
554,584c561,591
< system.cpu.iq.FU_type_0::IntAlu 412590919 67.76% 67.76% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 352109 0.06% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 133574983 21.94% 89.75% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 62408539 10.25% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 412584657 67.76% 67.76% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 352207 0.06% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 133573210 21.94% 89.75% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 62394989 10.25% 100.00% # Type of FU issued
587,595c594,602
< system.cpu.iq.FU_type_0::total 608926553 # Type of FU issued
< system.cpu.iq.rate 1.304674 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 135336427 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.222254 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 1824884935 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 788141663 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 594200588 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 96 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes
---
> system.cpu.iq.FU_type_0::total 608905066 # Type of FU issued
> system.cpu.iq.rate 1.289866 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 135340476 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.222269 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 1829844132 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 788130713 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 594185364 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 106 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 88 # Number of floating instruction queue writes
597,599c604,606
< system.cpu.iq.int_alu_accesses 744262920 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 7284479 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.int_alu_accesses 744245476 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 66 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 7285563 # Number of loads that had data forwarded from stores
601,604c608,611
< system.cpu.iew.lsq.thread0.squashedLoads 26474746 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 24624 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 29798 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 10662639 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 26474758 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 24641 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 29761 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 10660231 # Number of stores squashed
607,608c614,615
< system.cpu.iew.lsq.thread0.rescheduledLoads 225013 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 22508 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 224867 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 23122 # Number of times an access to memory failed due to the cache being blocked
610,613c617,620
< system.cpu.iew.iewSquashCycles 6771922 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 22843049 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 918168 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 669223084 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 6772149 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 23809987 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 977416 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 669217601 # Number of instructions dispatched to IQ
615,626c622,633
< system.cpu.iew.iewDispLoadInsts 142358029 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 67522859 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1490792 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 256633 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 523882 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 29798 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 3590923 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3742651 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 7333574 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 598420503 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 129081054 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 10506050 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 142358041 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 67520451 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1490836 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 256647 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 583506 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 29761 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 3591077 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3742851 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 7333928 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 598406414 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 129080217 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 10498652 # Number of squashed instructions skipped in execute
628,639c635,646
< system.cpu.iew.exec_nop 1492814 # number of nop insts executed
< system.cpu.iew.exec_refs 190002009 # number of memory reference insts executed
< system.cpu.iew.exec_branches 131263961 # Number of branches executed
< system.cpu.iew.exec_stores 60920955 # Number of stores executed
< system.cpu.iew.exec_rate 1.282164 # Inst execution rate
< system.cpu.iew.wb_sent 595445456 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 594200604 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 349565575 # num instructions producing a value
< system.cpu.iew.wb_consumers 571385188 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.273123 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.611786 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 107116116 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 1492787 # number of nop insts executed
> system.cpu.iew.exec_refs 189993781 # number of memory reference insts executed
> system.cpu.iew.exec_branches 131261458 # Number of branches executed
> system.cpu.iew.exec_stores 60913564 # Number of stores executed
> system.cpu.iew.exec_rate 1.267626 # Inst execution rate
> system.cpu.iew.wb_sent 595430710 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 594185380 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 349559163 # num instructions producing a value
> system.cpu.iew.wb_consumers 571371780 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.258685 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.611789 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 107108792 # The number of squashed insts skipped by commit
641,644c648,651
< system.cpu.commit.branchMispredicts 6744856 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 449285999 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.221253 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.890713 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 6745133 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 454284606 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.207816 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.884395 # Number of insts commited each cycle
646,654c653,661
< system.cpu.commit.committed_per_cycle::0 220514428 49.08% 49.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 116376748 25.90% 74.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 43480691 9.68% 84.66% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 23177999 5.16% 89.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 11514242 2.56% 92.38% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 7755129 1.73% 94.11% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 8259802 1.84% 95.95% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 4227193 0.94% 96.89% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 13979767 3.11% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 225505384 49.64% 49.64% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 116384460 25.62% 75.26% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 43472433 9.57% 84.83% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 23172184 5.10% 89.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 11521266 2.54% 92.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 7756423 1.71% 94.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 8277792 1.82% 95.99% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 4245082 0.93% 96.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 13949582 3.07% 100.00% # Number of insts commited each cycle
658c665
< system.cpu.commit.committed_per_cycle::total 449285999 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 454284606 # Number of insts commited each cycle
704,708c711,715
< system.cpu.commit.bw_lim_events 13979767 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 1091107249 # The number of ROB reads
< system.cpu.rob.rob_writes 1328306301 # The number of ROB writes
< system.cpu.timesIdled 14326 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 780311 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 13949582 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 1096128717 # The number of ROB reads
> system.cpu.rob.rob_writes 1328290478 # The number of ROB writes
> system.cpu.timesIdled 14613 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 1124363 # Total number of cycles that the CPU has spent unscheduled due to idling
711,716c718,723
< system.cpu.cpi 0.923782 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.923782 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.082507 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.082507 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 610129735 # number of integer regfile reads
< system.cpu.int_regfile_writes 327331512 # number of integer regfile writes
---
> system.cpu.cpi 0.934354 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.934354 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.070258 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.070258 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 610109745 # number of integer regfile reads
> system.cpu.int_regfile_writes 327329948 # number of integer regfile writes
718,720c725,727
< system.cpu.cc_regfile_reads 2166233884 # number of cc regfile reads
< system.cpu.cc_regfile_writes 376536291 # number of cc regfile writes
< system.cpu.misc_regfile_reads 217601523 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 2166188285 # number of cc regfile reads
> system.cpu.cc_regfile_writes 376531340 # number of cc regfile writes
> system.cpu.misc_regfile_reads 217592371 # number of misc regfile reads
722,729c729,736
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 2817306 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.628303 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 168866082 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 2817818 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 59.927959 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 501259000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.628303 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 2817297 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.628265 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 168862807 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 2817809 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 59.926988 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 504720000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.628265 # Average occupied blocks per requestor
733,734c740,741
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id
737,745c744,752
< system.cpu.dcache.tags.tag_accesses 355259202 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 355259202 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 114162091 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 114162091 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 51724043 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 51724043 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 2789 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 2789 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 355255813 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 355255813 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 114160281 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 114160281 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 51722579 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 51722579 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 2790 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 2790 # number of SoftPFReq hits
750,759c757,766
< system.cpu.dcache.demand_hits::cpu.data 165886134 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 165886134 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 165888923 # number of overall hits
< system.cpu.dcache.overall_hits::total 165888923 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 4839586 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 4839586 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 2515006 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2515006 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 165882860 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 165882860 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 165885650 # number of overall hits
> system.cpu.dcache.overall_hits::total 165885650 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 4839703 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 4839703 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 2516470 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2516470 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses
762,777c769,784
< system.cpu.dcache.demand_misses::cpu.data 7354592 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 7354592 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 7354602 # number of overall misses
< system.cpu.dcache.overall_misses::total 7354602 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 58596122500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 58596122500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 18922626430 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 18922626430 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1155000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 1155000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 77518748930 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 77518748930 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 77518748930 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 77518748930 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 119001677 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 119001677 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 7356173 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 7356173 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 7356185 # number of overall misses
> system.cpu.dcache.overall_misses::total 7356185 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 63969719500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 63969719500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 19897650428 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 19897650428 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1356500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 1356500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 83867369928 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 83867369928 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 83867369928 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 83867369928 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 118999984 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 118999984 # number of ReadReq accesses(hits+misses)
780,781c787,788
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2802 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2802 # number of SoftPFReq accesses(hits+misses)
786,795c793,802
< system.cpu.dcache.demand_accesses::cpu.data 173240726 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 173240726 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 173243525 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 173243525 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040668 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.040668 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046369 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.046369 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003573 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.003573 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 173239033 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 173239033 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 173241835 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 173241835 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040670 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046396 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.046396 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004283 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.004283 # miss rate for SoftPFReq accesses
798,823c805,830
< system.cpu.dcache.demand_miss_rate::cpu.data 0.042453 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.042453 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.042452 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.042452 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12107.672536 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 12107.672536 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7523.889180 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 7523.889180 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17500 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17500 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 10540.183457 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 10540.183457 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 10540.169125 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 10540.169125 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 907373 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 221320 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 4.099824 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 2817306 # number of writebacks
< system.cpu.dcache.writebacks::total 2817306 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541564 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2541564 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995189 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1995189 # number of WriteReq MSHR hits
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.042463 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.042463 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.042462 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.042462 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13217.695280 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13217.695280 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7906.969059 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 7906.969059 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20553.030303 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20553.030303 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 11400.951273 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 11400.951273 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 11400.932675 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 11400.932675 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 1093581 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 221181 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.333333 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 4.944281 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 2817297 # number of writebacks
> system.cpu.dcache.writebacks::total 2817297 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541719 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 2541719 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996628 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1996628 # number of WriteReq MSHR hits
826,849c833,856
< system.cpu.dcache.demand_mshr_hits::cpu.data 4536753 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 4536753 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 4536753 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 4536753 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298022 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 2298022 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519817 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 519817 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 2817839 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2817839 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2817848 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2817848 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30115234500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 30115234500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603448995 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603448995 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 602500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 602500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34718683495 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 34718683495 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34719285995 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 34719285995 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 4538347 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 4538347 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 4538347 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 4538347 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297984 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 2297984 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519842 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 519842 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 2817826 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2817826 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2817836 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2817836 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32775846000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 32775846000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786094494 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786094494 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1244000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1244000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37561940494 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 37561940494 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563184494 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 37563184494 # number of overall MSHR miss cycles
854,857c861,864
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003215 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003215 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016265 # mshr miss rate for demand accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003569 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016266 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016266 # mshr miss rate for demand accesses
860,879c867,886
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13104.850389 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13104.850389 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.903126 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.903126 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66944.444444 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66944.444444 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12321.031647 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 12321.031647 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12321.206110 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 12321.206110 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 76636 # number of replacements
< system.cpu.icache.tags.tagsinuse 466.486924 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 235189788 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 77148 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 3048.553274 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 115712400500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 466.486924 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.911107 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.911107 # Average percentage of cache occupancy
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14262.869541 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14262.869541 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9206.825332 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9206.825332 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 124400 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 124400 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13330.113532 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 13330.113532 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13330.507700 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 13330.507700 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 76619 # number of replacements
> system.cpu.icache.tags.tagsinuse 466.071602 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 235190778 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 77131 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 3049.238024 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 116612189500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 466.071602 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.910296 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.910296 # Average percentage of cache occupancy
881,884c888,891
< system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
887,913c894,920
< system.cpu.icache.tags.tag_accesses 470628332 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 470628332 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 235189788 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 235189788 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 235189788 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 235189788 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 235189788 # number of overall hits
< system.cpu.icache.overall_hits::total 235189788 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 85789 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 85789 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 85789 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 85789 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 85789 # number of overall misses
< system.cpu.icache.overall_misses::total 85789 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 1556704687 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 1556704687 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 1556704687 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 1556704687 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 1556704687 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 1556704687 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 235275577 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 235275577 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 235275577 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 235275577 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 235275577 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 235275577 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 470630395 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 470630395 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 235190778 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 235190778 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 235190778 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 235190778 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 235190778 # number of overall hits
> system.cpu.icache.overall_hits::total 235190778 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 85841 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 85841 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 85841 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 85841 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 85841 # number of overall misses
> system.cpu.icache.overall_misses::total 85841 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 1941915678 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 1941915678 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 1941915678 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 1941915678 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 1941915678 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 1941915678 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 235276619 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 235276619 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 235276619 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 235276619 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 235276619 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 235276619 # number of overall (read+write) accesses
920,951c927,958
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18145.737647 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18145.737647 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18145.737647 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18145.737647 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 171831 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 200 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 6857 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 25.059210 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 76636 # number of writebacks
< system.cpu.icache.writebacks::total 76636 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8610 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 8610 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 8610 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 8610 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 8610 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 8610 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77179 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 77179 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 77179 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 77179 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 77179 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 77179 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1268632793 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 1268632793 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1268632793 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 1268632793 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1268632793 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 1268632793 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22622.239699 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 22622.239699 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 22622.239699 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 22622.239699 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 206659 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 2170 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 7236 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 28.559840 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 197.272727 # average number of cycles each access was blocked
> system.cpu.icache.writebacks::writebacks 76619 # number of writebacks
> system.cpu.icache.writebacks::total 76619 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8683 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 8683 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 8683 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 8683 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 8683 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 8683 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77158 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 77158 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 77158 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 77158 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 77158 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 77158 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1536678279 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 1536678279 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1536678279 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 1536678279 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1536678279 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 1536678279 # number of overall MSHR miss cycles
958,967c965,974
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16437.538618 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16437.538618 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16437.538618 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 16437.538618 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16437.538618 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 16437.538618 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 8513734 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 8515093 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 374 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19915.994181 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19915.994181 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19915.994181 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 19915.994181 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19915.994181 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 19915.994181 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 8510000 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 8511429 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 428 # number of redundant prefetches already in prefetch queue
970,976c977,983
< system.cpu.l2cache.prefetcher.pfSpanPage 743899 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 390403 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 15000.108571 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2699085 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 406018 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.647698 # Average number of references to valid blocks.
---
> system.cpu.l2cache.prefetcher.pfSpanPage 743291 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 389594 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 15007.037789 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2698812 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 405195 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.660526 # Average number of references to valid blocks.
978,984c985,991
< system.cpu.l2cache.tags.occ_blocks::writebacks 14926.062493 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.046079 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.911015 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004519 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.915534 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 114 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15501 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 14932.547255 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.490534 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.911410 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004547 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.915957 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 98 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15503 # Occupied blocks per task id
986,1061c993,1067
< system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 46 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5426 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6626 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2533 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006958 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946106 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 95370697 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 95370697 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 2353941 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 2353941 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 516320 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 516320 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 516934 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 516934 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67108 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 67108 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130993 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 2130993 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 67108 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 2647927 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2715035 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 67108 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 2647927 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2715035 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 5078 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 5078 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10036 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 10036 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164813 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 164813 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 10036 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 169891 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 179927 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 10036 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 169891 # number of overall misses
< system.cpu.l2cache.overall_misses::total 179927 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 21000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 484083500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 484083500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 750585000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 750585000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12710440000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 12710440000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 750585000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13194523500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 13945108500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 750585000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13194523500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 13945108500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 2353941 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 2353941 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 516320 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 516320 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 30 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 30 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 522012 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 522012 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77144 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 77144 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295806 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 2295806 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 77144 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 2817818 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2894962 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 77144 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 2817818 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2894962 # number of overall (read+write) accesses
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 41 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 672 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5433 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6587 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2565 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.005981 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946228 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 95366335 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 95366335 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 2351800 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 2351800 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 518252 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 518252 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 516857 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 516857 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67161 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 67161 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130903 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 2130903 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 67161 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 2647760 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2714921 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 67161 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 2647760 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2714921 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 27 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 5168 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 5168 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9964 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 9964 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164881 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 164881 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 9964 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 170049 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 180013 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 9964 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 170049 # number of overall misses
> system.cpu.l2cache.overall_misses::total 180013 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 20500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 20500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 668599000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 668599000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1018287500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 1018287500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15371092500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 15371092500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1018287500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 16039691500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 17057979000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1018287500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 16039691500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 17057979000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 2351800 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 2351800 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 518252 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 518252 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 27 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 522025 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 522025 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77125 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 77125 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295784 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 2295784 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 77125 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 2817809 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2894934 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 77125 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 2817809 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2894934 # number of overall (read+write) accesses
1064,1089c1070,1095
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009728 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.009728 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.130094 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.130094 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071789 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071789 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.130094 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.060292 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.062152 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.130094 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.060292 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.062152 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 700 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 700 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95329.558881 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95329.558881 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74789.258669 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74789.258669 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77120.372786 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77120.372786 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74789.258669 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77664.640858 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 77504.257282 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74789.258669 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77664.640858 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 77504.257282 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009900 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.009900 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.129193 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.129193 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071819 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071819 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.129193 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.060348 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.062182 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.129193 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.060348 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.062182 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 759.259259 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 759.259259 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129372.871517 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129372.871517 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102196.657969 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102196.657969 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93225.371632 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93225.371632 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102196.657969 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94323.938982 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 94759.706243 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102196.657969 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94323.938982 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 94759.706243 # average overall miss latency
1096,1100c1102,1106
< system.cpu.l2cache.unused_prefetches 2029 # number of HardPF blocks evicted w/o reference
< system.cpu.l2cache.writebacks::writebacks 291427 # number of writebacks
< system.cpu.l2cache.writebacks::total 291427 # number of writebacks
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1416 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 1416 # number of ReadExReq MSHR hits
---
> system.cpu.l2cache.unused_prefetches 2063 # number of HardPF blocks evicted w/o reference
> system.cpu.l2cache.writebacks::writebacks 291274 # number of writebacks
> system.cpu.l2cache.writebacks::total 291274 # number of writebacks
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1581 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 1581 # number of ReadExReq MSHR hits
1103,1104c1109,1110
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4197 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4197 # number of ReadSharedReq MSHR hits
---
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4441 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4441 # number of ReadSharedReq MSHR hits
1106,1107c1112,1113
< system.cpu.l2cache.demand_mshr_hits::cpu.data 5613 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 5621 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 6022 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 6030 # number of demand (read+write) MSHR hits
1109,1144c1115,1150
< system.cpu.l2cache.overall_mshr_hits::cpu.data 5613 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 5621 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356222 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 356222 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3662 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 3662 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10028 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10028 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160616 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160616 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 10028 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 164278 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 174306 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 10028 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 164278 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356222 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 530528 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18747915458 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 462000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 462000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 336888000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 336888000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 689794500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 689794500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11439165000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11439165000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 689794500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11776053000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 12465847500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 689794500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11776053000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 31213762958 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 6022 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 6030 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 355324 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 355324 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3587 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 3587 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9956 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9956 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160440 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160440 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 9956 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 164027 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 173983 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 9956 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 164027 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 355324 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 529307 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21295211595 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21295211595 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 417500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 417500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 461178500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 461178500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 956729500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 956729500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14002333000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14002333000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 956729500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14463511500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 15420241000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 956729500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14463511500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21295211595 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 36715452595 # number of overall MSHR miss cycles
1149,1159c1155,1165
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007015 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007015 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129991 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069961 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069961 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.060210 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006871 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006871 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129089 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069885 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069885 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.060099 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for overall accesses
1161,1183c1167,1189
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.183259 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 52629.864124 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15400 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15400 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91995.630803 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91995.630803 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68786.846829 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68786.846829 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71220.582009 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71220.582009 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71517.030395 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58835.279114 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 5788969 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893984 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23717 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 99826 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99825 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.182839 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59931.813204 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15462.962963 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15462.962963 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128569.417340 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128569.417340 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96095.771394 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96095.771394 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87274.576166 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87274.576166 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88630.734037 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69365.137047 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 5788910 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893955 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23897 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 99240 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99239 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1185,1190c1191,1196
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 2372984 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 2645368 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 540001 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 98976 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 397627 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 2372941 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 2643074 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 542116 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 98320 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 402261 # Transaction distribution
1192,1208c1198,1214
< system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 522012 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 522012 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 77179 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295806 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230958 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453003 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8683961 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9841856 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360648000 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 370489856 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 788066 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 18653632 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 3683057 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.033555 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.180083 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 522025 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 522025 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 77158 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295784 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230901 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452970 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8683871 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839552 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360646848 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 370486400 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 791889 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 18643712 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 3686849 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.033410 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.179705 # Request fanout histogram
1210,1211c1216,1217
< system.cpu.toL2Bus.snoop_fanout::0 3559472 96.64% 96.64% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 123584 3.36% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 3563674 96.66% 96.66% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 123174 3.34% 100.00% # Request fanout histogram
1216,1217c1222,1223
< system.cpu.toL2Bus.snoop_fanout::total 3683057 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 5788426505 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3686849 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 5788371005 # Layer occupancy (ticks)
1221c1227
< system.cpu.toL2Bus.respLayer0.occupancy 115796940 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 115765939 # Layer occupancy (ticks)
1223c1229
< system.cpu.toL2Bus.respLayer1.occupancy 4226763956 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 4226743467 # Layer occupancy (ticks)
1225,1226c1231,1232
< system.membus.snoop_filter.tot_requests 821136 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 414105 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.membus.snoop_filter.tot_requests 819690 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 413483 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1231,1242c1237,1248
< system.membus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 427040 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 291427 # Transaction distribution
< system.membus.trans_dist::CleanEvict 98976 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 34 # Transaction distribution
< system.membus.trans_dist::ReadExReq 3658 # Transaction distribution
< system.membus.trans_dist::ReadExResp 3658 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 427041 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251834 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1251834 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46216000 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 46216000 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 426481 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 291274 # Transaction distribution
> system.membus.trans_dist::CleanEvict 98320 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 32 # Transaction distribution
> system.membus.trans_dist::ReadExReq 3582 # Transaction distribution
> system.membus.trans_dist::ReadExResp 3582 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 426482 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1249753 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1249753 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46165568 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 46165568 # Cumulative packet size per connected master and slave (bytes)
1245c1251
< system.membus.snoop_fanout::samples 430733 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 430096 # Request fanout histogram
1249c1255
< system.membus.snoop_fanout::0 430733 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 430096 100.00% 100.00% # Request fanout histogram
1254,1257c1260,1263
< system.membus.snoop_fanout::total 430733 # Request fanout histogram
< system.membus.reqLayer0.occupancy 2217216132 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2280002282 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 430096 # Request fanout histogram
> system.membus.reqLayer0.occupancy 2210866206 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2276438586 # Layer occupancy (ticks)