3,5c3,5
< sim_seconds 0.233283 # Number of seconds simulated
< sim_ticks 233282768000 # Number of ticks simulated
< final_tick 233282768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.233332 # Number of seconds simulated
> sim_ticks 233331881000 # Number of ticks simulated
> final_tick 233331881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 136250 # Simulator instruction rate (inst/s)
< host_op_rate 147606 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 62910352 # Simulator tick rate (ticks/s)
< host_mem_usage 320784 # Number of bytes of host memory used
< host_seconds 3708.18 # Real time elapsed on the host
---
> host_inst_rate 137799 # Simulator instruction rate (inst/s)
> host_op_rate 149285 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 63638999 # Simulator tick rate (ticks/s)
> host_mem_usage 320760 # Number of bytes of host memory used
> host_seconds 3666.49 # Real time elapsed on the host
16,53c16,53
< system.physmem.bytes_read::cpu.inst 683136 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9221056 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 16463744 # Number of bytes read from this memory
< system.physmem.bytes_read::total 26367936 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 683136 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 683136 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 18705728 # Number of bytes written to this memory
< system.physmem.bytes_written::total 18705728 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 10674 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 144079 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 257246 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 411999 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 292277 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 292277 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 2928360 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 39527377 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 70574197 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 113029935 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 2928360 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 2928360 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 80184782 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 80184782 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 80184782 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 2928360 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 39527377 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 70574197 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 193214717 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 411999 # Number of read requests accepted
< system.physmem.writeReqs 292277 # Number of write requests accepted
< system.physmem.readBursts 411999 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 292277 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 26229824 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 138112 # Total number of bytes read from write queue
< system.physmem.bytesWritten 18703872 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 26367936 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 18705728 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 2158 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bytes_read::cpu.inst 689792 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9194752 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 16497856 # Number of bytes read from this memory
> system.physmem.bytes_read::total 26382400 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 689792 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 689792 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 18714240 # Number of bytes written to this memory
> system.physmem.bytes_written::total 18714240 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 10778 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 143668 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 257779 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 412225 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 292410 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 292410 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 2956270 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 39406325 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 70705537 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 113068132 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 2956270 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 2956270 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 80204385 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 80204385 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 80204385 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 2956270 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 39406325 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 70705537 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 193272517 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 412225 # Number of read requests accepted
> system.physmem.writeReqs 292410 # Number of write requests accepted
> system.physmem.readBursts 412225 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 292410 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 26244608 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 137792 # Total number of bytes read from write queue
> system.physmem.bytesWritten 18711808 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 26382400 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 18714240 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 2153 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 7 # Number of DRAM write bursts merged with an existing one
55,86c55,86
< system.physmem.perBankRdBursts::0 26728 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25477 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25253 # Per bank write bursts
< system.physmem.perBankRdBursts::3 24678 # Per bank write bursts
< system.physmem.perBankRdBursts::4 27151 # Per bank write bursts
< system.physmem.perBankRdBursts::5 26546 # Per bank write bursts
< system.physmem.perBankRdBursts::6 25195 # Per bank write bursts
< system.physmem.perBankRdBursts::7 24195 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25840 # Per bank write bursts
< system.physmem.perBankRdBursts::9 24882 # Per bank write bursts
< system.physmem.perBankRdBursts::10 24886 # Per bank write bursts
< system.physmem.perBankRdBursts::11 26093 # Per bank write bursts
< system.physmem.perBankRdBursts::12 26302 # Per bank write bursts
< system.physmem.perBankRdBursts::13 26067 # Per bank write bursts
< system.physmem.perBankRdBursts::14 24895 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25653 # Per bank write bursts
< system.physmem.perBankWrBursts::0 18973 # Per bank write bursts
< system.physmem.perBankWrBursts::1 18287 # Per bank write bursts
< system.physmem.perBankWrBursts::2 17868 # Per bank write bursts
< system.physmem.perBankWrBursts::3 17935 # Per bank write bursts
< system.physmem.perBankWrBursts::4 18795 # Per bank write bursts
< system.physmem.perBankWrBursts::5 18319 # Per bank write bursts
< system.physmem.perBankWrBursts::6 17931 # Per bank write bursts
< system.physmem.perBankWrBursts::7 17655 # Per bank write bursts
< system.physmem.perBankWrBursts::8 18179 # Per bank write bursts
< system.physmem.perBankWrBursts::9 17927 # Per bank write bursts
< system.physmem.perBankWrBursts::10 17987 # Per bank write bursts
< system.physmem.perBankWrBursts::11 18662 # Per bank write bursts
< system.physmem.perBankWrBursts::12 18697 # Per bank write bursts
< system.physmem.perBankWrBursts::13 18344 # Per bank write bursts
< system.physmem.perBankWrBursts::14 18231 # Per bank write bursts
< system.physmem.perBankWrBursts::15 18458 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 26528 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25539 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25303 # Per bank write bursts
> system.physmem.perBankRdBursts::3 24713 # Per bank write bursts
> system.physmem.perBankRdBursts::4 27194 # Per bank write bursts
> system.physmem.perBankRdBursts::5 26607 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24941 # Per bank write bursts
> system.physmem.perBankRdBursts::7 24442 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25767 # Per bank write bursts
> system.physmem.perBankRdBursts::9 24723 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25091 # Per bank write bursts
> system.physmem.perBankRdBursts::11 26187 # Per bank write bursts
> system.physmem.perBankRdBursts::12 26462 # Per bank write bursts
> system.physmem.perBankRdBursts::13 26013 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25052 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25510 # Per bank write bursts
> system.physmem.perBankWrBursts::0 18779 # Per bank write bursts
> system.physmem.perBankWrBursts::1 18326 # Per bank write bursts
> system.physmem.perBankWrBursts::2 18027 # Per bank write bursts
> system.physmem.perBankWrBursts::3 17939 # Per bank write bursts
> system.physmem.perBankWrBursts::4 18703 # Per bank write bursts
> system.physmem.perBankWrBursts::5 18353 # Per bank write bursts
> system.physmem.perBankWrBursts::6 17755 # Per bank write bursts
> system.physmem.perBankWrBursts::7 17808 # Per bank write bursts
> system.physmem.perBankWrBursts::8 18074 # Per bank write bursts
> system.physmem.perBankWrBursts::9 17824 # Per bank write bursts
> system.physmem.perBankWrBursts::10 18093 # Per bank write bursts
> system.physmem.perBankWrBursts::11 18724 # Per bank write bursts
> system.physmem.perBankWrBursts::12 18814 # Per bank write bursts
> system.physmem.perBankWrBursts::13 18339 # Per bank write bursts
> system.physmem.perBankWrBursts::14 18411 # Per bank write bursts
> system.physmem.perBankWrBursts::15 18403 # Per bank write bursts
89c89
< system.physmem.totGap 233282750000 # Total gap between requests
---
> system.physmem.totGap 233331863000 # Total gap between requests
96c96
< system.physmem.readPktSize::6 411999 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 412225 # Read request sizes (log2)
103,117c103,117
< system.physmem.writePktSize::6 292277 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 312898 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 47873 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 13110 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 9133 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 7330 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 6176 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 5273 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 4418 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3450 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 96 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 11 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 292410 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 311682 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 49314 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 13194 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 9237 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 7343 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 6192 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 5234 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 4415 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3338 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see
151,175c151,175
< system.physmem.wrQLenPdf::15 6395 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 6689 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 13204 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 15353 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 16370 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 16918 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 17192 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 17443 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 17610 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 17839 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 18048 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 18366 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 18616 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 18818 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 19964 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 18185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 17459 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 40 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 6393 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 6662 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 15393 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 16401 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 16959 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 17206 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 17395 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 17650 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 17892 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 17983 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 18388 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 18586 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 18721 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 19985 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 18227 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 17652 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 17464 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 29 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
200,217c200,217
< system.physmem.bytesPerActivate::samples 306889 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 146.413224 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 102.997180 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 182.093051 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 184151 60.01% 60.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 82036 26.73% 86.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 16582 5.40% 92.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7394 2.41% 94.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4756 1.55% 96.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2254 0.73% 96.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1661 0.54% 97.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1625 0.53% 97.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 6430 2.10% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 306889 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 17312 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 23.673001 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 116.829793 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 17311 99.99% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 307255 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 146.312346 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 102.902161 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 182.114345 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 184693 60.11% 60.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 81851 26.64% 86.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 16642 5.42% 92.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7320 2.38% 94.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4729 1.54% 96.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2259 0.74% 96.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1737 0.57% 97.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1607 0.52% 97.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 6417 2.09% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 307255 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 17328 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 23.664070 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 116.589701 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 17327 99.99% 99.99% # Reads before turning the bus around for writes
219,234c219,234
< system.physmem.rdPerTurnAround::total 17312 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 17312 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.881238 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.838780 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.240848 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 10485 60.56% 60.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 306 1.77% 62.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 5502 31.78% 94.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 671 3.88% 97.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 134 0.77% 98.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 74 0.43% 99.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 42 0.24% 99.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 45 0.26% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 29 0.17% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 14 0.08% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 9 0.05% 99.99% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 17328 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 17328 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.872807 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.831610 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.219578 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 10506 60.63% 60.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 279 1.61% 62.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 5596 32.29% 94.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 616 3.55% 98.09% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 141 0.81% 98.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 60 0.35% 99.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 44 0.25% 99.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 41 0.24% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 25 0.14% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 12 0.07% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 7 0.04% 99.99% # Writes before turning the bus around for reads
236,240c236,240
< system.physmem.wrPerTurnAround::total 17312 # Writes before turning the bus around for reads
< system.physmem.totQLat 9036310212 # Total ticks spent queuing
< system.physmem.totMemAccLat 16720828962 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2049205000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 22048.33 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 17328 # Writes before turning the bus around for reads
> system.physmem.totQLat 9022211140 # Total ticks spent queuing
> system.physmem.totMemAccLat 16711061140 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2050360000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 22001.53 # Average queueing delay per DRAM burst
242,246c242,246
< system.physmem.avgMemAccLat 40798.33 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 112.44 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 80.18 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 113.03 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 80.18 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 40751.53 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 112.48 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 80.19 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 113.07 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 80.20 # Average system write bandwidth in MiByte/s
248c248
< system.physmem.busUtil 1.50 # Data bus utilization in percentage
---
> system.physmem.busUtil 1.51 # Data bus utilization in percentage
251,269c251,269
< system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 21.78 # Average write queue length when enqueuing
< system.physmem.readRowHits 299552 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95641 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 73.09 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes
< system.physmem.avgGap 331237.68 # Average gap between requests
< system.physmem.pageHitRate 56.29 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 1156763160 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 631170375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1600435200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 944401680 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 74473770375 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 74637909000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 168680907390 # Total energy per rank (pJ)
< system.physmem_0.averagePower 723.094931 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 123643637069 # Time in different power states
< system.physmem_0.memoryStateTime::REF 7789600000 # Time in different power states
---
> system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 21.59 # Average write queue length when enqueuing
> system.physmem.readRowHits 299444 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95740 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 32.74 # Row buffer hit rate for writes
> system.physmem.avgGap 331138.62 # Average gap between requests
> system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 1156823640 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 631203375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1601035800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 944071200 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 75187551735 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 74044498500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 168805201770 # Total energy per rank (pJ)
> system.physmem_0.averagePower 723.458661 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 122654182736 # Time in different power states
> system.physmem_0.memoryStateTime::REF 7791420000 # Time in different power states
271c271
< system.physmem_0.memoryStateTime::ACT 101845250931 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 102885452264 # Time in different power states
273,283c273,283
< system.physmem_1.actEnergy 1163007720 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 634577625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1595802000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 949158000 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 74040443550 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 75018020250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 168637466745 # Total energy per rank (pJ)
< system.physmem_1.averagePower 722.908711 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 124281047938 # Time in different power states
< system.physmem_1.memoryStateTime::REF 7789600000 # Time in different power states
---
> system.physmem_1.actEnergy 1166024160 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 636223500 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1597377600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 950499360 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 74554879950 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 74599507500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 168744529590 # Total energy per rank (pJ)
> system.physmem_1.averagePower 723.198461 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 123580654566 # Time in different power states
> system.physmem_1.memoryStateTime::REF 7791420000 # Time in different power states
285c285
< system.physmem_1.memoryStateTime::ACT 101208398062 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 101958813184 # Time in different power states
287,291c287,291
< system.cpu.branchPred.lookups 175089811 # Number of BP lookups
< system.cpu.branchPred.condPredicted 131337021 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 7444155 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 90376647 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 83876100 # Number of BTB hits
---
> system.cpu.branchPred.lookups 175090137 # Number of BP lookups
> system.cpu.branchPred.condPredicted 131338905 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 7443529 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 90540858 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 83879425 # Number of BTB hits
293,295c293,295
< system.cpu.branchPred.BTBHitPct 92.807271 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 12110019 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 104160 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 92.642622 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 12110692 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions.
414c414
< system.cpu.numCycles 466565537 # number of cpu cycles simulated
---
> system.cpu.numCycles 466663763 # number of cpu cycles simulated
417,430c417,430
< system.cpu.fetch.icacheStallCycles 7838065 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 731795546 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 175089811 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 95986119 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 450385778 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 14940817 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 5837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps
< system.cpu.fetch.IcacheWaitRetryStallCycles 14677 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 236716672 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 34578 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 465715008 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.701748 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.179403 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 7839248 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 731808788 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 175090137 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 95990117 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 450472274 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 14939659 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 5656 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps
> system.cpu.fetch.IcacheWaitRetryStallCycles 14269 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 236720425 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 34587 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 465801433 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.701462 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.179511 # Number of instructions fetched each cycle (Total)
432,435c432,435
< system.cpu.fetch.rateDist::0 93791115 20.14% 20.14% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 132693411 28.49% 48.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 57855471 12.42% 61.05% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 181375011 38.95% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 93869731 20.15% 20.15% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 132699774 28.49% 48.64% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 57852108 12.42% 61.06% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 181379820 38.94% 100.00% # Number of instructions fetched each cycle (Total)
439,465c439,465
< system.cpu.fetch.rateDist::total 465715008 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.375274 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.568473 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 32367511 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 117249871 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 287084329 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 22031549 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 6981748 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 24050134 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 496459 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 715800999 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 30008433 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 6981748 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 63425626 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 54212557 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 40336788 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 276681526 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 24076763 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 686589929 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 13340569 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 9410638 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 2384158 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1669115 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 1841927 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 831018421 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 3019159141 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 723918647 # Number of integer rename lookups
---
> system.cpu.fetch.rateDist::total 465801433 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.375195 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.568171 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 32373679 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 117343382 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 287062106 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 22041011 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 6981255 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 24049971 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 496386 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 715809364 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 30003912 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 6981255 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 63434666 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 54211510 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 40338612 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 276664591 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 24170799 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 686600417 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 13340367 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 9416739 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 2386420 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1670076 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 1927738 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 831025477 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 3019202538 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 723925996 # Number of integer rename lookups
468,485c468,485
< system.cpu.rename.UndoneMaps 176894670 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1544698 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 1534992 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 42289780 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 143526215 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 67981217 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 12855514 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 11197113 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 668159255 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2978326 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 610231748 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 5860169 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 123786636 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 319274742 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 694 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 465715008 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.310312 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.101358 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 176901726 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1544701 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 1534906 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 42308307 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 143530339 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 67981565 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 12860716 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 11266999 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 668170903 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2978331 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 610248763 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 5854866 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 123798289 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 319264737 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 699 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 465801433 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.310105 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.101429 # Number of insts issued each cycle
487,492c487,492
< system.cpu.iq.issued_per_cycle::0 148574576 31.90% 31.90% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 101171602 21.72% 53.63% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 145766544 31.30% 84.93% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 63282576 13.59% 98.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 6919220 1.49% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 490 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 148653685 31.91% 31.91% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 101184506 21.72% 53.64% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 145749505 31.29% 84.93% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 63290175 13.59% 98.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 6923088 1.49% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 474 0.00% 100.00% # Number of insts issued each cycle
499c499
< system.cpu.iq.issued_per_cycle::total 465715008 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 465801433 # Number of insts issued each cycle
501,531c501,531
< system.cpu.iq.fu_full::IntAlu 71921517 52.96% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 44556516 32.81% 85.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 19328890 14.23% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 71924616 52.97% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 44553347 32.81% 85.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 19296722 14.21% 100.00% # attempts to use FU when none available
535,536c535,536
< system.cpu.iq.FU_type_0::IntAlu 413144323 67.70% 67.70% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 351745 0.06% 67.76% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 413148587 67.70% 67.70% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 351752 0.06% 67.76% # Type of FU issued
564,565c564,565
< system.cpu.iq.FU_type_0::MemRead 134209580 21.99% 89.75% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 62526097 10.25% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 134215566 21.99% 89.75% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 62532855 10.25% 100.00% # Type of FU issued
568,574c568,574
< system.cpu.iq.FU_type_0::total 610231748 # Type of FU issued
< system.cpu.iq.rate 1.307923 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 135806953 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.222550 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 1827845333 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 794952356 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 594966802 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 610248763 # Type of FU issued
> system.cpu.iq.rate 1.307684 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 135774715 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.222491 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 1827928247 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 794975703 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 594980555 # Number of integer instruction queue wakeup accesses
578c578
< system.cpu.iq.int_alu_accesses 746038524 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 746023301 # Number of integer alu accesses
580c580
< system.cpu.iew.lsq.thread0.forwLoads 7273046 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 7276983 # Number of loads that had data forwarded from stores
582,585c582,585
< system.cpu.iew.lsq.thread0.squashedLoads 27641459 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 25471 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 28891 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 11120740 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 27645583 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 25497 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 28922 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 11121088 # Number of stores squashed
588,589c588,589
< system.cpu.iew.lsq.thread0.rescheduledLoads 225190 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 22470 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 225125 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 22421 # Number of times an access to memory failed due to the cache being blocked
591,594c591,594
< system.cpu.iew.iewSquashCycles 6981748 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 23001930 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 919984 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 672625014 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 6981255 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 22978687 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 924846 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 672636723 # Number of instructions dispatched to IQ
596,607c596,607
< system.cpu.iew.iewDispLoadInsts 143526215 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 67981217 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1489784 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 258650 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 525178 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 28891 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 3821630 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3731398 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 7553028 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 599382547 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 129570228 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 10849201 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 143530339 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 67981565 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1489789 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 258799 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 529739 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 28922 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 3821583 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3731049 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 7552632 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 599397786 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 129576337 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 10850977 # Number of squashed instructions skipped in execute
609,617c609,617
< system.cpu.iew.exec_nop 1487433 # number of nop insts executed
< system.cpu.iew.exec_refs 190523509 # number of memory reference insts executed
< system.cpu.iew.exec_branches 131370037 # Number of branches executed
< system.cpu.iew.exec_stores 60953281 # Number of stores executed
< system.cpu.iew.exec_rate 1.284670 # Inst execution rate
< system.cpu.iew.wb_sent 596261681 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 594966818 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 349901968 # num instructions producing a value
< system.cpu.iew.wb_consumers 570648646 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 1487489 # number of nop insts executed
> system.cpu.iew.exec_refs 190533026 # number of memory reference insts executed
> system.cpu.iew.exec_branches 131372234 # Number of branches executed
> system.cpu.iew.exec_stores 60956689 # Number of stores executed
> system.cpu.iew.exec_rate 1.284432 # Inst execution rate
> system.cpu.iew.wb_sent 596275489 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 594980571 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 349907425 # num instructions producing a value
> system.cpu.iew.wb_consumers 570632122 # num instructions consuming a value
619,620c619,620
< system.cpu.iew.wb_rate 1.275205 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.613165 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.274966 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.613193 # average fanout of values written-back
622c622
< system.cpu.commit.commitSquashedInsts 110016162 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 110027797 # The number of squashed insts skipped by commit
624,627c624,627
< system.cpu.commit.branchMispredicts 6955495 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 448601420 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.223123 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.887905 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 6954955 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 448686365 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.222892 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.888131 # Number of insts commited each cycle
629,637c629,637
< system.cpu.commit.committed_per_cycle::0 219539851 48.94% 48.94% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 116349885 25.94% 74.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 43748468 9.75% 84.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 23302371 5.19% 89.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 11552802 2.58% 92.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 7777273 1.73% 94.13% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 8275373 1.84% 95.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 4252092 0.95% 96.92% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 13803305 3.08% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 219669318 48.96% 48.96% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 116312485 25.92% 74.88% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 43742979 9.75% 84.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 23278779 5.19% 89.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 11577691 2.58% 92.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 7777719 1.73% 94.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 8261206 1.84% 95.97% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 4236050 0.94% 96.92% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 13830138 3.08% 100.00% # Number of insts commited each cycle
641c641
< system.cpu.commit.committed_per_cycle::total 448601420 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 448686365 # Number of insts commited each cycle
687,691c687,691
< system.cpu.commit.bw_lim_events 13803305 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 1093501968 # The number of ROB reads
< system.cpu.rob.rob_writes 1334565325 # The number of ROB writes
< system.cpu.timesIdled 13884 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 850529 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 13830138 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 1093571715 # The number of ROB reads
> system.cpu.rob.rob_writes 1334590067 # The number of ROB writes
> system.cpu.timesIdled 13966 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 862330 # Total number of cycles that the CPU has spent unscheduled due to idling
694,699c694,699
< system.cpu.cpi 0.923457 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.923457 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.082887 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.082887 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 611072880 # number of integer regfile reads
< system.cpu.int_regfile_writes 328111730 # number of integer regfile writes
---
> system.cpu.cpi 0.923652 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.923652 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.082659 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.082659 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 611088796 # number of integer regfile reads
> system.cpu.int_regfile_writes 328119086 # number of integer regfile writes
701,703c701,703
< system.cpu.cc_regfile_reads 2170116632 # number of cc regfile reads
< system.cpu.cc_regfile_writes 376537008 # number of cc regfile writes
< system.cpu.misc_regfile_reads 217962216 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 2170176811 # number of cc regfile reads
> system.cpu.cc_regfile_writes 376539852 # number of cc regfile writes
> system.cpu.misc_regfile_reads 217970841 # number of misc regfile reads
705,713c705,713
< system.cpu.dcache.tags.replacements 2820796 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.631791 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 169351038 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 2821308 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 60.025718 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 498038000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.631791 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.replacements 2820945 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.631358 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 169354520 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 2821457 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 60.023782 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 498530000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.631358 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999280 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999280 # Average percentage of cache occupancy
715,716c715,716
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id
719,726c719,726
< system.cpu.dcache.tags.tag_accesses 356237372 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 356237372 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 114646487 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 114646487 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 51724617 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 51724617 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 356242117 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 356242117 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 114648793 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 114648793 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 51725790 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 51725790 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits
731,740c731,740
< system.cpu.dcache.demand_hits::cpu.data 166371104 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 166371104 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 166373887 # number of overall hits
< system.cpu.dcache.overall_hits::total 166373887 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 4842277 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 4842277 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 2514689 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2514689 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 166374583 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 166374583 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 166377369 # number of overall hits
> system.cpu.dcache.overall_hits::total 166377369 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 4842267 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 4842267 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 2513516 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2513516 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses
743,758c743,758
< system.cpu.dcache.demand_misses::cpu.data 7356966 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 7356966 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 7356978 # number of overall misses
< system.cpu.dcache.overall_misses::total 7356978 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 56244825000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 56244825000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 18846227941 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 18846227941 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1242500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 1242500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 75091052941 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 75091052941 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 75091052941 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 75091052941 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 119488764 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 119488764 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 7355783 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 7355783 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 7355794 # number of overall misses
> system.cpu.dcache.overall_misses::total 7355794 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 56187510500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 56187510500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 19050466441 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 19050466441 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1271500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 1271500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 75237976941 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 75237976941 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 75237976941 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 75237976941 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 119491060 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 119491060 # number of ReadReq accesses(hits+misses)
761,762c761,762
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses)
767,776c767,776
< system.cpu.dcache.demand_accesses::cpu.data 173728070 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 173728070 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 173730865 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 173730865 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040525 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.040525 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046363 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.046363 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 173730366 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 173730366 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 173733163 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 173733163 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040524 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.040524 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046341 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.046341 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses
779,798c779,798
< system.cpu.dcache.demand_miss_rate::cpu.data 0.042348 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.042348 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.042347 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.042347 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11615.367109 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 11615.367109 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7494.456746 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 7494.456746 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18825.757576 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18825.757576 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 10206.796245 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 10206.796245 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 10206.779596 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 10206.779596 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 911242 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 221024 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.500000 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 4.122819 # average number of cycles each access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.042340 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.042340 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.042340 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.042340 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11603.554802 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 11603.554802 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7579.210334 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 7579.210334 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19265.151515 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19265.151515 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 10228.411706 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 10228.411706 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 10228.396410 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 10228.396410 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 931670 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 221105 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.333333 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 4.213699 # average number of cycles each access was blocked
801,806c801,806
< system.cpu.dcache.writebacks::writebacks 2356243 # number of writebacks
< system.cpu.dcache.writebacks::total 2356243 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540565 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2540565 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995076 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1995076 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 2357131 # number of writebacks
> system.cpu.dcache.writebacks::total 2357131 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540406 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 2540406 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1993903 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1993903 # number of WriteReq MSHR hits
809,814c809,814
< system.cpu.dcache.demand_mshr_hits::cpu.data 4535641 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 4535641 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 4535641 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 4535641 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301712 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 2301712 # number of ReadReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 4534309 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 4534309 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 4534309 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 4534309 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301861 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 2301861 # number of ReadReq MSHR misses
819,834c819,834
< system.cpu.dcache.demand_mshr_misses::cpu.data 2821325 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 2821325 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 2821335 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 2821335 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28710026000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 28710026000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4575255494 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4575255494 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 657000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 657000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33285281494 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 33285281494 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33285938494 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 33285938494 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019263 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019263 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 2821474 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 2821474 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 2821484 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 2821484 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28687651000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 28687651000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4620185994 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4620185994 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 674500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 674500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33307836994 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 33307836994 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33308511494 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 33308511494 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019264 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019264 # mshr miss rate for ReadReq accesses
837,840c837,840
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016240 # mshr miss rate for demand accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016241 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016241 # mshr miss rate for demand accesses
843,852c843,852
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12473.335500 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12473.335500 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8805.121300 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8805.121300 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65700 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65700 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.748042 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.748042 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.939094 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.939094 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.807702 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.807702 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8891.590461 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8891.590461 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67450 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67450 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11805.119237 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 11805.119237 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11805.316455 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 11805.316455 # average overall mshr miss latency
854,862c854,862
< system.cpu.icache.tags.replacements 73477 # number of replacements
< system.cpu.icache.tags.tagsinuse 466.193561 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 236634038 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 73989 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 3198.232683 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 114977932500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 466.193561 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.910534 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.910534 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 73454 # number of replacements
> system.cpu.icache.tags.tagsinuse 466.198570 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 236637753 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 73966 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 3199.277411 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 114991601500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 466.198570 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.910544 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.910544 # Average percentage of cache occupancy
870,895c870,895
< system.cpu.icache.tags.tag_accesses 473507120 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 473507120 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 236634038 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 236634038 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 236634038 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 236634038 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 236634038 # number of overall hits
< system.cpu.icache.overall_hits::total 236634038 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 82514 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 82514 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 82514 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 82514 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 82514 # number of overall misses
< system.cpu.icache.overall_misses::total 82514 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 1544948153 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 1544948153 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 1544948153 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 1544948153 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 1544948153 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 1544948153 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 236716552 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 236716552 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 236716552 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 236716552 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 236716552 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 236716552 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 473514607 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 473514607 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 236637753 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 236637753 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 236637753 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 236637753 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 236637753 # number of overall hits
> system.cpu.icache.overall_hits::total 236637753 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 82554 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 82554 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 82554 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 82554 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 82554 # number of overall misses
> system.cpu.icache.overall_misses::total 82554 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 1566745159 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 1566745159 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 1566745159 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 1566745159 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 1566745159 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 1566745159 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 236720307 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 236720307 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 236720307 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 236720307 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 236720307 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 236720307 # number of overall (read+write) accesses
902,913c902,913
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18723.466963 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 18723.466963 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 18723.466963 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 18723.466963 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 18723.466963 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 18723.466963 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 193180 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 6947 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 27.807687 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18978.428168 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 18978.428168 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 18978.428168 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 18978.428168 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 18978.428168 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 18978.428168 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 198034 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 7006 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 28.266343 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked
916,933c916,933
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8497 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 8497 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 8497 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 8497 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 8497 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 8497 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74017 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 74017 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 74017 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 74017 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 74017 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 74017 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1266772756 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 1266772756 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1266772756 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 1266772756 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1266772756 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 1266772756 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8560 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 8560 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 8560 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 8560 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 8560 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 8560 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73994 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 73994 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 73994 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 73994 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 73994 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 73994 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1278636265 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 1278636265 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1278636265 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 1278636265 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1278636265 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 1278636265 # number of overall MSHR miss cycles
940,945c940,945
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17114.619020 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17114.619020 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17114.619020 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 17114.619020 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17114.619020 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 17114.619020 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17280.269549 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17280.269549 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17280.269549 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 17280.269549 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17280.269549 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 17280.269549 # average overall mshr miss latency
947,949c947,949
< system.cpu.l2cache.prefetcher.num_hwpf_issued 8510429 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 8512950 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 1055 # number of redundant prefetches already in prefetch queue
---
> system.cpu.l2cache.prefetcher.num_hwpf_issued 8511909 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 8513040 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 167 # number of redundant prefetches already in prefetch queue
952,984c952,983
< system.cpu.l2cache.prefetcher.pfSpanPage 742850 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.replacements 400878 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 15418.113154 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 5066482 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 417216 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 12.143547 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 34592827000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 8451.219479 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 476.205325 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 4934.937237 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1555.751112 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.515822 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.029065 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.301205 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.094956 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.941047 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 1092 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15246 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 37 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 235 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 819 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1560 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9946 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3385 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066650 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930542 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 93192221 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 93192221 # Number of data accesses
< system.cpu.l2cache.Writeback_hits::writebacks 2356243 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 2356243 # number of Writeback hits
---
> system.cpu.l2cache.prefetcher.pfSpanPage 743544 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.replacements 401080 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 15418.085448 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 5068240 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 417417 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 12.141911 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 34601120500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 8466.854939 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 473.689855 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 4911.860449 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1565.680205 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.516776 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.028912 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.299796 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095562 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.941045 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 1090 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15247 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 32 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 243 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 815 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1541 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10024 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3332 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066528 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930603 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 93191002 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 93191002 # Number of data accesses
> system.cpu.l2cache.Writeback_hits::writebacks 2357131 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 2357131 # number of Writeback hits
987,998c986,997
< system.cpu.l2cache.ReadExReq_hits::cpu.data 516767 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 516767 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 63301 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 63301 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2154697 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 2154697 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 63301 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 2671464 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2734765 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 63301 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 2671464 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2734765 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 516789 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 516789 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 63176 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 63176 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2155511 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 2155511 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 63176 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 2672300 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2735476 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 63176 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 2672300 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2735476 # number of overall hits
1001,1026c1000,1025
< system.cpu.l2cache.ReadExReq_misses::cpu.data 5205 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 5205 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10683 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 10683 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 144639 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 144639 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 10683 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 149844 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 160527 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 10683 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 149844 # number of overall misses
< system.cpu.l2cache.overall_misses::total 160527 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 460413000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 460413000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 779781500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 779781500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11147875000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 11147875000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 779781500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11608288000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 12388069500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 779781500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11608288000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 12388069500 # number of overall miss cycles
< system.cpu.l2cache.Writeback_accesses::writebacks 2356243 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 2356243 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 5171 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 5171 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10785 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 10785 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 143986 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 143986 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 10785 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 149157 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 159942 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 10785 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 149157 # number of overall misses
> system.cpu.l2cache.overall_misses::total 159942 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 505481000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 505481000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 792508500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 792508500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11120056000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 11120056000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 792508500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11625537000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12418045500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 792508500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11625537000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12418045500 # number of overall miss cycles
> system.cpu.l2cache.Writeback_accesses::writebacks 2357131 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 2357131 # number of Writeback accesses(hits+misses)
1029,1040c1028,1039
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 521972 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 521972 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 73984 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 73984 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299336 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 2299336 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 73984 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 2821308 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2895292 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 73984 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 2821308 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2895292 # number of overall (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 521960 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 521960 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 73961 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 73961 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299497 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 2299497 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 73961 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 2821457 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2895418 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 73961 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 2821457 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2895418 # number of overall (read+write) accesses
1043,1066c1042,1065
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009972 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.009972 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.144396 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.144396 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.062905 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.062905 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.144396 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.053112 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.055444 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144396 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.053112 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.055444 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88455.907781 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88455.907781 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72992.745483 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72992.745483 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77073.783696 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77073.783696 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72992.745483 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77469.154587 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 77171.251565 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72992.745483 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77469.154587 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 77171.251565 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009907 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.009907 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.145820 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.145820 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.062616 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.062616 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.145820 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.052865 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.055240 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.145820 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.052865 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.055240 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97753.045833 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97753.045833 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73482.475661 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73482.475661 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77230.119595 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77230.119595 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73482.475661 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77941.611859 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77640.929212 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73482.475661 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77941.611859 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77640.929212 # average overall miss latency
1075,1092c1074,1091
< system.cpu.l2cache.writebacks::writebacks 292277 # number of writebacks
< system.cpu.l2cache.writebacks::total 292277 # number of writebacks
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1529 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 1529 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 8 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4235 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4235 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 5764 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 5772 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 5764 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 5772 # number of overall MSHR hits
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6839 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 6839 # number of CleanEvict MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 274923 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 274923 # number of HardPFReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 292410 # number of writebacks
> system.cpu.l2cache.writebacks::total 292410 # number of writebacks
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1449 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 1449 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 6 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4039 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4039 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 5488 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 5494 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 5488 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 5494 # number of overall MSHR hits
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6957 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 6957 # number of CleanEvict MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275571 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 275571 # number of HardPFReq MSHR misses
1095,1124c1094,1123
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3676 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 3676 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10675 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10675 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 140404 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 140404 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 10675 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 144080 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 154755 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 10675 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 144080 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 274923 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 429678 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19117391245 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19117391245 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 33000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 33000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 289648000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 289648000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 715179500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 715179500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9979387500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9979387500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 715179500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10269035500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10984215000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 715179500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10269035500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19117391245 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 30101606245 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3722 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 3722 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10779 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10779 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 139947 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 139947 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 10779 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143669 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 154448 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 10779 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143669 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275571 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 430019 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19018555494 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19018555494 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 33500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 33500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 344223500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 344223500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 727200000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 727200000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9979336000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9979336000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 727200000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10323559500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 11050759500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 727200000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10323559500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19018555494 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30069314994 # number of overall MSHR miss cycles
1131,1141c1130,1140
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007043 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007043 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144288 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.061063 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.061063 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051069 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.053451 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051069 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007131 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007131 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.145739 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060860 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060860 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.053342 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for overall accesses
1143,1160c1142,1159
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.148406 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69537.256777 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16500 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16500 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78794.341676 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78794.341676 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66995.737705 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66995.737705 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71076.233583 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71076.233583 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70978.094407 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70056.196140 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.148517 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69015.083205 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16750 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16750 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92483.476625 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92483.476625 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67464.514333 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67464.514333 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71307.966587 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71307.966587 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71550.033021 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69925.549787 # average overall mshr miss latency
1162,1165c1161,1164
< system.cpu.toL2Bus.trans_dist::ReadResp 2373352 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 2648520 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 622852 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 320716 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2373490 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 2649541 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 621819 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 317371 # Transaction distribution
1168,1181c1167,1180
< system.cpu.toL2Bus.trans_dist::ReadExReq 521972 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 521972 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 74017 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299336 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220623 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440541 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8661164 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734912 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331363264 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 336098176 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 721627 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 6511219 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.110823 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.313913 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 521960 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 521960 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 73994 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299497 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220555 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440647 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8661202 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733440 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331429632 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 336163072 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 718484 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 6508328 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.110389 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram
1184,1185c1183,1184
< system.cpu.toL2Bus.snoop_fanout::1 5789625 88.92% 88.92% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 721594 11.08% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 5789877 88.96% 88.96% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 718451 11.04% 100.00% # Request fanout histogram
1189,1190c1188,1189
< system.cpu.toL2Bus.snoop_fanout::total 6511219 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 5251055500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 6508328 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 5252069500 # Layer occupancy (ticks)
1192c1191
< system.cpu.toL2Bus.respLayer0.occupancy 111049948 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 111018442 # Layer occupancy (ticks)
1194c1193
< system.cpu.toL2Bus.respLayer1.occupancy 4231992466 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 4232215467 # Layer occupancy (ticks)
1196,1198c1195,1197
< system.membus.trans_dist::ReadResp 408324 # Transaction distribution
< system.membus.trans_dist::Writeback 292277 # Transaction distribution
< system.membus.trans_dist::CleanEvict 103036 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 408504 # Transaction distribution
> system.membus.trans_dist::Writeback 292410 # Transaction distribution
> system.membus.trans_dist::CleanEvict 103085 # Transaction distribution
1201,1207c1200,1206
< system.membus.trans_dist::ReadExReq 3675 # Transaction distribution
< system.membus.trans_dist::ReadExResp 3675 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 408324 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219317 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1219317 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45073664 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 45073664 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadExReq 3721 # Transaction distribution
> system.membus.trans_dist::ReadExResp 3721 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 408504 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219951 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1219951 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45096640 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 45096640 # Cumulative packet size per connected master and slave (bytes)
1209c1208
< system.membus.snoop_fanout::samples 807315 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 807723 # Request fanout histogram
1213c1212
< system.membus.snoop_fanout::0 807315 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 807723 100.00% 100.00% # Request fanout histogram
1218,1219c1217,1218
< system.membus.snoop_fanout::total 807315 # Request fanout histogram
< system.membus.reqLayer0.occupancy 2175050688 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 807723 # Request fanout histogram
> system.membus.reqLayer0.occupancy 2173813941 # Layer occupancy (ticks)
1221c1220
< system.membus.respLayer1.occupancy 2177979128 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2179181168 # Layer occupancy (ticks)