| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.233382 # Number of seconds simulated 4sim_ticks 233381523500 # Number of ticks simulated 5final_tick 233381523500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 139639 # Simulator instruction rate (inst/s) 8host_op_rate 151279 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 64502789 # Simulator tick rate (ticks/s) 10host_mem_usage 317896 # Number of bytes of host memory used 11host_seconds 3618.16 # Real time elapsed on the host 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 547350944 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 689856 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9181056 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 16498240 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26369152 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 689856 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 689856 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18710272 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18710272 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 10779 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 143454 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 257785 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 412018 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 292348 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 292348 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 2955915 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 39339258 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 70692143 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 112987316 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 2955915 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 2955915 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 80170322 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 80170322 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 80170322 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 2955915 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 39339258 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 70692143 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 193157639 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 412018 # Number of read requests accepted 44system.physmem.writeReqs 292348 # Number of write requests accepted 45system.physmem.readBursts 412018 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 292348 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 26233536 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 135616 # Total number of bytes read from write queue 49system.physmem.bytesWritten 18708736 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 26369152 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 18710272 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 2119 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 26413 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25441 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25280 # Per bank write bursts 58system.physmem.perBankRdBursts::3 24861 # Per bank write bursts 59system.physmem.perBankRdBursts::4 26943 # Per bank write bursts 60system.physmem.perBankRdBursts::5 26409 # Per bank write bursts 61system.physmem.perBankRdBursts::6 25350 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24226 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25719 # Per bank write bursts 64system.physmem.perBankRdBursts::9 24800 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25359 # Per bank write bursts 66system.physmem.perBankRdBursts::11 26216 # Per bank write bursts 67system.physmem.perBankRdBursts::12 26433 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25856 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25009 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25584 # Per bank write bursts 71system.physmem.perBankWrBursts::0 18684 # Per bank write bursts 72system.physmem.perBankWrBursts::1 18331 # Per bank write bursts 73system.physmem.perBankWrBursts::2 18001 # Per bank write bursts 74system.physmem.perBankWrBursts::3 18053 # Per bank write bursts 75system.physmem.perBankWrBursts::4 18581 # Per bank write bursts 76system.physmem.perBankWrBursts::5 18287 # Per bank write bursts 77system.physmem.perBankWrBursts::6 18028 # Per bank write bursts 78system.physmem.perBankWrBursts::7 17667 # Per bank write bursts 79system.physmem.perBankWrBursts::8 18026 # Per bank write bursts 80system.physmem.perBankWrBursts::9 17689 # Per bank write bursts 81system.physmem.perBankWrBursts::10 18246 # Per bank write bursts 82system.physmem.perBankWrBursts::11 18799 # Per bank write bursts 83system.physmem.perBankWrBursts::12 18831 # Per bank write bursts 84system.physmem.perBankWrBursts::13 18312 # Per bank write bursts 85system.physmem.perBankWrBursts::14 18349 # Per bank write bursts 86system.physmem.perBankWrBursts::15 18440 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 233381437000 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 412018 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 292348 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 312437 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 47937 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 13197 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 9328 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 7381 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 5333 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4454 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3421 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 72 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 17 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 6242 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 6513 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 15344 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 16357 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 16904 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 17203 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 17602 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 17794 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 18042 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 18396 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 18527 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 18799 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 19969 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 18456 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 17828 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 49 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 307121 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 146.330964 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 102.916756 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 182.072957 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 184589 60.10% 60.10% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 81854 26.65% 86.76% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 16654 5.42% 92.18% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 7226 2.35% 94.53% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 4782 1.56% 96.09% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 2270 0.74% 96.83% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1753 0.57% 97.40% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1588 0.52% 97.91% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 6405 2.09% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 307121 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 17353 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 23.620930 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 116.705820 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-511 17352 99.99% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::total 17353 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 17353 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.845733 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.805125 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 1.212117 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16 10719 61.77% 61.77% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::17 285 1.64% 63.41% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 5449 31.40% 94.81% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::19 585 3.37% 98.18% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20 128 0.74% 98.92% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::21 65 0.37% 99.30% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::22 37 0.21% 99.51% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::23 35 0.20% 99.71% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::24 29 0.17% 99.88% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::25 15 0.09% 99.97% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::26 4 0.02% 99.99% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 17353 # Writes before turning the bus around for reads 238system.physmem.totQLat 9387910450 # Total ticks spent queuing 239system.physmem.totMemAccLat 17073516700 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 2049495000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 22902.98 # Average queueing delay per DRAM burst 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 243system.physmem.avgMemAccLat 41652.98 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 112.41 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 112.99 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 80.17 # Average system write bandwidth in MiByte/s 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 1.50 # Data bus utilization in percentage 250system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 21.73 # Average write queue length when enqueuing 254system.physmem.readRowHits 299659 # Number of row buffer hits during reads 255system.physmem.writeRowHits 95432 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 73.11 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 32.64 # Row buffer hit rate for writes 258system.physmem.avgGap 331335.47 # Average gap between requests 259system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined 260system.physmem_0.actEnergy 1156453200 # Energy for activate commands per rank (pJ) 261system.physmem_0.preEnergy 631001250 # Energy for precharge commands per rank (pJ) 262system.physmem_0.readEnergy 1598134200 # Energy for read commands per rank (pJ) 263system.physmem_0.writeEnergy 943500960 # Energy for write commands per rank (pJ) 264system.physmem_0.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) 265system.physmem_0.actBackEnergy 74948893020 # Energy for active background per rank (pJ) 266system.physmem_0.preBackEnergy 74281875750 # Energy for precharge background per rank (pJ) 267system.physmem_0.totalEnergy 168802927260 # Total energy per rank (pJ) 268system.physmem_0.averagePower 723.304109 # Core power per rank (mW) 269system.physmem_0.memoryStateTime::IDLE 123045424463 # Time in different power states 270system.physmem_0.memoryStateTime::REF 7792980000 # Time in different power states 271system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 272system.physmem_0.memoryStateTime::ACT 102539140537 # Time in different power states 273system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 274system.physmem_1.actEnergy 1165048920 # Energy for activate commands per rank (pJ) 275system.physmem_1.preEnergy 635691375 # Energy for precharge commands per rank (pJ) 276system.physmem_1.readEnergy 1598610000 # Energy for read commands per rank (pJ) 277system.physmem_1.writeEnergy 950447520 # Energy for write commands per rank (pJ) 278system.physmem_1.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) 279system.physmem_1.actBackEnergy 74482095510 # Energy for active background per rank (pJ) 280system.physmem_1.preBackEnergy 74691339000 # Energy for precharge background per rank (pJ) 281system.physmem_1.totalEnergy 168766301205 # Total energy per rank (pJ) 282system.physmem_1.averagePower 723.147212 # Core power per rank (mW) 283system.physmem_1.memoryStateTime::IDLE 123736015873 # Time in different power states 284system.physmem_1.memoryStateTime::REF 7792980000 # Time in different power states 285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 286system.physmem_1.memoryStateTime::ACT 101848756127 # Time in different power states 287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 288system.cpu.branchPred.lookups 175093442 # Number of BP lookups 289system.cpu.branchPred.condPredicted 131339013 # Number of conditional branches predicted 290system.cpu.branchPred.condIncorrect 7445255 # Number of conditional branches incorrect 291system.cpu.branchPred.BTBLookups 90524838 # Number of BTB lookups 292system.cpu.branchPred.BTBHits 83882931 # Number of BTB hits 293system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 294system.cpu.branchPred.BTBHitPct 92.662890 # BTB Hit Percentage 295system.cpu.branchPred.usedRAS 12110656 # Number of times the RAS was used to get a target. 296system.cpu.branchPred.RASInCorrect 104163 # Number of incorrect RAS predictions. 297system.cpu_clk_domain.clock 500 # Clock period in ticks 298system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 307system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 308system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 309system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 310system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 311system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 314system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 315system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 316system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 317system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 318system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 319system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 320system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 321system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 322system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 323system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 324system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 325system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 326system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 327system.cpu.dtb.walker.walks 0 # Table walker walks requested 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.inst_hits 0 # ITB inst hits 336system.cpu.dtb.inst_misses 0 # ITB inst misses 337system.cpu.dtb.read_hits 0 # DTB read hits 338system.cpu.dtb.read_misses 0 # DTB read misses 339system.cpu.dtb.write_hits 0 # DTB write hits 340system.cpu.dtb.write_misses 0 # DTB write misses 341system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 342system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 343system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 344system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 345system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 346system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 347system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 348system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 349system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 350system.cpu.dtb.read_accesses 0 # DTB read accesses 351system.cpu.dtb.write_accesses 0 # DTB write accesses 352system.cpu.dtb.inst_accesses 0 # ITB inst accesses 353system.cpu.dtb.hits 0 # DTB hits 354system.cpu.dtb.misses 0 # DTB misses 355system.cpu.dtb.accesses 0 # DTB accesses 356system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 365system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 366system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 367system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 368system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 369system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 372system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 373system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 374system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 375system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 376system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 377system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 378system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 379system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 380system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 381system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 382system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 383system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 384system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 385system.cpu.itb.walker.walks 0 # Table walker walks requested 386system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.inst_hits 0 # ITB inst hits 394system.cpu.itb.inst_misses 0 # ITB inst misses 395system.cpu.itb.read_hits 0 # DTB read hits 396system.cpu.itb.read_misses 0 # DTB read misses 397system.cpu.itb.write_hits 0 # DTB write hits 398system.cpu.itb.write_misses 0 # DTB write misses 399system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 400system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 401system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 402system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 403system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 404system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 405system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 406system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 407system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu.itb.read_accesses 0 # DTB read accesses 409system.cpu.itb.write_accesses 0 # DTB write accesses 410system.cpu.itb.inst_accesses 0 # ITB inst accesses 411system.cpu.itb.hits 0 # DTB hits 412system.cpu.itb.misses 0 # DTB misses 413system.cpu.itb.accesses 0 # DTB accesses 414system.cpu.workload.num_syscalls 548 # Number of system calls 415system.cpu.numCycles 466763048 # number of cpu cycles simulated 416system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 417system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 418system.cpu.fetch.icacheStallCycles 7833738 # Number of cycles fetch is stalled on an Icache miss 419system.cpu.fetch.Insts 731827371 # Number of instructions fetch has processed 420system.cpu.fetch.Branches 175093442 # Number of branches that fetch encountered 421system.cpu.fetch.predictedBranches 95993587 # Number of branches that fetch has predicted taken 422system.cpu.fetch.Cycles 450556948 # Number of cycles fetch has run and was not squashing or blocked 423system.cpu.fetch.SquashCycles 14942959 # Number of cycles fetch has spent squashing 424system.cpu.fetch.MiscStallCycles 6375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 425system.cpu.fetch.PendingTrapStallCycles 162 # Number of stall cycles due to pending traps 426system.cpu.fetch.IcacheWaitRetryStallCycles 12684 # Number of stall cycles due to full MSHR 427system.cpu.fetch.CacheLines 236728618 # Number of cache lines fetched 428system.cpu.fetch.IcacheSquashes 34396 # Number of outstanding Icache misses that were squashed 429system.cpu.fetch.rateDist::samples 465881386 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::mean 1.701216 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::stdev 1.179605 # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 433system.cpu.fetch.rateDist::0 93942381 20.16% 20.16% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::1 132696529 28.48% 48.65% # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::2 57859169 12.42% 61.07% # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::3 181383307 38.93% 100.00% # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::total 465881386 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.branchRate 0.375123 # Number of branch fetches per cycle 442system.cpu.fetch.rate 1.567878 # Number of inst fetches per cycle 443system.cpu.decode.IdleCycles 32362328 # Number of cycles decode is idle 444system.cpu.decode.BlockedCycles 117422213 # Number of cycles decode is blocked 445system.cpu.decode.RunCycles 287082190 # Number of cycles decode is running 446system.cpu.decode.UnblockCycles 22031979 # Number of cycles decode is unblocking 447system.cpu.decode.SquashCycles 6982676 # Number of cycles decode is squashing 448system.cpu.decode.BranchResolved 24051776 # Number of times decode resolved a branch 449system.cpu.decode.BranchMispred 496598 # Number of times decode detected a branch misprediction 450system.cpu.decode.DecodedInsts 715820836 # Number of instructions handled by decode 451system.cpu.decode.SquashedInsts 30011268 # Number of squashed instructions handled by decode 452system.cpu.rename.SquashCycles 6982676 # Number of cycles rename is squashing 453system.cpu.rename.IdleCycles 63423410 # Number of cycles rename is idle 454system.cpu.rename.BlockCycles 54356901 # Number of cycles rename is blocking 455system.cpu.rename.serializeStallCycles 40333857 # count of cycles rename stalled for serializing inst 456system.cpu.rename.RunCycles 276674345 # Number of cycles rename is running 457system.cpu.rename.UnblockCycles 24110197 # Number of cycles rename is unblocking 458system.cpu.rename.RenamedInsts 686603373 # Number of instructions processed by rename 459system.cpu.rename.SquashedInsts 13342977 # Number of squashed instructions processed by rename 460system.cpu.rename.ROBFullEvents 9430232 # Number of times rename has blocked due to ROB full 461system.cpu.rename.IQFullEvents 2385222 # Number of times rename has blocked due to IQ full 462system.cpu.rename.LQFullEvents 1668168 # Number of times rename has blocked due to LQ full 463system.cpu.rename.SQFullEvents 1866322 # Number of times rename has blocked due to SQ full 464system.cpu.rename.RenamedOperands 831029947 # Number of destination operands rename has renamed 465system.cpu.rename.RenameLookups 3019214336 # Number of register rename lookups that rename has made 466system.cpu.rename.int_rename_lookups 723928049 # Number of integer rename lookups 467system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 468system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed 469system.cpu.rename.UndoneMaps 176906196 # Number of HB maps that are undone due to squashing 470system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed 471system.cpu.rename.tempSerializingInsts 1534779 # count of temporary serializing insts renamed 472system.cpu.rename.skidInsts 42310456 # count of insts added to the skid buffer 473system.cpu.memDep0.insertedLoads 143529227 # Number of loads inserted to the mem dependence unit. 474system.cpu.memDep0.insertedStores 67980457 # Number of stores inserted to the mem dependence unit. 475system.cpu.memDep0.conflictingLoads 12876117 # Number of conflicting loads. 476system.cpu.memDep0.conflictingStores 11223865 # Number of conflicting stores. 477system.cpu.iq.iqInstsAdded 668168633 # Number of instructions added to the IQ (excludes non-spec) 478system.cpu.iq.iqNonSpecInstsAdded 2978333 # Number of non-speculative instructions added to the IQ 479system.cpu.iq.iqInstsIssued 610244720 # Number of instructions issued 480system.cpu.iq.iqSquashedInstsIssued 5860928 # Number of squashed instructions issued 481system.cpu.iq.iqSquashedInstsExamined 122748160 # Number of squashed instructions iterated over during squash; mainly for profiling 482system.cpu.iq.iqSquashedOperandsExamined 319249921 # Number of squashed operands that are examined and possibly removed from graph 483system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed 484system.cpu.iq.issued_per_cycle::samples 465881386 # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::mean 1.309871 # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::stdev 1.101485 # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::0 148726725 31.92% 31.92% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::1 101219272 21.73% 53.65% # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::2 145704053 31.27% 84.93% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::3 63308472 13.59% 98.51% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::4 6922394 1.49% 100.00% # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::total 465881386 # Number of insts issued each cycle 501system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 502system.cpu.iq.fu_full::IntAlu 71926892 52.97% 52.97% # attempts to use FU when none available 503system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available 504system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available 505system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available 506system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available 507system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available 508system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available 509system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available 510system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available 531system.cpu.iq.fu_full::MemRead 44548808 32.81% 85.78% # attempts to use FU when none available 532system.cpu.iq.fu_full::MemWrite 19308609 14.22% 100.00% # attempts to use FU when none available 533system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 534system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 535system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 536system.cpu.iq.FU_type_0::IntAlu 413151205 67.70% 67.70% # Type of FU issued 537system.cpu.iq.FU_type_0::IntMult 351762 0.06% 67.76% # Type of FU issued 538system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 541system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 542system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 543system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 544system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 565system.cpu.iq.FU_type_0::MemRead 134213175 21.99% 89.75% # Type of FU issued 566system.cpu.iq.FU_type_0::MemWrite 62528575 10.25% 100.00% # Type of FU issued 567system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 568system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 569system.cpu.iq.FU_type_0::total 610244720 # Type of FU issued 570system.cpu.iq.rate 1.307397 # Inst issue rate 571system.cpu.iq.fu_busy_cnt 135784339 # FU busy when requested 572system.cpu.iq.fu_busy_rate 0.222508 # FU busy rate (busy events/executed inst) 573system.cpu.iq.int_inst_queue_reads 1828015800 # Number of integer instruction queue reads 574system.cpu.iq.int_inst_queue_writes 793923222 # Number of integer instruction queue writes 575system.cpu.iq.int_inst_queue_wakeup_accesses 594984495 # Number of integer instruction queue wakeup accesses 576system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads 577system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes 578system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 579system.cpu.iq.int_alu_accesses 746028882 # Number of integer alu accesses 580system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses 581system.cpu.iew.lsq.thread0.forwLoads 7272735 # Number of loads that had data forwarded from stores 582system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 583system.cpu.iew.lsq.thread0.squashedLoads 27644471 # Number of loads squashed 584system.cpu.iew.lsq.thread0.ignoredResponses 25523 # Number of memory responses ignored because the instruction is squashed 585system.cpu.iew.lsq.thread0.memOrderViolation 28862 # Number of memory ordering violations 586system.cpu.iew.lsq.thread0.squashedStores 11119980 # Number of stores squashed 587system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 588system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 589system.cpu.iew.lsq.thread0.rescheduledLoads 225173 # Number of loads that were rescheduled 590system.cpu.iew.lsq.thread0.cacheBlocked 19543 # Number of times an access to memory failed due to the cache being blocked 591system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 592system.cpu.iew.iewSquashCycles 6982676 # Number of cycles IEW is squashing 593system.cpu.iew.iewBlockCycles 23041794 # Number of cycles IEW is blocking 594system.cpu.iew.iewUnblockCycles 922625 # Number of cycles IEW is unblocking 595system.cpu.iew.iewDispatchedInsts 672634659 # Number of instructions dispatched to IQ 596system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 597system.cpu.iew.iewDispLoadInsts 143529227 # Number of dispatched load instructions 598system.cpu.iew.iewDispStoreInsts 67980457 # Number of dispatched store instructions 599system.cpu.iew.iewDispNonSpecInsts 1489791 # Number of dispatched non-speculative instructions 600system.cpu.iew.iewIQFullEvents 257738 # Number of times the IQ has become full, causing a stall 601system.cpu.iew.iewLSQFullEvents 528673 # Number of times the LSQ has become full, causing a stall 602system.cpu.iew.memOrderViolationEvents 28862 # Number of memory order violations 603system.cpu.iew.predictedTakenIncorrect 3822612 # Number of branches that were predicted taken incorrectly 604system.cpu.iew.predictedNotTakenIncorrect 3731799 # Number of branches that were predicted not taken incorrectly 605system.cpu.iew.branchMispredicts 7554411 # Number of branch mispredicts detected at execute 606system.cpu.iew.iewExecutedInsts 599400407 # Number of executed instructions 607system.cpu.iew.iewExecLoadInsts 129575642 # Number of load instructions executed 608system.cpu.iew.iewExecSquashedInsts 10844313 # Number of squashed instructions skipped in execute 609system.cpu.iew.exec_swp 0 # number of swp insts executed 610system.cpu.iew.exec_nop 1487693 # number of nop insts executed 611system.cpu.iew.exec_refs 190530493 # number of memory reference insts executed 612system.cpu.iew.exec_branches 131374378 # Number of branches executed 613system.cpu.iew.exec_stores 60954851 # Number of stores executed 614system.cpu.iew.exec_rate 1.284164 # Inst execution rate 615system.cpu.iew.wb_sent 596279757 # cumulative count of insts sent to commit 616system.cpu.iew.wb_count 594984511 # cumulative count of insts written-back 617system.cpu.iew.wb_producers 349915362 # num instructions producing a value 618system.cpu.iew.wb_consumers 570660996 # num instructions consuming a value 619system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 620system.cpu.iew.wb_rate 1.274704 # insts written-back per cycle 621system.cpu.iew.wb_fanout 0.613176 # average fanout of values written-back 622system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 623system.cpu.commit.commitSquashedInsts 110032490 # The number of squashed insts skipped by commit 624system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 625system.cpu.commit.branchMispredicts 6956452 # The number of times a branch was mispredicted 626system.cpu.commit.committed_per_cycle::samples 448764802 # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::mean 1.222678 # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::stdev 1.888107 # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::0 219732753 48.96% 48.96% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::1 116339584 25.92% 74.89% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::2 43745322 9.75% 84.64% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::3 23276938 5.19% 89.82% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::4 11568250 2.58% 92.40% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::5 7761637 1.73% 94.13% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::6 8261110 1.84% 95.97% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::7 4247723 0.95% 96.92% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::8 13831485 3.08% 100.00% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::total 448764802 # Number of insts commited each cycle 643system.cpu.commit.committedInsts 506581607 # Number of instructions committed 644system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed 645system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 646system.cpu.commit.refs 172745233 # Number of memory references committed 647system.cpu.commit.loads 115884756 # Number of loads committed 648system.cpu.commit.membars 1488542 # Number of memory barriers committed 649system.cpu.commit.branches 121548301 # Number of branches committed 650system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 651system.cpu.commit.int_insts 448454354 # Number of committed integer instructions. 652system.cpu.commit.function_calls 9757362 # Number of function calls committed. 653system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction 655system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 656system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 657system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 658system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 659system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 660system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 661system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 662system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 683system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 684system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 687system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction 688system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.233382 # Number of seconds simulated 4sim_ticks 233381523500 # Number of ticks simulated 5final_tick 233381523500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 139639 # Simulator instruction rate (inst/s) 8host_op_rate 151279 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 64502789 # Simulator tick rate (ticks/s) 10host_mem_usage 317896 # Number of bytes of host memory used 11host_seconds 3618.16 # Real time elapsed on the host 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 547350944 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 689856 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9181056 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 16498240 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26369152 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 689856 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 689856 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18710272 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18710272 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 10779 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 143454 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 257785 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 412018 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 292348 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 292348 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 2955915 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 39339258 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 70692143 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 112987316 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 2955915 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 2955915 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 80170322 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 80170322 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 80170322 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 2955915 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 39339258 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 70692143 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 193157639 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 412018 # Number of read requests accepted 44system.physmem.writeReqs 292348 # Number of write requests accepted 45system.physmem.readBursts 412018 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 292348 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 26233536 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 135616 # Total number of bytes read from write queue 49system.physmem.bytesWritten 18708736 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 26369152 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 18710272 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 2119 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 26413 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25441 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25280 # Per bank write bursts 58system.physmem.perBankRdBursts::3 24861 # Per bank write bursts 59system.physmem.perBankRdBursts::4 26943 # Per bank write bursts 60system.physmem.perBankRdBursts::5 26409 # Per bank write bursts 61system.physmem.perBankRdBursts::6 25350 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24226 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25719 # Per bank write bursts 64system.physmem.perBankRdBursts::9 24800 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25359 # Per bank write bursts 66system.physmem.perBankRdBursts::11 26216 # Per bank write bursts 67system.physmem.perBankRdBursts::12 26433 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25856 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25009 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25584 # Per bank write bursts 71system.physmem.perBankWrBursts::0 18684 # Per bank write bursts 72system.physmem.perBankWrBursts::1 18331 # Per bank write bursts 73system.physmem.perBankWrBursts::2 18001 # Per bank write bursts 74system.physmem.perBankWrBursts::3 18053 # Per bank write bursts 75system.physmem.perBankWrBursts::4 18581 # Per bank write bursts 76system.physmem.perBankWrBursts::5 18287 # Per bank write bursts 77system.physmem.perBankWrBursts::6 18028 # Per bank write bursts 78system.physmem.perBankWrBursts::7 17667 # Per bank write bursts 79system.physmem.perBankWrBursts::8 18026 # Per bank write bursts 80system.physmem.perBankWrBursts::9 17689 # Per bank write bursts 81system.physmem.perBankWrBursts::10 18246 # Per bank write bursts 82system.physmem.perBankWrBursts::11 18799 # Per bank write bursts 83system.physmem.perBankWrBursts::12 18831 # Per bank write bursts 84system.physmem.perBankWrBursts::13 18312 # Per bank write bursts 85system.physmem.perBankWrBursts::14 18349 # Per bank write bursts 86system.physmem.perBankWrBursts::15 18440 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 233381437000 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 412018 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 292348 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 312437 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 47937 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 13197 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 9328 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 7381 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 5333 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4454 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3421 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 72 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 17 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 6242 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 6513 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 15344 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 16357 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 16904 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 17203 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 17602 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 17794 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 18042 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 18396 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 18527 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 18799 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 19969 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 18456 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 17828 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 49 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 307121 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 146.330964 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 102.916756 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 182.072957 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 184589 60.10% 60.10% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 81854 26.65% 86.76% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 16654 5.42% 92.18% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 7226 2.35% 94.53% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 4782 1.56% 96.09% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 2270 0.74% 96.83% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1753 0.57% 97.40% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1588 0.52% 97.91% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 6405 2.09% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 307121 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 17353 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 23.620930 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 116.705820 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-511 17352 99.99% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::total 17353 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 17353 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.845733 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.805125 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 1.212117 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16 10719 61.77% 61.77% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::17 285 1.64% 63.41% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 5449 31.40% 94.81% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::19 585 3.37% 98.18% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20 128 0.74% 98.92% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::21 65 0.37% 99.30% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::22 37 0.21% 99.51% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::23 35 0.20% 99.71% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::24 29 0.17% 99.88% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::25 15 0.09% 99.97% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::26 4 0.02% 99.99% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 17353 # Writes before turning the bus around for reads 238system.physmem.totQLat 9387910450 # Total ticks spent queuing 239system.physmem.totMemAccLat 17073516700 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 2049495000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 22902.98 # Average queueing delay per DRAM burst 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 243system.physmem.avgMemAccLat 41652.98 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 112.41 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 112.99 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 80.17 # Average system write bandwidth in MiByte/s 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 1.50 # Data bus utilization in percentage 250system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 21.73 # Average write queue length when enqueuing 254system.physmem.readRowHits 299659 # Number of row buffer hits during reads 255system.physmem.writeRowHits 95432 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 73.11 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 32.64 # Row buffer hit rate for writes 258system.physmem.avgGap 331335.47 # Average gap between requests 259system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined 260system.physmem_0.actEnergy 1156453200 # Energy for activate commands per rank (pJ) 261system.physmem_0.preEnergy 631001250 # Energy for precharge commands per rank (pJ) 262system.physmem_0.readEnergy 1598134200 # Energy for read commands per rank (pJ) 263system.physmem_0.writeEnergy 943500960 # Energy for write commands per rank (pJ) 264system.physmem_0.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) 265system.physmem_0.actBackEnergy 74948893020 # Energy for active background per rank (pJ) 266system.physmem_0.preBackEnergy 74281875750 # Energy for precharge background per rank (pJ) 267system.physmem_0.totalEnergy 168802927260 # Total energy per rank (pJ) 268system.physmem_0.averagePower 723.304109 # Core power per rank (mW) 269system.physmem_0.memoryStateTime::IDLE 123045424463 # Time in different power states 270system.physmem_0.memoryStateTime::REF 7792980000 # Time in different power states 271system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 272system.physmem_0.memoryStateTime::ACT 102539140537 # Time in different power states 273system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 274system.physmem_1.actEnergy 1165048920 # Energy for activate commands per rank (pJ) 275system.physmem_1.preEnergy 635691375 # Energy for precharge commands per rank (pJ) 276system.physmem_1.readEnergy 1598610000 # Energy for read commands per rank (pJ) 277system.physmem_1.writeEnergy 950447520 # Energy for write commands per rank (pJ) 278system.physmem_1.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) 279system.physmem_1.actBackEnergy 74482095510 # Energy for active background per rank (pJ) 280system.physmem_1.preBackEnergy 74691339000 # Energy for precharge background per rank (pJ) 281system.physmem_1.totalEnergy 168766301205 # Total energy per rank (pJ) 282system.physmem_1.averagePower 723.147212 # Core power per rank (mW) 283system.physmem_1.memoryStateTime::IDLE 123736015873 # Time in different power states 284system.physmem_1.memoryStateTime::REF 7792980000 # Time in different power states 285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 286system.physmem_1.memoryStateTime::ACT 101848756127 # Time in different power states 287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 288system.cpu.branchPred.lookups 175093442 # Number of BP lookups 289system.cpu.branchPred.condPredicted 131339013 # Number of conditional branches predicted 290system.cpu.branchPred.condIncorrect 7445255 # Number of conditional branches incorrect 291system.cpu.branchPred.BTBLookups 90524838 # Number of BTB lookups 292system.cpu.branchPred.BTBHits 83882931 # Number of BTB hits 293system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 294system.cpu.branchPred.BTBHitPct 92.662890 # BTB Hit Percentage 295system.cpu.branchPred.usedRAS 12110656 # Number of times the RAS was used to get a target. 296system.cpu.branchPred.RASInCorrect 104163 # Number of incorrect RAS predictions. 297system.cpu_clk_domain.clock 500 # Clock period in ticks 298system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 307system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 308system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 309system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 310system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 311system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 314system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 315system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 316system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 317system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 318system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 319system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 320system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 321system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 322system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 323system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 324system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 325system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 326system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 327system.cpu.dtb.walker.walks 0 # Table walker walks requested 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.inst_hits 0 # ITB inst hits 336system.cpu.dtb.inst_misses 0 # ITB inst misses 337system.cpu.dtb.read_hits 0 # DTB read hits 338system.cpu.dtb.read_misses 0 # DTB read misses 339system.cpu.dtb.write_hits 0 # DTB write hits 340system.cpu.dtb.write_misses 0 # DTB write misses 341system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 342system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 343system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 344system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 345system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 346system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 347system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 348system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 349system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 350system.cpu.dtb.read_accesses 0 # DTB read accesses 351system.cpu.dtb.write_accesses 0 # DTB write accesses 352system.cpu.dtb.inst_accesses 0 # ITB inst accesses 353system.cpu.dtb.hits 0 # DTB hits 354system.cpu.dtb.misses 0 # DTB misses 355system.cpu.dtb.accesses 0 # DTB accesses 356system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 365system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 366system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 367system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 368system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 369system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 372system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 373system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 374system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 375system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 376system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 377system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 378system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 379system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 380system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 381system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 382system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 383system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 384system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 385system.cpu.itb.walker.walks 0 # Table walker walks requested 386system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.inst_hits 0 # ITB inst hits 394system.cpu.itb.inst_misses 0 # ITB inst misses 395system.cpu.itb.read_hits 0 # DTB read hits 396system.cpu.itb.read_misses 0 # DTB read misses 397system.cpu.itb.write_hits 0 # DTB write hits 398system.cpu.itb.write_misses 0 # DTB write misses 399system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 400system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 401system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 402system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 403system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 404system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 405system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 406system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 407system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu.itb.read_accesses 0 # DTB read accesses 409system.cpu.itb.write_accesses 0 # DTB write accesses 410system.cpu.itb.inst_accesses 0 # ITB inst accesses 411system.cpu.itb.hits 0 # DTB hits 412system.cpu.itb.misses 0 # DTB misses 413system.cpu.itb.accesses 0 # DTB accesses 414system.cpu.workload.num_syscalls 548 # Number of system calls 415system.cpu.numCycles 466763048 # number of cpu cycles simulated 416system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 417system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 418system.cpu.fetch.icacheStallCycles 7833738 # Number of cycles fetch is stalled on an Icache miss 419system.cpu.fetch.Insts 731827371 # Number of instructions fetch has processed 420system.cpu.fetch.Branches 175093442 # Number of branches that fetch encountered 421system.cpu.fetch.predictedBranches 95993587 # Number of branches that fetch has predicted taken 422system.cpu.fetch.Cycles 450556948 # Number of cycles fetch has run and was not squashing or blocked 423system.cpu.fetch.SquashCycles 14942959 # Number of cycles fetch has spent squashing 424system.cpu.fetch.MiscStallCycles 6375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 425system.cpu.fetch.PendingTrapStallCycles 162 # Number of stall cycles due to pending traps 426system.cpu.fetch.IcacheWaitRetryStallCycles 12684 # Number of stall cycles due to full MSHR 427system.cpu.fetch.CacheLines 236728618 # Number of cache lines fetched 428system.cpu.fetch.IcacheSquashes 34396 # Number of outstanding Icache misses that were squashed 429system.cpu.fetch.rateDist::samples 465881386 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::mean 1.701216 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::stdev 1.179605 # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 433system.cpu.fetch.rateDist::0 93942381 20.16% 20.16% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::1 132696529 28.48% 48.65% # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::2 57859169 12.42% 61.07% # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::3 181383307 38.93% 100.00% # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::total 465881386 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.branchRate 0.375123 # Number of branch fetches per cycle 442system.cpu.fetch.rate 1.567878 # Number of inst fetches per cycle 443system.cpu.decode.IdleCycles 32362328 # Number of cycles decode is idle 444system.cpu.decode.BlockedCycles 117422213 # Number of cycles decode is blocked 445system.cpu.decode.RunCycles 287082190 # Number of cycles decode is running 446system.cpu.decode.UnblockCycles 22031979 # Number of cycles decode is unblocking 447system.cpu.decode.SquashCycles 6982676 # Number of cycles decode is squashing 448system.cpu.decode.BranchResolved 24051776 # Number of times decode resolved a branch 449system.cpu.decode.BranchMispred 496598 # Number of times decode detected a branch misprediction 450system.cpu.decode.DecodedInsts 715820836 # Number of instructions handled by decode 451system.cpu.decode.SquashedInsts 30011268 # Number of squashed instructions handled by decode 452system.cpu.rename.SquashCycles 6982676 # Number of cycles rename is squashing 453system.cpu.rename.IdleCycles 63423410 # Number of cycles rename is idle 454system.cpu.rename.BlockCycles 54356901 # Number of cycles rename is blocking 455system.cpu.rename.serializeStallCycles 40333857 # count of cycles rename stalled for serializing inst 456system.cpu.rename.RunCycles 276674345 # Number of cycles rename is running 457system.cpu.rename.UnblockCycles 24110197 # Number of cycles rename is unblocking 458system.cpu.rename.RenamedInsts 686603373 # Number of instructions processed by rename 459system.cpu.rename.SquashedInsts 13342977 # Number of squashed instructions processed by rename 460system.cpu.rename.ROBFullEvents 9430232 # Number of times rename has blocked due to ROB full 461system.cpu.rename.IQFullEvents 2385222 # Number of times rename has blocked due to IQ full 462system.cpu.rename.LQFullEvents 1668168 # Number of times rename has blocked due to LQ full 463system.cpu.rename.SQFullEvents 1866322 # Number of times rename has blocked due to SQ full 464system.cpu.rename.RenamedOperands 831029947 # Number of destination operands rename has renamed 465system.cpu.rename.RenameLookups 3019214336 # Number of register rename lookups that rename has made 466system.cpu.rename.int_rename_lookups 723928049 # Number of integer rename lookups 467system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 468system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed 469system.cpu.rename.UndoneMaps 176906196 # Number of HB maps that are undone due to squashing 470system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed 471system.cpu.rename.tempSerializingInsts 1534779 # count of temporary serializing insts renamed 472system.cpu.rename.skidInsts 42310456 # count of insts added to the skid buffer 473system.cpu.memDep0.insertedLoads 143529227 # Number of loads inserted to the mem dependence unit. 474system.cpu.memDep0.insertedStores 67980457 # Number of stores inserted to the mem dependence unit. 475system.cpu.memDep0.conflictingLoads 12876117 # Number of conflicting loads. 476system.cpu.memDep0.conflictingStores 11223865 # Number of conflicting stores. 477system.cpu.iq.iqInstsAdded 668168633 # Number of instructions added to the IQ (excludes non-spec) 478system.cpu.iq.iqNonSpecInstsAdded 2978333 # Number of non-speculative instructions added to the IQ 479system.cpu.iq.iqInstsIssued 610244720 # Number of instructions issued 480system.cpu.iq.iqSquashedInstsIssued 5860928 # Number of squashed instructions issued 481system.cpu.iq.iqSquashedInstsExamined 122748160 # Number of squashed instructions iterated over during squash; mainly for profiling 482system.cpu.iq.iqSquashedOperandsExamined 319249921 # Number of squashed operands that are examined and possibly removed from graph 483system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed 484system.cpu.iq.issued_per_cycle::samples 465881386 # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::mean 1.309871 # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::stdev 1.101485 # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::0 148726725 31.92% 31.92% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::1 101219272 21.73% 53.65% # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::2 145704053 31.27% 84.93% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::3 63308472 13.59% 98.51% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::4 6922394 1.49% 100.00% # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::total 465881386 # Number of insts issued each cycle 501system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 502system.cpu.iq.fu_full::IntAlu 71926892 52.97% 52.97% # attempts to use FU when none available 503system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available 504system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available 505system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available 506system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available 507system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available 508system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available 509system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available 510system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available 531system.cpu.iq.fu_full::MemRead 44548808 32.81% 85.78% # attempts to use FU when none available 532system.cpu.iq.fu_full::MemWrite 19308609 14.22% 100.00% # attempts to use FU when none available 533system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 534system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 535system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 536system.cpu.iq.FU_type_0::IntAlu 413151205 67.70% 67.70% # Type of FU issued 537system.cpu.iq.FU_type_0::IntMult 351762 0.06% 67.76% # Type of FU issued 538system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 541system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 542system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 543system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 544system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 565system.cpu.iq.FU_type_0::MemRead 134213175 21.99% 89.75% # Type of FU issued 566system.cpu.iq.FU_type_0::MemWrite 62528575 10.25% 100.00% # Type of FU issued 567system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 568system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 569system.cpu.iq.FU_type_0::total 610244720 # Type of FU issued 570system.cpu.iq.rate 1.307397 # Inst issue rate 571system.cpu.iq.fu_busy_cnt 135784339 # FU busy when requested 572system.cpu.iq.fu_busy_rate 0.222508 # FU busy rate (busy events/executed inst) 573system.cpu.iq.int_inst_queue_reads 1828015800 # Number of integer instruction queue reads 574system.cpu.iq.int_inst_queue_writes 793923222 # Number of integer instruction queue writes 575system.cpu.iq.int_inst_queue_wakeup_accesses 594984495 # Number of integer instruction queue wakeup accesses 576system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads 577system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes 578system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 579system.cpu.iq.int_alu_accesses 746028882 # Number of integer alu accesses 580system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses 581system.cpu.iew.lsq.thread0.forwLoads 7272735 # Number of loads that had data forwarded from stores 582system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 583system.cpu.iew.lsq.thread0.squashedLoads 27644471 # Number of loads squashed 584system.cpu.iew.lsq.thread0.ignoredResponses 25523 # Number of memory responses ignored because the instruction is squashed 585system.cpu.iew.lsq.thread0.memOrderViolation 28862 # Number of memory ordering violations 586system.cpu.iew.lsq.thread0.squashedStores 11119980 # Number of stores squashed 587system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 588system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 589system.cpu.iew.lsq.thread0.rescheduledLoads 225173 # Number of loads that were rescheduled 590system.cpu.iew.lsq.thread0.cacheBlocked 19543 # Number of times an access to memory failed due to the cache being blocked 591system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 592system.cpu.iew.iewSquashCycles 6982676 # Number of cycles IEW is squashing 593system.cpu.iew.iewBlockCycles 23041794 # Number of cycles IEW is blocking 594system.cpu.iew.iewUnblockCycles 922625 # Number of cycles IEW is unblocking 595system.cpu.iew.iewDispatchedInsts 672634659 # Number of instructions dispatched to IQ 596system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 597system.cpu.iew.iewDispLoadInsts 143529227 # Number of dispatched load instructions 598system.cpu.iew.iewDispStoreInsts 67980457 # Number of dispatched store instructions 599system.cpu.iew.iewDispNonSpecInsts 1489791 # Number of dispatched non-speculative instructions 600system.cpu.iew.iewIQFullEvents 257738 # Number of times the IQ has become full, causing a stall 601system.cpu.iew.iewLSQFullEvents 528673 # Number of times the LSQ has become full, causing a stall 602system.cpu.iew.memOrderViolationEvents 28862 # Number of memory order violations 603system.cpu.iew.predictedTakenIncorrect 3822612 # Number of branches that were predicted taken incorrectly 604system.cpu.iew.predictedNotTakenIncorrect 3731799 # Number of branches that were predicted not taken incorrectly 605system.cpu.iew.branchMispredicts 7554411 # Number of branch mispredicts detected at execute 606system.cpu.iew.iewExecutedInsts 599400407 # Number of executed instructions 607system.cpu.iew.iewExecLoadInsts 129575642 # Number of load instructions executed 608system.cpu.iew.iewExecSquashedInsts 10844313 # Number of squashed instructions skipped in execute 609system.cpu.iew.exec_swp 0 # number of swp insts executed 610system.cpu.iew.exec_nop 1487693 # number of nop insts executed 611system.cpu.iew.exec_refs 190530493 # number of memory reference insts executed 612system.cpu.iew.exec_branches 131374378 # Number of branches executed 613system.cpu.iew.exec_stores 60954851 # Number of stores executed 614system.cpu.iew.exec_rate 1.284164 # Inst execution rate 615system.cpu.iew.wb_sent 596279757 # cumulative count of insts sent to commit 616system.cpu.iew.wb_count 594984511 # cumulative count of insts written-back 617system.cpu.iew.wb_producers 349915362 # num instructions producing a value 618system.cpu.iew.wb_consumers 570660996 # num instructions consuming a value 619system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 620system.cpu.iew.wb_rate 1.274704 # insts written-back per cycle 621system.cpu.iew.wb_fanout 0.613176 # average fanout of values written-back 622system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 623system.cpu.commit.commitSquashedInsts 110032490 # The number of squashed insts skipped by commit 624system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 625system.cpu.commit.branchMispredicts 6956452 # The number of times a branch was mispredicted 626system.cpu.commit.committed_per_cycle::samples 448764802 # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::mean 1.222678 # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::stdev 1.888107 # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::0 219732753 48.96% 48.96% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::1 116339584 25.92% 74.89% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::2 43745322 9.75% 84.64% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::3 23276938 5.19% 89.82% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::4 11568250 2.58% 92.40% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::5 7761637 1.73% 94.13% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::6 8261110 1.84% 95.97% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::7 4247723 0.95% 96.92% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::8 13831485 3.08% 100.00% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::total 448764802 # Number of insts commited each cycle 643system.cpu.commit.committedInsts 506581607 # Number of instructions committed 644system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed 645system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 646system.cpu.commit.refs 172745233 # Number of memory references committed 647system.cpu.commit.loads 115884756 # Number of loads committed 648system.cpu.commit.membars 1488542 # Number of memory barriers committed 649system.cpu.commit.branches 121548301 # Number of branches committed 650system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 651system.cpu.commit.int_insts 448454354 # Number of committed integer instructions. 652system.cpu.commit.function_calls 9757362 # Number of function calls committed. 653system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction 655system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 656system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 657system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 658system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 659system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 660system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 661system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 662system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 683system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 684system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 687system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction 688system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached |
| 689system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 690system.cpu.rob.rob_reads 1093653497 # The number of ROB reads 691system.cpu.rob.rob_writes 1334601058 # The number of ROB writes 692system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself 693system.cpu.idleCycles 881662 # Total number of cycles that the CPU has spent unscheduled due to idling 694system.cpu.committedInsts 505237723 # Number of Instructions Simulated 695system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated 696system.cpu.cpi 0.923848 # CPI: Cycles Per Instruction 697system.cpu.cpi_total 0.923848 # CPI: Total CPI of All Threads 698system.cpu.ipc 1.082429 # IPC: Instructions Per Cycle 699system.cpu.ipc_total 1.082429 # IPC: Total IPC of All Threads 700system.cpu.int_regfile_reads 611089137 # number of integer regfile reads 701system.cpu.int_regfile_writes 328121807 # number of integer regfile writes 702system.cpu.fp_regfile_reads 16 # number of floating regfile reads 703system.cpu.cc_regfile_reads 2170187431 # number of cc regfile reads 704system.cpu.cc_regfile_writes 376547848 # number of cc regfile writes 705system.cpu.misc_regfile_reads 217970630 # number of misc regfile reads 706system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 707system.cpu.dcache.tags.replacements 2821443 # number of replacements 708system.cpu.dcache.tags.tagsinuse 511.630682 # Cycle average of tags in use 709system.cpu.dcache.tags.total_refs 169417803 # Total number of references to valid blocks. 710system.cpu.dcache.tags.sampled_refs 2821955 # Sample count of references to valid blocks. 711system.cpu.dcache.tags.avg_refs 60.035615 # Average number of references to valid blocks. 712system.cpu.dcache.tags.warmup_cycle 498977500 # Cycle when the warmup percentage was hit. 713system.cpu.dcache.tags.occ_blocks::cpu.data 511.630682 # Average occupied blocks per requestor 714system.cpu.dcache.tags.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy 715system.cpu.dcache.tags.occ_percent::total 0.999279 # Average percentage of cache occupancy 716system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 717system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id 718system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id 719system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 720system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 721system.cpu.dcache.tags.tag_accesses 356251797 # Number of tag accesses 722system.cpu.dcache.tags.data_accesses 356251797 # Number of data accesses 723system.cpu.dcache.ReadReq_hits::cpu.data 114676407 # number of ReadReq hits 724system.cpu.dcache.ReadReq_hits::total 114676407 # number of ReadReq hits 725system.cpu.dcache.WriteReq_hits::cpu.data 51761464 # number of WriteReq hits 726system.cpu.dcache.WriteReq_hits::total 51761464 # number of WriteReq hits 727system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits 728system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits 729system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits 730system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits 731system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 732system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 733system.cpu.dcache.demand_hits::cpu.data 166437871 # number of demand (read+write) hits 734system.cpu.dcache.demand_hits::total 166437871 # number of demand (read+write) hits 735system.cpu.dcache.overall_hits::cpu.data 166440653 # number of overall hits 736system.cpu.dcache.overall_hits::total 166440653 # number of overall hits 737system.cpu.dcache.ReadReq_misses::cpu.data 4819248 # number of ReadReq misses 738system.cpu.dcache.ReadReq_misses::total 4819248 # number of ReadReq misses 739system.cpu.dcache.WriteReq_misses::cpu.data 2477842 # number of WriteReq misses 740system.cpu.dcache.WriteReq_misses::total 2477842 # number of WriteReq misses 741system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses 742system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses 743system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 744system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses 745system.cpu.dcache.demand_misses::cpu.data 7297090 # number of demand (read+write) misses 746system.cpu.dcache.demand_misses::total 7297090 # number of demand (read+write) misses 747system.cpu.dcache.overall_misses::cpu.data 7297102 # number of overall misses 748system.cpu.dcache.overall_misses::total 7297102 # number of overall misses 749system.cpu.dcache.ReadReq_miss_latency::cpu.data 56184151983 # number of ReadReq miss cycles 750system.cpu.dcache.ReadReq_miss_latency::total 56184151983 # number of ReadReq miss cycles 751system.cpu.dcache.WriteReq_miss_latency::cpu.data 18816988488 # number of WriteReq miss cycles 752system.cpu.dcache.WriteReq_miss_latency::total 18816988488 # number of WriteReq miss cycles 753system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1349500 # number of LoadLockedReq miss cycles 754system.cpu.dcache.LoadLockedReq_miss_latency::total 1349500 # number of LoadLockedReq miss cycles 755system.cpu.dcache.demand_miss_latency::cpu.data 75001140471 # number of demand (read+write) miss cycles 756system.cpu.dcache.demand_miss_latency::total 75001140471 # number of demand (read+write) miss cycles 757system.cpu.dcache.overall_miss_latency::cpu.data 75001140471 # number of overall miss cycles 758system.cpu.dcache.overall_miss_latency::total 75001140471 # number of overall miss cycles 759system.cpu.dcache.ReadReq_accesses::cpu.data 119495655 # number of ReadReq accesses(hits+misses) 760system.cpu.dcache.ReadReq_accesses::total 119495655 # number of ReadReq accesses(hits+misses) 761system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 762system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 763system.cpu.dcache.SoftPFReq_accesses::cpu.data 2794 # number of SoftPFReq accesses(hits+misses) 764system.cpu.dcache.SoftPFReq_accesses::total 2794 # number of SoftPFReq accesses(hits+misses) 765system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) 766system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) 767system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 768system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 769system.cpu.dcache.demand_accesses::cpu.data 173734961 # number of demand (read+write) accesses 770system.cpu.dcache.demand_accesses::total 173734961 # number of demand (read+write) accesses 771system.cpu.dcache.overall_accesses::cpu.data 173737755 # number of overall (read+write) accesses 772system.cpu.dcache.overall_accesses::total 173737755 # number of overall (read+write) accesses 773system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040330 # miss rate for ReadReq accesses 774system.cpu.dcache.ReadReq_miss_rate::total 0.040330 # miss rate for ReadReq accesses 775system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045684 # miss rate for WriteReq accesses 776system.cpu.dcache.WriteReq_miss_rate::total 0.045684 # miss rate for WriteReq accesses 777system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004295 # miss rate for SoftPFReq accesses 778system.cpu.dcache.SoftPFReq_miss_rate::total 0.004295 # miss rate for SoftPFReq accesses 779system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 780system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses 781system.cpu.dcache.demand_miss_rate::cpu.data 0.042001 # miss rate for demand accesses 782system.cpu.dcache.demand_miss_rate::total 0.042001 # miss rate for demand accesses 783system.cpu.dcache.overall_miss_rate::cpu.data 0.042001 # miss rate for overall accesses 784system.cpu.dcache.overall_miss_rate::total 0.042001 # miss rate for overall accesses 785system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11658.281952 # average ReadReq miss latency 786system.cpu.dcache.ReadReq_avg_miss_latency::total 11658.281952 # average ReadReq miss latency 787system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7594.103453 # average WriteReq miss latency 788system.cpu.dcache.WriteReq_avg_miss_latency::total 7594.103453 # average WriteReq miss latency 789system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20446.969697 # average LoadLockedReq miss latency 790system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20446.969697 # average LoadLockedReq miss latency 791system.cpu.dcache.demand_avg_miss_latency::cpu.data 10278.226042 # average overall miss latency 792system.cpu.dcache.demand_avg_miss_latency::total 10278.226042 # average overall miss latency 793system.cpu.dcache.overall_avg_miss_latency::cpu.data 10278.209140 # average overall miss latency 794system.cpu.dcache.overall_avg_miss_latency::total 10278.209140 # average overall miss latency 795system.cpu.dcache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked 796system.cpu.dcache.blocked_cycles::no_targets 705176 # number of cycles access was blocked 797system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked 798system.cpu.dcache.blocked::no_targets 220270 # number of cycles access was blocked 799system.cpu.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked 800system.cpu.dcache.avg_blocked_cycles::no_targets 3.201416 # average number of cycles each access was blocked 801system.cpu.dcache.fast_writes 0 # number of fast writes performed 802system.cpu.dcache.cache_copies 0 # number of cache copies performed 803system.cpu.dcache.writebacks::writebacks 2356074 # number of writebacks 804system.cpu.dcache.writebacks::total 2356074 # number of writebacks 805system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2516883 # number of ReadReq MSHR hits 806system.cpu.dcache.ReadReq_mshr_hits::total 2516883 # number of ReadReq MSHR hits 807system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1958234 # number of WriteReq MSHR hits 808system.cpu.dcache.WriteReq_mshr_hits::total 1958234 # number of WriteReq MSHR hits 809system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 810system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits 811system.cpu.dcache.demand_mshr_hits::cpu.data 4475117 # number of demand (read+write) MSHR hits 812system.cpu.dcache.demand_mshr_hits::total 4475117 # number of demand (read+write) MSHR hits 813system.cpu.dcache.overall_mshr_hits::cpu.data 4475117 # number of overall MSHR hits 814system.cpu.dcache.overall_mshr_hits::total 4475117 # number of overall MSHR hits 815system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2302365 # number of ReadReq MSHR misses 816system.cpu.dcache.ReadReq_mshr_misses::total 2302365 # number of ReadReq MSHR misses 817system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519608 # number of WriteReq MSHR misses 818system.cpu.dcache.WriteReq_mshr_misses::total 519608 # number of WriteReq MSHR misses 819system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 820system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 821system.cpu.dcache.demand_mshr_misses::cpu.data 2821973 # number of demand (read+write) MSHR misses 822system.cpu.dcache.demand_mshr_misses::total 2821973 # number of demand (read+write) MSHR misses 823system.cpu.dcache.overall_mshr_misses::cpu.data 2821983 # number of overall MSHR misses 824system.cpu.dcache.overall_mshr_misses::total 2821983 # number of overall MSHR misses 825system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27555148045 # number of ReadReq MSHR miss cycles 826system.cpu.dcache.ReadReq_mshr_miss_latency::total 27555148045 # number of ReadReq MSHR miss cycles 827system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4324407514 # number of WriteReq MSHR miss cycles 828system.cpu.dcache.WriteReq_mshr_miss_latency::total 4324407514 # number of WriteReq MSHR miss cycles 829system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 652250 # number of SoftPFReq MSHR miss cycles 830system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 652250 # number of SoftPFReq MSHR miss cycles 831system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31879555559 # number of demand (read+write) MSHR miss cycles 832system.cpu.dcache.demand_mshr_miss_latency::total 31879555559 # number of demand (read+write) MSHR miss cycles 833system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31880207809 # number of overall MSHR miss cycles 834system.cpu.dcache.overall_mshr_miss_latency::total 31880207809 # number of overall MSHR miss cycles 835system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019267 # mshr miss rate for ReadReq accesses 836system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019267 # mshr miss rate for ReadReq accesses 837system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses 838system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses 839system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003579 # mshr miss rate for SoftPFReq accesses 840system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003579 # mshr miss rate for SoftPFReq accesses 841system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for demand accesses 842system.cpu.dcache.demand_mshr_miss_rate::total 0.016243 # mshr miss rate for demand accesses 843system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for overall accesses 844system.cpu.dcache.overall_mshr_miss_rate::total 0.016243 # mshr miss rate for overall accesses 845system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11968.192726 # average ReadReq mshr miss latency 846system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11968.192726 # average ReadReq mshr miss latency 847system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8322.442137 # average WriteReq mshr miss latency 848system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8322.442137 # average WriteReq mshr miss latency 849system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65225 # average SoftPFReq mshr miss latency 850system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65225 # average SoftPFReq mshr miss latency 851system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11296.903110 # average overall mshr miss latency 852system.cpu.dcache.demand_avg_mshr_miss_latency::total 11296.903110 # average overall mshr miss latency 853system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11297.094210 # average overall mshr miss latency 854system.cpu.dcache.overall_avg_mshr_miss_latency::total 11297.094210 # average overall mshr miss latency 855system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 856system.cpu.icache.tags.replacements 73466 # number of replacements 857system.cpu.icache.tags.tagsinuse 466.200525 # Cycle average of tags in use 858system.cpu.icache.tags.total_refs 236646541 # Total number of references to valid blocks. 859system.cpu.icache.tags.sampled_refs 73978 # Sample count of references to valid blocks. 860system.cpu.icache.tags.avg_refs 3198.877247 # Average number of references to valid blocks. 861system.cpu.icache.tags.warmup_cycle 115003506250 # Cycle when the warmup percentage was hit. 862system.cpu.icache.tags.occ_blocks::cpu.inst 466.200525 # Average occupied blocks per requestor 863system.cpu.icache.tags.occ_percent::cpu.inst 0.910548 # Average percentage of cache occupancy 864system.cpu.icache.tags.occ_percent::total 0.910548 # Average percentage of cache occupancy 865system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 866system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 867system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 868system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id 869system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id 870system.cpu.icache.tags.age_task_id_blocks_1024::4 15 # Occupied blocks per task id 871system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 872system.cpu.icache.tags.tag_accesses 473531001 # Number of tag accesses 873system.cpu.icache.tags.data_accesses 473531001 # Number of data accesses 874system.cpu.icache.ReadReq_hits::cpu.inst 236646541 # number of ReadReq hits 875system.cpu.icache.ReadReq_hits::total 236646541 # number of ReadReq hits 876system.cpu.icache.demand_hits::cpu.inst 236646541 # number of demand (read+write) hits 877system.cpu.icache.demand_hits::total 236646541 # number of demand (read+write) hits 878system.cpu.icache.overall_hits::cpu.inst 236646541 # number of overall hits 879system.cpu.icache.overall_hits::total 236646541 # number of overall hits 880system.cpu.icache.ReadReq_misses::cpu.inst 81956 # number of ReadReq misses 881system.cpu.icache.ReadReq_misses::total 81956 # number of ReadReq misses 882system.cpu.icache.demand_misses::cpu.inst 81956 # number of demand (read+write) misses 883system.cpu.icache.demand_misses::total 81956 # number of demand (read+write) misses 884system.cpu.icache.overall_misses::cpu.inst 81956 # number of overall misses 885system.cpu.icache.overall_misses::total 81956 # number of overall misses 886system.cpu.icache.ReadReq_miss_latency::cpu.inst 1579166787 # number of ReadReq miss cycles 887system.cpu.icache.ReadReq_miss_latency::total 1579166787 # number of ReadReq miss cycles 888system.cpu.icache.demand_miss_latency::cpu.inst 1579166787 # number of demand (read+write) miss cycles 889system.cpu.icache.demand_miss_latency::total 1579166787 # number of demand (read+write) miss cycles 890system.cpu.icache.overall_miss_latency::cpu.inst 1579166787 # number of overall miss cycles 891system.cpu.icache.overall_miss_latency::total 1579166787 # number of overall miss cycles 892system.cpu.icache.ReadReq_accesses::cpu.inst 236728497 # number of ReadReq accesses(hits+misses) 893system.cpu.icache.ReadReq_accesses::total 236728497 # number of ReadReq accesses(hits+misses) 894system.cpu.icache.demand_accesses::cpu.inst 236728497 # number of demand (read+write) accesses 895system.cpu.icache.demand_accesses::total 236728497 # number of demand (read+write) accesses 896system.cpu.icache.overall_accesses::cpu.inst 236728497 # number of overall (read+write) accesses 897system.cpu.icache.overall_accesses::total 236728497 # number of overall (read+write) accesses 898system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses 899system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses 900system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses 901system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses 902system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses 903system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses 904system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19268.470728 # average ReadReq miss latency 905system.cpu.icache.ReadReq_avg_miss_latency::total 19268.470728 # average ReadReq miss latency 906system.cpu.icache.demand_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency 907system.cpu.icache.demand_avg_miss_latency::total 19268.470728 # average overall miss latency 908system.cpu.icache.overall_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency 909system.cpu.icache.overall_avg_miss_latency::total 19268.470728 # average overall miss latency 910system.cpu.icache.blocked_cycles::no_mshrs 192617 # number of cycles access was blocked 911system.cpu.icache.blocked_cycles::no_targets 91 # number of cycles access was blocked 912system.cpu.icache.blocked::no_mshrs 6539 # number of cycles access was blocked 913system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked 914system.cpu.icache.avg_blocked_cycles::no_mshrs 29.456645 # average number of cycles each access was blocked 915system.cpu.icache.avg_blocked_cycles::no_targets 22.750000 # average number of cycles each access was blocked 916system.cpu.icache.fast_writes 0 # number of fast writes performed 917system.cpu.icache.cache_copies 0 # number of cache copies performed 918system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7948 # number of ReadReq MSHR hits 919system.cpu.icache.ReadReq_mshr_hits::total 7948 # number of ReadReq MSHR hits 920system.cpu.icache.demand_mshr_hits::cpu.inst 7948 # number of demand (read+write) MSHR hits 921system.cpu.icache.demand_mshr_hits::total 7948 # number of demand (read+write) MSHR hits 922system.cpu.icache.overall_mshr_hits::cpu.inst 7948 # number of overall MSHR hits 923system.cpu.icache.overall_mshr_hits::total 7948 # number of overall MSHR hits 924system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74008 # number of ReadReq MSHR misses 925system.cpu.icache.ReadReq_mshr_misses::total 74008 # number of ReadReq MSHR misses 926system.cpu.icache.demand_mshr_misses::cpu.inst 74008 # number of demand (read+write) MSHR misses 927system.cpu.icache.demand_mshr_misses::total 74008 # number of demand (read+write) MSHR misses 928system.cpu.icache.overall_mshr_misses::cpu.inst 74008 # number of overall MSHR misses 929system.cpu.icache.overall_mshr_misses::total 74008 # number of overall MSHR misses 930system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1251050514 # number of ReadReq MSHR miss cycles 931system.cpu.icache.ReadReq_mshr_miss_latency::total 1251050514 # number of ReadReq MSHR miss cycles 932system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1251050514 # number of demand (read+write) MSHR miss cycles 933system.cpu.icache.demand_mshr_miss_latency::total 1251050514 # number of demand (read+write) MSHR miss cycles 934system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1251050514 # number of overall MSHR miss cycles 935system.cpu.icache.overall_mshr_miss_latency::total 1251050514 # number of overall MSHR miss cycles 936system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses 937system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses 938system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses 939system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses 940system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses 941system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses 942system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16904.260539 # average ReadReq mshr miss latency 943system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16904.260539 # average ReadReq mshr miss latency 944system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency 945system.cpu.icache.demand_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency 946system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency 947system.cpu.icache.overall_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency 948system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 949system.cpu.l2cache.prefetcher.num_hwpf_issued 8510841 # number of hwpf issued 950system.cpu.l2cache.prefetcher.pfIdentified 8513336 # number of prefetch candidates identified 951system.cpu.l2cache.prefetcher.pfBufferHit 1033 # number of redundant prefetches already in prefetch queue 952system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 953system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 954system.cpu.l2cache.prefetcher.pfSpanPage 743496 # number of prefetches not generated due to page crossing 955system.cpu.l2cache.tags.replacements 401010 # number of replacements 956system.cpu.l2cache.tags.tagsinuse 15417.841274 # Cycle average of tags in use 957system.cpu.l2cache.tags.total_refs 4560227 # Total number of references to valid blocks. 958system.cpu.l2cache.tags.sampled_refs 417347 # Sample count of references to valid blocks. 959system.cpu.l2cache.tags.avg_refs 10.926704 # Average number of references to valid blocks. 960system.cpu.l2cache.tags.warmup_cycle 34597011000 # Cycle when the warmup percentage was hit. 961system.cpu.l2cache.tags.occ_blocks::writebacks 8457.509015 # Average occupied blocks per requestor 962system.cpu.l2cache.tags.occ_blocks::cpu.inst 475.097428 # Average occupied blocks per requestor 963system.cpu.l2cache.tags.occ_blocks::cpu.data 4918.264697 # Average occupied blocks per requestor 964system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1566.970133 # Average occupied blocks per requestor 965system.cpu.l2cache.tags.occ_percent::writebacks 0.516205 # Average percentage of cache occupancy 966system.cpu.l2cache.tags.occ_percent::cpu.inst 0.028998 # Average percentage of cache occupancy 967system.cpu.l2cache.tags.occ_percent::cpu.data 0.300187 # Average percentage of cache occupancy 968system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095640 # Average percentage of cache occupancy 969system.cpu.l2cache.tags.occ_percent::total 0.941030 # Average percentage of cache occupancy 970system.cpu.l2cache.tags.occ_task_id_blocks::1022 1096 # Occupied blocks per task id 971system.cpu.l2cache.tags.occ_task_id_blocks::1024 15241 # Occupied blocks per task id 972system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 973system.cpu.l2cache.tags.age_task_id_blocks_1022::2 31 # Occupied blocks per task id 974system.cpu.l2cache.tags.age_task_id_blocks_1022::3 254 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1022::4 810 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1567 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9927 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3395 # Occupied blocks per task id 981system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066895 # Percentage of cache occupancy per task id 982system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930237 # Percentage of cache occupancy per task id 983system.cpu.l2cache.tags.tag_accesses 84971798 # Number of tag accesses 984system.cpu.l2cache.tags.data_accesses 84971798 # Number of data accesses 985system.cpu.l2cache.ReadReq_hits::cpu.inst 63191 # number of ReadReq hits 986system.cpu.l2cache.ReadReq_hits::cpu.data 2156048 # number of ReadReq hits 987system.cpu.l2cache.ReadReq_hits::total 2219239 # number of ReadReq hits 988system.cpu.l2cache.Writeback_hits::writebacks 2356074 # number of Writeback hits 989system.cpu.l2cache.Writeback_hits::total 2356074 # number of Writeback hits 990system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 991system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 992system.cpu.l2cache.ReadExReq_hits::cpu.data 516713 # number of ReadExReq hits 993system.cpu.l2cache.ReadExReq_hits::total 516713 # number of ReadExReq hits 994system.cpu.l2cache.demand_hits::cpu.inst 63191 # number of demand (read+write) hits 995system.cpu.l2cache.demand_hits::cpu.data 2672761 # number of demand (read+write) hits 996system.cpu.l2cache.demand_hits::total 2735952 # number of demand (read+write) hits 997system.cpu.l2cache.overall_hits::cpu.inst 63191 # number of overall hits 998system.cpu.l2cache.overall_hits::cpu.data 2672761 # number of overall hits 999system.cpu.l2cache.overall_hits::total 2735952 # number of overall hits 1000system.cpu.l2cache.ReadReq_misses::cpu.inst 10784 # number of ReadReq misses 1001system.cpu.l2cache.ReadReq_misses::cpu.data 143994 # number of ReadReq misses 1002system.cpu.l2cache.ReadReq_misses::total 154778 # number of ReadReq misses 1003system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 1004system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 1005system.cpu.l2cache.ReadExReq_misses::cpu.data 5200 # number of ReadExReq misses 1006system.cpu.l2cache.ReadExReq_misses::total 5200 # number of ReadExReq misses 1007system.cpu.l2cache.demand_misses::cpu.inst 10784 # number of demand (read+write) misses 1008system.cpu.l2cache.demand_misses::cpu.data 149194 # number of demand (read+write) misses 1009system.cpu.l2cache.demand_misses::total 159978 # number of demand (read+write) misses 1010system.cpu.l2cache.overall_misses::cpu.inst 10784 # number of overall misses 1011system.cpu.l2cache.overall_misses::cpu.data 149194 # number of overall misses 1012system.cpu.l2cache.overall_misses::total 159978 # number of overall misses 1013system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 802172675 # number of ReadReq miss cycles 1014system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11140653266 # number of ReadReq miss cycles 1015system.cpu.l2cache.ReadReq_miss_latency::total 11942825941 # number of ReadReq miss cycles 1016system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 468295272 # number of ReadExReq miss cycles 1017system.cpu.l2cache.ReadExReq_miss_latency::total 468295272 # number of ReadExReq miss cycles 1018system.cpu.l2cache.demand_miss_latency::cpu.inst 802172675 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.demand_miss_latency::cpu.data 11608948538 # number of demand (read+write) miss cycles 1020system.cpu.l2cache.demand_miss_latency::total 12411121213 # number of demand (read+write) miss cycles 1021system.cpu.l2cache.overall_miss_latency::cpu.inst 802172675 # number of overall miss cycles 1022system.cpu.l2cache.overall_miss_latency::cpu.data 11608948538 # number of overall miss cycles 1023system.cpu.l2cache.overall_miss_latency::total 12411121213 # number of overall miss cycles 1024system.cpu.l2cache.ReadReq_accesses::cpu.inst 73975 # number of ReadReq accesses(hits+misses) 1025system.cpu.l2cache.ReadReq_accesses::cpu.data 2300042 # number of ReadReq accesses(hits+misses) 1026system.cpu.l2cache.ReadReq_accesses::total 2374017 # number of ReadReq accesses(hits+misses) 1027system.cpu.l2cache.Writeback_accesses::writebacks 2356074 # number of Writeback accesses(hits+misses) 1028system.cpu.l2cache.Writeback_accesses::total 2356074 # number of Writeback accesses(hits+misses) 1029system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28 # number of UpgradeReq accesses(hits+misses) 1030system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) 1031system.cpu.l2cache.ReadExReq_accesses::cpu.data 521913 # number of ReadExReq accesses(hits+misses) 1032system.cpu.l2cache.ReadExReq_accesses::total 521913 # number of ReadExReq accesses(hits+misses) 1033system.cpu.l2cache.demand_accesses::cpu.inst 73975 # number of demand (read+write) accesses 1034system.cpu.l2cache.demand_accesses::cpu.data 2821955 # number of demand (read+write) accesses 1035system.cpu.l2cache.demand_accesses::total 2895930 # number of demand (read+write) accesses 1036system.cpu.l2cache.overall_accesses::cpu.inst 73975 # number of overall (read+write) accesses 1037system.cpu.l2cache.overall_accesses::cpu.data 2821955 # number of overall (read+write) accesses 1038system.cpu.l2cache.overall_accesses::total 2895930 # number of overall (read+write) accesses 1039system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.145779 # miss rate for ReadReq accesses 1040system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062605 # miss rate for ReadReq accesses 1041system.cpu.l2cache.ReadReq_miss_rate::total 0.065197 # miss rate for ReadReq accesses 1042system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.071429 # miss rate for UpgradeReq accesses 1043system.cpu.l2cache.UpgradeReq_miss_rate::total 0.071429 # miss rate for UpgradeReq accesses 1044system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009963 # miss rate for ReadExReq accesses 1045system.cpu.l2cache.ReadExReq_miss_rate::total 0.009963 # miss rate for ReadExReq accesses 1046system.cpu.l2cache.demand_miss_rate::cpu.inst 0.145779 # miss rate for demand accesses 1047system.cpu.l2cache.demand_miss_rate::cpu.data 0.052869 # miss rate for demand accesses 1048system.cpu.l2cache.demand_miss_rate::total 0.055242 # miss rate for demand accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.inst 0.145779 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::cpu.data 0.052869 # miss rate for overall accesses 1051system.cpu.l2cache.overall_miss_rate::total 0.055242 # miss rate for overall accesses 1052system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74385.448349 # average ReadReq miss latency 1053system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77368.871384 # average ReadReq miss latency 1054system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.004413 # average ReadReq miss latency 1055system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90056.783077 # average ReadExReq miss latency 1056system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90056.783077 # average ReadExReq miss latency 1057system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74385.448349 # average overall miss latency 1058system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77811.095205 # average overall miss latency 1059system.cpu.l2cache.demand_avg_miss_latency::total 77580.174855 # average overall miss latency 1060system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74385.448349 # average overall miss latency 1061system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77811.095205 # average overall miss latency 1062system.cpu.l2cache.overall_avg_miss_latency::total 77580.174855 # average overall miss latency 1063system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1064system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1065system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1066system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1067system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1068system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1069system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1070system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1071system.cpu.l2cache.writebacks::writebacks 292348 # number of writebacks 1072system.cpu.l2cache.writebacks::total 292348 # number of writebacks 1073system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 1074system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4205 # number of ReadReq MSHR hits 1075system.cpu.l2cache.ReadReq_mshr_hits::total 4209 # number of ReadReq MSHR hits 1076system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1534 # number of ReadExReq MSHR hits 1077system.cpu.l2cache.ReadExReq_mshr_hits::total 1534 # number of ReadExReq MSHR hits 1078system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 1079system.cpu.l2cache.demand_mshr_hits::cpu.data 5739 # number of demand (read+write) MSHR hits 1080system.cpu.l2cache.demand_mshr_hits::total 5743 # number of demand (read+write) MSHR hits 1081system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 1082system.cpu.l2cache.overall_mshr_hits::cpu.data 5739 # number of overall MSHR hits 1083system.cpu.l2cache.overall_mshr_hits::total 5743 # number of overall MSHR hits 1084system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10780 # number of ReadReq MSHR misses 1085system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 139789 # number of ReadReq MSHR misses 1086system.cpu.l2cache.ReadReq_mshr_misses::total 150569 # number of ReadReq MSHR misses 1087system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275622 # number of HardPFReq MSHR misses 1088system.cpu.l2cache.HardPFReq_mshr_misses::total 275622 # number of HardPFReq MSHR misses 1089system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 1090system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 1091system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3666 # number of ReadExReq MSHR misses 1092system.cpu.l2cache.ReadExReq_mshr_misses::total 3666 # number of ReadExReq MSHR misses 1093system.cpu.l2cache.demand_mshr_misses::cpu.inst 10780 # number of demand (read+write) MSHR misses 1094system.cpu.l2cache.demand_mshr_misses::cpu.data 143455 # number of demand (read+write) MSHR misses 1095system.cpu.l2cache.demand_mshr_misses::total 154235 # number of demand (read+write) MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::cpu.inst 10780 # number of overall MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::cpu.data 143455 # number of overall MSHR misses 1098system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275622 # number of overall MSHR misses 1099system.cpu.l2cache.overall_mshr_misses::total 429857 # number of overall MSHR misses 1100system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 710057825 # number of ReadReq MSHR miss cycles 1101system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9596193047 # number of ReadReq MSHR miss cycles 1102system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10306250872 # number of ReadReq MSHR miss cycles 1103system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of HardPFReq MSHR miss cycles 1104system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18910984010 # number of HardPFReq MSHR miss cycles 1105system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles 1106system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles 1107system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 283384780 # number of ReadExReq MSHR miss cycles 1108system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 283384780 # number of ReadExReq MSHR miss cycles 1109system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 710057825 # number of demand (read+write) MSHR miss cycles 1110system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9879577827 # number of demand (read+write) MSHR miss cycles 1111system.cpu.l2cache.demand_mshr_miss_latency::total 10589635652 # number of demand (read+write) MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 710057825 # number of overall MSHR miss cycles 1113system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9879577827 # number of overall MSHR miss cycles 1114system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of overall MSHR miss cycles 1115system.cpu.l2cache.overall_mshr_miss_latency::total 29500619662 # number of overall MSHR miss cycles 1116system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for ReadReq accesses 1117system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060777 # mshr miss rate for ReadReq accesses 1118system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063424 # mshr miss rate for ReadReq accesses 1119system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1120system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1121system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.071429 # mshr miss rate for UpgradeReq accesses 1122system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.071429 # mshr miss rate for UpgradeReq accesses 1123system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007024 # mshr miss rate for ReadExReq accesses 1124system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007024 # mshr miss rate for ReadExReq accesses 1125system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for demand accesses 1126system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for demand accesses 1127system.cpu.l2cache.demand_mshr_miss_rate::total 0.053259 # mshr miss rate for demand accesses 1128system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for overall accesses 1129system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for overall accesses 1130system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1131system.cpu.l2cache.overall_mshr_miss_rate::total 0.148435 # mshr miss rate for overall accesses 1132system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65868.072820 # average ReadReq mshr miss latency 1133system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68647.697938 # average ReadReq mshr miss latency 1134system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68448.690448 # average ReadReq mshr miss latency 1135system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average HardPFReq mshr miss latency 1136system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 68612.026652 # average HardPFReq mshr miss latency 1137system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency 1138system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency 1139system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77300.812875 # average ReadExReq mshr miss latency 1140system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77300.812875 # average ReadExReq mshr miss latency 1141system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency 1142system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency 1143system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68659.095873 # average overall mshr miss latency 1144system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency 1145system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency 1146system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average overall mshr miss latency 1147system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68628.915342 # average overall mshr miss latency 1148system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1149system.cpu.toL2Bus.trans_dist::ReadReq 2374050 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::ReadResp 2374049 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::Writeback 2356074 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::HardPFReq 317604 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::ReadExReq 521913 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::ReadExResp 521913 # Transaction distribution 1157system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147982 # Packet count per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8000040 # Packet count per connected master and slave (bytes) 1159system.cpu.toL2Bus.pkt_count::total 8148022 # Packet count per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734336 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331393856 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu.toL2Bus.pkt_size::total 336128192 # Cumulative packet size per connected master and slave (bytes) 1163system.cpu.toL2Bus.snoops 317637 # Total snoops (count) 1164system.cpu.toL2Bus.snoop_fanout::samples 5569669 # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::mean 3.057024 # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::stdev 0.231888 # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::3 5252065 94.30% 94.30% # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::4 317604 5.70% 100.00% # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::total 5569669 # Request fanout histogram 1177system.cpu.toL2Bus.reqLayer0.occupancy 4982106500 # Layer occupancy (ticks) 1178system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) 1179system.cpu.toL2Bus.respLayer0.occupancy 112829788 # Layer occupancy (ticks) 1180system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1181system.cpu.toL2Bus.respLayer1.occupancy 4256050685 # Layer occupancy (ticks) 1182system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 1183system.membus.trans_dist::ReadReq 408353 # Transaction distribution 1184system.membus.trans_dist::ReadResp 408353 # Transaction distribution 1185system.membus.trans_dist::Writeback 292348 # Transaction distribution 1186system.membus.trans_dist::UpgradeReq 3 # Transaction distribution 1187system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 1188system.membus.trans_dist::ReadExReq 3665 # Transaction distribution 1189system.membus.trans_dist::ReadExResp 3665 # Transaction distribution 1190system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1116390 # Packet count per connected master and slave (bytes) 1191system.membus.pkt_count::total 1116390 # Packet count per connected master and slave (bytes) 1192system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45079424 # Cumulative packet size per connected master and slave (bytes) 1193system.membus.pkt_size::total 45079424 # Cumulative packet size per connected master and slave (bytes) 1194system.membus.snoops 0 # Total snoops (count) 1195system.membus.snoop_fanout::samples 704369 # Request fanout histogram 1196system.membus.snoop_fanout::mean 0 # Request fanout histogram 1197system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1198system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1199system.membus.snoop_fanout::0 704369 100.00% 100.00% # Request fanout histogram 1200system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1201system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1202system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1203system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1204system.membus.snoop_fanout::total 704369 # Request fanout histogram 1205system.membus.reqLayer0.occupancy 2100254662 # Layer occupancy (ticks) 1206system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 1207system.membus.respLayer1.occupancy 2178151058 # Layer occupancy (ticks) 1208system.membus.respLayer1.utilization 0.9 # Layer utilization (%) 1209 1210---------- End Simulation Statistics ---------- | 689system.cpu.rob.rob_reads 1093653497 # The number of ROB reads 690system.cpu.rob.rob_writes 1334601058 # The number of ROB writes 691system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself 692system.cpu.idleCycles 881662 # Total number of cycles that the CPU has spent unscheduled due to idling 693system.cpu.committedInsts 505237723 # Number of Instructions Simulated 694system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated 695system.cpu.cpi 0.923848 # CPI: Cycles Per Instruction 696system.cpu.cpi_total 0.923848 # CPI: Total CPI of All Threads 697system.cpu.ipc 1.082429 # IPC: Instructions Per Cycle 698system.cpu.ipc_total 1.082429 # IPC: Total IPC of All Threads 699system.cpu.int_regfile_reads 611089137 # number of integer regfile reads 700system.cpu.int_regfile_writes 328121807 # number of integer regfile writes 701system.cpu.fp_regfile_reads 16 # number of floating regfile reads 702system.cpu.cc_regfile_reads 2170187431 # number of cc regfile reads 703system.cpu.cc_regfile_writes 376547848 # number of cc regfile writes 704system.cpu.misc_regfile_reads 217970630 # number of misc regfile reads 705system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 706system.cpu.dcache.tags.replacements 2821443 # number of replacements 707system.cpu.dcache.tags.tagsinuse 511.630682 # Cycle average of tags in use 708system.cpu.dcache.tags.total_refs 169417803 # Total number of references to valid blocks. 709system.cpu.dcache.tags.sampled_refs 2821955 # Sample count of references to valid blocks. 710system.cpu.dcache.tags.avg_refs 60.035615 # Average number of references to valid blocks. 711system.cpu.dcache.tags.warmup_cycle 498977500 # Cycle when the warmup percentage was hit. 712system.cpu.dcache.tags.occ_blocks::cpu.data 511.630682 # Average occupied blocks per requestor 713system.cpu.dcache.tags.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy 714system.cpu.dcache.tags.occ_percent::total 0.999279 # Average percentage of cache occupancy 715system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 716system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id 717system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id 718system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 719system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 720system.cpu.dcache.tags.tag_accesses 356251797 # Number of tag accesses 721system.cpu.dcache.tags.data_accesses 356251797 # Number of data accesses 722system.cpu.dcache.ReadReq_hits::cpu.data 114676407 # number of ReadReq hits 723system.cpu.dcache.ReadReq_hits::total 114676407 # number of ReadReq hits 724system.cpu.dcache.WriteReq_hits::cpu.data 51761464 # number of WriteReq hits 725system.cpu.dcache.WriteReq_hits::total 51761464 # number of WriteReq hits 726system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits 727system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits 728system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits 729system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits 730system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 731system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 732system.cpu.dcache.demand_hits::cpu.data 166437871 # number of demand (read+write) hits 733system.cpu.dcache.demand_hits::total 166437871 # number of demand (read+write) hits 734system.cpu.dcache.overall_hits::cpu.data 166440653 # number of overall hits 735system.cpu.dcache.overall_hits::total 166440653 # number of overall hits 736system.cpu.dcache.ReadReq_misses::cpu.data 4819248 # number of ReadReq misses 737system.cpu.dcache.ReadReq_misses::total 4819248 # number of ReadReq misses 738system.cpu.dcache.WriteReq_misses::cpu.data 2477842 # number of WriteReq misses 739system.cpu.dcache.WriteReq_misses::total 2477842 # number of WriteReq misses 740system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses 741system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses 742system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 743system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses 744system.cpu.dcache.demand_misses::cpu.data 7297090 # number of demand (read+write) misses 745system.cpu.dcache.demand_misses::total 7297090 # number of demand (read+write) misses 746system.cpu.dcache.overall_misses::cpu.data 7297102 # number of overall misses 747system.cpu.dcache.overall_misses::total 7297102 # number of overall misses 748system.cpu.dcache.ReadReq_miss_latency::cpu.data 56184151983 # number of ReadReq miss cycles 749system.cpu.dcache.ReadReq_miss_latency::total 56184151983 # number of ReadReq miss cycles 750system.cpu.dcache.WriteReq_miss_latency::cpu.data 18816988488 # number of WriteReq miss cycles 751system.cpu.dcache.WriteReq_miss_latency::total 18816988488 # number of WriteReq miss cycles 752system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1349500 # number of LoadLockedReq miss cycles 753system.cpu.dcache.LoadLockedReq_miss_latency::total 1349500 # number of LoadLockedReq miss cycles 754system.cpu.dcache.demand_miss_latency::cpu.data 75001140471 # number of demand (read+write) miss cycles 755system.cpu.dcache.demand_miss_latency::total 75001140471 # number of demand (read+write) miss cycles 756system.cpu.dcache.overall_miss_latency::cpu.data 75001140471 # number of overall miss cycles 757system.cpu.dcache.overall_miss_latency::total 75001140471 # number of overall miss cycles 758system.cpu.dcache.ReadReq_accesses::cpu.data 119495655 # number of ReadReq accesses(hits+misses) 759system.cpu.dcache.ReadReq_accesses::total 119495655 # number of ReadReq accesses(hits+misses) 760system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 761system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 762system.cpu.dcache.SoftPFReq_accesses::cpu.data 2794 # number of SoftPFReq accesses(hits+misses) 763system.cpu.dcache.SoftPFReq_accesses::total 2794 # number of SoftPFReq accesses(hits+misses) 764system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) 765system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) 766system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 767system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 768system.cpu.dcache.demand_accesses::cpu.data 173734961 # number of demand (read+write) accesses 769system.cpu.dcache.demand_accesses::total 173734961 # number of demand (read+write) accesses 770system.cpu.dcache.overall_accesses::cpu.data 173737755 # number of overall (read+write) accesses 771system.cpu.dcache.overall_accesses::total 173737755 # number of overall (read+write) accesses 772system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040330 # miss rate for ReadReq accesses 773system.cpu.dcache.ReadReq_miss_rate::total 0.040330 # miss rate for ReadReq accesses 774system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045684 # miss rate for WriteReq accesses 775system.cpu.dcache.WriteReq_miss_rate::total 0.045684 # miss rate for WriteReq accesses 776system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004295 # miss rate for SoftPFReq accesses 777system.cpu.dcache.SoftPFReq_miss_rate::total 0.004295 # miss rate for SoftPFReq accesses 778system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 779system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses 780system.cpu.dcache.demand_miss_rate::cpu.data 0.042001 # miss rate for demand accesses 781system.cpu.dcache.demand_miss_rate::total 0.042001 # miss rate for demand accesses 782system.cpu.dcache.overall_miss_rate::cpu.data 0.042001 # miss rate for overall accesses 783system.cpu.dcache.overall_miss_rate::total 0.042001 # miss rate for overall accesses 784system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11658.281952 # average ReadReq miss latency 785system.cpu.dcache.ReadReq_avg_miss_latency::total 11658.281952 # average ReadReq miss latency 786system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7594.103453 # average WriteReq miss latency 787system.cpu.dcache.WriteReq_avg_miss_latency::total 7594.103453 # average WriteReq miss latency 788system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20446.969697 # average LoadLockedReq miss latency 789system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20446.969697 # average LoadLockedReq miss latency 790system.cpu.dcache.demand_avg_miss_latency::cpu.data 10278.226042 # average overall miss latency 791system.cpu.dcache.demand_avg_miss_latency::total 10278.226042 # average overall miss latency 792system.cpu.dcache.overall_avg_miss_latency::cpu.data 10278.209140 # average overall miss latency 793system.cpu.dcache.overall_avg_miss_latency::total 10278.209140 # average overall miss latency 794system.cpu.dcache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked 795system.cpu.dcache.blocked_cycles::no_targets 705176 # number of cycles access was blocked 796system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked 797system.cpu.dcache.blocked::no_targets 220270 # number of cycles access was blocked 798system.cpu.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked 799system.cpu.dcache.avg_blocked_cycles::no_targets 3.201416 # average number of cycles each access was blocked 800system.cpu.dcache.fast_writes 0 # number of fast writes performed 801system.cpu.dcache.cache_copies 0 # number of cache copies performed 802system.cpu.dcache.writebacks::writebacks 2356074 # number of writebacks 803system.cpu.dcache.writebacks::total 2356074 # number of writebacks 804system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2516883 # number of ReadReq MSHR hits 805system.cpu.dcache.ReadReq_mshr_hits::total 2516883 # number of ReadReq MSHR hits 806system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1958234 # number of WriteReq MSHR hits 807system.cpu.dcache.WriteReq_mshr_hits::total 1958234 # number of WriteReq MSHR hits 808system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 809system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits 810system.cpu.dcache.demand_mshr_hits::cpu.data 4475117 # number of demand (read+write) MSHR hits 811system.cpu.dcache.demand_mshr_hits::total 4475117 # number of demand (read+write) MSHR hits 812system.cpu.dcache.overall_mshr_hits::cpu.data 4475117 # number of overall MSHR hits 813system.cpu.dcache.overall_mshr_hits::total 4475117 # number of overall MSHR hits 814system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2302365 # number of ReadReq MSHR misses 815system.cpu.dcache.ReadReq_mshr_misses::total 2302365 # number of ReadReq MSHR misses 816system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519608 # number of WriteReq MSHR misses 817system.cpu.dcache.WriteReq_mshr_misses::total 519608 # number of WriteReq MSHR misses 818system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 819system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 820system.cpu.dcache.demand_mshr_misses::cpu.data 2821973 # number of demand (read+write) MSHR misses 821system.cpu.dcache.demand_mshr_misses::total 2821973 # number of demand (read+write) MSHR misses 822system.cpu.dcache.overall_mshr_misses::cpu.data 2821983 # number of overall MSHR misses 823system.cpu.dcache.overall_mshr_misses::total 2821983 # number of overall MSHR misses 824system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27555148045 # number of ReadReq MSHR miss cycles 825system.cpu.dcache.ReadReq_mshr_miss_latency::total 27555148045 # number of ReadReq MSHR miss cycles 826system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4324407514 # number of WriteReq MSHR miss cycles 827system.cpu.dcache.WriteReq_mshr_miss_latency::total 4324407514 # number of WriteReq MSHR miss cycles 828system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 652250 # number of SoftPFReq MSHR miss cycles 829system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 652250 # number of SoftPFReq MSHR miss cycles 830system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31879555559 # number of demand (read+write) MSHR miss cycles 831system.cpu.dcache.demand_mshr_miss_latency::total 31879555559 # number of demand (read+write) MSHR miss cycles 832system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31880207809 # number of overall MSHR miss cycles 833system.cpu.dcache.overall_mshr_miss_latency::total 31880207809 # number of overall MSHR miss cycles 834system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019267 # mshr miss rate for ReadReq accesses 835system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019267 # mshr miss rate for ReadReq accesses 836system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses 837system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses 838system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003579 # mshr miss rate for SoftPFReq accesses 839system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003579 # mshr miss rate for SoftPFReq accesses 840system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for demand accesses 841system.cpu.dcache.demand_mshr_miss_rate::total 0.016243 # mshr miss rate for demand accesses 842system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for overall accesses 843system.cpu.dcache.overall_mshr_miss_rate::total 0.016243 # mshr miss rate for overall accesses 844system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11968.192726 # average ReadReq mshr miss latency 845system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11968.192726 # average ReadReq mshr miss latency 846system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8322.442137 # average WriteReq mshr miss latency 847system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8322.442137 # average WriteReq mshr miss latency 848system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65225 # average SoftPFReq mshr miss latency 849system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65225 # average SoftPFReq mshr miss latency 850system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11296.903110 # average overall mshr miss latency 851system.cpu.dcache.demand_avg_mshr_miss_latency::total 11296.903110 # average overall mshr miss latency 852system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11297.094210 # average overall mshr miss latency 853system.cpu.dcache.overall_avg_mshr_miss_latency::total 11297.094210 # average overall mshr miss latency 854system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 855system.cpu.icache.tags.replacements 73466 # number of replacements 856system.cpu.icache.tags.tagsinuse 466.200525 # Cycle average of tags in use 857system.cpu.icache.tags.total_refs 236646541 # Total number of references to valid blocks. 858system.cpu.icache.tags.sampled_refs 73978 # Sample count of references to valid blocks. 859system.cpu.icache.tags.avg_refs 3198.877247 # Average number of references to valid blocks. 860system.cpu.icache.tags.warmup_cycle 115003506250 # Cycle when the warmup percentage was hit. 861system.cpu.icache.tags.occ_blocks::cpu.inst 466.200525 # Average occupied blocks per requestor 862system.cpu.icache.tags.occ_percent::cpu.inst 0.910548 # Average percentage of cache occupancy 863system.cpu.icache.tags.occ_percent::total 0.910548 # Average percentage of cache occupancy 864system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 865system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 866system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 867system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id 868system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id 869system.cpu.icache.tags.age_task_id_blocks_1024::4 15 # Occupied blocks per task id 870system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 871system.cpu.icache.tags.tag_accesses 473531001 # Number of tag accesses 872system.cpu.icache.tags.data_accesses 473531001 # Number of data accesses 873system.cpu.icache.ReadReq_hits::cpu.inst 236646541 # number of ReadReq hits 874system.cpu.icache.ReadReq_hits::total 236646541 # number of ReadReq hits 875system.cpu.icache.demand_hits::cpu.inst 236646541 # number of demand (read+write) hits 876system.cpu.icache.demand_hits::total 236646541 # number of demand (read+write) hits 877system.cpu.icache.overall_hits::cpu.inst 236646541 # number of overall hits 878system.cpu.icache.overall_hits::total 236646541 # number of overall hits 879system.cpu.icache.ReadReq_misses::cpu.inst 81956 # number of ReadReq misses 880system.cpu.icache.ReadReq_misses::total 81956 # number of ReadReq misses 881system.cpu.icache.demand_misses::cpu.inst 81956 # number of demand (read+write) misses 882system.cpu.icache.demand_misses::total 81956 # number of demand (read+write) misses 883system.cpu.icache.overall_misses::cpu.inst 81956 # number of overall misses 884system.cpu.icache.overall_misses::total 81956 # number of overall misses 885system.cpu.icache.ReadReq_miss_latency::cpu.inst 1579166787 # number of ReadReq miss cycles 886system.cpu.icache.ReadReq_miss_latency::total 1579166787 # number of ReadReq miss cycles 887system.cpu.icache.demand_miss_latency::cpu.inst 1579166787 # number of demand (read+write) miss cycles 888system.cpu.icache.demand_miss_latency::total 1579166787 # number of demand (read+write) miss cycles 889system.cpu.icache.overall_miss_latency::cpu.inst 1579166787 # number of overall miss cycles 890system.cpu.icache.overall_miss_latency::total 1579166787 # number of overall miss cycles 891system.cpu.icache.ReadReq_accesses::cpu.inst 236728497 # number of ReadReq accesses(hits+misses) 892system.cpu.icache.ReadReq_accesses::total 236728497 # number of ReadReq accesses(hits+misses) 893system.cpu.icache.demand_accesses::cpu.inst 236728497 # number of demand (read+write) accesses 894system.cpu.icache.demand_accesses::total 236728497 # number of demand (read+write) accesses 895system.cpu.icache.overall_accesses::cpu.inst 236728497 # number of overall (read+write) accesses 896system.cpu.icache.overall_accesses::total 236728497 # number of overall (read+write) accesses 897system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses 898system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses 899system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses 900system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses 901system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses 902system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses 903system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19268.470728 # average ReadReq miss latency 904system.cpu.icache.ReadReq_avg_miss_latency::total 19268.470728 # average ReadReq miss latency 905system.cpu.icache.demand_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency 906system.cpu.icache.demand_avg_miss_latency::total 19268.470728 # average overall miss latency 907system.cpu.icache.overall_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency 908system.cpu.icache.overall_avg_miss_latency::total 19268.470728 # average overall miss latency 909system.cpu.icache.blocked_cycles::no_mshrs 192617 # number of cycles access was blocked 910system.cpu.icache.blocked_cycles::no_targets 91 # number of cycles access was blocked 911system.cpu.icache.blocked::no_mshrs 6539 # number of cycles access was blocked 912system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked 913system.cpu.icache.avg_blocked_cycles::no_mshrs 29.456645 # average number of cycles each access was blocked 914system.cpu.icache.avg_blocked_cycles::no_targets 22.750000 # average number of cycles each access was blocked 915system.cpu.icache.fast_writes 0 # number of fast writes performed 916system.cpu.icache.cache_copies 0 # number of cache copies performed 917system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7948 # number of ReadReq MSHR hits 918system.cpu.icache.ReadReq_mshr_hits::total 7948 # number of ReadReq MSHR hits 919system.cpu.icache.demand_mshr_hits::cpu.inst 7948 # number of demand (read+write) MSHR hits 920system.cpu.icache.demand_mshr_hits::total 7948 # number of demand (read+write) MSHR hits 921system.cpu.icache.overall_mshr_hits::cpu.inst 7948 # number of overall MSHR hits 922system.cpu.icache.overall_mshr_hits::total 7948 # number of overall MSHR hits 923system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74008 # number of ReadReq MSHR misses 924system.cpu.icache.ReadReq_mshr_misses::total 74008 # number of ReadReq MSHR misses 925system.cpu.icache.demand_mshr_misses::cpu.inst 74008 # number of demand (read+write) MSHR misses 926system.cpu.icache.demand_mshr_misses::total 74008 # number of demand (read+write) MSHR misses 927system.cpu.icache.overall_mshr_misses::cpu.inst 74008 # number of overall MSHR misses 928system.cpu.icache.overall_mshr_misses::total 74008 # number of overall MSHR misses 929system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1251050514 # number of ReadReq MSHR miss cycles 930system.cpu.icache.ReadReq_mshr_miss_latency::total 1251050514 # number of ReadReq MSHR miss cycles 931system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1251050514 # number of demand (read+write) MSHR miss cycles 932system.cpu.icache.demand_mshr_miss_latency::total 1251050514 # number of demand (read+write) MSHR miss cycles 933system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1251050514 # number of overall MSHR miss cycles 934system.cpu.icache.overall_mshr_miss_latency::total 1251050514 # number of overall MSHR miss cycles 935system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses 936system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses 937system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses 938system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses 939system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses 940system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses 941system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16904.260539 # average ReadReq mshr miss latency 942system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16904.260539 # average ReadReq mshr miss latency 943system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency 944system.cpu.icache.demand_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency 945system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency 946system.cpu.icache.overall_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency 947system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 948system.cpu.l2cache.prefetcher.num_hwpf_issued 8510841 # number of hwpf issued 949system.cpu.l2cache.prefetcher.pfIdentified 8513336 # number of prefetch candidates identified 950system.cpu.l2cache.prefetcher.pfBufferHit 1033 # number of redundant prefetches already in prefetch queue 951system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 952system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 953system.cpu.l2cache.prefetcher.pfSpanPage 743496 # number of prefetches not generated due to page crossing 954system.cpu.l2cache.tags.replacements 401010 # number of replacements 955system.cpu.l2cache.tags.tagsinuse 15417.841274 # Cycle average of tags in use 956system.cpu.l2cache.tags.total_refs 4560227 # Total number of references to valid blocks. 957system.cpu.l2cache.tags.sampled_refs 417347 # Sample count of references to valid blocks. 958system.cpu.l2cache.tags.avg_refs 10.926704 # Average number of references to valid blocks. 959system.cpu.l2cache.tags.warmup_cycle 34597011000 # Cycle when the warmup percentage was hit. 960system.cpu.l2cache.tags.occ_blocks::writebacks 8457.509015 # Average occupied blocks per requestor 961system.cpu.l2cache.tags.occ_blocks::cpu.inst 475.097428 # Average occupied blocks per requestor 962system.cpu.l2cache.tags.occ_blocks::cpu.data 4918.264697 # Average occupied blocks per requestor 963system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1566.970133 # Average occupied blocks per requestor 964system.cpu.l2cache.tags.occ_percent::writebacks 0.516205 # Average percentage of cache occupancy 965system.cpu.l2cache.tags.occ_percent::cpu.inst 0.028998 # Average percentage of cache occupancy 966system.cpu.l2cache.tags.occ_percent::cpu.data 0.300187 # Average percentage of cache occupancy 967system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095640 # Average percentage of cache occupancy 968system.cpu.l2cache.tags.occ_percent::total 0.941030 # Average percentage of cache occupancy 969system.cpu.l2cache.tags.occ_task_id_blocks::1022 1096 # Occupied blocks per task id 970system.cpu.l2cache.tags.occ_task_id_blocks::1024 15241 # Occupied blocks per task id 971system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 972system.cpu.l2cache.tags.age_task_id_blocks_1022::2 31 # Occupied blocks per task id 973system.cpu.l2cache.tags.age_task_id_blocks_1022::3 254 # Occupied blocks per task id 974system.cpu.l2cache.tags.age_task_id_blocks_1022::4 810 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1567 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9927 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3395 # Occupied blocks per task id 980system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066895 # Percentage of cache occupancy per task id 981system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930237 # Percentage of cache occupancy per task id 982system.cpu.l2cache.tags.tag_accesses 84971798 # Number of tag accesses 983system.cpu.l2cache.tags.data_accesses 84971798 # Number of data accesses 984system.cpu.l2cache.ReadReq_hits::cpu.inst 63191 # number of ReadReq hits 985system.cpu.l2cache.ReadReq_hits::cpu.data 2156048 # number of ReadReq hits 986system.cpu.l2cache.ReadReq_hits::total 2219239 # number of ReadReq hits 987system.cpu.l2cache.Writeback_hits::writebacks 2356074 # number of Writeback hits 988system.cpu.l2cache.Writeback_hits::total 2356074 # number of Writeback hits 989system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 990system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 991system.cpu.l2cache.ReadExReq_hits::cpu.data 516713 # number of ReadExReq hits 992system.cpu.l2cache.ReadExReq_hits::total 516713 # number of ReadExReq hits 993system.cpu.l2cache.demand_hits::cpu.inst 63191 # number of demand (read+write) hits 994system.cpu.l2cache.demand_hits::cpu.data 2672761 # number of demand (read+write) hits 995system.cpu.l2cache.demand_hits::total 2735952 # number of demand (read+write) hits 996system.cpu.l2cache.overall_hits::cpu.inst 63191 # number of overall hits 997system.cpu.l2cache.overall_hits::cpu.data 2672761 # number of overall hits 998system.cpu.l2cache.overall_hits::total 2735952 # number of overall hits 999system.cpu.l2cache.ReadReq_misses::cpu.inst 10784 # number of ReadReq misses 1000system.cpu.l2cache.ReadReq_misses::cpu.data 143994 # number of ReadReq misses 1001system.cpu.l2cache.ReadReq_misses::total 154778 # number of ReadReq misses 1002system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 1003system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 1004system.cpu.l2cache.ReadExReq_misses::cpu.data 5200 # number of ReadExReq misses 1005system.cpu.l2cache.ReadExReq_misses::total 5200 # number of ReadExReq misses 1006system.cpu.l2cache.demand_misses::cpu.inst 10784 # number of demand (read+write) misses 1007system.cpu.l2cache.demand_misses::cpu.data 149194 # number of demand (read+write) misses 1008system.cpu.l2cache.demand_misses::total 159978 # number of demand (read+write) misses 1009system.cpu.l2cache.overall_misses::cpu.inst 10784 # number of overall misses 1010system.cpu.l2cache.overall_misses::cpu.data 149194 # number of overall misses 1011system.cpu.l2cache.overall_misses::total 159978 # number of overall misses 1012system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 802172675 # number of ReadReq miss cycles 1013system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11140653266 # number of ReadReq miss cycles 1014system.cpu.l2cache.ReadReq_miss_latency::total 11942825941 # number of ReadReq miss cycles 1015system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 468295272 # number of ReadExReq miss cycles 1016system.cpu.l2cache.ReadExReq_miss_latency::total 468295272 # number of ReadExReq miss cycles 1017system.cpu.l2cache.demand_miss_latency::cpu.inst 802172675 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.demand_miss_latency::cpu.data 11608948538 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.demand_miss_latency::total 12411121213 # number of demand (read+write) miss cycles 1020system.cpu.l2cache.overall_miss_latency::cpu.inst 802172675 # number of overall miss cycles 1021system.cpu.l2cache.overall_miss_latency::cpu.data 11608948538 # number of overall miss cycles 1022system.cpu.l2cache.overall_miss_latency::total 12411121213 # number of overall miss cycles 1023system.cpu.l2cache.ReadReq_accesses::cpu.inst 73975 # number of ReadReq accesses(hits+misses) 1024system.cpu.l2cache.ReadReq_accesses::cpu.data 2300042 # number of ReadReq accesses(hits+misses) 1025system.cpu.l2cache.ReadReq_accesses::total 2374017 # number of ReadReq accesses(hits+misses) 1026system.cpu.l2cache.Writeback_accesses::writebacks 2356074 # number of Writeback accesses(hits+misses) 1027system.cpu.l2cache.Writeback_accesses::total 2356074 # number of Writeback accesses(hits+misses) 1028system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28 # number of UpgradeReq accesses(hits+misses) 1029system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) 1030system.cpu.l2cache.ReadExReq_accesses::cpu.data 521913 # number of ReadExReq accesses(hits+misses) 1031system.cpu.l2cache.ReadExReq_accesses::total 521913 # number of ReadExReq accesses(hits+misses) 1032system.cpu.l2cache.demand_accesses::cpu.inst 73975 # number of demand (read+write) accesses 1033system.cpu.l2cache.demand_accesses::cpu.data 2821955 # number of demand (read+write) accesses 1034system.cpu.l2cache.demand_accesses::total 2895930 # number of demand (read+write) accesses 1035system.cpu.l2cache.overall_accesses::cpu.inst 73975 # number of overall (read+write) accesses 1036system.cpu.l2cache.overall_accesses::cpu.data 2821955 # number of overall (read+write) accesses 1037system.cpu.l2cache.overall_accesses::total 2895930 # number of overall (read+write) accesses 1038system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.145779 # miss rate for ReadReq accesses 1039system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062605 # miss rate for ReadReq accesses 1040system.cpu.l2cache.ReadReq_miss_rate::total 0.065197 # miss rate for ReadReq accesses 1041system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.071429 # miss rate for UpgradeReq accesses 1042system.cpu.l2cache.UpgradeReq_miss_rate::total 0.071429 # miss rate for UpgradeReq accesses 1043system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009963 # miss rate for ReadExReq accesses 1044system.cpu.l2cache.ReadExReq_miss_rate::total 0.009963 # miss rate for ReadExReq accesses 1045system.cpu.l2cache.demand_miss_rate::cpu.inst 0.145779 # miss rate for demand accesses 1046system.cpu.l2cache.demand_miss_rate::cpu.data 0.052869 # miss rate for demand accesses 1047system.cpu.l2cache.demand_miss_rate::total 0.055242 # miss rate for demand accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.inst 0.145779 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.data 0.052869 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::total 0.055242 # miss rate for overall accesses 1051system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74385.448349 # average ReadReq miss latency 1052system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77368.871384 # average ReadReq miss latency 1053system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.004413 # average ReadReq miss latency 1054system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90056.783077 # average ReadExReq miss latency 1055system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90056.783077 # average ReadExReq miss latency 1056system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74385.448349 # average overall miss latency 1057system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77811.095205 # average overall miss latency 1058system.cpu.l2cache.demand_avg_miss_latency::total 77580.174855 # average overall miss latency 1059system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74385.448349 # average overall miss latency 1060system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77811.095205 # average overall miss latency 1061system.cpu.l2cache.overall_avg_miss_latency::total 77580.174855 # average overall miss latency 1062system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1063system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1064system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1065system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1066system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1067system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1068system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1069system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1070system.cpu.l2cache.writebacks::writebacks 292348 # number of writebacks 1071system.cpu.l2cache.writebacks::total 292348 # number of writebacks 1072system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 1073system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4205 # number of ReadReq MSHR hits 1074system.cpu.l2cache.ReadReq_mshr_hits::total 4209 # number of ReadReq MSHR hits 1075system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1534 # number of ReadExReq MSHR hits 1076system.cpu.l2cache.ReadExReq_mshr_hits::total 1534 # number of ReadExReq MSHR hits 1077system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 1078system.cpu.l2cache.demand_mshr_hits::cpu.data 5739 # number of demand (read+write) MSHR hits 1079system.cpu.l2cache.demand_mshr_hits::total 5743 # number of demand (read+write) MSHR hits 1080system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 1081system.cpu.l2cache.overall_mshr_hits::cpu.data 5739 # number of overall MSHR hits 1082system.cpu.l2cache.overall_mshr_hits::total 5743 # number of overall MSHR hits 1083system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10780 # number of ReadReq MSHR misses 1084system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 139789 # number of ReadReq MSHR misses 1085system.cpu.l2cache.ReadReq_mshr_misses::total 150569 # number of ReadReq MSHR misses 1086system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275622 # number of HardPFReq MSHR misses 1087system.cpu.l2cache.HardPFReq_mshr_misses::total 275622 # number of HardPFReq MSHR misses 1088system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 1089system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 1090system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3666 # number of ReadExReq MSHR misses 1091system.cpu.l2cache.ReadExReq_mshr_misses::total 3666 # number of ReadExReq MSHR misses 1092system.cpu.l2cache.demand_mshr_misses::cpu.inst 10780 # number of demand (read+write) MSHR misses 1093system.cpu.l2cache.demand_mshr_misses::cpu.data 143455 # number of demand (read+write) MSHR misses 1094system.cpu.l2cache.demand_mshr_misses::total 154235 # number of demand (read+write) MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 10780 # number of overall MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::cpu.data 143455 # number of overall MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275622 # number of overall MSHR misses 1098system.cpu.l2cache.overall_mshr_misses::total 429857 # number of overall MSHR misses 1099system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 710057825 # number of ReadReq MSHR miss cycles 1100system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9596193047 # number of ReadReq MSHR miss cycles 1101system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10306250872 # number of ReadReq MSHR miss cycles 1102system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of HardPFReq MSHR miss cycles 1103system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18910984010 # number of HardPFReq MSHR miss cycles 1104system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles 1105system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles 1106system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 283384780 # number of ReadExReq MSHR miss cycles 1107system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 283384780 # number of ReadExReq MSHR miss cycles 1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 710057825 # number of demand (read+write) MSHR miss cycles 1109system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9879577827 # number of demand (read+write) MSHR miss cycles 1110system.cpu.l2cache.demand_mshr_miss_latency::total 10589635652 # number of demand (read+write) MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 710057825 # number of overall MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9879577827 # number of overall MSHR miss cycles 1113system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of overall MSHR miss cycles 1114system.cpu.l2cache.overall_mshr_miss_latency::total 29500619662 # number of overall MSHR miss cycles 1115system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for ReadReq accesses 1116system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060777 # mshr miss rate for ReadReq accesses 1117system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063424 # mshr miss rate for ReadReq accesses 1118system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1119system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1120system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.071429 # mshr miss rate for UpgradeReq accesses 1121system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.071429 # mshr miss rate for UpgradeReq accesses 1122system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007024 # mshr miss rate for ReadExReq accesses 1123system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007024 # mshr miss rate for ReadExReq accesses 1124system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for demand accesses 1125system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for demand accesses 1126system.cpu.l2cache.demand_mshr_miss_rate::total 0.053259 # mshr miss rate for demand accesses 1127system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for overall accesses 1128system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for overall accesses 1129system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1130system.cpu.l2cache.overall_mshr_miss_rate::total 0.148435 # mshr miss rate for overall accesses 1131system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65868.072820 # average ReadReq mshr miss latency 1132system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68647.697938 # average ReadReq mshr miss latency 1133system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68448.690448 # average ReadReq mshr miss latency 1134system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average HardPFReq mshr miss latency 1135system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 68612.026652 # average HardPFReq mshr miss latency 1136system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency 1137system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency 1138system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77300.812875 # average ReadExReq mshr miss latency 1139system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77300.812875 # average ReadExReq mshr miss latency 1140system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency 1141system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency 1142system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68659.095873 # average overall mshr miss latency 1143system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency 1144system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency 1145system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average overall mshr miss latency 1146system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68628.915342 # average overall mshr miss latency 1147system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1148system.cpu.toL2Bus.trans_dist::ReadReq 2374050 # Transaction distribution 1149system.cpu.toL2Bus.trans_dist::ReadResp 2374049 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::Writeback 2356074 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::HardPFReq 317604 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::ReadExReq 521913 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::ReadExResp 521913 # Transaction distribution 1156system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147982 # Packet count per connected master and slave (bytes) 1157system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8000040 # Packet count per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_count::total 8148022 # Packet count per connected master and slave (bytes) 1159system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734336 # Cumulative packet size per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331393856 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu.toL2Bus.pkt_size::total 336128192 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu.toL2Bus.snoops 317637 # Total snoops (count) 1163system.cpu.toL2Bus.snoop_fanout::samples 5569669 # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::mean 3.057024 # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::stdev 0.231888 # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::3 5252065 94.30% 94.30% # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::4 317604 5.70% 100.00% # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::total 5569669 # Request fanout histogram 1176system.cpu.toL2Bus.reqLayer0.occupancy 4982106500 # Layer occupancy (ticks) 1177system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) 1178system.cpu.toL2Bus.respLayer0.occupancy 112829788 # Layer occupancy (ticks) 1179system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1180system.cpu.toL2Bus.respLayer1.occupancy 4256050685 # Layer occupancy (ticks) 1181system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 1182system.membus.trans_dist::ReadReq 408353 # Transaction distribution 1183system.membus.trans_dist::ReadResp 408353 # Transaction distribution 1184system.membus.trans_dist::Writeback 292348 # Transaction distribution 1185system.membus.trans_dist::UpgradeReq 3 # Transaction distribution 1186system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 1187system.membus.trans_dist::ReadExReq 3665 # Transaction distribution 1188system.membus.trans_dist::ReadExResp 3665 # Transaction distribution 1189system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1116390 # Packet count per connected master and slave (bytes) 1190system.membus.pkt_count::total 1116390 # Packet count per connected master and slave (bytes) 1191system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45079424 # Cumulative packet size per connected master and slave (bytes) 1192system.membus.pkt_size::total 45079424 # Cumulative packet size per connected master and slave (bytes) 1193system.membus.snoops 0 # Total snoops (count) 1194system.membus.snoop_fanout::samples 704369 # Request fanout histogram 1195system.membus.snoop_fanout::mean 0 # Request fanout histogram 1196system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1197system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1198system.membus.snoop_fanout::0 704369 100.00% 100.00% # Request fanout histogram 1199system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1200system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1201system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1202system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1203system.membus.snoop_fanout::total 704369 # Request fanout histogram 1204system.membus.reqLayer0.occupancy 2100254662 # Layer occupancy (ticks) 1205system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 1206system.membus.respLayer1.occupancy 2178151058 # Layer occupancy (ticks) 1207system.membus.respLayer1.utilization 0.9 # Layer utilization (%) 1208 1209---------- End Simulation Statistics ---------- |