1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.233058 # Number of seconds simulated
4sim_ticks 233057542500 # Number of ticks simulated
5final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 104599 # Simulator instruction rate (inst/s)
8host_op_rate 117832 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 47897344 # Simulator tick rate (ticks/s)
10host_mem_usage 237516 # Number of bytes of host memory used
11host_seconds 4865.77 # Real time elapsed on the host
12sim_insts 508954936 # Number of instructions simulated
13sim_ops 573341497 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 15214144 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 10947904 # Number of bytes written to this memory
17system.physmem.num_reads 237721 # Number of read requests responded to by this memory
18system.physmem.num_writes 171061 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 331 unchanged lines hidden (view full) ---
363system.cpu.icache.overall_miss_latency::total 267894500 # number of overall miss cycles
364system.cpu.icache.ReadReq_accesses::cpu.inst 126860220 # number of ReadReq accesses(hits+misses)
365system.cpu.icache.ReadReq_accesses::total 126860220 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.demand_accesses::cpu.inst 126860220 # number of demand (read+write) accesses
367system.cpu.icache.demand_accesses::total 126860220 # number of demand (read+write) accesses
368system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses
369system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses
370system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses
371system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses
372system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses
373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency
374system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency
375system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency
376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
380system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
381system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
382system.cpu.icache.fast_writes 0 # number of fast writes performed
383system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 13 unchanged lines hidden (view full) ---
397system.cpu.icache.overall_mshr_misses::total 18132 # number of overall MSHR misses
398system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171640500 # number of ReadReq MSHR miss cycles
399system.cpu.icache.ReadReq_mshr_miss_latency::total 171640500 # number of ReadReq MSHR miss cycles
400system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171640500 # number of demand (read+write) MSHR miss cycles
401system.cpu.icache.demand_mshr_miss_latency::total 171640500 # number of demand (read+write) MSHR miss cycles
402system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles
403system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles
404system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses
405system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses
406system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses
407system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency
408system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency
409system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency
410system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
411system.cpu.dcache.replacements 1204809 # number of replacements
412system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use
413system.cpu.dcache.total_refs 197317737 # Total number of references to valid blocks.
414system.cpu.dcache.sampled_refs 1208905 # Sample count of references to valid blocks.
415system.cpu.dcache.avg_refs 163.220217 # Average number of references to valid blocks.
416system.cpu.dcache.warmup_cycle 5518270000 # Cycle when the warmup percentage was hit.
417system.cpu.dcache.occ_blocks::cpu.data 4052.906677 # Average occupied blocks per requestor
--- 39 unchanged lines hidden (view full) ---
457system.cpu.dcache.LoadLockedReq_accesses::total 2238567 # number of LoadLockedReq accesses(hits+misses)
458system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231982 # number of StoreCondReq accesses(hits+misses)
459system.cpu.dcache.StoreCondReq_accesses::total 2231982 # number of StoreCondReq accesses(hits+misses)
460system.cpu.dcache.demand_accesses::cpu.data 195622115 # number of demand (read+write) accesses
461system.cpu.dcache.demand_accesses::total 195622115 # number of demand (read+write) accesses
462system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses
463system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses
464system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses
465system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses
466system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses
467system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses
468system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses
469system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency
470system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency
471system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency
472system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency
473system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency
474system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
475system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked
476system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
477system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked
478system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
479system.cpu.dcache.avg_blocked_cycles::no_targets 6543.478261 # average number of cycles each access was blocked
480system.cpu.dcache.fast_writes 0 # number of fast writes performed
481system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 21 unchanged lines hidden (view full) ---
503system.cpu.dcache.ReadReq_mshr_miss_latency::total 6208585000 # number of ReadReq MSHR miss cycles
504system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4381340497 # number of WriteReq MSHR miss cycles
505system.cpu.dcache.WriteReq_mshr_miss_latency::total 4381340497 # number of WriteReq MSHR miss cycles
506system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10589925497 # number of demand (read+write) MSHR miss cycles
507system.cpu.dcache.demand_mshr_miss_latency::total 10589925497 # number of demand (read+write) MSHR miss cycles
508system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles
509system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles
510system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses
511system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses
512system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses
513system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses
514system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency
515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency
516system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency
517system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency
518system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
519system.cpu.l2cache.replacements 218501 # number of replacements
520system.cpu.l2cache.tagsinuse 20930.395337 # Cycle average of tags in use
521system.cpu.l2cache.total_refs 1557466 # Total number of references to valid blocks.
522system.cpu.l2cache.sampled_refs 238907 # Sample count of references to valid blocks.
523system.cpu.l2cache.avg_refs 6.519131 # Average number of references to valid blocks.
524system.cpu.l2cache.warmup_cycle 170551572000 # Cycle when the warmup percentage was hit.
525system.cpu.l2cache.occ_blocks::writebacks 13694.941090 # Average occupied blocks per requestor
--- 56 unchanged lines hidden (view full) ---
582system.cpu.l2cache.demand_accesses::cpu.inst 18017 # number of demand (read+write) accesses
583system.cpu.l2cache.demand_accesses::cpu.data 1208896 # number of demand (read+write) accesses
584system.cpu.l2cache.demand_accesses::total 1226913 # number of demand (read+write) accesses
585system.cpu.l2cache.overall_accesses::cpu.inst 18017 # number of overall (read+write) accesses
586system.cpu.l2cache.overall_accesses::cpu.data 1208896 # number of overall (read+write) accesses
587system.cpu.l2cache.overall_accesses::total 1226913 # number of overall (read+write) accesses
588system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.213798 # miss rate for ReadReq accesses
589system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.143718 # miss rate for ReadReq accesses
590system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for UpgradeReq accesses
591system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319698 # miss rate for ReadExReq accesses
592system.cpu.l2cache.demand_miss_rate::cpu.inst 0.213798 # miss rate for demand accesses
593system.cpu.l2cache.demand_miss_rate::cpu.data 0.193480 # miss rate for demand accesses
594system.cpu.l2cache.overall_miss_rate::cpu.inst 0.213798 # miss rate for overall accesses
595system.cpu.l2cache.overall_miss_rate::cpu.data 0.193480 # miss rate for overall accesses
596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.474559 # average ReadReq miss latency
597system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.118961 # average ReadReq miss latency
598system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6212.121212 # average UpgradeReq miss latency
599system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34242.649952 # average ReadExReq miss latency
600system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency
601system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency
602system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency
603system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency
604system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
605system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
606system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
607system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
608system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
609system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
610system.cpu.l2cache.fast_writes 0 # number of fast writes performed
611system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 31 unchanged lines hidden (view full) ---
643system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 119582500 # number of demand (read+write) MSHR miss cycles
644system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7255661000 # number of demand (read+write) MSHR miss cycles
645system.cpu.l2cache.demand_mshr_miss_latency::total 7375243500 # number of demand (read+write) MSHR miss cycles
646system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 119582500 # number of overall MSHR miss cycles
647system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7255661000 # number of overall MSHR miss cycles
648system.cpu.l2cache.overall_mshr_miss_latency::total 7375243500 # number of overall MSHR miss cycles
649system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for ReadReq accesses
650system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143693 # mshr miss rate for ReadReq accesses
651system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for UpgradeReq accesses
652system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319698 # mshr miss rate for ReadExReq accesses
653system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for demand accesses
654system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for demand accesses
655system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for overall accesses
656system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for overall accesses
657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385 # average ReadReq mshr miss latency
658system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970 # average ReadReq mshr miss latency
659system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545 # average UpgradeReq mshr miss latency
660system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency
661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency
662system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency
663system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency
664system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency
665system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
666
667---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.233058 # Number of seconds simulated
4sim_ticks 233057542500 # Number of ticks simulated
5final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 104599 # Simulator instruction rate (inst/s)
8host_op_rate 117832 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 47897344 # Simulator tick rate (ticks/s)
10host_mem_usage 237516 # Number of bytes of host memory used
11host_seconds 4865.77 # Real time elapsed on the host
12sim_insts 508954936 # Number of instructions simulated
13sim_ops 573341497 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 15214144 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 10947904 # Number of bytes written to this memory
17system.physmem.num_reads 237721 # Number of read requests responded to by this memory
18system.physmem.num_writes 171061 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 331 unchanged lines hidden (view full) ---
363system.cpu.icache.overall_miss_latency::total 267894500 # number of overall miss cycles
364system.cpu.icache.ReadReq_accesses::cpu.inst 126860220 # number of ReadReq accesses(hits+misses)
365system.cpu.icache.ReadReq_accesses::total 126860220 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.demand_accesses::cpu.inst 126860220 # number of demand (read+write) accesses
367system.cpu.icache.demand_accesses::total 126860220 # number of demand (read+write) accesses
368system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses
369system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses
370system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses
371system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses
372system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses
373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency
374system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency
375system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency
376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
380system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
381system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
382system.cpu.icache.fast_writes 0 # number of fast writes performed
383system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 13 unchanged lines hidden (view full) ---
397system.cpu.icache.overall_mshr_misses::total 18132 # number of overall MSHR misses
398system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171640500 # number of ReadReq MSHR miss cycles
399system.cpu.icache.ReadReq_mshr_miss_latency::total 171640500 # number of ReadReq MSHR miss cycles
400system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171640500 # number of demand (read+write) MSHR miss cycles
401system.cpu.icache.demand_mshr_miss_latency::total 171640500 # number of demand (read+write) MSHR miss cycles
402system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles
403system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles
404system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses
405system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses
406system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses
407system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency
408system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency
409system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency
410system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
411system.cpu.dcache.replacements 1204809 # number of replacements
412system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use
413system.cpu.dcache.total_refs 197317737 # Total number of references to valid blocks.
414system.cpu.dcache.sampled_refs 1208905 # Sample count of references to valid blocks.
415system.cpu.dcache.avg_refs 163.220217 # Average number of references to valid blocks.
416system.cpu.dcache.warmup_cycle 5518270000 # Cycle when the warmup percentage was hit.
417system.cpu.dcache.occ_blocks::cpu.data 4052.906677 # Average occupied blocks per requestor
--- 39 unchanged lines hidden (view full) ---
457system.cpu.dcache.LoadLockedReq_accesses::total 2238567 # number of LoadLockedReq accesses(hits+misses)
458system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231982 # number of StoreCondReq accesses(hits+misses)
459system.cpu.dcache.StoreCondReq_accesses::total 2231982 # number of StoreCondReq accesses(hits+misses)
460system.cpu.dcache.demand_accesses::cpu.data 195622115 # number of demand (read+write) accesses
461system.cpu.dcache.demand_accesses::total 195622115 # number of demand (read+write) accesses
462system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses
463system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses
464system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses
465system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses
466system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses
467system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses
468system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses
469system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency
470system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency
471system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency
472system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency
473system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency
474system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
475system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked
476system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
477system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked
478system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
479system.cpu.dcache.avg_blocked_cycles::no_targets 6543.478261 # average number of cycles each access was blocked
480system.cpu.dcache.fast_writes 0 # number of fast writes performed
481system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 21 unchanged lines hidden (view full) ---
503system.cpu.dcache.ReadReq_mshr_miss_latency::total 6208585000 # number of ReadReq MSHR miss cycles
504system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4381340497 # number of WriteReq MSHR miss cycles
505system.cpu.dcache.WriteReq_mshr_miss_latency::total 4381340497 # number of WriteReq MSHR miss cycles
506system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10589925497 # number of demand (read+write) MSHR miss cycles
507system.cpu.dcache.demand_mshr_miss_latency::total 10589925497 # number of demand (read+write) MSHR miss cycles
508system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles
509system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles
510system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses
511system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses
512system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses
513system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses
514system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency
515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency
516system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency
517system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency
518system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
519system.cpu.l2cache.replacements 218501 # number of replacements
520system.cpu.l2cache.tagsinuse 20930.395337 # Cycle average of tags in use
521system.cpu.l2cache.total_refs 1557466 # Total number of references to valid blocks.
522system.cpu.l2cache.sampled_refs 238907 # Sample count of references to valid blocks.
523system.cpu.l2cache.avg_refs 6.519131 # Average number of references to valid blocks.
524system.cpu.l2cache.warmup_cycle 170551572000 # Cycle when the warmup percentage was hit.
525system.cpu.l2cache.occ_blocks::writebacks 13694.941090 # Average occupied blocks per requestor
--- 56 unchanged lines hidden (view full) ---
582system.cpu.l2cache.demand_accesses::cpu.inst 18017 # number of demand (read+write) accesses
583system.cpu.l2cache.demand_accesses::cpu.data 1208896 # number of demand (read+write) accesses
584system.cpu.l2cache.demand_accesses::total 1226913 # number of demand (read+write) accesses
585system.cpu.l2cache.overall_accesses::cpu.inst 18017 # number of overall (read+write) accesses
586system.cpu.l2cache.overall_accesses::cpu.data 1208896 # number of overall (read+write) accesses
587system.cpu.l2cache.overall_accesses::total 1226913 # number of overall (read+write) accesses
588system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.213798 # miss rate for ReadReq accesses
589system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.143718 # miss rate for ReadReq accesses
590system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for UpgradeReq accesses
591system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319698 # miss rate for ReadExReq accesses
592system.cpu.l2cache.demand_miss_rate::cpu.inst 0.213798 # miss rate for demand accesses
593system.cpu.l2cache.demand_miss_rate::cpu.data 0.193480 # miss rate for demand accesses
594system.cpu.l2cache.overall_miss_rate::cpu.inst 0.213798 # miss rate for overall accesses
595system.cpu.l2cache.overall_miss_rate::cpu.data 0.193480 # miss rate for overall accesses
596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.474559 # average ReadReq miss latency
597system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.118961 # average ReadReq miss latency
598system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6212.121212 # average UpgradeReq miss latency
599system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34242.649952 # average ReadExReq miss latency
600system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency
601system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency
602system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency
603system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency
604system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
605system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
606system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
607system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
608system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
609system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
610system.cpu.l2cache.fast_writes 0 # number of fast writes performed
611system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 31 unchanged lines hidden (view full) ---
643system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 119582500 # number of demand (read+write) MSHR miss cycles
644system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7255661000 # number of demand (read+write) MSHR miss cycles
645system.cpu.l2cache.demand_mshr_miss_latency::total 7375243500 # number of demand (read+write) MSHR miss cycles
646system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 119582500 # number of overall MSHR miss cycles
647system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7255661000 # number of overall MSHR miss cycles
648system.cpu.l2cache.overall_mshr_miss_latency::total 7375243500 # number of overall MSHR miss cycles
649system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for ReadReq accesses
650system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143693 # mshr miss rate for ReadReq accesses
651system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for UpgradeReq accesses
652system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319698 # mshr miss rate for ReadExReq accesses
653system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for demand accesses
654system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for demand accesses
655system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for overall accesses
656system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for overall accesses
657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385 # average ReadReq mshr miss latency
658system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970 # average ReadReq mshr miss latency
659system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545 # average UpgradeReq mshr miss latency
660system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency
661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency
662system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency
663system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency
664system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency
665system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
666
667---------- End Simulation Statistics ----------