1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.195021 # Number of seconds simulated
4sim_ticks 195020773000 # Number of ticks simulated
5final_tick 195020773000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 105873 # Simulator instruction rate (inst/s)
8host_op_rate 114698 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 40866801 # Simulator tick rate (ticks/s)
10host_mem_usage 257276 # Number of bytes of host memory used
11host_seconds 4772.11 # Real time elapsed on the host
12sim_insts 505237723 # Number of instructions simulated
13sim_ops 547350944 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 207936 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9274560 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9482496 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 207936 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 207936 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 6243584 # Number of bytes written to this memory
22system.physmem.bytes_written::total 6243584 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 3249 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 144915 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 148164 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 97556 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 97556 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 1066225 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 47556780 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 48623005 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 1066225 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 1066225 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 32014969 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 32014969 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 32014969 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 1066225 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 47556780 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 80637974 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 148164 # Number of read requests accepted
40system.physmem.writeReqs 97556 # Number of write requests accepted
41system.physmem.readBursts 148164 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 97556 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 9474176 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
45system.physmem.bytesWritten 6241856 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 9482496 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 6243584 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 9585 # Per bank write bursts
52system.physmem.perBankRdBursts::1 9250 # Per bank write bursts
53system.physmem.perBankRdBursts::2 9223 # Per bank write bursts
54system.physmem.perBankRdBursts::3 8986 # Per bank write bursts
55system.physmem.perBankRdBursts::4 9777 # Per bank write bursts
56system.physmem.perBankRdBursts::5 9541 # Per bank write bursts
57system.physmem.perBankRdBursts::6 9063 # Per bank write bursts
58system.physmem.perBankRdBursts::7 8318 # Per bank write bursts
59system.physmem.perBankRdBursts::8 8791 # Per bank write bursts
60system.physmem.perBankRdBursts::9 8912 # Per bank write bursts
61system.physmem.perBankRdBursts::10 8928 # Per bank write bursts
62system.physmem.perBankRdBursts::11 9775 # Per bank write bursts
63system.physmem.perBankRdBursts::12 9650 # Per bank write bursts
64system.physmem.perBankRdBursts::13 9761 # Per bank write bursts
65system.physmem.perBankRdBursts::14 8979 # Per bank write bursts
66system.physmem.perBankRdBursts::15 9495 # Per bank write bursts
67system.physmem.perBankWrBursts::0 6258 # Per bank write bursts
68system.physmem.perBankWrBursts::1 6150 # Per bank write bursts
69system.physmem.perBankWrBursts::2 6073 # Per bank write bursts
70system.physmem.perBankWrBursts::3 5890 # Per bank write bursts
71system.physmem.perBankWrBursts::4 6255 # Per bank write bursts
72system.physmem.perBankWrBursts::5 6221 # Per bank write bursts
73system.physmem.perBankWrBursts::6 6024 # Per bank write bursts
74system.physmem.perBankWrBursts::7 5542 # Per bank write bursts
75system.physmem.perBankWrBursts::8 5802 # Per bank write bursts
76system.physmem.perBankWrBursts::9 5901 # Per bank write bursts
77system.physmem.perBankWrBursts::10 5976 # Per bank write bursts
78system.physmem.perBankWrBursts::11 6519 # Per bank write bursts
79system.physmem.perBankWrBursts::12 6371 # Per bank write bursts
80system.physmem.perBankWrBursts::13 6333 # Per bank write bursts
81system.physmem.perBankWrBursts::14 6062 # Per bank write bursts
82system.physmem.perBankWrBursts::15 6152 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 195020664000 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 148164 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 97556 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 137840 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 9554 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 574 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see

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139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 2105 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 2265 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 5823 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 5839 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 5855 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 5867 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 5891 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 5873 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 5884 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 5884 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 5906 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 5955 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 5832 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 5848 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 5868 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::33 21 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see

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188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196system.physmem.bytesPerActivate::samples 65254 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::mean 240.825329 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::gmean 153.977579 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::stdev 256.120796 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::0-127 26634 40.82% 40.82% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::128-255 17090 26.19% 67.01% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::256-383 6012 9.21% 76.22% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::384-511 6427 9.85% 86.07% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::512-639 3020 4.63% 90.70% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::640-767 1342 2.06% 92.75% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::768-895 838 1.28% 94.04% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::896-1023 692 1.06% 95.10% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1024-1151 3199 4.90% 100.00% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::total 65254 # Bytes accessed per row activation
210system.physmem.rdPerTurnAround::samples 5732 # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::mean 25.824669 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::stdev 376.283766 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::0-1023 5727 99.91% 99.91% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::total 5732 # Reads before turning the bus around for writes
217system.physmem.wrPerTurnAround::samples 5732 # Writes before turning the bus around for reads
218system.physmem.wrPerTurnAround::mean 17.014829 # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::gmean 16.919448 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::stdev 2.243342 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::16-17 3608 62.94% 62.94% # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::18-19 1943 33.90% 96.84% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::20-21 77 1.34% 98.19% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::22-23 32 0.56% 98.74% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::24-25 17 0.30% 99.04% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::28-29 11 0.19% 99.56% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::30-31 3 0.05% 99.62% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::32-33 2 0.03% 99.65% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::34-35 6 0.10% 99.76% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::36-37 2 0.03% 99.79% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::38-39 3 0.05% 99.84% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::40-41 2 0.03% 99.88% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::42-43 1 0.02% 99.90% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::50-51 3 0.05% 99.97% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::total 5732 # Writes before turning the bus around for reads
240system.physmem.totQLat 1847546250 # Total ticks spent queuing
241system.physmem.totMemAccLat 4623183750 # Total ticks spent from burst creation until serviced by the DRAM
242system.physmem.totBusLat 740170000 # Total ticks spent in databus transfers
243system.physmem.avgQLat 12480.55 # Average queueing delay per DRAM burst
244system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
245system.physmem.avgMemAccLat 31230.55 # Average memory access latency per DRAM burst
246system.physmem.avgRdBW 48.58 # Average DRAM read bandwidth in MiByte/s
247system.physmem.avgWrBW 32.01 # Average achieved write bandwidth in MiByte/s
248system.physmem.avgRdBWSys 48.62 # Average system read bandwidth in MiByte/s
249system.physmem.avgWrBWSys 32.01 # Average system write bandwidth in MiByte/s
250system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
251system.physmem.busUtil 0.63 # Data bus utilization in percentage
252system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads
253system.physmem.busUtilWrite 0.25 # Data bus utilization in percentage for writes
254system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
255system.physmem.avgWrQLen 19.21 # Average write queue length when enqueuing
256system.physmem.readRowHits 116004 # Number of row buffer hits during reads
257system.physmem.writeRowHits 64298 # Number of row buffer hits during writes
258system.physmem.readRowHitRate 78.36 # Row buffer hit rate for reads
259system.physmem.writeRowHitRate 65.91 # Row buffer hit rate for writes
260system.physmem.avgGap 793670.29 # Average gap between requests
261system.physmem.pageHitRate 73.42 # Row buffer hit rate, read and write combined
262system.physmem.memoryStateTime::IDLE 115260013250 # Time in different power states
263system.physmem.memoryStateTime::REF 6511960000 # Time in different power states
264system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
265system.physmem.memoryStateTime::ACT 73245775250 # Time in different power states
266system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
267system.membus.throughput 80637974 # Throughput (bytes/s)
268system.membus.trans_dist::ReadReq 46897 # Transaction distribution
269system.membus.trans_dist::ReadResp 46897 # Transaction distribution
270system.membus.trans_dist::Writeback 97556 # Transaction distribution
271system.membus.trans_dist::UpgradeReq 9 # Transaction distribution
272system.membus.trans_dist::UpgradeResp 9 # Transaction distribution
273system.membus.trans_dist::ReadExReq 101267 # Transaction distribution
274system.membus.trans_dist::ReadExResp 101267 # Transaction distribution
275system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393902 # Packet count per connected master and slave (bytes)
276system.membus.pkt_count::total 393902 # Packet count per connected master and slave (bytes)
277system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15726080 # Cumulative packet size per connected master and slave (bytes)
278system.membus.tot_pkt_size::total 15726080 # Cumulative packet size per connected master and slave (bytes)
279system.membus.data_through_bus 15726080 # Total data (bytes)
280system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
281system.membus.reqLayer0.occupancy 1079373000 # Layer occupancy (ticks)
282system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
283system.membus.respLayer1.occupancy 1394503741 # Layer occupancy (ticks)
284system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
285system.cpu_clk_domain.clock 500 # Clock period in ticks
286system.cpu.branchPred.lookups 200189098 # Number of BP lookups
287system.cpu.branchPred.condPredicted 149602484 # Number of conditional branches predicted
288system.cpu.branchPred.condIncorrect 7338467 # Number of conditional branches incorrect
289system.cpu.branchPred.BTBLookups 107397070 # Number of BTB lookups
290system.cpu.branchPred.BTBHits 96034676 # Number of BTB hits
291system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
292system.cpu.branchPred.BTBHitPct 89.420201 # BTB Hit Percentage
293system.cpu.branchPred.usedRAS 14381720 # Number of times the RAS was used to get a target.
294system.cpu.branchPred.RASInCorrect 112950 # Number of incorrect RAS predictions.
295system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
296system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
297system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
298system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
299system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
300system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
301system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
302system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

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372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
373system.cpu.itb.read_accesses 0 # DTB read accesses
374system.cpu.itb.write_accesses 0 # DTB write accesses
375system.cpu.itb.inst_accesses 0 # ITB inst accesses
376system.cpu.itb.hits 0 # DTB hits
377system.cpu.itb.misses 0 # DTB misses
378system.cpu.itb.accesses 0 # DTB accesses
379system.cpu.workload.num_syscalls 548 # Number of system calls
380system.cpu.numCycles 390041547 # number of cpu cycles simulated
381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
383system.cpu.fetch.icacheStallCycles 129697358 # Number of cycles fetch is stalled on an Icache miss
384system.cpu.fetch.Insts 835224616 # Number of instructions fetch has processed
385system.cpu.fetch.Branches 200189098 # Number of branches that fetch encountered
386system.cpu.fetch.predictedBranches 110416396 # Number of branches that fetch has predicted taken
387system.cpu.fetch.Cycles 251952283 # Number of cycles fetch has run and was not squashing or blocked
388system.cpu.fetch.SquashCycles 16305676 # Number of cycles fetch has spent squashing
389system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
390system.cpu.fetch.PendingTrapStallCycles 725 # Number of stall cycles due to pending traps
391system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR
392system.cpu.fetch.CacheLines 125022986 # Number of cache lines fetched
393system.cpu.fetch.IcacheSquashes 2819221 # Number of outstanding Icache misses that were squashed
394system.cpu.fetch.rateDist::samples 389803312 # Number of instructions fetched each cycle (Total)
395system.cpu.fetch.rateDist::mean 2.324321 # Number of instructions fetched each cycle (Total)
396system.cpu.fetch.rateDist::stdev 2.986703 # Number of instructions fetched each cycle (Total)
397system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
398system.cpu.fetch.rateDist::0 204497213 52.46% 52.46% # Number of instructions fetched each cycle (Total)
399system.cpu.fetch.rateDist::1 16740879 4.29% 56.76% # Number of instructions fetched each cycle (Total)
400system.cpu.fetch.rateDist::2 25096143 6.44% 63.19% # Number of instructions fetched each cycle (Total)
401system.cpu.fetch.rateDist::3 25406235 6.52% 69.71% # Number of instructions fetched each cycle (Total)
402system.cpu.fetch.rateDist::4 22255484 5.71% 75.42% # Number of instructions fetched each cycle (Total)
403system.cpu.fetch.rateDist::5 19361790 4.97% 80.39% # Number of instructions fetched each cycle (Total)
404system.cpu.fetch.rateDist::6 11228649 2.88% 83.27% # Number of instructions fetched each cycle (Total)
405system.cpu.fetch.rateDist::7 12061789 3.09% 86.36% # Number of instructions fetched each cycle (Total)
406system.cpu.fetch.rateDist::8 53155130 13.64% 100.00% # Number of instructions fetched each cycle (Total)
407system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
408system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
409system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
410system.cpu.fetch.rateDist::total 389803312 # Number of instructions fetched each cycle (Total)
411system.cpu.fetch.branchRate 0.513251 # Number of branch fetches per cycle
412system.cpu.fetch.rate 2.141373 # Number of inst fetches per cycle
413system.cpu.decode.IdleCycles 103986680 # Number of cycles decode is idle
414system.cpu.decode.BlockedCycles 118578898 # Number of cycles decode is blocked
415system.cpu.decode.RunCycles 144750042 # Number of cycles decode is running
416system.cpu.decode.UnblockCycles 14406980 # Number of cycles decode is unblocking
417system.cpu.decode.SquashCycles 8080712 # Number of cycles decode is squashing
418system.cpu.decode.BranchResolved 27470111 # Number of times decode resolved a branch
419system.cpu.decode.BranchMispred 74706 # Number of times decode detected a branch misprediction
420system.cpu.decode.DecodedInsts 847095448 # Number of instructions handled by decode
421system.cpu.decode.SquashedInsts 284101 # Number of squashed instructions handled by decode
422system.cpu.rename.SquashCycles 8080712 # Number of cycles rename is squashing
423system.cpu.rename.IdleCycles 110645607 # Number of cycles rename is idle
424system.cpu.rename.BlockCycles 38128402 # Number of cycles rename is blocking
425system.cpu.rename.serializeStallCycles 58728570 # count of cycles rename stalled for serializing inst
426system.cpu.rename.RunCycles 152416718 # Number of cycles rename is running
427system.cpu.rename.UnblockCycles 21803303 # Number of cycles rename is unblocking
428system.cpu.rename.RenamedInsts 812473012 # Number of instructions processed by rename
429system.cpu.rename.ROBFullEvents 12287 # Number of times rename has blocked due to ROB full
430system.cpu.rename.IQFullEvents 7169304 # Number of times rename has blocked due to IQ full
431system.cpu.rename.LQFullEvents 5481410 # Number of times rename has blocked due to LQ full
432system.cpu.rename.SQFullEvents 7159011 # Number of times rename has blocked due to SQ full
433system.cpu.rename.RenamedOperands 991790845 # Number of destination operands rename has renamed
434system.cpu.rename.RenameLookups 3569028243 # Number of register rename lookups that rename has made
435system.cpu.rename.int_rename_lookups 858899446 # Number of integer rename lookups
436system.cpu.rename.fp_rename_lookups 368 # Number of floating rename lookups
437system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
438system.cpu.rename.UndoneMaps 337667094 # Number of HB maps that are undone due to squashing
439system.cpu.rename.serializingInsts 2298389 # count of serializing insts renamed
440system.cpu.rename.tempSerializingInsts 3025745 # count of temporary serializing insts renamed
441system.cpu.rename.skidInsts 46474458 # count of insts added to the skid buffer
442system.cpu.memDep0.insertedLoads 165564895 # Number of loads inserted to the mem dependence unit.
443system.cpu.memDep0.insertedStores 77029612 # Number of stores inserted to the mem dependence unit.
444system.cpu.memDep0.conflictingLoads 33913346 # Number of conflicting loads.
445system.cpu.memDep0.conflictingStores 24718127 # Number of conflicting stores.
446system.cpu.iq.iqInstsAdded 764294822 # Number of instructions added to the IQ (excludes non-spec)
447system.cpu.iq.iqNonSpecInstsAdded 3785962 # Number of non-speculative instructions added to the IQ
448system.cpu.iq.iqInstsIssued 654447179 # Number of instructions issued
449system.cpu.iq.iqSquashedInstsIssued 456586 # Number of squashed instructions issued
450system.cpu.iq.iqSquashedInstsExamined 218477687 # Number of squashed instructions iterated over during squash; mainly for profiling
451system.cpu.iq.iqSquashedOperandsExamined 578622397 # Number of squashed operands that are examined and possibly removed from graph
452system.cpu.iq.iqSquashedNonSpecRemoved 808330 # Number of squashed non-spec instructions that were removed
453system.cpu.iq.issued_per_cycle::samples 389803312 # Number of insts issued each cycle
454system.cpu.iq.issued_per_cycle::mean 1.678916 # Number of insts issued each cycle
455system.cpu.iq.issued_per_cycle::stdev 1.824028 # Number of insts issued each cycle
456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
457system.cpu.iq.issued_per_cycle::0 146772690 37.65% 37.65% # Number of insts issued each cycle
458system.cpu.iq.issued_per_cycle::1 67318590 17.27% 54.92% # Number of insts issued each cycle
459system.cpu.iq.issued_per_cycle::2 64772838 16.62% 71.54% # Number of insts issued each cycle
460system.cpu.iq.issued_per_cycle::3 47064670 12.07% 83.61% # Number of insts issued each cycle
461system.cpu.iq.issued_per_cycle::4 29521584 7.57% 91.19% # Number of insts issued each cycle
462system.cpu.iq.issued_per_cycle::5 16702188 4.28% 95.47% # Number of insts issued each cycle
463system.cpu.iq.issued_per_cycle::6 11171964 2.87% 98.34% # Number of insts issued each cycle
464system.cpu.iq.issued_per_cycle::7 4070461 1.04% 99.38% # Number of insts issued each cycle
465system.cpu.iq.issued_per_cycle::8 2408327 0.62% 100.00% # Number of insts issued each cycle
466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
468system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
469system.cpu.iq.issued_per_cycle::total 389803312 # Number of insts issued each cycle
470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
471system.cpu.iq.fu_full::IntAlu 1532664 16.20% 16.20% # attempts to use FU when none available
472system.cpu.iq.fu_full::IntMult 0 0.00% 16.20% # attempts to use FU when none available
473system.cpu.iq.fu_full::IntDiv 0 0.00% 16.20% # attempts to use FU when none available
474system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.20% # attempts to use FU when none available
475system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.20% # attempts to use FU when none available
476system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.20% # attempts to use FU when none available
477system.cpu.iq.fu_full::FloatMult 0 0.00% 16.20% # attempts to use FU when none available
478system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.20% # attempts to use FU when none available
479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.20% # attempts to use FU when none available
480system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.20% # attempts to use FU when none available
481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.20% # attempts to use FU when none available
482system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.20% # attempts to use FU when none available
483system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.20% # attempts to use FU when none available
484system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.20% # attempts to use FU when none available
485system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.20% # attempts to use FU when none available
486system.cpu.iq.fu_full::SimdMult 0 0.00% 16.20% # attempts to use FU when none available
487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.20% # attempts to use FU when none available
488system.cpu.iq.fu_full::SimdShift 0 0.00% 16.20% # attempts to use FU when none available
489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.20% # attempts to use FU when none available
490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.20% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.20% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.20% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.20% # attempts to use FU when none available
494system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.20% # attempts to use FU when none available
495system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.20% # attempts to use FU when none available
496system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.20% # attempts to use FU when none available
497system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.20% # attempts to use FU when none available
498system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.20% # attempts to use FU when none available
499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.20% # attempts to use FU when none available
500system.cpu.iq.fu_full::MemRead 4929602 52.11% 68.31% # attempts to use FU when none available
501system.cpu.iq.fu_full::MemWrite 2998000 31.69% 100.00% # attempts to use FU when none available
502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
505system.cpu.iq.FU_type_0::IntAlu 441248731 67.42% 67.42% # Type of FU issued
506system.cpu.iq.FU_type_0::IntMult 435633 0.07% 67.49% # Type of FU issued
507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued
508system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued
509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued
510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued
511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued
512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued
513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued
514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued
515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued
516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued
517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued
518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued
519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued
520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued
521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued
522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued
523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued
524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued
525system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued
526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued
527system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued
528system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued
529system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.49% # Type of FU issued
530system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.49% # Type of FU issued
531system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.49% # Type of FU issued
532system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.49% # Type of FU issued
533system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.49% # Type of FU issued
534system.cpu.iq.FU_type_0::MemRead 147725739 22.57% 90.06% # Type of FU issued
535system.cpu.iq.FU_type_0::MemWrite 65037073 9.94% 100.00% # Type of FU issued
536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
538system.cpu.iq.FU_type_0::total 654447179 # Type of FU issued
539system.cpu.iq.rate 1.677891 # Inst issue rate
540system.cpu.iq.fu_busy_cnt 9460266 # FU busy when requested
541system.cpu.iq.fu_busy_rate 0.014455 # FU busy rate (busy events/executed inst)
542system.cpu.iq.int_inst_queue_reads 1708614343 # Number of integer instruction queue reads
543system.cpu.iq.int_inst_queue_writes 987386046 # Number of integer instruction queue writes
544system.cpu.iq.int_inst_queue_wakeup_accesses 633379143 # Number of integer instruction queue wakeup accesses
545system.cpu.iq.fp_inst_queue_reads 179 # Number of floating instruction queue reads
546system.cpu.iq.fp_inst_queue_writes 280 # Number of floating instruction queue writes
547system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
548system.cpu.iq.int_alu_accesses 663907354 # Number of integer alu accesses
549system.cpu.iq.fp_alu_accesses 91 # Number of floating point alu accesses
550system.cpu.iew.lsq.thread0.forwLoads 7666119 # Number of loads that had data forwarded from stores
551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
552system.cpu.iew.lsq.thread0.squashedLoads 49680139 # Number of loads squashed
553system.cpu.iew.lsq.thread0.ignoredResponses 29913 # Number of memory responses ignored because the instruction is squashed
554system.cpu.iew.lsq.thread0.memOrderViolation 831675 # Number of memory ordering violations
555system.cpu.iew.lsq.thread0.squashedStores 20169135 # Number of stores squashed
556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
558system.cpu.iew.lsq.thread0.rescheduledLoads 1622994 # Number of loads that were rescheduled
559system.cpu.iew.lsq.thread0.cacheBlocked 4397 # Number of times an access to memory failed due to the cache being blocked
560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
561system.cpu.iew.iewSquashCycles 8080712 # Number of cycles IEW is squashing
562system.cpu.iew.iewBlockCycles 32831376 # Number of cycles IEW is blocking
563system.cpu.iew.iewUnblockCycles 2550941 # Number of cycles IEW is unblocking
564system.cpu.iew.iewDispatchedInsts 769700415 # Number of instructions dispatched to IQ
565system.cpu.iew.iewDispSquashedInsts 729466 # Number of squashed instructions skipped by dispatch
566system.cpu.iew.iewDispLoadInsts 165564895 # Number of dispatched load instructions
567system.cpu.iew.iewDispStoreInsts 77029612 # Number of dispatched store instructions
568system.cpu.iew.iewDispNonSpecInsts 2297420 # Number of dispatched non-speculative instructions
569system.cpu.iew.iewIQFullEvents 241239 # Number of times the IQ has become full, causing a stall
570system.cpu.iew.iewLSQFullEvents 2243400 # Number of times the LSQ has become full, causing a stall
571system.cpu.iew.memOrderViolationEvents 831675 # Number of memory order violations
572system.cpu.iew.predictedTakenIncorrect 4474207 # Number of branches that were predicted taken incorrectly
573system.cpu.iew.predictedNotTakenIncorrect 4147009 # Number of branches that were predicted not taken incorrectly
574system.cpu.iew.branchMispredicts 8621216 # Number of branch mispredicts detected at execute
575system.cpu.iew.iewExecutedInsts 645315428 # Number of executed instructions
576system.cpu.iew.iewExecLoadInsts 144284542 # Number of load instructions executed
577system.cpu.iew.iewExecSquashedInsts 9131751 # Number of squashed instructions skipped in execute
578system.cpu.iew.exec_swp 0 # number of swp insts executed
579system.cpu.iew.exec_nop 1619631 # number of nop insts executed
580system.cpu.iew.exec_refs 207974195 # number of memory reference insts executed
581system.cpu.iew.exec_branches 141482846 # Number of branches executed
582system.cpu.iew.exec_stores 63689653 # Number of stores executed
583system.cpu.iew.exec_rate 1.654479 # Inst execution rate
584system.cpu.iew.wb_sent 638544011 # cumulative count of insts sent to commit
585system.cpu.iew.wb_count 633379159 # cumulative count of insts written-back
586system.cpu.iew.wb_producers 371951295 # num instructions producing a value
587system.cpu.iew.wb_consumers 631497340 # num instructions consuming a value
588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
589system.cpu.iew.wb_rate 1.623876 # insts written-back per cycle
590system.cpu.iew.wb_fanout 0.588999 # average fanout of values written-back
591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
592system.cpu.commit.commitSquashedInsts 221053017 # The number of squashed insts skipped by commit
593system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
594system.cpu.commit.branchMispredicts 7266341 # The number of times a branch was mispredicted
595system.cpu.commit.committed_per_cycle::samples 357986400 # Number of insts commited each cycle
596system.cpu.commit.committed_per_cycle::mean 1.532725 # Number of insts commited each cycle
597system.cpu.commit.committed_per_cycle::stdev 2.266212 # Number of insts commited each cycle
598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
599system.cpu.commit.committed_per_cycle::0 161840085 45.21% 45.21% # Number of insts commited each cycle
600system.cpu.commit.committed_per_cycle::1 93598872 26.15% 71.35% # Number of insts commited each cycle
601system.cpu.commit.committed_per_cycle::2 31669454 8.85% 80.20% # Number of insts commited each cycle
602system.cpu.commit.committed_per_cycle::3 16147172 4.51% 84.71% # Number of insts commited each cycle
603system.cpu.commit.committed_per_cycle::4 14656641 4.09% 88.81% # Number of insts commited each cycle
604system.cpu.commit.committed_per_cycle::5 6778711 1.89% 90.70% # Number of insts commited each cycle
605system.cpu.commit.committed_per_cycle::6 6277378 1.75% 92.45% # Number of insts commited each cycle
606system.cpu.commit.committed_per_cycle::7 3013551 0.84% 93.29% # Number of insts commited each cycle
607system.cpu.commit.committed_per_cycle::8 24004536 6.71% 100.00% # Number of insts commited each cycle
608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
611system.cpu.commit.committed_per_cycle::total 357986400 # Number of insts commited each cycle
612system.cpu.commit.committedInsts 506581607 # Number of instructions committed
613system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed
614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
615system.cpu.commit.refs 172745233 # Number of memory references committed
616system.cpu.commit.loads 115884756 # Number of loads committed
617system.cpu.commit.membars 1488542 # Number of memory barriers committed
618system.cpu.commit.branches 121548301 # Number of branches committed
619system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.

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649system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
650system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
651system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
652system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction
653system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction
654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
656system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction
657system.cpu.commit.bw_lim_events 24004536 # number cycles where commit BW limit reached
658system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
659system.cpu.rob.rob_reads 1103722571 # The number of ROB reads
660system.cpu.rob.rob_writes 1571491093 # The number of ROB writes
661system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself
662system.cpu.idleCycles 238235 # Total number of cycles that the CPU has spent unscheduled due to idling
663system.cpu.committedInsts 505237723 # Number of Instructions Simulated
664system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated
665system.cpu.cpi 0.771996 # CPI: Cycles Per Instruction
666system.cpu.cpi_total 0.771996 # CPI: Total CPI of All Threads
667system.cpu.ipc 1.295343 # IPC: Instructions Per Cycle
668system.cpu.ipc_total 1.295343 # IPC: Total IPC of All Threads
669system.cpu.int_regfile_reads 652860530 # number of integer regfile reads
670system.cpu.int_regfile_writes 354600440 # number of integer regfile writes
671system.cpu.fp_regfile_reads 16 # number of floating regfile reads
672system.cpu.cc_regfile_reads 2339325657 # number of cc regfile reads
673system.cpu.cc_regfile_writes 397666160 # number of cc regfile writes
674system.cpu.misc_regfile_reads 231739115 # number of misc regfile reads
675system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
676system.cpu.toL2Bus.throughput 764614178 # Throughput (bytes/s)
677system.cpu.toL2Bus.trans_dist::ReadReq 866616 # Transaction distribution
678system.cpu.toL2Bus.trans_dist::ReadResp 866616 # Transaction distribution
679system.cpu.toL2Bus.trans_dist::Writeback 1114497 # Transaction distribution
680system.cpu.toL2Bus.trans_dist::UpgradeReq 52 # Transaction distribution
681system.cpu.toL2Bus.trans_dist::UpgradeResp 52 # Transaction distribution
682system.cpu.toL2Bus.trans_dist::ReadExReq 348819 # Transaction distribution
683system.cpu.toL2Bus.trans_dist::ReadExResp 348819 # Transaction distribution
684system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30021 # Packet count per connected master and slave (bytes)
685system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3515389 # Packet count per connected master and slave (bytes)
686system.cpu.toL2Bus.pkt_count::total 3545410 # Packet count per connected master and slave (bytes)
687system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 958720 # Cumulative packet size per connected master and slave (bytes)
688system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 148153024 # Cumulative packet size per connected master and slave (bytes)
689system.cpu.toL2Bus.tot_pkt_size::total 149111744 # Cumulative packet size per connected master and slave (bytes)
690system.cpu.toL2Bus.data_through_bus 149111744 # Total data (bytes)
691system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes)
692system.cpu.toL2Bus.reqLayer0.occupancy 2279489000 # Layer occupancy (ticks)
693system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
694system.cpu.toL2Bus.respLayer0.occupancy 23116485 # Layer occupancy (ticks)
695system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
696system.cpu.toL2Bus.respLayer1.occupancy 1829335495 # Layer occupancy (ticks)
697system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
698system.cpu.icache.tags.replacements 13145 # number of replacements
699system.cpu.icache.tags.tagsinuse 1062.088688 # Cycle average of tags in use
700system.cpu.icache.tags.total_refs 125003617 # Total number of references to valid blocks.
701system.cpu.icache.tags.sampled_refs 14983 # Sample count of references to valid blocks.
702system.cpu.icache.tags.avg_refs 8343.029901 # Average number of references to valid blocks.
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706system.cpu.icache.tags.occ_percent::total 0.518598 # Average percentage of cache occupancy
707system.cpu.icache.tags.occ_task_id_blocks::1024 1838 # Occupied blocks per task id
708system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
709system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id
710system.cpu.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id
711system.cpu.icache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id
712system.cpu.icache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id
713system.cpu.icache.tags.occ_task_id_percent::1024 0.897461 # Percentage of cache occupancy per task id
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717system.cpu.icache.ReadReq_hits::total 125003619 # number of ReadReq hits
718system.cpu.icache.demand_hits::cpu.inst 125003619 # number of demand (read+write) hits
719system.cpu.icache.demand_hits::total 125003619 # number of demand (read+write) hits
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721system.cpu.icache.overall_hits::total 125003619 # number of overall hits
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723system.cpu.icache.ReadReq_misses::total 19366 # number of ReadReq misses
724system.cpu.icache.demand_misses::cpu.inst 19366 # number of demand (read+write) misses
725system.cpu.icache.demand_misses::total 19366 # number of demand (read+write) misses
726system.cpu.icache.overall_misses::cpu.inst 19366 # number of overall misses
727system.cpu.icache.overall_misses::total 19366 # number of overall misses
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729system.cpu.icache.ReadReq_miss_latency::total 525397483 # number of ReadReq miss cycles
730system.cpu.icache.demand_miss_latency::cpu.inst 525397483 # number of demand (read+write) miss cycles
731system.cpu.icache.demand_miss_latency::total 525397483 # number of demand (read+write) miss cycles
732system.cpu.icache.overall_miss_latency::cpu.inst 525397483 # number of overall miss cycles
733system.cpu.icache.overall_miss_latency::total 525397483 # number of overall miss cycles
734system.cpu.icache.ReadReq_accesses::cpu.inst 125022985 # number of ReadReq accesses(hits+misses)
735system.cpu.icache.ReadReq_accesses::total 125022985 # number of ReadReq accesses(hits+misses)
736system.cpu.icache.demand_accesses::cpu.inst 125022985 # number of demand (read+write) accesses
737system.cpu.icache.demand_accesses::total 125022985 # number of demand (read+write) accesses
738system.cpu.icache.overall_accesses::cpu.inst 125022985 # number of overall (read+write) accesses
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741system.cpu.icache.ReadReq_miss_rate::total 0.000155 # miss rate for ReadReq accesses
742system.cpu.icache.demand_miss_rate::cpu.inst 0.000155 # miss rate for demand accesses
743system.cpu.icache.demand_miss_rate::total 0.000155 # miss rate for demand accesses
744system.cpu.icache.overall_miss_rate::cpu.inst 0.000155 # miss rate for overall accesses
745system.cpu.icache.overall_miss_rate::total 0.000155 # miss rate for overall accesses
746system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27129.891717 # average ReadReq miss latency
747system.cpu.icache.ReadReq_avg_miss_latency::total 27129.891717 # average ReadReq miss latency
748system.cpu.icache.demand_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency
749system.cpu.icache.demand_avg_miss_latency::total 27129.891717 # average overall miss latency
750system.cpu.icache.overall_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency
751system.cpu.icache.overall_avg_miss_latency::total 27129.891717 # average overall miss latency
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754system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
755system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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757system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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762system.cpu.icache.demand_mshr_hits::cpu.inst 4325 # number of demand (read+write) MSHR hits
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764system.cpu.icache.overall_mshr_hits::cpu.inst 4325 # number of overall MSHR hits
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767system.cpu.icache.ReadReq_mshr_misses::total 15041 # number of ReadReq MSHR misses
768system.cpu.icache.demand_mshr_misses::cpu.inst 15041 # number of demand (read+write) MSHR misses
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777system.cpu.icache.overall_mshr_miss_latency::total 373138014 # number of overall MSHR miss cycles
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779system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000120 # mshr miss rate for ReadReq accesses
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781system.cpu.icache.demand_mshr_miss_rate::total 0.000120 # mshr miss rate for demand accesses
782system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for overall accesses
783system.cpu.icache.overall_mshr_miss_rate::total 0.000120 # mshr miss rate for overall accesses
784system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24808.058906 # average ReadReq mshr miss latency
785system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24808.058906 # average ReadReq mshr miss latency
786system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24808.058906 # average overall mshr miss latency
787system.cpu.icache.demand_avg_mshr_miss_latency::total 24808.058906 # average overall mshr miss latency
788system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24808.058906 # average overall mshr miss latency
789system.cpu.icache.overall_avg_mshr_miss_latency::total 24808.058906 # average overall mshr miss latency
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791system.cpu.l2cache.tags.replacements 115421 # number of replacements
792system.cpu.l2cache.tags.tagsinuse 26962.800734 # Cycle average of tags in use
793system.cpu.l2cache.tags.total_refs 1786499 # Total number of references to valid blocks.
794system.cpu.l2cache.tags.sampled_refs 146666 # Sample count of references to valid blocks.
795system.cpu.l2cache.tags.avg_refs 12.180730 # Average number of references to valid blocks.
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797system.cpu.l2cache.tags.occ_blocks::writebacks 22928.497316 # Average occupied blocks per requestor
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804system.cpu.l2cache.tags.occ_task_id_blocks::1024 31245 # Occupied blocks per task id
805system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
806system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2223 # Occupied blocks per task id
807system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7659 # Occupied blocks per task id
808system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21300 # Occupied blocks per task id
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815system.cpu.l2cache.Writeback_hits::writebacks 1114497 # number of Writeback hits
816system.cpu.l2cache.Writeback_hits::total 1114497 # number of Writeback hits
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949system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64538.644382 # average ReadReq mshr miss latency
950system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64322.174126 # average ReadReq mshr miss latency
951system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
952system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
953system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60050.660630 # average ReadExReq mshr miss latency
954system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60050.660630 # average ReadExReq mshr miss latency
955system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61414.050477 # average overall mshr miss latency
956system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61402.429010 # average overall mshr miss latency
957system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61402.683850 # average overall mshr miss latency
958system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61414.050477 # average overall mshr miss latency
959system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61402.429010 # average overall mshr miss latency
960system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61402.683850 # average overall mshr miss latency
961system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
962system.cpu.dcache.tags.replacements 1196298 # number of replacements
963system.cpu.dcache.tags.tagsinuse 4055.671895 # Cycle average of tags in use
964system.cpu.dcache.tags.total_refs 184137490 # Total number of references to valid blocks.
965system.cpu.dcache.tags.sampled_refs 1200394 # Sample count of references to valid blocks.
966system.cpu.dcache.tags.avg_refs 153.397543 # Average number of references to valid blocks.
967system.cpu.dcache.tags.warmup_cycle 4287130250 # Cycle when the warmup percentage was hit.
968system.cpu.dcache.tags.occ_blocks::cpu.data 4055.671895 # Average occupied blocks per requestor
969system.cpu.dcache.tags.occ_percent::cpu.data 0.990154 # Average percentage of cache occupancy
970system.cpu.dcache.tags.occ_percent::total 0.990154 # Average percentage of cache occupancy
971system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
972system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
973system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
974system.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id
975system.cpu.dcache.tags.age_task_id_blocks_1024::3 1686 # Occupied blocks per task id
976system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
977system.cpu.dcache.tags.tag_accesses 379628218 # Number of tag accesses
978system.cpu.dcache.tags.data_accesses 379628218 # Number of data accesses
979system.cpu.dcache.ReadReq_hits::cpu.data 130278206 # number of ReadReq hits
980system.cpu.dcache.ReadReq_hits::total 130278206 # number of ReadReq hits
981system.cpu.dcache.WriteReq_hits::cpu.data 50877875 # number of WriteReq hits
982system.cpu.dcache.WriteReq_hits::total 50877875 # number of WriteReq hits
983system.cpu.dcache.SoftPFReq_hits::cpu.data 3872 # number of SoftPFReq hits
984system.cpu.dcache.SoftPFReq_hits::total 3872 # number of SoftPFReq hits
985system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488856 # number of LoadLockedReq hits
986system.cpu.dcache.LoadLockedReq_hits::total 1488856 # number of LoadLockedReq hits
987system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
988system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
989system.cpu.dcache.demand_hits::cpu.data 181156081 # number of demand (read+write) hits
990system.cpu.dcache.demand_hits::total 181156081 # number of demand (read+write) hits
991system.cpu.dcache.overall_hits::cpu.data 181159953 # number of overall hits
992system.cpu.dcache.overall_hits::total 181159953 # number of overall hits
993system.cpu.dcache.ReadReq_misses::cpu.data 1715015 # number of ReadReq misses
994system.cpu.dcache.ReadReq_misses::total 1715015 # number of ReadReq misses
995system.cpu.dcache.WriteReq_misses::cpu.data 3361431 # number of WriteReq misses
996system.cpu.dcache.WriteReq_misses::total 3361431 # number of WriteReq misses
997system.cpu.dcache.SoftPFReq_misses::cpu.data 76 # number of SoftPFReq misses
998system.cpu.dcache.SoftPFReq_misses::total 76 # number of SoftPFReq misses
999system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses
1000system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses
1001system.cpu.dcache.demand_misses::cpu.data 5076446 # number of demand (read+write) misses
1002system.cpu.dcache.demand_misses::total 5076446 # number of demand (read+write) misses
1003system.cpu.dcache.overall_misses::cpu.data 5076522 # number of overall misses
1004system.cpu.dcache.overall_misses::total 5076522 # number of overall misses
1005system.cpu.dcache.ReadReq_miss_latency::cpu.data 29355008484 # number of ReadReq miss cycles
1006system.cpu.dcache.ReadReq_miss_latency::total 29355008484 # number of ReadReq miss cycles
1007system.cpu.dcache.WriteReq_miss_latency::cpu.data 73441852684 # number of WriteReq miss cycles
1008system.cpu.dcache.WriteReq_miss_latency::total 73441852684 # number of WriteReq miss cycles
1009system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 636000 # number of LoadLockedReq miss cycles
1010system.cpu.dcache.LoadLockedReq_miss_latency::total 636000 # number of LoadLockedReq miss cycles
1011system.cpu.dcache.demand_miss_latency::cpu.data 102796861168 # number of demand (read+write) miss cycles
1012system.cpu.dcache.demand_miss_latency::total 102796861168 # number of demand (read+write) miss cycles
1013system.cpu.dcache.overall_miss_latency::cpu.data 102796861168 # number of overall miss cycles
1014system.cpu.dcache.overall_miss_latency::total 102796861168 # number of overall miss cycles
1015system.cpu.dcache.ReadReq_accesses::cpu.data 131993221 # number of ReadReq accesses(hits+misses)
1016system.cpu.dcache.ReadReq_accesses::total 131993221 # number of ReadReq accesses(hits+misses)
1017system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
1018system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
1019system.cpu.dcache.SoftPFReq_accesses::cpu.data 3948 # number of SoftPFReq accesses(hits+misses)
1020system.cpu.dcache.SoftPFReq_accesses::total 3948 # number of SoftPFReq accesses(hits+misses)
1021system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488896 # number of LoadLockedReq accesses(hits+misses)
1022system.cpu.dcache.LoadLockedReq_accesses::total 1488896 # number of LoadLockedReq accesses(hits+misses)
1023system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
1024system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
1025system.cpu.dcache.demand_accesses::cpu.data 186232527 # number of demand (read+write) accesses
1026system.cpu.dcache.demand_accesses::total 186232527 # number of demand (read+write) accesses
1027system.cpu.dcache.overall_accesses::cpu.data 186236475 # number of overall (read+write) accesses
1028system.cpu.dcache.overall_accesses::total 186236475 # number of overall (read+write) accesses
1029system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012993 # miss rate for ReadReq accesses
1030system.cpu.dcache.ReadReq_miss_rate::total 0.012993 # miss rate for ReadReq accesses
1031system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061974 # miss rate for WriteReq accesses
1032system.cpu.dcache.WriteReq_miss_rate::total 0.061974 # miss rate for WriteReq accesses
1033system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.019250 # miss rate for SoftPFReq accesses
1034system.cpu.dcache.SoftPFReq_miss_rate::total 0.019250 # miss rate for SoftPFReq accesses
1035system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000027 # miss rate for LoadLockedReq accesses
1036system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000027 # miss rate for LoadLockedReq accesses
1037system.cpu.dcache.demand_miss_rate::cpu.data 0.027259 # miss rate for demand accesses
1038system.cpu.dcache.demand_miss_rate::total 0.027259 # miss rate for demand accesses
1039system.cpu.dcache.overall_miss_rate::cpu.data 0.027258 # miss rate for overall accesses
1040system.cpu.dcache.overall_miss_rate::total 0.027258 # miss rate for overall accesses
1041system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17116.473316 # average ReadReq miss latency
1042system.cpu.dcache.ReadReq_avg_miss_latency::total 17116.473316 # average ReadReq miss latency
1043system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21848.389178 # average WriteReq miss latency
1044system.cpu.dcache.WriteReq_avg_miss_latency::total 21848.389178 # average WriteReq miss latency
1045system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15900 # average LoadLockedReq miss latency
1046system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15900 # average LoadLockedReq miss latency
1047system.cpu.dcache.demand_avg_miss_latency::cpu.data 20249.769458 # average overall miss latency
1048system.cpu.dcache.demand_avg_miss_latency::total 20249.769458 # average overall miss latency
1049system.cpu.dcache.overall_avg_miss_latency::cpu.data 20249.466302 # average overall miss latency
1050system.cpu.dcache.overall_avg_miss_latency::total 20249.466302 # average overall miss latency
1051system.cpu.dcache.blocked_cycles::no_mshrs 21467 # number of cycles access was blocked
1052system.cpu.dcache.blocked_cycles::no_targets 55050 # number of cycles access was blocked
1053system.cpu.dcache.blocked::no_mshrs 2269 # number of cycles access was blocked
1054system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked
1055system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.460996 # average number of cycles each access was blocked
1056system.cpu.dcache.avg_blocked_cycles::no_targets 83.282905 # average number of cycles each access was blocked
1057system.cpu.dcache.fast_writes 0 # number of fast writes performed
1058system.cpu.dcache.cache_copies 0 # number of cache copies performed
1059system.cpu.dcache.writebacks::writebacks 1114497 # number of writebacks
1060system.cpu.dcache.writebacks::total 1114497 # number of writebacks
1061system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862982 # number of ReadReq MSHR hits
1062system.cpu.dcache.ReadReq_mshr_hits::total 862982 # number of ReadReq MSHR hits
1063system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3013069 # number of WriteReq MSHR hits
1064system.cpu.dcache.WriteReq_mshr_hits::total 3013069 # number of WriteReq MSHR hits
1065system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits
1066system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits
1067system.cpu.dcache.demand_mshr_hits::cpu.data 3876051 # number of demand (read+write) MSHR hits
1068system.cpu.dcache.demand_mshr_hits::total 3876051 # number of demand (read+write) MSHR hits
1069system.cpu.dcache.overall_mshr_hits::cpu.data 3876051 # number of overall MSHR hits
1070system.cpu.dcache.overall_mshr_hits::total 3876051 # number of overall MSHR hits
1071system.cpu.dcache.ReadReq_mshr_misses::cpu.data 852033 # number of ReadReq MSHR misses
1072system.cpu.dcache.ReadReq_mshr_misses::total 852033 # number of ReadReq MSHR misses
1073system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348362 # number of WriteReq MSHR misses
1074system.cpu.dcache.WriteReq_mshr_misses::total 348362 # number of WriteReq MSHR misses
1075system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 51 # number of SoftPFReq MSHR misses
1076system.cpu.dcache.SoftPFReq_mshr_misses::total 51 # number of SoftPFReq MSHR misses
1077system.cpu.dcache.demand_mshr_misses::cpu.data 1200395 # number of demand (read+write) MSHR misses
1078system.cpu.dcache.demand_mshr_misses::total 1200395 # number of demand (read+write) MSHR misses
1079system.cpu.dcache.overall_mshr_misses::cpu.data 1200446 # number of overall MSHR misses
1080system.cpu.dcache.overall_mshr_misses::total 1200446 # number of overall MSHR misses
1081system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12334131763 # number of ReadReq MSHR miss cycles
1082system.cpu.dcache.ReadReq_mshr_miss_latency::total 12334131763 # number of ReadReq MSHR miss cycles
1083system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10183047234 # number of WriteReq MSHR miss cycles
1084system.cpu.dcache.WriteReq_mshr_miss_latency::total 10183047234 # number of WriteReq MSHR miss cycles
1085system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2581000 # number of SoftPFReq MSHR miss cycles
1086system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2581000 # number of SoftPFReq MSHR miss cycles
1087system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22517178997 # number of demand (read+write) MSHR miss cycles
1088system.cpu.dcache.demand_mshr_miss_latency::total 22517178997 # number of demand (read+write) MSHR miss cycles
1089system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22519759997 # number of overall MSHR miss cycles
1090system.cpu.dcache.overall_mshr_miss_latency::total 22519759997 # number of overall MSHR miss cycles
1091system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006455 # mshr miss rate for ReadReq accesses
1092system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006455 # mshr miss rate for ReadReq accesses
1093system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
1094system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
1095system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for SoftPFReq accesses
1096system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.012918 # mshr miss rate for SoftPFReq accesses
1097system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for demand accesses
1098system.cpu.dcache.demand_mshr_miss_rate::total 0.006446 # mshr miss rate for demand accesses
1099system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for overall accesses
1100system.cpu.dcache.overall_mshr_miss_rate::total 0.006446 # mshr miss rate for overall accesses
1101system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14476.119778 # average ReadReq mshr miss latency
1102system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14476.119778 # average ReadReq mshr miss latency
1103system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29231.222791 # average WriteReq mshr miss latency
1104system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29231.222791 # average WriteReq mshr miss latency
1105system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50607.843137 # average SoftPFReq mshr miss latency
1106system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50607.843137 # average SoftPFReq mshr miss latency
1107system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18758.141276 # average overall mshr miss latency
1108system.cpu.dcache.demand_avg_mshr_miss_latency::total 18758.141276 # average overall mshr miss latency
1109system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18759.494385 # average overall mshr miss latency
1110system.cpu.dcache.overall_avg_mshr_miss_latency::total 18759.494385 # average overall mshr miss latency
1111system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1112
1113---------- End Simulation Statistics ----------