1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.199930 # Number of seconds simulated
4sim_ticks 199930442500 # Number of ticks simulated
5final_tick 199930442500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 127290 # Simulator instruction rate (inst/s)
8host_op_rate 143512 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 50370674 # Simulator tick rate (ticks/s)
10host_mem_usage 265580 # Number of bytes of host memory used
11host_seconds 3969.18 # Real time elapsed on the host
12sim_insts 505237723 # Number of instructions simulated
13sim_ops 569624283 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 216192 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 9265152 # Number of bytes read from this memory
16system.physmem.bytes_read::total 9481344 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 216192 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 216192 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 6247552 # Number of bytes written to this memory
20system.physmem.bytes_written::total 6247552 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 3378 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 144768 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 148146 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 97618 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 97618 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 1081336 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 46341877 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 47423213 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 1081336 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 1081336 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 31248628 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 31248628 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 31248628 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 1081336 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 46341877 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 78671841 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.readReqs 148147 # Total number of read requests seen
38system.physmem.writeReqs 97618 # Total number of write requests seen
39system.physmem.cpureqs 247832 # Reqs generatd by CPU via cache - shady
40system.physmem.bytesRead 9481344 # Total number of bytes read from memory
41system.physmem.bytesWritten 6247552 # Total number of bytes written to memory
42system.physmem.bytesConsumedRd 9481344 # bytesRead derated as per pkt->getSize()
43system.physmem.bytesConsumedWr 6247552 # bytesWritten derated as per pkt->getSize()
44system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
45system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed
46system.physmem.perBankRdReqs::0 9166 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::1 9182 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::2 9622 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::3 9866 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::4 9514 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::5 9519 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::6 9403 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::7 9092 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::8 9052 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::9 9254 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::10 8851 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::11 9077 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::12 9220 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::13 9034 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::14 9025 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::15 9210 # Track reads on a per bank basis
62system.physmem.perBankWrReqs::0 5950 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::1 5982 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::2 6289 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::3 6482 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::4 6170 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::5 6223 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::6 6230 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::7 6032 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::8 5973 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::9 6184 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::10 5908 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::11 6109 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::12 5989 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::13 5940 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::14 6062 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::15 6095 # Track writes on a per bank basis
78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
79system.physmem.numWrRetry 2058 # Number of times wr buffer was full causing retry
80system.physmem.totGap 199930425500 # Total gap between requests
81system.physmem.readPktSize::0 0 # Categorize read packet sizes
82system.physmem.readPktSize::1 0 # Categorize read packet sizes
83system.physmem.readPktSize::2 0 # Categorize read packet sizes
84system.physmem.readPktSize::3 0 # Categorize read packet sizes
85system.physmem.readPktSize::4 0 # Categorize read packet sizes
86system.physmem.readPktSize::5 0 # Categorize read packet sizes
87system.physmem.readPktSize::6 148147 # Categorize read packet sizes
88system.physmem.writePktSize::0 0 # Categorize write packet sizes
89system.physmem.writePktSize::1 0 # Categorize write packet sizes
90system.physmem.writePktSize::2 0 # Categorize write packet sizes
91system.physmem.writePktSize::3 0 # Categorize write packet sizes
92system.physmem.writePktSize::4 0 # Categorize write packet sizes
93system.physmem.writePktSize::5 0 # Categorize write packet sizes
94system.physmem.writePktSize::6 97618 # Categorize write packet sizes
95system.physmem.rdQLenPdf::0 137980 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::1 9444 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see

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119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
127system.physmem.wrQLenPdf::0 4208 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::1 4224 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::2 4229 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::3 4230 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::4 4232 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::5 4234 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::6 4234 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::7 4234 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::8 4234 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::23 37 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
159system.physmem.totQLat 1712037750 # Total cycles spent in queuing delays
160system.physmem.totMemAccLat 4981606500 # Sum of mem lat for all requests
161system.physmem.totBusLat 740435000 # Total cycles spent in databus access
162system.physmem.totBankLat 2529133750 # Total cycles spent in bank access
163system.physmem.avgQLat 11561.03 # Average queueing delay per request
164system.physmem.avgBankLat 17078.70 # Average bank access latency per request
165system.physmem.avgBusLat 5000.00 # Average bus latency per request
166system.physmem.avgMemAccLat 33639.73 # Average memory access latency
167system.physmem.avgRdBW 47.42 # Average achieved read bandwidth in MB/s
168system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s
169system.physmem.avgConsumedRdBW 47.42 # Average consumed read bandwidth in MB/s
170system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s
171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
172system.physmem.busUtil 0.61 # Data bus utilization in percentage
173system.physmem.avgRdQLen 0.02 # Average read queue length over time
174system.physmem.avgWrQLen 8.71 # Average write queue length over time
175system.physmem.readRowHits 125393 # Number of row buffer hits during reads
176system.physmem.writeRowHits 52794 # Number of row buffer hits during writes
177system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads
178system.physmem.writeRowHitRate 54.08 # Row buffer hit rate for writes
179system.physmem.avgGap 813502.43 # Average gap between requests
180system.cpu.branchPred.lookups 182807672 # Number of BP lookups
181system.cpu.branchPred.condPredicted 143119940 # Number of conditional branches predicted
182system.cpu.branchPred.condIncorrect 7265200 # Number of conditional branches incorrect
183system.cpu.branchPred.BTBLookups 92612738 # Number of BTB lookups
184system.cpu.branchPred.BTBHits 87226650 # Number of BTB hits
185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
186system.cpu.branchPred.BTBHitPct 94.184290 # BTB Hit Percentage
187system.cpu.branchPred.usedRAS 12677704 # Number of times the RAS was used to get a target.
188system.cpu.branchPred.RASInCorrect 116304 # Number of incorrect RAS predictions.
189system.cpu.dtb.inst_hits 0 # ITB inst hits
190system.cpu.dtb.inst_misses 0 # ITB inst misses
191system.cpu.dtb.read_hits 0 # DTB read hits
192system.cpu.dtb.read_misses 0 # DTB read misses
193system.cpu.dtb.write_hits 0 # DTB write hits
194system.cpu.dtb.write_misses 0 # DTB write misses
195system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
196system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 27 unchanged lines hidden (view full) ---

224system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
225system.cpu.itb.read_accesses 0 # DTB read accesses
226system.cpu.itb.write_accesses 0 # DTB write accesses
227system.cpu.itb.inst_accesses 0 # ITB inst accesses
228system.cpu.itb.hits 0 # DTB hits
229system.cpu.itb.misses 0 # DTB misses
230system.cpu.itb.accesses 0 # DTB accesses
231system.cpu.workload.num_syscalls 548 # Number of system calls
232system.cpu.numCycles 399860886 # number of cpu cycles simulated
233system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
234system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
235system.cpu.fetch.icacheStallCycles 119358222 # Number of cycles fetch is stalled on an Icache miss
236system.cpu.fetch.Insts 761608008 # Number of instructions fetch has processed
237system.cpu.fetch.Branches 182807672 # Number of branches that fetch encountered
238system.cpu.fetch.predictedBranches 99904354 # Number of branches that fetch has predicted taken
239system.cpu.fetch.Cycles 170147877 # Number of cycles fetch has run and was not squashing or blocked
240system.cpu.fetch.SquashCycles 35680811 # Number of cycles fetch has spent squashing
241system.cpu.fetch.BlockedCycles 75396284 # Number of cycles fetch has spent blocked
242system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
243system.cpu.fetch.PendingTrapStallCycles 468 # Number of stall cycles due to pending traps
244system.cpu.fetch.IcacheWaitRetryStallCycles 45 # Number of stall cycles due to full MSHR
245system.cpu.fetch.CacheLines 114514342 # Number of cache lines fetched
246system.cpu.fetch.IcacheSquashes 2439022 # Number of outstanding Icache misses that were squashed
247system.cpu.fetch.rateDist::samples 392517505 # Number of instructions fetched each cycle (Total)
248system.cpu.fetch.rateDist::mean 2.176152 # Number of instructions fetched each cycle (Total)
249system.cpu.fetch.rateDist::stdev 2.990501 # Number of instructions fetched each cycle (Total)
250system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
251system.cpu.fetch.rateDist::0 222382247 56.66% 56.66% # Number of instructions fetched each cycle (Total)
252system.cpu.fetch.rateDist::1 14190044 3.62% 60.27% # Number of instructions fetched each cycle (Total)
253system.cpu.fetch.rateDist::2 22888927 5.83% 66.10% # Number of instructions fetched each cycle (Total)
254system.cpu.fetch.rateDist::3 22740218 5.79% 71.90% # Number of instructions fetched each cycle (Total)
255system.cpu.fetch.rateDist::4 20908888 5.33% 77.22% # Number of instructions fetched each cycle (Total)
256system.cpu.fetch.rateDist::5 11594217 2.95% 80.18% # Number of instructions fetched each cycle (Total)
257system.cpu.fetch.rateDist::6 13063164 3.33% 83.50% # Number of instructions fetched each cycle (Total)
258system.cpu.fetch.rateDist::7 11994936 3.06% 86.56% # Number of instructions fetched each cycle (Total)
259system.cpu.fetch.rateDist::8 52754864 13.44% 100.00% # Number of instructions fetched each cycle (Total)
260system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
261system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
262system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
263system.cpu.fetch.rateDist::total 392517505 # Number of instructions fetched each cycle (Total)
264system.cpu.fetch.branchRate 0.457178 # Number of branch fetches per cycle
265system.cpu.fetch.rate 1.904682 # Number of inst fetches per cycle
266system.cpu.decode.IdleCycles 129005298 # Number of cycles decode is idle
267system.cpu.decode.BlockedCycles 70927026 # Number of cycles decode is blocked
268system.cpu.decode.RunCycles 158858538 # Number of cycles decode is running
269system.cpu.decode.UnblockCycles 6186097 # Number of cycles decode is unblocking
270system.cpu.decode.SquashCycles 27540546 # Number of cycles decode is squashing
271system.cpu.decode.BranchResolved 26127343 # Number of times decode resolved a branch
272system.cpu.decode.BranchMispred 76683 # Number of times decode detected a branch misprediction
273system.cpu.decode.DecodedInsts 825553021 # Number of instructions handled by decode
274system.cpu.decode.SquashedInsts 296390 # Number of squashed instructions handled by decode
275system.cpu.rename.SquashCycles 27540546 # Number of cycles rename is squashing
276system.cpu.rename.IdleCycles 135586345 # Number of cycles rename is idle
277system.cpu.rename.BlockCycles 9628782 # Number of cycles rename is blocking
278system.cpu.rename.serializeStallCycles 46469860 # count of cycles rename stalled for serializing inst
279system.cpu.rename.RunCycles 158285767 # Number of cycles rename is running
280system.cpu.rename.UnblockCycles 15006205 # Number of cycles rename is unblocking
281system.cpu.rename.RenamedInsts 800628342 # Number of instructions processed by rename
282system.cpu.rename.ROBFullEvents 1130 # Number of times rename has blocked due to ROB full
283system.cpu.rename.IQFullEvents 3045894 # Number of times rename has blocked due to IQ full
284system.cpu.rename.LSQFullEvents 8758928 # Number of times rename has blocked due to LSQ full
285system.cpu.rename.FullRegisterEvents 294 # Number of times there has been no free registers
286system.cpu.rename.RenamedOperands 954382842 # Number of destination operands rename has renamed
287system.cpu.rename.RenameLookups 3500628672 # Number of register rename lookups that rename has made
288system.cpu.rename.int_rename_lookups 3500627387 # Number of integer rename lookups
289system.cpu.rename.fp_rename_lookups 1285 # Number of floating rename lookups
290system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
291system.cpu.rename.UndoneMaps 288130551 # Number of HB maps that are undone due to squashing
292system.cpu.rename.serializingInsts 2292970 # count of serializing insts renamed
293system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed
294system.cpu.rename.skidInsts 41448640 # count of insts added to the skid buffer
295system.cpu.memDep0.insertedLoads 170247105 # Number of loads inserted to the mem dependence unit.
296system.cpu.memDep0.insertedStores 73473871 # Number of stores inserted to the mem dependence unit.
297system.cpu.memDep0.conflictingLoads 28488219 # Number of conflicting loads.
298system.cpu.memDep0.conflictingStores 15923707 # Number of conflicting stores.
299system.cpu.iq.iqInstsAdded 755060750 # Number of instructions added to the IQ (excludes non-spec)
300system.cpu.iq.iqNonSpecInstsAdded 3775315 # Number of non-speculative instructions added to the IQ
301system.cpu.iq.iqInstsIssued 665323167 # Number of instructions issued
302system.cpu.iq.iqSquashedInstsIssued 1373619 # Number of squashed instructions issued
303system.cpu.iq.iqSquashedInstsExamined 187375419 # Number of squashed instructions iterated over during squash; mainly for profiling
304system.cpu.iq.iqSquashedOperandsExamined 479909972 # Number of squashed operands that are examined and possibly removed from graph
305system.cpu.iq.iqSquashedNonSpecRemoved 797683 # Number of squashed non-spec instructions that were removed
306system.cpu.iq.issued_per_cycle::samples 392517505 # Number of insts issued each cycle
307system.cpu.iq.issued_per_cycle::mean 1.695015 # Number of insts issued each cycle
308system.cpu.iq.issued_per_cycle::stdev 1.735938 # Number of insts issued each cycle
309system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
310system.cpu.iq.issued_per_cycle::0 137188203 34.95% 34.95% # Number of insts issued each cycle
311system.cpu.iq.issued_per_cycle::1 69757763 17.77% 52.72% # Number of insts issued each cycle
312system.cpu.iq.issued_per_cycle::2 71444239 18.20% 70.92% # Number of insts issued each cycle
313system.cpu.iq.issued_per_cycle::3 53382766 13.60% 84.52% # Number of insts issued each cycle
314system.cpu.iq.issued_per_cycle::4 31199092 7.95% 92.47% # Number of insts issued each cycle
315system.cpu.iq.issued_per_cycle::5 16084863 4.10% 96.57% # Number of insts issued each cycle
316system.cpu.iq.issued_per_cycle::6 8731670 2.22% 98.80% # Number of insts issued each cycle
317system.cpu.iq.issued_per_cycle::7 2913347 0.74% 99.54% # Number of insts issued each cycle
318system.cpu.iq.issued_per_cycle::8 1815562 0.46% 100.00% # Number of insts issued each cycle
319system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
320system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
321system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
322system.cpu.iq.issued_per_cycle::total 392517505 # Number of insts issued each cycle
323system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
324system.cpu.iq.fu_full::IntAlu 478854 5.03% 5.03% # attempts to use FU when none available
325system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available
326system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available
327system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available
328system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available
329system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available
330system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available
331system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available
332system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available
333system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available
334system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available
335system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available
336system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available
337system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available
338system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available
339system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available
340system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available
341system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available
342system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available
343system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available
344system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available
345system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available
346system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available
347system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available
348system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available
349system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available
350system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available
351system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available
352system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available
353system.cpu.iq.fu_full::MemRead 6518035 68.44% 73.47% # attempts to use FU when none available
354system.cpu.iq.fu_full::MemWrite 2526744 26.53% 100.00% # attempts to use FU when none available
355system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
356system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
357system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
358system.cpu.iq.FU_type_0::IntAlu 447790300 67.30% 67.30% # Type of FU issued
359system.cpu.iq.FU_type_0::IntMult 383235 0.06% 67.36% # Type of FU issued
360system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued
361system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued
362system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
363system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
364system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
365system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued
366system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued
367system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued
368system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued
369system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued

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379system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued
380system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued
381system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued
382system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued
383system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued
384system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
385system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
386system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
387system.cpu.iq.FU_type_0::MemRead 153391187 23.06% 90.42% # Type of FU issued
388system.cpu.iq.FU_type_0::MemWrite 63758352 9.58% 100.00% # Type of FU issued
389system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
390system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
391system.cpu.iq.FU_type_0::total 665323167 # Type of FU issued
392system.cpu.iq.rate 1.663887 # Inst issue rate
393system.cpu.iq.fu_busy_cnt 9523633 # FU busy when requested
394system.cpu.iq.fu_busy_rate 0.014314 # FU busy rate (busy events/executed inst)
395system.cpu.iq.int_inst_queue_reads 1734060876 # Number of integer instruction queue reads
396system.cpu.iq.int_inst_queue_writes 947018314 # Number of integer instruction queue writes
397system.cpu.iq.int_inst_queue_wakeup_accesses 646045006 # Number of integer instruction queue wakeup accesses
398system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads
399system.cpu.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes
400system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
401system.cpu.iq.int_alu_accesses 674846691 # Number of integer alu accesses
402system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses
403system.cpu.iew.lsq.thread0.forwLoads 8570702 # Number of loads that had data forwarded from stores
404system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
405system.cpu.iew.lsq.thread0.squashedLoads 44217550 # Number of loads squashed
406system.cpu.iew.lsq.thread0.ignoredResponses 42225 # Number of memory responses ignored because the instruction is squashed
407system.cpu.iew.lsq.thread0.memOrderViolation 810789 # Number of memory ordering violations
408system.cpu.iew.lsq.thread0.squashedStores 16613394 # Number of stores squashed
409system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
410system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
411system.cpu.iew.lsq.thread0.rescheduledLoads 19530 # Number of loads that were rescheduled
412system.cpu.iew.lsq.thread0.cacheBlocked 4440 # Number of times an access to memory failed due to the cache being blocked
413system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
414system.cpu.iew.iewSquashCycles 27540546 # Number of cycles IEW is squashing
415system.cpu.iew.iewBlockCycles 5027645 # Number of cycles IEW is blocking
416system.cpu.iew.iewUnblockCycles 374127 # Number of cycles IEW is unblocking
417system.cpu.iew.iewDispatchedInsts 760395240 # Number of instructions dispatched to IQ
418system.cpu.iew.iewDispSquashedInsts 1110246 # Number of squashed instructions skipped by dispatch
419system.cpu.iew.iewDispLoadInsts 170247105 # Number of dispatched load instructions
420system.cpu.iew.iewDispStoreInsts 73473871 # Number of dispatched store instructions
421system.cpu.iew.iewDispNonSpecInsts 2286773 # Number of dispatched non-speculative instructions
422system.cpu.iew.iewIQFullEvents 218357 # Number of times the IQ has become full, causing a stall
423system.cpu.iew.iewLSQFullEvents 11618 # Number of times the LSQ has become full, causing a stall
424system.cpu.iew.memOrderViolationEvents 810789 # Number of memory order violations
425system.cpu.iew.predictedTakenIncorrect 4336068 # Number of branches that were predicted taken incorrectly
426system.cpu.iew.predictedNotTakenIncorrect 4004006 # Number of branches that were predicted not taken incorrectly
427system.cpu.iew.branchMispredicts 8340074 # Number of branch mispredicts detected at execute
428system.cpu.iew.iewExecutedInsts 655902697 # Number of executed instructions
429system.cpu.iew.iewExecLoadInsts 150107572 # Number of load instructions executed
430system.cpu.iew.iewExecSquashedInsts 9420470 # Number of squashed instructions skipped in execute
431system.cpu.iew.exec_swp 0 # number of swp insts executed
432system.cpu.iew.exec_nop 1559175 # number of nop insts executed
433system.cpu.iew.exec_refs 212574642 # number of memory reference insts executed
434system.cpu.iew.exec_branches 138502057 # Number of branches executed
435system.cpu.iew.exec_stores 62467070 # Number of stores executed
436system.cpu.iew.exec_rate 1.640327 # Inst execution rate
437system.cpu.iew.wb_sent 651021062 # cumulative count of insts sent to commit
438system.cpu.iew.wb_count 646045022 # cumulative count of insts written-back
439system.cpu.iew.wb_producers 374765758 # num instructions producing a value
440system.cpu.iew.wb_consumers 646459860 # num instructions consuming a value
441system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
442system.cpu.iew.wb_rate 1.615674 # insts written-back per cycle
443system.cpu.iew.wb_fanout 0.579720 # average fanout of values written-back
444system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
445system.cpu.commit.commitSquashedInsts 189453742 # The number of squashed insts skipped by commit
446system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
447system.cpu.commit.branchMispredicts 7191165 # The number of times a branch was mispredicted
448system.cpu.commit.committed_per_cycle::samples 364976959 # Number of insts commited each cycle
449system.cpu.commit.committed_per_cycle::mean 1.564395 # Number of insts commited each cycle
450system.cpu.commit.committed_per_cycle::stdev 2.233817 # Number of insts commited each cycle
451system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
452system.cpu.commit.committed_per_cycle::0 157310366 43.10% 43.10% # Number of insts commited each cycle
453system.cpu.commit.committed_per_cycle::1 98490082 26.99% 70.09% # Number of insts commited each cycle
454system.cpu.commit.committed_per_cycle::2 33805907 9.26% 79.35% # Number of insts commited each cycle
455system.cpu.commit.committed_per_cycle::3 18787402 5.15% 84.50% # Number of insts commited each cycle
456system.cpu.commit.committed_per_cycle::4 16180614 4.43% 88.93% # Number of insts commited each cycle
457system.cpu.commit.committed_per_cycle::5 7431287 2.04% 90.97% # Number of insts commited each cycle
458system.cpu.commit.committed_per_cycle::6 6987633 1.91% 92.88% # Number of insts commited each cycle
459system.cpu.commit.committed_per_cycle::7 3169968 0.87% 93.75% # Number of insts commited each cycle
460system.cpu.commit.committed_per_cycle::8 22813700 6.25% 100.00% # Number of insts commited each cycle
461system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
462system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
463system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
464system.cpu.commit.committed_per_cycle::total 364976959 # Number of insts commited each cycle
465system.cpu.commit.committedInsts 506581607 # Number of instructions committed
466system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
467system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
468system.cpu.commit.refs 182890032 # Number of memory references committed
469system.cpu.commit.loads 126029555 # Number of loads committed
470system.cpu.commit.membars 1488542 # Number of memory barriers committed
471system.cpu.commit.branches 121548301 # Number of branches committed
472system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
473system.cpu.commit.int_insts 470727693 # Number of committed integer instructions.
474system.cpu.commit.function_calls 9757362 # Number of function calls committed.
475system.cpu.commit.bw_lim_events 22813700 # number cycles where commit BW limit reached
476system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
477system.cpu.rob.rob_reads 1102578030 # The number of ROB reads
478system.cpu.rob.rob_writes 1548505178 # The number of ROB writes
479system.cpu.timesIdled 308567 # Number of times that the entire CPU went into an idle state and unscheduled itself
480system.cpu.idleCycles 7343381 # Total number of cycles that the CPU has spent unscheduled due to idling
481system.cpu.committedInsts 505237723 # Number of Instructions Simulated
482system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
483system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated
484system.cpu.cpi 0.791431 # CPI: Cycles Per Instruction
485system.cpu.cpi_total 0.791431 # CPI: Total CPI of All Threads
486system.cpu.ipc 1.263534 # IPC: Instructions Per Cycle
487system.cpu.ipc_total 1.263534 # IPC: Total IPC of All Threads
488system.cpu.int_regfile_reads 3058706465 # number of integer regfile reads
489system.cpu.int_regfile_writes 752037507 # number of integer regfile writes
490system.cpu.fp_regfile_reads 16 # number of floating regfile reads
491system.cpu.misc_regfile_reads 210820275 # number of misc regfile reads
492system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
493system.cpu.icache.replacements 15019 # number of replacements
494system.cpu.icache.tagsinuse 1100.569602 # Cycle average of tags in use
495system.cpu.icache.total_refs 114493231 # Total number of references to valid blocks.
496system.cpu.icache.sampled_refs 16877 # Sample count of references to valid blocks.
497system.cpu.icache.avg_refs 6783.980032 # Average number of references to valid blocks.
498system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
499system.cpu.icache.occ_blocks::cpu.inst 1100.569602 # Average occupied blocks per requestor
500system.cpu.icache.occ_percent::cpu.inst 0.537388 # Average percentage of cache occupancy
501system.cpu.icache.occ_percent::total 0.537388 # Average percentage of cache occupancy
502system.cpu.icache.ReadReq_hits::cpu.inst 114493231 # number of ReadReq hits
503system.cpu.icache.ReadReq_hits::total 114493231 # number of ReadReq hits
504system.cpu.icache.demand_hits::cpu.inst 114493231 # number of demand (read+write) hits
505system.cpu.icache.demand_hits::total 114493231 # number of demand (read+write) hits
506system.cpu.icache.overall_hits::cpu.inst 114493231 # number of overall hits
507system.cpu.icache.overall_hits::total 114493231 # number of overall hits
508system.cpu.icache.ReadReq_misses::cpu.inst 21111 # number of ReadReq misses
509system.cpu.icache.ReadReq_misses::total 21111 # number of ReadReq misses
510system.cpu.icache.demand_misses::cpu.inst 21111 # number of demand (read+write) misses
511system.cpu.icache.demand_misses::total 21111 # number of demand (read+write) misses
512system.cpu.icache.overall_misses::cpu.inst 21111 # number of overall misses
513system.cpu.icache.overall_misses::total 21111 # number of overall misses
514system.cpu.icache.ReadReq_miss_latency::cpu.inst 514757500 # number of ReadReq miss cycles
515system.cpu.icache.ReadReq_miss_latency::total 514757500 # number of ReadReq miss cycles
516system.cpu.icache.demand_miss_latency::cpu.inst 514757500 # number of demand (read+write) miss cycles
517system.cpu.icache.demand_miss_latency::total 514757500 # number of demand (read+write) miss cycles
518system.cpu.icache.overall_miss_latency::cpu.inst 514757500 # number of overall miss cycles
519system.cpu.icache.overall_miss_latency::total 514757500 # number of overall miss cycles
520system.cpu.icache.ReadReq_accesses::cpu.inst 114514342 # number of ReadReq accesses(hits+misses)
521system.cpu.icache.ReadReq_accesses::total 114514342 # number of ReadReq accesses(hits+misses)
522system.cpu.icache.demand_accesses::cpu.inst 114514342 # number of demand (read+write) accesses
523system.cpu.icache.demand_accesses::total 114514342 # number of demand (read+write) accesses
524system.cpu.icache.overall_accesses::cpu.inst 114514342 # number of overall (read+write) accesses
525system.cpu.icache.overall_accesses::total 114514342 # number of overall (read+write) accesses
526system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses
527system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses
528system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses
529system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses
530system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses
531system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses
532system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24383.378334 # average ReadReq miss latency
533system.cpu.icache.ReadReq_avg_miss_latency::total 24383.378334 # average ReadReq miss latency
534system.cpu.icache.demand_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency
535system.cpu.icache.demand_avg_miss_latency::total 24383.378334 # average overall miss latency
536system.cpu.icache.overall_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency
537system.cpu.icache.overall_avg_miss_latency::total 24383.378334 # average overall miss latency
538system.cpu.icache.blocked_cycles::no_mshrs 1152 # number of cycles access was blocked
539system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
540system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
541system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
542system.cpu.icache.avg_blocked_cycles::no_mshrs 88.615385 # average number of cycles each access was blocked
543system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
544system.cpu.icache.fast_writes 0 # number of fast writes performed
545system.cpu.icache.cache_copies 0 # number of cache copies performed
546system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4153 # number of ReadReq MSHR hits
547system.cpu.icache.ReadReq_mshr_hits::total 4153 # number of ReadReq MSHR hits
548system.cpu.icache.demand_mshr_hits::cpu.inst 4153 # number of demand (read+write) MSHR hits
549system.cpu.icache.demand_mshr_hits::total 4153 # number of demand (read+write) MSHR hits
550system.cpu.icache.overall_mshr_hits::cpu.inst 4153 # number of overall MSHR hits
551system.cpu.icache.overall_mshr_hits::total 4153 # number of overall MSHR hits
552system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16958 # number of ReadReq MSHR misses
553system.cpu.icache.ReadReq_mshr_misses::total 16958 # number of ReadReq MSHR misses
554system.cpu.icache.demand_mshr_misses::cpu.inst 16958 # number of demand (read+write) MSHR misses
555system.cpu.icache.demand_mshr_misses::total 16958 # number of demand (read+write) MSHR misses
556system.cpu.icache.overall_mshr_misses::cpu.inst 16958 # number of overall MSHR misses
557system.cpu.icache.overall_mshr_misses::total 16958 # number of overall MSHR misses
558system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375680500 # number of ReadReq MSHR miss cycles
559system.cpu.icache.ReadReq_mshr_miss_latency::total 375680500 # number of ReadReq MSHR miss cycles
560system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375680500 # number of demand (read+write) MSHR miss cycles
561system.cpu.icache.demand_mshr_miss_latency::total 375680500 # number of demand (read+write) MSHR miss cycles
562system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375680500 # number of overall MSHR miss cycles
563system.cpu.icache.overall_mshr_miss_latency::total 375680500 # number of overall MSHR miss cycles
564system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses
565system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses
566system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses
567system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses
568system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses
569system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses
570system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22153.585328 # average ReadReq mshr miss latency
571system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22153.585328 # average ReadReq mshr miss latency
572system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22153.585328 # average overall mshr miss latency
573system.cpu.icache.demand_avg_mshr_miss_latency::total 22153.585328 # average overall mshr miss latency
574system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22153.585328 # average overall mshr miss latency
575system.cpu.icache.overall_avg_mshr_miss_latency::total 22153.585328 # average overall mshr miss latency
576system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
577system.cpu.l2cache.replacements 115398 # number of replacements
578system.cpu.l2cache.tagsinuse 27101.777399 # Cycle average of tags in use
579system.cpu.l2cache.total_refs 1781753 # Total number of references to valid blocks.
580system.cpu.l2cache.sampled_refs 146655 # Sample count of references to valid blocks.
581system.cpu.l2cache.avg_refs 12.149282 # Average number of references to valid blocks.
582system.cpu.l2cache.warmup_cycle 100667210000 # Cycle when the warmup percentage was hit.
583system.cpu.l2cache.occ_blocks::writebacks 23032.613766 # Average occupied blocks per requestor
584system.cpu.l2cache.occ_blocks::cpu.inst 362.003835 # Average occupied blocks per requestor
585system.cpu.l2cache.occ_blocks::cpu.data 3707.159797 # Average occupied blocks per requestor
586system.cpu.l2cache.occ_percent::writebacks 0.702900 # Average percentage of cache occupancy
587system.cpu.l2cache.occ_percent::cpu.inst 0.011047 # Average percentage of cache occupancy
588system.cpu.l2cache.occ_percent::cpu.data 0.113134 # Average percentage of cache occupancy
589system.cpu.l2cache.occ_percent::total 0.827081 # Average percentage of cache occupancy
590system.cpu.l2cache.ReadReq_hits::cpu.inst 13488 # number of ReadReq hits
591system.cpu.l2cache.ReadReq_hits::cpu.data 804399 # number of ReadReq hits
592system.cpu.l2cache.ReadReq_hits::total 817887 # number of ReadReq hits
593system.cpu.l2cache.Writeback_hits::writebacks 1110977 # number of Writeback hits
594system.cpu.l2cache.Writeback_hits::total 1110977 # number of Writeback hits
595system.cpu.l2cache.UpgradeReq_hits::cpu.data 73 # number of UpgradeReq hits
596system.cpu.l2cache.UpgradeReq_hits::total 73 # number of UpgradeReq hits
597system.cpu.l2cache.ReadExReq_hits::cpu.data 247537 # number of ReadExReq hits
598system.cpu.l2cache.ReadExReq_hits::total 247537 # number of ReadExReq hits
599system.cpu.l2cache.demand_hits::cpu.inst 13488 # number of demand (read+write) hits
600system.cpu.l2cache.demand_hits::cpu.data 1051936 # number of demand (read+write) hits
601system.cpu.l2cache.demand_hits::total 1065424 # number of demand (read+write) hits
602system.cpu.l2cache.overall_hits::cpu.inst 13488 # number of overall hits
603system.cpu.l2cache.overall_hits::cpu.data 1051936 # number of overall hits
604system.cpu.l2cache.overall_hits::total 1065424 # number of overall hits
605system.cpu.l2cache.ReadReq_misses::cpu.inst 3382 # number of ReadReq misses
606system.cpu.l2cache.ReadReq_misses::cpu.data 43478 # number of ReadReq misses
607system.cpu.l2cache.ReadReq_misses::total 46860 # number of ReadReq misses
608system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
609system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
610system.cpu.l2cache.ReadExReq_misses::cpu.data 101314 # number of ReadExReq misses
611system.cpu.l2cache.ReadExReq_misses::total 101314 # number of ReadExReq misses
612system.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses
613system.cpu.l2cache.demand_misses::cpu.data 144792 # number of demand (read+write) misses
614system.cpu.l2cache.demand_misses::total 148174 # number of demand (read+write) misses
615system.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses
616system.cpu.l2cache.overall_misses::cpu.data 144792 # number of overall misses
617system.cpu.l2cache.overall_misses::total 148174 # number of overall misses
618system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223286000 # number of ReadReq miss cycles
619system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2917634500 # number of ReadReq miss cycles
620system.cpu.l2cache.ReadReq_miss_latency::total 3140920500 # number of ReadReq miss cycles
621system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5217385000 # number of ReadExReq miss cycles
622system.cpu.l2cache.ReadExReq_miss_latency::total 5217385000 # number of ReadExReq miss cycles
623system.cpu.l2cache.demand_miss_latency::cpu.inst 223286000 # number of demand (read+write) miss cycles
624system.cpu.l2cache.demand_miss_latency::cpu.data 8135019500 # number of demand (read+write) miss cycles
625system.cpu.l2cache.demand_miss_latency::total 8358305500 # number of demand (read+write) miss cycles
626system.cpu.l2cache.overall_miss_latency::cpu.inst 223286000 # number of overall miss cycles
627system.cpu.l2cache.overall_miss_latency::cpu.data 8135019500 # number of overall miss cycles
628system.cpu.l2cache.overall_miss_latency::total 8358305500 # number of overall miss cycles
629system.cpu.l2cache.ReadReq_accesses::cpu.inst 16870 # number of ReadReq accesses(hits+misses)
630system.cpu.l2cache.ReadReq_accesses::cpu.data 847877 # number of ReadReq accesses(hits+misses)
631system.cpu.l2cache.ReadReq_accesses::total 864747 # number of ReadReq accesses(hits+misses)
632system.cpu.l2cache.Writeback_accesses::writebacks 1110977 # number of Writeback accesses(hits+misses)
633system.cpu.l2cache.Writeback_accesses::total 1110977 # number of Writeback accesses(hits+misses)
634system.cpu.l2cache.UpgradeReq_accesses::cpu.data 82 # number of UpgradeReq accesses(hits+misses)
635system.cpu.l2cache.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses)
636system.cpu.l2cache.ReadExReq_accesses::cpu.data 348851 # number of ReadExReq accesses(hits+misses)
637system.cpu.l2cache.ReadExReq_accesses::total 348851 # number of ReadExReq accesses(hits+misses)
638system.cpu.l2cache.demand_accesses::cpu.inst 16870 # number of demand (read+write) accesses
639system.cpu.l2cache.demand_accesses::cpu.data 1196728 # number of demand (read+write) accesses
640system.cpu.l2cache.demand_accesses::total 1213598 # number of demand (read+write) accesses
641system.cpu.l2cache.overall_accesses::cpu.inst 16870 # number of overall (read+write) accesses
642system.cpu.l2cache.overall_accesses::cpu.data 1196728 # number of overall (read+write) accesses
643system.cpu.l2cache.overall_accesses::total 1213598 # number of overall (read+write) accesses
644system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200474 # miss rate for ReadReq accesses
645system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051279 # miss rate for ReadReq accesses
646system.cpu.l2cache.ReadReq_miss_rate::total 0.054189 # miss rate for ReadReq accesses
647system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.109756 # miss rate for UpgradeReq accesses
648system.cpu.l2cache.UpgradeReq_miss_rate::total 0.109756 # miss rate for UpgradeReq accesses
649system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290422 # miss rate for ReadExReq accesses
650system.cpu.l2cache.ReadExReq_miss_rate::total 0.290422 # miss rate for ReadExReq accesses
651system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200474 # miss rate for demand accesses
652system.cpu.l2cache.demand_miss_rate::cpu.data 0.120990 # miss rate for demand accesses
653system.cpu.l2cache.demand_miss_rate::total 0.122095 # miss rate for demand accesses
654system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200474 # miss rate for overall accesses
655system.cpu.l2cache.overall_miss_rate::cpu.data 0.120990 # miss rate for overall accesses
656system.cpu.l2cache.overall_miss_rate::total 0.122095 # miss rate for overall accesses
657system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66021.880544 # average ReadReq miss latency
658system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67105.996136 # average ReadReq miss latency
659system.cpu.l2cache.ReadReq_avg_miss_latency::total 67027.752881 # average ReadReq miss latency
660system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51497.177093 # average ReadExReq miss latency
661system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51497.177093 # average ReadExReq miss latency
662system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66021.880544 # average overall miss latency
663system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56184.177993 # average overall miss latency
664system.cpu.l2cache.demand_avg_miss_latency::total 56408.718804 # average overall miss latency
665system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66021.880544 # average overall miss latency
666system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56184.177993 # average overall miss latency
667system.cpu.l2cache.overall_avg_miss_latency::total 56408.718804 # average overall miss latency
668system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
669system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
670system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
671system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
672system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
673system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
674system.cpu.l2cache.fast_writes 0 # number of fast writes performed
675system.cpu.l2cache.cache_copies 0 # number of cache copies performed
676system.cpu.l2cache.writebacks::writebacks 97618 # number of writebacks
677system.cpu.l2cache.writebacks::total 97618 # number of writebacks
678system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
679system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
680system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
681system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
682system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
683system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
684system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
685system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
686system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
687system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3378 # number of ReadReq MSHR misses
688system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43455 # number of ReadReq MSHR misses
689system.cpu.l2cache.ReadReq_mshr_misses::total 46833 # number of ReadReq MSHR misses
690system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses
691system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
692system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101314 # number of ReadExReq MSHR misses
693system.cpu.l2cache.ReadExReq_mshr_misses::total 101314 # number of ReadExReq MSHR misses
694system.cpu.l2cache.demand_mshr_misses::cpu.inst 3378 # number of demand (read+write) MSHR misses
695system.cpu.l2cache.demand_mshr_misses::cpu.data 144769 # number of demand (read+write) MSHR misses
696system.cpu.l2cache.demand_mshr_misses::total 148147 # number of demand (read+write) MSHR misses
697system.cpu.l2cache.overall_mshr_misses::cpu.inst 3378 # number of overall MSHR misses
698system.cpu.l2cache.overall_mshr_misses::cpu.data 144769 # number of overall MSHR misses
699system.cpu.l2cache.overall_mshr_misses::total 148147 # number of overall MSHR misses
700system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180723170 # number of ReadReq MSHR miss cycles
701system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2376770410 # number of ReadReq MSHR miss cycles
702system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2557493580 # number of ReadReq MSHR miss cycles
703system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles
704system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles
705system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3952267092 # number of ReadExReq MSHR miss cycles
706system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3952267092 # number of ReadExReq MSHR miss cycles
707system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180723170 # number of demand (read+write) MSHR miss cycles
708system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6329037502 # number of demand (read+write) MSHR miss cycles
709system.cpu.l2cache.demand_mshr_miss_latency::total 6509760672 # number of demand (read+write) MSHR miss cycles
710system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180723170 # number of overall MSHR miss cycles
711system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6329037502 # number of overall MSHR miss cycles
712system.cpu.l2cache.overall_mshr_miss_latency::total 6509760672 # number of overall MSHR miss cycles
713system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for ReadReq accesses
714system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051252 # mshr miss rate for ReadReq accesses
715system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054158 # mshr miss rate for ReadReq accesses
716system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.109756 # mshr miss rate for UpgradeReq accesses
717system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.109756 # mshr miss rate for UpgradeReq accesses
718system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290422 # mshr miss rate for ReadExReq accesses
719system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290422 # mshr miss rate for ReadExReq accesses
720system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for demand accesses
721system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for demand accesses
722system.cpu.l2cache.demand_mshr_miss_rate::total 0.122073 # mshr miss rate for demand accesses
723system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for overall accesses
724system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for overall accesses
725system.cpu.l2cache.overall_mshr_miss_rate::total 0.122073 # mshr miss rate for overall accesses
726system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53500.050326 # average ReadReq mshr miss latency
727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54694.981245 # average ReadReq mshr miss latency
728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.792518 # average ReadReq mshr miss latency
729system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
730system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
731system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39010.078489 # average ReadExReq mshr miss latency
732system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39010.078489 # average ReadExReq mshr miss latency
733system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency
734system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency
735system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency
736system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency
737system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency
738system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency
739system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
740system.cpu.dcache.replacements 1192631 # number of replacements
741system.cpu.dcache.tagsinuse 4058.209057 # Cycle average of tags in use
742system.cpu.dcache.total_refs 190187917 # Total number of references to valid blocks.
743system.cpu.dcache.sampled_refs 1196727 # Sample count of references to valid blocks.
744system.cpu.dcache.avg_refs 158.923394 # Average number of references to valid blocks.
745system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit.
746system.cpu.dcache.occ_blocks::cpu.data 4058.209057 # Average occupied blocks per requestor
747system.cpu.dcache.occ_percent::cpu.data 0.990774 # Average percentage of cache occupancy
748system.cpu.dcache.occ_percent::total 0.990774 # Average percentage of cache occupancy
749system.cpu.dcache.ReadReq_hits::cpu.data 136218647 # number of ReadReq hits
750system.cpu.dcache.ReadReq_hits::total 136218647 # number of ReadReq hits
751system.cpu.dcache.WriteReq_hits::cpu.data 50991635 # number of WriteReq hits
752system.cpu.dcache.WriteReq_hits::total 50991635 # number of WriteReq hits
753system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488827 # number of LoadLockedReq hits
754system.cpu.dcache.LoadLockedReq_hits::total 1488827 # number of LoadLockedReq hits
755system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
756system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
757system.cpu.dcache.demand_hits::cpu.data 187210282 # number of demand (read+write) hits
758system.cpu.dcache.demand_hits::total 187210282 # number of demand (read+write) hits
759system.cpu.dcache.overall_hits::cpu.data 187210282 # number of overall hits
760system.cpu.dcache.overall_hits::total 187210282 # number of overall hits
761system.cpu.dcache.ReadReq_misses::cpu.data 1699163 # number of ReadReq misses
762system.cpu.dcache.ReadReq_misses::total 1699163 # number of ReadReq misses
763system.cpu.dcache.WriteReq_misses::cpu.data 3247671 # number of WriteReq misses
764system.cpu.dcache.WriteReq_misses::total 3247671 # number of WriteReq misses
765system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses
766system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses
767system.cpu.dcache.demand_misses::cpu.data 4946834 # number of demand (read+write) misses
768system.cpu.dcache.demand_misses::total 4946834 # number of demand (read+write) misses
769system.cpu.dcache.overall_misses::cpu.data 4946834 # number of overall misses
770system.cpu.dcache.overall_misses::total 4946834 # number of overall misses
771system.cpu.dcache.ReadReq_miss_latency::cpu.data 26685574500 # number of ReadReq miss cycles
772system.cpu.dcache.ReadReq_miss_latency::total 26685574500 # number of ReadReq miss cycles
773system.cpu.dcache.WriteReq_miss_latency::cpu.data 57046648448 # number of WriteReq miss cycles
774system.cpu.dcache.WriteReq_miss_latency::total 57046648448 # number of WriteReq miss cycles
775system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 615500 # number of LoadLockedReq miss cycles
776system.cpu.dcache.LoadLockedReq_miss_latency::total 615500 # number of LoadLockedReq miss cycles
777system.cpu.dcache.demand_miss_latency::cpu.data 83732222948 # number of demand (read+write) miss cycles
778system.cpu.dcache.demand_miss_latency::total 83732222948 # number of demand (read+write) miss cycles
779system.cpu.dcache.overall_miss_latency::cpu.data 83732222948 # number of overall miss cycles
780system.cpu.dcache.overall_miss_latency::total 83732222948 # number of overall miss cycles
781system.cpu.dcache.ReadReq_accesses::cpu.data 137917810 # number of ReadReq accesses(hits+misses)
782system.cpu.dcache.ReadReq_accesses::total 137917810 # number of ReadReq accesses(hits+misses)
783system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
784system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
785system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488868 # number of LoadLockedReq accesses(hits+misses)
786system.cpu.dcache.LoadLockedReq_accesses::total 1488868 # number of LoadLockedReq accesses(hits+misses)
787system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
788system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
789system.cpu.dcache.demand_accesses::cpu.data 192157116 # number of demand (read+write) accesses
790system.cpu.dcache.demand_accesses::total 192157116 # number of demand (read+write) accesses
791system.cpu.dcache.overall_accesses::cpu.data 192157116 # number of overall (read+write) accesses
792system.cpu.dcache.overall_accesses::total 192157116 # number of overall (read+write) accesses
793system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012320 # miss rate for ReadReq accesses
794system.cpu.dcache.ReadReq_miss_rate::total 0.012320 # miss rate for ReadReq accesses
795system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses
796system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses
797system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses
798system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses
799system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses
800system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses
801system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses
802system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses
803system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15705.129231 # average ReadReq miss latency
804system.cpu.dcache.ReadReq_avg_miss_latency::total 15705.129231 # average ReadReq miss latency
805system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17565.402545 # average WriteReq miss latency
806system.cpu.dcache.WriteReq_avg_miss_latency::total 17565.402545 # average WriteReq miss latency
807system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15012.195122 # average LoadLockedReq miss latency
808system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15012.195122 # average LoadLockedReq miss latency
809system.cpu.dcache.demand_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency
810system.cpu.dcache.demand_avg_miss_latency::total 16926.426670 # average overall miss latency
811system.cpu.dcache.overall_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency
812system.cpu.dcache.overall_avg_miss_latency::total 16926.426670 # average overall miss latency
813system.cpu.dcache.blocked_cycles::no_mshrs 18054 # number of cycles access was blocked
814system.cpu.dcache.blocked_cycles::no_targets 15751 # number of cycles access was blocked
815system.cpu.dcache.blocked::no_mshrs 1658 # number of cycles access was blocked
816system.cpu.dcache.blocked::no_targets 601 # number of cycles access was blocked
817system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.889023 # average number of cycles each access was blocked
818system.cpu.dcache.avg_blocked_cycles::no_targets 26.207987 # average number of cycles each access was blocked
819system.cpu.dcache.fast_writes 0 # number of fast writes performed
820system.cpu.dcache.cache_copies 0 # number of cache copies performed
821system.cpu.dcache.writebacks::writebacks 1110977 # number of writebacks
822system.cpu.dcache.writebacks::total 1110977 # number of writebacks
823system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850754 # number of ReadReq MSHR hits
824system.cpu.dcache.ReadReq_mshr_hits::total 850754 # number of ReadReq MSHR hits
825system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899270 # number of WriteReq MSHR hits
826system.cpu.dcache.WriteReq_mshr_hits::total 2899270 # number of WriteReq MSHR hits
827system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits
828system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits
829system.cpu.dcache.demand_mshr_hits::cpu.data 3750024 # number of demand (read+write) MSHR hits
830system.cpu.dcache.demand_mshr_hits::total 3750024 # number of demand (read+write) MSHR hits
831system.cpu.dcache.overall_mshr_hits::cpu.data 3750024 # number of overall MSHR hits
832system.cpu.dcache.overall_mshr_hits::total 3750024 # number of overall MSHR hits
833system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848409 # number of ReadReq MSHR misses
834system.cpu.dcache.ReadReq_mshr_misses::total 848409 # number of ReadReq MSHR misses
835system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348401 # number of WriteReq MSHR misses
836system.cpu.dcache.WriteReq_mshr_misses::total 348401 # number of WriteReq MSHR misses
837system.cpu.dcache.demand_mshr_misses::cpu.data 1196810 # number of demand (read+write) MSHR misses
838system.cpu.dcache.demand_mshr_misses::total 1196810 # number of demand (read+write) MSHR misses
839system.cpu.dcache.overall_mshr_misses::cpu.data 1196810 # number of overall MSHR misses
840system.cpu.dcache.overall_mshr_misses::total 1196810 # number of overall MSHR misses
841system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11849237000 # number of ReadReq MSHR miss cycles
842system.cpu.dcache.ReadReq_mshr_miss_latency::total 11849237000 # number of ReadReq MSHR miss cycles
843system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8091181496 # number of WriteReq MSHR miss cycles
844system.cpu.dcache.WriteReq_mshr_miss_latency::total 8091181496 # number of WriteReq MSHR miss cycles
845system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19940418496 # number of demand (read+write) MSHR miss cycles
846system.cpu.dcache.demand_mshr_miss_latency::total 19940418496 # number of demand (read+write) MSHR miss cycles
847system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19940418496 # number of overall MSHR miss cycles
848system.cpu.dcache.overall_mshr_miss_latency::total 19940418496 # number of overall MSHR miss cycles
849system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses
850system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses
851system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
852system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
853system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses
854system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses
855system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses
856system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses
857system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13966.420677 # average ReadReq mshr miss latency
858system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13966.420677 # average ReadReq mshr miss latency
859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23223.760827 # average WriteReq mshr miss latency
860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23223.760827 # average WriteReq mshr miss latency
861system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency
862system.cpu.dcache.demand_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency
863system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency
864system.cpu.dcache.overall_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency
865system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
866
867---------- End Simulation Statistics ----------