1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.235850 # Number of seconds simulated
4sim_ticks 235850129000 # Number of ticks simulated
5final_tick 235850129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 254127 # Simulator instruction rate (inst/s)
8host_op_rate 275309 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 118629630 # Simulator tick rate (ticks/s)
10host_mem_usage 302132 # Number of bytes of host memory used
11host_seconds 1988.12 # Real time elapsed on the host
12sim_insts 505234934 # Number of instructions simulated
13sim_ops 547348155 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 651264 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 10497792 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 # Number of bytes read from this memory
20system.physmem.bytes_read::total 27559104 # Number of bytes read from this memory
21system.physmem.bytes_inst_read::cpu.inst 651264 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 651264 # Number of instructions bytes read from this memory
23system.physmem.bytes_written::writebacks 18653440 # Number of bytes written to this memory
24system.physmem.bytes_written::total 18653440 # Number of bytes written to this memory
25system.physmem.num_reads::cpu.inst 10176 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 164028 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.l2cache.prefetcher 256407 # Number of read requests responded to by this memory
28system.physmem.num_reads::total 430611 # Number of read requests responded to by this memory
29system.physmem.num_writes::writebacks 291460 # Number of write requests responded to by this memory
30system.physmem.num_writes::total 291460 # Number of write requests responded to by this memory
31system.physmem.bw_read::cpu.inst 2761347 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.data 44510436 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::total 116850070 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::cpu.inst 2761347 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::total 2761347 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_write::writebacks 79090226 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_write::total 79090226 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_total::writebacks 79090226 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.inst 2761347 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.data 44510436 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::total 195940296 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.readReqs 430611 # Number of read requests accepted
45system.physmem.writeReqs 291460 # Number of write requests accepted
46system.physmem.readBursts 430611 # Number of DRAM read bursts, including those serviced by the write queue
47system.physmem.writeBursts 291460 # Number of DRAM write bursts, including those merged in the write queue
48system.physmem.bytesReadDRAM 27396288 # Total number of bytes read from DRAM
49system.physmem.bytesReadWrQ 162816 # Total number of bytes read from write queue
50system.physmem.bytesWritten 18651392 # Total number of bytes written to DRAM
51system.physmem.bytesReadSys 27559104 # Total read bytes from the system interface side
52system.physmem.bytesWrittenSys 18653440 # Total written bytes from the system interface side
53system.physmem.servicedByWrQ 2544 # Number of DRAM read bursts serviced by the write queue
54system.physmem.mergedWrBursts 9 # Number of DRAM write bursts merged with an existing one
55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
56system.physmem.perBankRdBursts::0 27102 # Per bank write bursts
57system.physmem.perBankRdBursts::1 26174 # Per bank write bursts
58system.physmem.perBankRdBursts::2 25664 # Per bank write bursts
59system.physmem.perBankRdBursts::3 33006 # Per bank write bursts
60system.physmem.perBankRdBursts::4 27996 # Per bank write bursts
61system.physmem.perBankRdBursts::5 29984 # Per bank write bursts
62system.physmem.perBankRdBursts::6 25487 # Per bank write bursts
63system.physmem.perBankRdBursts::7 24586 # Per bank write bursts
64system.physmem.perBankRdBursts::8 25526 # Per bank write bursts
65system.physmem.perBankRdBursts::9 25681 # Per bank write bursts
66system.physmem.perBankRdBursts::10 25862 # Per bank write bursts
67system.physmem.perBankRdBursts::11 26092 # Per bank write bursts
68system.physmem.perBankRdBursts::12 27614 # Per bank write bursts
69system.physmem.perBankRdBursts::13 26106 # Per bank write bursts
70system.physmem.perBankRdBursts::14 25123 # Per bank write bursts
71system.physmem.perBankRdBursts::15 26064 # Per bank write bursts
72system.physmem.perBankWrBursts::0 18530 # Per bank write bursts
73system.physmem.perBankWrBursts::1 18172 # Per bank write bursts
74system.physmem.perBankWrBursts::2 17960 # Per bank write bursts
75system.physmem.perBankWrBursts::3 17946 # Per bank write bursts
76system.physmem.perBankWrBursts::4 18535 # Per bank write bursts
77system.physmem.perBankWrBursts::5 18092 # Per bank write bursts
78system.physmem.perBankWrBursts::6 17937 # Per bank write bursts
79system.physmem.perBankWrBursts::7 17864 # Per bank write bursts
80system.physmem.perBankWrBursts::8 17881 # Per bank write bursts
81system.physmem.perBankWrBursts::9 17814 # Per bank write bursts
82system.physmem.perBankWrBursts::10 18253 # Per bank write bursts
83system.physmem.perBankWrBursts::11 18685 # Per bank write bursts
84system.physmem.perBankWrBursts::12 18794 # Per bank write bursts
85system.physmem.perBankWrBursts::13 18180 # Per bank write bursts
86system.physmem.perBankWrBursts::14 18427 # Per bank write bursts
87system.physmem.perBankWrBursts::15 18358 # Per bank write bursts
88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
90system.physmem.totGap 235850076500 # Total gap between requests
91system.physmem.readPktSize::0 0 # Read request sizes (log2)
92system.physmem.readPktSize::1 0 # Read request sizes (log2)
93system.physmem.readPktSize::2 0 # Read request sizes (log2)
94system.physmem.readPktSize::3 0 # Read request sizes (log2)
95system.physmem.readPktSize::4 0 # Read request sizes (log2)
96system.physmem.readPktSize::5 0 # Read request sizes (log2)
97system.physmem.readPktSize::6 430611 # Read request sizes (log2)
98system.physmem.writePktSize::0 0 # Write request sizes (log2)
99system.physmem.writePktSize::1 0 # Write request sizes (log2)
100system.physmem.writePktSize::2 0 # Write request sizes (log2)
101system.physmem.writePktSize::3 0 # Write request sizes (log2)
102system.physmem.writePktSize::4 0 # Write request sizes (log2)
103system.physmem.writePktSize::5 0 # Write request sizes (log2)
104system.physmem.writePktSize::6 291460 # Write request sizes (log2)
105system.physmem.rdQLenPdf::0 318665 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::1 60579 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::2 13349 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::4 7328 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::6 5231 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::7 4311 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::8 3288 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::10 37 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see

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144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::15 6820 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::16 7302 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::17 12035 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::18 14838 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::19 16182 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::20 16933 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::21 17312 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::22 17637 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::23 17893 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::24 18126 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::25 18306 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::26 18426 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::27 18598 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::28 18683 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::29 18906 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::30 18563 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::31 17444 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::32 17201 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::33 121 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
201system.physmem.bytesPerActivate::samples 329170 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::mean 139.885214 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::gmean 98.537517 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::stdev 178.782393 # Bytes accessed per row activation
205system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::total 329170 # Bytes accessed per row activation
215system.physmem.rdPerTurnAround::samples 17054 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::mean 25.096224 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::stdev 145.074041 # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::total 17054 # Reads before turning the bus around for writes
222system.physmem.wrPerTurnAround::samples 17054 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::mean 17.088542 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::gmean 17.022727 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::stdev 1.689258 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::32-33 2 0.01% 99.95% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::34-35 1 0.01% 99.95% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::36-37 1 0.01% 99.96% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::42-43 3 0.02% 99.98% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::46-47 1 0.01% 99.98% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::62-63 1 0.01% 99.99% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::74-75 2 0.01% 100.00% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::total 17054 # Writes before turning the bus around for reads
242system.physmem.totQLat 14249250266 # Total ticks spent queuing
243system.physmem.totMemAccLat 22275506516 # Total ticks spent from burst creation until serviced by the DRAM
244system.physmem.totBusLat 2140335000 # Total ticks spent in databus transfers
245system.physmem.avgQLat 33287.43 # Average queueing delay per DRAM burst
246system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
247system.physmem.avgMemAccLat 52037.43 # Average memory access latency per DRAM burst
248system.physmem.avgRdBW 116.16 # Average DRAM read bandwidth in MiByte/s
249system.physmem.avgWrBW 79.08 # Average achieved write bandwidth in MiByte/s
250system.physmem.avgRdBWSys 116.85 # Average system read bandwidth in MiByte/s
251system.physmem.avgWrBWSys 79.09 # Average system write bandwidth in MiByte/s
252system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
253system.physmem.busUtil 1.53 # Data bus utilization in percentage
254system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads
255system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes
256system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing
257system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing
258system.physmem.readRowHits 308139 # Number of row buffer hits during reads
259system.physmem.writeRowHits 82177 # Number of row buffer hits during writes
260system.physmem.readRowHitRate 71.98 # Row buffer hit rate for reads
261system.physmem.writeRowHitRate 28.20 # Row buffer hit rate for writes
262system.physmem.avgGap 326630.04 # Average gap between requests
263system.physmem.pageHitRate 54.25 # Row buffer hit rate, read and write combined
264system.physmem_0.actEnergy 1195207440 # Energy for activate commands per rank (pJ)
265system.physmem_0.preEnergy 635245050 # Energy for precharge commands per rank (pJ)
266system.physmem_0.readEnergy 1570792860 # Energy for read commands per rank (pJ)
267system.physmem_0.writeEnergy 757087920 # Energy for write commands per rank (pJ)
268system.physmem_0.refreshEnergy 15735398640.000004 # Energy for refresh commands per rank (pJ)
269system.physmem_0.actBackEnergy 13510945980 # Energy for active background per rank (pJ)
270system.physmem_0.preBackEnergy 615046560 # Energy for precharge background per rank (pJ)
271system.physmem_0.actPowerDownEnergy 46117601610 # Energy for active power-down per rank (pJ)
272system.physmem_0.prePowerDownEnergy 17430135360 # Energy for precharge power-down per rank (pJ)
273system.physmem_0.selfRefreshEnergy 15587831640 # Energy for self refresh per rank (pJ)
274system.physmem_0.totalEnergy 113161874670 # Total energy per rank (pJ)
275system.physmem_0.averagePower 479.804155 # Core power per rank (mW)
276system.physmem_0.totalIdleTime 204603400415 # Total Idle time Per DRAM Rank
277system.physmem_0.memoryStateTime::IDLE 912794276 # Time in different power states
278system.physmem_0.memoryStateTime::REF 6674692000 # Time in different power states
279system.physmem_0.memoryStateTime::SREF 58078463500 # Time in different power states
280system.physmem_0.memoryStateTime::PRE_PDN 45390268663 # Time in different power states
281system.physmem_0.memoryStateTime::ACT 23659127059 # Time in different power states
282system.physmem_0.memoryStateTime::ACT_PDN 101134783502 # Time in different power states
283system.physmem_1.actEnergy 1155130620 # Energy for activate commands per rank (pJ)
284system.physmem_1.preEnergy 613955100 # Energy for precharge commands per rank (pJ)
285system.physmem_1.readEnergy 1485605520 # Energy for read commands per rank (pJ)
286system.physmem_1.writeEnergy 764166240 # Energy for write commands per rank (pJ)
287system.physmem_1.refreshEnergy 15039011520.000004 # Energy for refresh commands per rank (pJ)
288system.physmem_1.actBackEnergy 13474802850 # Energy for active background per rank (pJ)
289system.physmem_1.preBackEnergy 604322400 # Energy for precharge background per rank (pJ)
290system.physmem_1.actPowerDownEnergy 42537889890 # Energy for active power-down per rank (pJ)
291system.physmem_1.prePowerDownEnergy 17081497440 # Energy for precharge power-down per rank (pJ)
292system.physmem_1.selfRefreshEnergy 17718944700 # Energy for self refresh per rank (pJ)
293system.physmem_1.totalEnergy 110481339780 # Total energy per rank (pJ)
294system.physmem_1.averagePower 468.438739 # Core power per rank (mW)
295system.physmem_1.totalIdleTime 204713337667 # Total Idle time Per DRAM Rank
296system.physmem_1.memoryStateTime::IDLE 914400899 # Time in different power states
297system.physmem_1.memoryStateTime::REF 6380142000 # Time in different power states
298system.physmem_1.memoryStateTime::SREF 66945121250 # Time in different power states
299system.physmem_1.memoryStateTime::PRE_PDN 44482448304 # Time in different power states
300system.physmem_1.memoryStateTime::ACT 23842248434 # Time in different power states
301system.physmem_1.memoryStateTime::ACT_PDN 93285768113 # Time in different power states
302system.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
303system.cpu.branchPred.lookups 174426540 # Number of BP lookups
304system.cpu.branchPred.condPredicted 130958868 # Number of conditional branches predicted
305system.cpu.branchPred.condIncorrect 7258964 # Number of conditional branches incorrect
306system.cpu.branchPred.BTBLookups 89936054 # Number of BTB lookups
307system.cpu.branchPred.BTBHits 78903188 # Number of BTB hits
308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
309system.cpu.branchPred.BTBHitPct 87.732544 # BTB Hit Percentage
310system.cpu.branchPred.usedRAS 12071651 # Number of times the RAS was used to get a target.
311system.cpu.branchPred.RASInCorrect 104612 # Number of incorrect RAS predictions.
312system.cpu.branchPred.indirectLookups 4685817 # Number of indirect predictor lookups.
313system.cpu.branchPred.indirectHits 4672093 # Number of indirect target hits.
314system.cpu.branchPred.indirectMisses 13724 # Number of indirect misses.
315system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches.
316system.cpu_clk_domain.clock 500 # Clock period in ticks
317system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
318system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
324system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
325system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

339system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
340system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
341system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
342system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
343system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
344system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
345system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
346system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
347system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
348system.cpu.dtb.walker.walks 0 # Table walker walks requested
349system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
350system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
351system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
352system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
353system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
354system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
355system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

369system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
370system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
371system.cpu.dtb.read_accesses 0 # DTB read accesses
372system.cpu.dtb.write_accesses 0 # DTB write accesses
373system.cpu.dtb.inst_accesses 0 # ITB inst accesses
374system.cpu.dtb.hits 0 # DTB hits
375system.cpu.dtb.misses 0 # DTB misses
376system.cpu.dtb.accesses 0 # DTB accesses
377system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
378system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
381system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
382system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
383system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
384system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
385system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

399system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
400system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
401system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
402system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
403system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
404system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
405system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
406system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
407system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
408system.cpu.itb.walker.walks 0 # Table walker walks requested
409system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
410system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
411system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
412system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
413system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
414system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
415system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

430system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
431system.cpu.itb.read_accesses 0 # DTB read accesses
432system.cpu.itb.write_accesses 0 # DTB write accesses
433system.cpu.itb.inst_accesses 0 # ITB inst accesses
434system.cpu.itb.hits 0 # DTB hits
435system.cpu.itb.misses 0 # DTB misses
436system.cpu.itb.accesses 0 # DTB accesses
437system.cpu.workload.num_syscalls 548 # Number of system calls
438system.cpu.pwrStateResidencyTicks::ON 235850129000 # Cumulative time (in ticks) in various power states
439system.cpu.numCycles 471700259 # number of cpu cycles simulated
440system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
441system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
442system.cpu.fetch.icacheStallCycles 7689412 # Number of cycles fetch is stalled on an Icache miss
443system.cpu.fetch.Insts 726848478 # Number of instructions fetch has processed
444system.cpu.fetch.Branches 174426540 # Number of branches that fetch encountered
445system.cpu.fetch.predictedBranches 95646932 # Number of branches that fetch has predicted taken
446system.cpu.fetch.Cycles 455559849 # Number of cycles fetch has run and was not squashing or blocked
447system.cpu.fetch.SquashCycles 14571167 # Number of cycles fetch has spent squashing
448system.cpu.fetch.MiscStallCycles 7088 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
449system.cpu.fetch.PendingTrapStallCycles 169 # Number of stall cycles due to pending traps
450system.cpu.fetch.IcacheWaitRetryStallCycles 15067 # Number of stall cycles due to full MSHR
451system.cpu.fetch.CacheLines 235109896 # Number of cache lines fetched
452system.cpu.fetch.IcacheSquashes 36736 # Number of outstanding Icache misses that were squashed
453system.cpu.fetch.rateDist::samples 470557168 # Number of instructions fetched each cycle (Total)
454system.cpu.fetch.rateDist::mean 1.672087 # Number of instructions fetched each cycle (Total)
455system.cpu.fetch.rateDist::stdev 1.189865 # Number of instructions fetched each cycle (Total)
456system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
457system.cpu.fetch.rateDist::0 101222144 21.51% 21.51% # Number of instructions fetched each cycle (Total)
458system.cpu.fetch.rateDist::1 131885544 28.03% 49.54% # Number of instructions fetched each cycle (Total)
459system.cpu.fetch.rateDist::2 57421464 12.20% 61.74% # Number of instructions fetched each cycle (Total)
460system.cpu.fetch.rateDist::3 180028016 38.26% 100.00% # Number of instructions fetched each cycle (Total)
461system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
462system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
463system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
464system.cpu.fetch.rateDist::total 470557168 # Number of instructions fetched each cycle (Total)
465system.cpu.fetch.branchRate 0.369783 # Number of branch fetches per cycle
466system.cpu.fetch.rate 1.540912 # Number of inst fetches per cycle
467system.cpu.decode.IdleCycles 32637512 # Number of cycles decode is idle
468system.cpu.decode.BlockedCycles 125886415 # Number of cycles decode is blocked
469system.cpu.decode.RunCycles 282414401 # Number of cycles decode is running
470system.cpu.decode.UnblockCycles 22855437 # Number of cycles decode is unblocking
471system.cpu.decode.SquashCycles 6763403 # Number of cycles decode is squashing
472system.cpu.decode.BranchResolved 71909343 # Number of times decode resolved a branch
473system.cpu.decode.BranchMispred 530427 # Number of times decode detected a branch misprediction
474system.cpu.decode.DecodedInsts 710086582 # Number of instructions handled by decode
475system.cpu.decode.SquashedInsts 29127059 # Number of squashed instructions handled by decode
476system.cpu.rename.SquashCycles 6763403 # Number of cycles rename is squashing
477system.cpu.rename.IdleCycles 63488458 # Number of cycles rename is idle
478system.cpu.rename.BlockCycles 61155779 # Number of cycles rename is blocking
479system.cpu.rename.serializeStallCycles 40463668 # count of cycles rename stalled for serializing inst
480system.cpu.rename.RunCycles 273022741 # Number of cycles rename is running
481system.cpu.rename.UnblockCycles 25663119 # Number of cycles rename is unblocking
482system.cpu.rename.RenamedInsts 681926435 # Number of instructions processed by rename
483system.cpu.rename.SquashedInsts 12775010 # Number of squashed instructions processed by rename
484system.cpu.rename.ROBFullEvents 10060236 # Number of times rename has blocked due to ROB full
485system.cpu.rename.IQFullEvents 2531231 # Number of times rename has blocked due to IQ full
486system.cpu.rename.LQFullEvents 1813266 # Number of times rename has blocked due to LQ full
487system.cpu.rename.SQFullEvents 2373970 # Number of times rename has blocked due to SQ full
488system.cpu.rename.RenamedOperands 826391408 # Number of destination operands rename has renamed
489system.cpu.rename.RenameLookups 2997146717 # Number of register rename lookups that rename has made
490system.cpu.rename.int_rename_lookups 717894841 # Number of integer rename lookups
491system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups
492system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed
493system.cpu.rename.UndoneMaps 172295734 # Number of HB maps that are undone due to squashing
494system.cpu.rename.serializingInsts 1545774 # count of serializing insts renamed
495system.cpu.rename.tempSerializingInsts 1536126 # count of temporary serializing insts renamed
496system.cpu.rename.skidInsts 43961162 # count of insts added to the skid buffer
497system.cpu.memDep0.insertedLoads 142203026 # Number of loads inserted to the mem dependence unit.
498system.cpu.memDep0.insertedStores 67513624 # Number of stores inserted to the mem dependence unit.
499system.cpu.memDep0.conflictingLoads 12913434 # Number of conflicting loads.
500system.cpu.memDep0.conflictingStores 11193544 # Number of conflicting stores.
501system.cpu.iq.iqInstsAdded 664083030 # Number of instructions added to the IQ (excludes non-spec)
502system.cpu.iq.iqNonSpecInstsAdded 2979301 # Number of non-speculative instructions added to the IQ
503system.cpu.iq.iqInstsIssued 608560988 # Number of instructions issued
504system.cpu.iq.iqSquashedInstsIssued 5743597 # Number of squashed instructions issued
505system.cpu.iq.iqSquashedInstsExamined 119714176 # Number of squashed instructions iterated over during squash; mainly for profiling
506system.cpu.iq.iqSquashedOperandsExamined 304959820 # Number of squashed operands that are examined and possibly removed from graph
507system.cpu.iq.iqSquashedNonSpecRemoved 1669 # Number of squashed non-spec instructions that were removed
508system.cpu.iq.issued_per_cycle::samples 470557168 # Number of insts issued each cycle
509system.cpu.iq.issued_per_cycle::mean 1.293277 # Number of insts issued each cycle
510system.cpu.iq.issued_per_cycle::stdev 1.104886 # Number of insts issued each cycle
511system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
512system.cpu.iq.issued_per_cycle::0 154355830 32.80% 32.80% # Number of insts issued each cycle
513system.cpu.iq.issued_per_cycle::1 100909501 21.44% 54.25% # Number of insts issued each cycle
514system.cpu.iq.issued_per_cycle::2 145256303 30.87% 85.12% # Number of insts issued each cycle
515system.cpu.iq.issued_per_cycle::3 63003898 13.39% 98.51% # Number of insts issued each cycle
516system.cpu.iq.issued_per_cycle::4 7030993 1.49% 100.00% # Number of insts issued each cycle
517system.cpu.iq.issued_per_cycle::5 643 0.00% 100.00% # Number of insts issued each cycle
518system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
519system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
520system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
521system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
522system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
523system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
524system.cpu.iq.issued_per_cycle::total 470557168 # Number of insts issued each cycle
525system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
526system.cpu.iq.fu_full::IntAlu 71776446 52.99% 52.99% # attempts to use FU when none available
527system.cpu.iq.fu_full::IntMult 30 0.00% 52.99% # attempts to use FU when none available
528system.cpu.iq.fu_full::IntDiv 0 0.00% 52.99% # attempts to use FU when none available
529system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.99% # attempts to use FU when none available
530system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.99% # attempts to use FU when none available
531system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.99% # attempts to use FU when none available
532system.cpu.iq.fu_full::FloatMult 0 0.00% 52.99% # attempts to use FU when none available
533system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available
534system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.99% # attempts to use FU when none available
535system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.99% # attempts to use FU when none available
536system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.99% # attempts to use FU when none available
537system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.99% # attempts to use FU when none available
538system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.99% # attempts to use FU when none available
539system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.99% # attempts to use FU when none available
540system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.99% # attempts to use FU when none available
541system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.99% # attempts to use FU when none available
542system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.99% # attempts to use FU when none available
543system.cpu.iq.fu_full::SimdMult 0 0.00% 52.99% # attempts to use FU when none available
544system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.99% # attempts to use FU when none available
545system.cpu.iq.fu_full::SimdShift 0 0.00% 52.99% # attempts to use FU when none available
546system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.99% # attempts to use FU when none available
547system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.99% # attempts to use FU when none available
548system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.99% # attempts to use FU when none available
549system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.99% # attempts to use FU when none available
550system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.99% # attempts to use FU when none available
551system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.99% # attempts to use FU when none available
552system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.99% # attempts to use FU when none available
553system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.99% # attempts to use FU when none available
554system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.99% # attempts to use FU when none available
555system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available
556system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.99% # attempts to use FU when none available
557system.cpu.iq.fu_full::MemRead 44249945 32.67% 85.65% # attempts to use FU when none available
558system.cpu.iq.fu_full::MemWrite 19436717 14.35% 100.00% # attempts to use FU when none available
559system.cpu.iq.fu_full::FloatMemRead 9 0.00% 100.00% # attempts to use FU when none available
560system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available
561system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
562system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
563system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
564system.cpu.iq.FU_type_0::IntAlu 412327933 67.75% 67.75% # Type of FU issued
565system.cpu.iq.FU_type_0::IntMult 351836 0.06% 67.81% # Type of FU issued
566system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued
567system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued
568system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued
569system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued
570system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued
571system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% # Type of FU issued
572system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued
573system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% # Type of FU issued

--- 13 unchanged lines hidden (view full) ---

587system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued
588system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued
589system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued
590system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued
591system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued
592system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued
593system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued
594system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued
595system.cpu.iq.FU_type_0::MemRead 133457436 21.93% 89.74% # Type of FU issued
596system.cpu.iq.FU_type_0::MemWrite 62423748 10.26% 100.00% # Type of FU issued
597system.cpu.iq.FU_type_0::FloatMemRead 16 0.00% 100.00% # Type of FU issued
598system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued
599system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
600system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
601system.cpu.iq.FU_type_0::total 608560988 # Type of FU issued
602system.cpu.iq.rate 1.290143 # Inst issue rate
603system.cpu.iq.fu_busy_cnt 135463169 # FU busy when requested
604system.cpu.iq.fu_busy_rate 0.222596 # FU busy rate (busy events/executed inst)
605system.cpu.iq.int_inst_queue_reads 1828885813 # Number of integer instruction queue reads
606system.cpu.iq.int_inst_queue_writes 786805257 # Number of integer instruction queue writes
607system.cpu.iq.int_inst_queue_wakeup_accesses 593918713 # Number of integer instruction queue wakeup accesses
608system.cpu.iq.fp_inst_queue_reads 97 # Number of floating instruction queue reads
609system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes
610system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
611system.cpu.iq.int_alu_accesses 744024094 # Number of integer alu accesses
612system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses
613system.cpu.iew.lsq.thread0.forwLoads 7272380 # Number of loads that had data forwarded from stores
614system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
615system.cpu.iew.lsq.thread0.squashedLoads 26319743 # Number of loads squashed
616system.cpu.iew.lsq.thread0.ignoredResponses 24134 # Number of memory responses ignored because the instruction is squashed
617system.cpu.iew.lsq.thread0.memOrderViolation 29234 # Number of memory ordering violations
618system.cpu.iew.lsq.thread0.squashedStores 10653404 # Number of stores squashed
619system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
620system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
621system.cpu.iew.lsq.thread0.rescheduledLoads 224604 # Number of loads that were rescheduled
622system.cpu.iew.lsq.thread0.cacheBlocked 23301 # Number of times an access to memory failed due to the cache being blocked
623system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
624system.cpu.iew.iewSquashCycles 6763403 # Number of cycles IEW is squashing
625system.cpu.iew.iewBlockCycles 23756716 # Number of cycles IEW is blocking
626system.cpu.iew.iewUnblockCycles 981361 # Number of cycles IEW is unblocking
627system.cpu.iew.iewDispatchedInsts 668554311 # Number of instructions dispatched to IQ
628system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
629system.cpu.iew.iewDispLoadInsts 142203026 # Number of dispatched load instructions
630system.cpu.iew.iewDispStoreInsts 67513624 # Number of dispatched store instructions
631system.cpu.iew.iewDispNonSpecInsts 1490759 # Number of dispatched non-speculative instructions
632system.cpu.iew.iewIQFullEvents 256987 # Number of times the IQ has become full, causing a stall
633system.cpu.iew.iewLSQFullEvents 586437 # Number of times the LSQ has become full, causing a stall
634system.cpu.iew.memOrderViolationEvents 29234 # Number of memory order violations
635system.cpu.iew.predictedTakenIncorrect 3560929 # Number of branches that were predicted taken incorrectly
636system.cpu.iew.predictedNotTakenIncorrect 3767464 # Number of branches that were predicted not taken incorrectly
637system.cpu.iew.branchMispredicts 7328393 # Number of branch mispredicts detected at execute
638system.cpu.iew.iewExecutedInsts 598121332 # Number of executed instructions
639system.cpu.iew.iewExecLoadInsts 128978812 # Number of load instructions executed
640system.cpu.iew.iewExecSquashedInsts 10439656 # Number of squashed instructions skipped in execute
641system.cpu.iew.exec_swp 0 # number of swp insts executed
642system.cpu.iew.exec_nop 1491980 # number of nop insts executed
643system.cpu.iew.exec_refs 189925083 # number of memory reference insts executed
644system.cpu.iew.exec_branches 131214447 # Number of branches executed
645system.cpu.iew.exec_stores 60946271 # Number of stores executed
646system.cpu.iew.exec_rate 1.268011 # Inst execution rate
647system.cpu.iew.wb_sent 595160432 # cumulative count of insts sent to commit
648system.cpu.iew.wb_count 593918729 # cumulative count of insts written-back
649system.cpu.iew.wb_producers 349300209 # num instructions producing a value
650system.cpu.iew.wb_consumers 571006140 # num instructions consuming a value
651system.cpu.iew.wb_rate 1.259102 # insts written-back per cycle
652system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back
653system.cpu.commit.commitSquashedInsts 106531473 # The number of squashed insts skipped by commit
654system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
655system.cpu.commit.branchMispredicts 6736784 # The number of times a branch was mispredicted
656system.cpu.commit.committed_per_cycle::samples 453954004 # Number of insts commited each cycle
657system.cpu.commit.committed_per_cycle::mean 1.208695 # Number of insts commited each cycle
658system.cpu.commit.committed_per_cycle::stdev 1.885174 # Number of insts commited each cycle
659system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
660system.cpu.commit.committed_per_cycle::0 225266208 49.62% 49.62% # Number of insts commited each cycle
661system.cpu.commit.committed_per_cycle::1 116316093 25.62% 75.25% # Number of insts commited each cycle
662system.cpu.commit.committed_per_cycle::2 43463338 9.57% 84.82% # Number of insts commited each cycle
663system.cpu.commit.committed_per_cycle::3 23021553 5.07% 89.89% # Number of insts commited each cycle
664system.cpu.commit.committed_per_cycle::4 11663985 2.57% 92.46% # Number of insts commited each cycle
665system.cpu.commit.committed_per_cycle::5 7751412 1.71% 94.17% # Number of insts commited each cycle
666system.cpu.commit.committed_per_cycle::6 8276330 1.82% 95.99% # Number of insts commited each cycle
667system.cpu.commit.committed_per_cycle::7 4247049 0.94% 96.93% # Number of insts commited each cycle
668system.cpu.commit.committed_per_cycle::8 13948036 3.07% 100.00% # Number of insts commited each cycle
669system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
670system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
671system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
672system.cpu.commit.committed_per_cycle::total 453954004 # Number of insts commited each cycle
673system.cpu.commit.committedInsts 506578818 # Number of instructions committed
674system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed
675system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
676system.cpu.commit.refs 172743503 # Number of memory references committed
677system.cpu.commit.loads 115883283 # Number of loads committed
678system.cpu.commit.membars 1488542 # Number of memory barriers committed
679system.cpu.commit.branches 121552863 # Number of branches committed
680system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.

--- 33 unchanged lines hidden (view full) ---

714system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
715system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
716system.cpu.commit.op_class_0::MemWrite 56860204 10.36% 100.00% # Class of committed instruction
717system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
718system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction
719system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
720system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
721system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction
722system.cpu.commit.bw_lim_events 13948036 # number cycles where commit BW limit reached
723system.cpu.rob.rob_reads 1095222342 # The number of ROB reads
724system.cpu.rob.rob_writes 1327086117 # The number of ROB writes
725system.cpu.timesIdled 14782 # Number of times that the entire CPU went into an idle state and unscheduled itself
726system.cpu.idleCycles 1143091 # Total number of cycles that the CPU has spent unscheduled due to idling
727system.cpu.committedInsts 505234934 # Number of Instructions Simulated
728system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated
729system.cpu.cpi 0.933626 # CPI: Cycles Per Instruction
730system.cpu.cpi_total 0.933626 # CPI: Total CPI of All Threads
731system.cpu.ipc 1.071093 # IPC: Instructions Per Cycle
732system.cpu.ipc_total 1.071093 # IPC: Total IPC of All Threads
733system.cpu.int_regfile_reads 609897818 # number of integer regfile reads
734system.cpu.int_regfile_writes 327085541 # number of integer regfile writes
735system.cpu.fp_regfile_reads 16 # number of floating regfile reads
736system.cpu.cc_regfile_reads 2165040622 # number of cc regfile reads
737system.cpu.cc_regfile_writes 376344417 # number of cc regfile writes
738system.cpu.misc_regfile_reads 217537377 # number of misc regfile reads
739system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
740system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
741system.cpu.dcache.tags.replacements 2817480 # number of replacements
742system.cpu.dcache.tags.tagsinuse 511.627959 # Cycle average of tags in use
743system.cpu.dcache.tags.total_refs 168773991 # Total number of references to valid blocks.
744system.cpu.dcache.tags.sampled_refs 2817992 # Sample count of references to valid blocks.
745system.cpu.dcache.tags.avg_refs 59.891579 # Average number of references to valid blocks.
746system.cpu.dcache.tags.warmup_cycle 504701000 # Cycle when the warmup percentage was hit.
747system.cpu.dcache.tags.occ_blocks::cpu.data 511.627959 # Average occupied blocks per requestor
748system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy
749system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy
750system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
751system.cpu.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
752system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
753system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
754system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
755system.cpu.dcache.tags.tag_accesses 355076080 # Number of tag accesses
756system.cpu.dcache.tags.data_accesses 355076080 # Number of data accesses
757system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
758system.cpu.dcache.ReadReq_hits::cpu.data 114071383 # number of ReadReq hits
759system.cpu.dcache.ReadReq_hits::total 114071383 # number of ReadReq hits
760system.cpu.dcache.WriteReq_hits::cpu.data 51722665 # number of WriteReq hits
761system.cpu.dcache.WriteReq_hits::total 51722665 # number of WriteReq hits
762system.cpu.dcache.SoftPFReq_hits::cpu.data 2778 # number of SoftPFReq hits
763system.cpu.dcache.SoftPFReq_hits::total 2778 # number of SoftPFReq hits
764system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits
765system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits
766system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
767system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
768system.cpu.dcache.demand_hits::cpu.data 165794048 # number of demand (read+write) hits
769system.cpu.dcache.demand_hits::total 165794048 # number of demand (read+write) hits
770system.cpu.dcache.overall_hits::cpu.data 165796826 # number of overall hits
771system.cpu.dcache.overall_hits::total 165796826 # number of overall hits
772system.cpu.dcache.ReadReq_misses::cpu.data 4838662 # number of ReadReq misses
773system.cpu.dcache.ReadReq_misses::total 4838662 # number of ReadReq misses
774system.cpu.dcache.WriteReq_misses::cpu.data 2516384 # number of WriteReq misses
775system.cpu.dcache.WriteReq_misses::total 2516384 # number of WriteReq misses
776system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses
777system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses
778system.cpu.dcache.LoadLockedReq_misses::cpu.data 65 # number of LoadLockedReq misses
779system.cpu.dcache.LoadLockedReq_misses::total 65 # number of LoadLockedReq misses
780system.cpu.dcache.demand_misses::cpu.data 7355046 # number of demand (read+write) misses
781system.cpu.dcache.demand_misses::total 7355046 # number of demand (read+write) misses
782system.cpu.dcache.overall_misses::cpu.data 7355056 # number of overall misses
783system.cpu.dcache.overall_misses::total 7355056 # number of overall misses
784system.cpu.dcache.ReadReq_miss_latency::cpu.data 63735397500 # number of ReadReq miss cycles
785system.cpu.dcache.ReadReq_miss_latency::total 63735397500 # number of ReadReq miss cycles
786system.cpu.dcache.WriteReq_miss_latency::cpu.data 19938555937 # number of WriteReq miss cycles
787system.cpu.dcache.WriteReq_miss_latency::total 19938555937 # number of WriteReq miss cycles
788system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 846000 # number of LoadLockedReq miss cycles
789system.cpu.dcache.LoadLockedReq_miss_latency::total 846000 # number of LoadLockedReq miss cycles
790system.cpu.dcache.demand_miss_latency::cpu.data 83673953437 # number of demand (read+write) miss cycles
791system.cpu.dcache.demand_miss_latency::total 83673953437 # number of demand (read+write) miss cycles
792system.cpu.dcache.overall_miss_latency::cpu.data 83673953437 # number of overall miss cycles
793system.cpu.dcache.overall_miss_latency::total 83673953437 # number of overall miss cycles
794system.cpu.dcache.ReadReq_accesses::cpu.data 118910045 # number of ReadReq accesses(hits+misses)
795system.cpu.dcache.ReadReq_accesses::total 118910045 # number of ReadReq accesses(hits+misses)
796system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
797system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
798system.cpu.dcache.SoftPFReq_accesses::cpu.data 2788 # number of SoftPFReq accesses(hits+misses)
799system.cpu.dcache.SoftPFReq_accesses::total 2788 # number of SoftPFReq accesses(hits+misses)
800system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488621 # number of LoadLockedReq accesses(hits+misses)
801system.cpu.dcache.LoadLockedReq_accesses::total 1488621 # number of LoadLockedReq accesses(hits+misses)
802system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
803system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
804system.cpu.dcache.demand_accesses::cpu.data 173149094 # number of demand (read+write) accesses
805system.cpu.dcache.demand_accesses::total 173149094 # number of demand (read+write) accesses
806system.cpu.dcache.overall_accesses::cpu.data 173151882 # number of overall (read+write) accesses
807system.cpu.dcache.overall_accesses::total 173151882 # number of overall (read+write) accesses
808system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040692 # miss rate for ReadReq accesses
809system.cpu.dcache.ReadReq_miss_rate::total 0.040692 # miss rate for ReadReq accesses
810system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046394 # miss rate for WriteReq accesses
811system.cpu.dcache.WriteReq_miss_rate::total 0.046394 # miss rate for WriteReq accesses
812system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003587 # miss rate for SoftPFReq accesses
813system.cpu.dcache.SoftPFReq_miss_rate::total 0.003587 # miss rate for SoftPFReq accesses
814system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses
815system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses
816system.cpu.dcache.demand_miss_rate::cpu.data 0.042478 # miss rate for demand accesses
817system.cpu.dcache.demand_miss_rate::total 0.042478 # miss rate for demand accesses
818system.cpu.dcache.overall_miss_rate::cpu.data 0.042477 # miss rate for overall accesses
819system.cpu.dcache.overall_miss_rate::total 0.042477 # miss rate for overall accesses
820system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13172.111939 # average ReadReq miss latency
821system.cpu.dcache.ReadReq_avg_miss_latency::total 13172.111939 # average ReadReq miss latency
822system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7923.494958 # average WriteReq miss latency
823system.cpu.dcache.WriteReq_avg_miss_latency::total 7923.494958 # average WriteReq miss latency
824system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13015.384615 # average LoadLockedReq miss latency
825system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13015.384615 # average LoadLockedReq miss latency
826system.cpu.dcache.demand_avg_miss_latency::cpu.data 11376.401104 # average overall miss latency
827system.cpu.dcache.demand_avg_miss_latency::total 11376.401104 # average overall miss latency
828system.cpu.dcache.overall_avg_miss_latency::cpu.data 11376.385637 # average overall miss latency
829system.cpu.dcache.overall_avg_miss_latency::total 11376.385637 # average overall miss latency
830system.cpu.dcache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked
831system.cpu.dcache.blocked_cycles::no_targets 1100252 # number of cycles access was blocked
832system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
833system.cpu.dcache.blocked::no_targets 221126 # number of cycles access was blocked
834system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.666667 # average number of cycles each access was blocked
835system.cpu.dcache.avg_blocked_cycles::no_targets 4.975679 # average number of cycles each access was blocked
836system.cpu.dcache.writebacks::writebacks 2817480 # number of writebacks
837system.cpu.dcache.writebacks::total 2817480 # number of writebacks
838system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540507 # number of ReadReq MSHR hits
839system.cpu.dcache.ReadReq_mshr_hits::total 2540507 # number of ReadReq MSHR hits
840system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996523 # number of WriteReq MSHR hits
841system.cpu.dcache.WriteReq_mshr_hits::total 1996523 # number of WriteReq MSHR hits
842system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 65 # number of LoadLockedReq MSHR hits
843system.cpu.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits
844system.cpu.dcache.demand_mshr_hits::cpu.data 4537030 # number of demand (read+write) MSHR hits
845system.cpu.dcache.demand_mshr_hits::total 4537030 # number of demand (read+write) MSHR hits
846system.cpu.dcache.overall_mshr_hits::cpu.data 4537030 # number of overall MSHR hits
847system.cpu.dcache.overall_mshr_hits::total 4537030 # number of overall MSHR hits
848system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298155 # number of ReadReq MSHR misses
849system.cpu.dcache.ReadReq_mshr_misses::total 2298155 # number of ReadReq MSHR misses
850system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519861 # number of WriteReq MSHR misses
851system.cpu.dcache.WriteReq_mshr_misses::total 519861 # number of WriteReq MSHR misses
852system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses
853system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses
854system.cpu.dcache.demand_mshr_misses::cpu.data 2818016 # number of demand (read+write) MSHR misses
855system.cpu.dcache.demand_mshr_misses::total 2818016 # number of demand (read+write) MSHR misses
856system.cpu.dcache.overall_mshr_misses::cpu.data 2818025 # number of overall MSHR misses
857system.cpu.dcache.overall_mshr_misses::total 2818025 # number of overall MSHR misses
858system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32727255000 # number of ReadReq MSHR miss cycles
859system.cpu.dcache.ReadReq_mshr_miss_latency::total 32727255000 # number of ReadReq MSHR miss cycles
860system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4791332496 # number of WriteReq MSHR miss cycles
861system.cpu.dcache.WriteReq_mshr_miss_latency::total 4791332496 # number of WriteReq MSHR miss cycles
862system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1174000 # number of SoftPFReq MSHR miss cycles
863system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1174000 # number of SoftPFReq MSHR miss cycles
864system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37518587496 # number of demand (read+write) MSHR miss cycles
865system.cpu.dcache.demand_mshr_miss_latency::total 37518587496 # number of demand (read+write) MSHR miss cycles
866system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37519761496 # number of overall MSHR miss cycles
867system.cpu.dcache.overall_mshr_miss_latency::total 37519761496 # number of overall MSHR miss cycles
868system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019327 # mshr miss rate for ReadReq accesses
869system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019327 # mshr miss rate for ReadReq accesses
870system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009585 # mshr miss rate for WriteReq accesses
871system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009585 # mshr miss rate for WriteReq accesses
872system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003228 # mshr miss rate for SoftPFReq accesses
873system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003228 # mshr miss rate for SoftPFReq accesses
874system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for demand accesses
875system.cpu.dcache.demand_mshr_miss_rate::total 0.016275 # mshr miss rate for demand accesses
876system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for overall accesses
877system.cpu.dcache.overall_mshr_miss_rate::total 0.016275 # mshr miss rate for overall accesses
878system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14240.664794 # average ReadReq mshr miss latency
879system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14240.664794 # average ReadReq mshr miss latency
880system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9216.564612 # average WriteReq mshr miss latency
881system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9216.564612 # average WriteReq mshr miss latency
882system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 130444.444444 # average SoftPFReq mshr miss latency
883system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 130444.444444 # average SoftPFReq mshr miss latency
884system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13313.830545 # average overall mshr miss latency
885system.cpu.dcache.demand_avg_mshr_miss_latency::total 13313.830545 # average overall mshr miss latency
886system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13314.204628 # average overall mshr miss latency
887system.cpu.dcache.overall_avg_mshr_miss_latency::total 13314.204628 # average overall mshr miss latency
888system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
889system.cpu.icache.tags.replacements 76537 # number of replacements
890system.cpu.icache.tags.tagsinuse 465.899675 # Cycle average of tags in use
891system.cpu.icache.tags.total_refs 235023805 # Total number of references to valid blocks.
892system.cpu.icache.tags.sampled_refs 77049 # Sample count of references to valid blocks.
893system.cpu.icache.tags.avg_refs 3050.316098 # Average number of references to valid blocks.
894system.cpu.icache.tags.warmup_cycle 116553680500 # Cycle when the warmup percentage was hit.
895system.cpu.icache.tags.occ_blocks::cpu.inst 465.899675 # Average occupied blocks per requestor
896system.cpu.icache.tags.occ_percent::cpu.inst 0.909960 # Average percentage of cache occupancy
897system.cpu.icache.tags.occ_percent::total 0.909960 # Average percentage of cache occupancy
898system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
899system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
900system.cpu.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id
901system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
902system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
903system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id
904system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
905system.cpu.icache.tags.tag_accesses 470296624 # Number of tag accesses
906system.cpu.icache.tags.data_accesses 470296624 # Number of data accesses
907system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
908system.cpu.icache.ReadReq_hits::cpu.inst 235023805 # number of ReadReq hits
909system.cpu.icache.ReadReq_hits::total 235023805 # number of ReadReq hits
910system.cpu.icache.demand_hits::cpu.inst 235023805 # number of demand (read+write) hits
911system.cpu.icache.demand_hits::total 235023805 # number of demand (read+write) hits
912system.cpu.icache.overall_hits::cpu.inst 235023805 # number of overall hits
913system.cpu.icache.overall_hits::total 235023805 # number of overall hits
914system.cpu.icache.ReadReq_misses::cpu.inst 85967 # number of ReadReq misses
915system.cpu.icache.ReadReq_misses::total 85967 # number of ReadReq misses
916system.cpu.icache.demand_misses::cpu.inst 85967 # number of demand (read+write) misses
917system.cpu.icache.demand_misses::total 85967 # number of demand (read+write) misses
918system.cpu.icache.overall_misses::cpu.inst 85967 # number of overall misses
919system.cpu.icache.overall_misses::total 85967 # number of overall misses
920system.cpu.icache.ReadReq_miss_latency::cpu.inst 1954653197 # number of ReadReq miss cycles
921system.cpu.icache.ReadReq_miss_latency::total 1954653197 # number of ReadReq miss cycles
922system.cpu.icache.demand_miss_latency::cpu.inst 1954653197 # number of demand (read+write) miss cycles
923system.cpu.icache.demand_miss_latency::total 1954653197 # number of demand (read+write) miss cycles
924system.cpu.icache.overall_miss_latency::cpu.inst 1954653197 # number of overall miss cycles
925system.cpu.icache.overall_miss_latency::total 1954653197 # number of overall miss cycles
926system.cpu.icache.ReadReq_accesses::cpu.inst 235109772 # number of ReadReq accesses(hits+misses)
927system.cpu.icache.ReadReq_accesses::total 235109772 # number of ReadReq accesses(hits+misses)
928system.cpu.icache.demand_accesses::cpu.inst 235109772 # number of demand (read+write) accesses
929system.cpu.icache.demand_accesses::total 235109772 # number of demand (read+write) accesses
930system.cpu.icache.overall_accesses::cpu.inst 235109772 # number of overall (read+write) accesses
931system.cpu.icache.overall_accesses::total 235109772 # number of overall (read+write) accesses
932system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses
933system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses
934system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses
935system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses
936system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses
937system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses
938system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22737.250305 # average ReadReq miss latency
939system.cpu.icache.ReadReq_avg_miss_latency::total 22737.250305 # average ReadReq miss latency
940system.cpu.icache.demand_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency
941system.cpu.icache.demand_avg_miss_latency::total 22737.250305 # average overall miss latency
942system.cpu.icache.overall_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency
943system.cpu.icache.overall_avg_miss_latency::total 22737.250305 # average overall miss latency
944system.cpu.icache.blocked_cycles::no_mshrs 201943 # number of cycles access was blocked
945system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked
946system.cpu.icache.blocked::no_mshrs 7203 # number of cycles access was blocked
947system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
948system.cpu.icache.avg_blocked_cycles::no_mshrs 28.035957 # average number of cycles each access was blocked
949system.cpu.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked
950system.cpu.icache.writebacks::writebacks 76537 # number of writebacks
951system.cpu.icache.writebacks::total 76537 # number of writebacks
952system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8885 # number of ReadReq MSHR hits
953system.cpu.icache.ReadReq_mshr_hits::total 8885 # number of ReadReq MSHR hits
954system.cpu.icache.demand_mshr_hits::cpu.inst 8885 # number of demand (read+write) MSHR hits
955system.cpu.icache.demand_mshr_hits::total 8885 # number of demand (read+write) MSHR hits
956system.cpu.icache.overall_mshr_hits::cpu.inst 8885 # number of overall MSHR hits
957system.cpu.icache.overall_mshr_hits::total 8885 # number of overall MSHR hits
958system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77082 # number of ReadReq MSHR misses
959system.cpu.icache.ReadReq_mshr_misses::total 77082 # number of ReadReq MSHR misses
960system.cpu.icache.demand_mshr_misses::cpu.inst 77082 # number of demand (read+write) MSHR misses
961system.cpu.icache.demand_mshr_misses::total 77082 # number of demand (read+write) MSHR misses
962system.cpu.icache.overall_mshr_misses::cpu.inst 77082 # number of overall MSHR misses
963system.cpu.icache.overall_mshr_misses::total 77082 # number of overall MSHR misses
964system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551815800 # number of ReadReq MSHR miss cycles
965system.cpu.icache.ReadReq_mshr_miss_latency::total 1551815800 # number of ReadReq MSHR miss cycles
966system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551815800 # number of demand (read+write) MSHR miss cycles
967system.cpu.icache.demand_mshr_miss_latency::total 1551815800 # number of demand (read+write) MSHR miss cycles
968system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551815800 # number of overall MSHR miss cycles
969system.cpu.icache.overall_mshr_miss_latency::total 1551815800 # number of overall MSHR miss cycles
970system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses
971system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses
972system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses
973system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses
974system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses
975system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses
976system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20132.012662 # average ReadReq mshr miss latency
977system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20132.012662 # average ReadReq mshr miss latency
978system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency
979system.cpu.icache.demand_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency
980system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency
981system.cpu.icache.overall_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency
982system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
983system.cpu.l2cache.prefetcher.num_hwpf_issued 8513754 # number of hwpf issued
984system.cpu.l2cache.prefetcher.pfIdentified 8515198 # number of prefetch candidates identified
985system.cpu.l2cache.prefetcher.pfBufferHit 454 # number of redundant prefetches already in prefetch queue
986system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
987system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
988system.cpu.l2cache.prefetcher.pfSpanPage 744250 # number of prefetches not generated due to page crossing
989system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
990system.cpu.l2cache.tags.replacements 390446 # number of replacements
991system.cpu.l2cache.tags.tagsinuse 15006.522104 # Cycle average of tags in use
992system.cpu.l2cache.tags.total_refs 2698185 # Total number of references to valid blocks.
993system.cpu.l2cache.tags.sampled_refs 406039 # Sample count of references to valid blocks.
994system.cpu.l2cache.tags.avg_refs 6.645138 # Average number of references to valid blocks.
995system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
996system.cpu.l2cache.tags.occ_blocks::writebacks 14933.160754 # Average occupied blocks per requestor
997system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 73.361350 # Average occupied blocks per requestor
998system.cpu.l2cache.tags.occ_percent::writebacks 0.911448 # Average percentage of cache occupancy
999system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004478 # Average percentage of cache occupancy
1000system.cpu.l2cache.tags.occ_percent::total 0.915925 # Average percentage of cache occupancy
1001system.cpu.l2cache.tags.occ_task_id_blocks::1022 107 # Occupied blocks per task id
1002system.cpu.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id
1003system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id
1004system.cpu.l2cache.tags.age_task_id_blocks_1022::3 51 # Occupied blocks per task id
1005system.cpu.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id
1006system.cpu.l2cache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id
1007system.cpu.l2cache.tags.age_task_id_blocks_1024::1 675 # Occupied blocks per task id
1008system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5453 # Occupied blocks per task id
1009system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6496 # Occupied blocks per task id
1010system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2623 # Occupied blocks per task id
1011system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006531 # Percentage of cache occupancy per task id
1012system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id
1013system.cpu.l2cache.tags.tag_accesses 95374967 # Number of tag accesses
1014system.cpu.l2cache.tags.data_accesses 95374967 # Number of data accesses
1015system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
1016system.cpu.l2cache.WritebackDirty_hits::writebacks 2350430 # number of WritebackDirty hits
1017system.cpu.l2cache.WritebackDirty_hits::total 2350430 # number of WritebackDirty hits
1018system.cpu.l2cache.WritebackClean_hits::writebacks 520007 # number of WritebackClean hits
1019system.cpu.l2cache.WritebackClean_hits::total 520007 # number of WritebackClean hits
1020system.cpu.l2cache.ReadExReq_hits::cpu.data 516734 # number of ReadExReq hits
1021system.cpu.l2cache.ReadExReq_hits::total 516734 # number of ReadExReq hits
1022system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 66859 # number of ReadCleanReq hits
1023system.cpu.l2cache.ReadCleanReq_hits::total 66859 # number of ReadCleanReq hits
1024system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2131098 # number of ReadSharedReq hits
1025system.cpu.l2cache.ReadSharedReq_hits::total 2131098 # number of ReadSharedReq hits
1026system.cpu.l2cache.demand_hits::cpu.inst 66859 # number of demand (read+write) hits
1027system.cpu.l2cache.demand_hits::cpu.data 2647832 # number of demand (read+write) hits
1028system.cpu.l2cache.demand_hits::total 2714691 # number of demand (read+write) hits
1029system.cpu.l2cache.overall_hits::cpu.inst 66859 # number of overall hits
1030system.cpu.l2cache.overall_hits::cpu.data 2647832 # number of overall hits
1031system.cpu.l2cache.overall_hits::total 2714691 # number of overall hits
1032system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses
1033system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses
1034system.cpu.l2cache.ReadExReq_misses::cpu.data 5281 # number of ReadExReq misses
1035system.cpu.l2cache.ReadExReq_misses::total 5281 # number of ReadExReq misses
1036system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10187 # number of ReadCleanReq misses
1037system.cpu.l2cache.ReadCleanReq_misses::total 10187 # number of ReadCleanReq misses
1038system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164879 # number of ReadSharedReq misses
1039system.cpu.l2cache.ReadSharedReq_misses::total 164879 # number of ReadSharedReq misses
1040system.cpu.l2cache.demand_misses::cpu.inst 10187 # number of demand (read+write) misses
1041system.cpu.l2cache.demand_misses::cpu.data 170160 # number of demand (read+write) misses
1042system.cpu.l2cache.demand_misses::total 180347 # number of demand (read+write) misses
1043system.cpu.l2cache.overall_misses::cpu.inst 10187 # number of overall misses
1044system.cpu.l2cache.overall_misses::cpu.data 170160 # number of overall misses
1045system.cpu.l2cache.overall_misses::total 180347 # number of overall misses
1046system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 87000 # number of UpgradeReq miss cycles
1047system.cpu.l2cache.UpgradeReq_miss_latency::total 87000 # number of UpgradeReq miss cycles
1048system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 674041000 # number of ReadExReq miss cycles
1049system.cpu.l2cache.ReadExReq_miss_latency::total 674041000 # number of ReadExReq miss cycles
1050system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1035576000 # number of ReadCleanReq miss cycles
1051system.cpu.l2cache.ReadCleanReq_miss_latency::total 1035576000 # number of ReadCleanReq miss cycles
1052system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15320195500 # number of ReadSharedReq miss cycles
1053system.cpu.l2cache.ReadSharedReq_miss_latency::total 15320195500 # number of ReadSharedReq miss cycles
1054system.cpu.l2cache.demand_miss_latency::cpu.inst 1035576000 # number of demand (read+write) miss cycles
1055system.cpu.l2cache.demand_miss_latency::cpu.data 15994236500 # number of demand (read+write) miss cycles
1056system.cpu.l2cache.demand_miss_latency::total 17029812500 # number of demand (read+write) miss cycles
1057system.cpu.l2cache.overall_miss_latency::cpu.inst 1035576000 # number of overall miss cycles
1058system.cpu.l2cache.overall_miss_latency::cpu.data 15994236500 # number of overall miss cycles
1059system.cpu.l2cache.overall_miss_latency::total 17029812500 # number of overall miss cycles
1060system.cpu.l2cache.WritebackDirty_accesses::writebacks 2350430 # number of WritebackDirty accesses(hits+misses)
1061system.cpu.l2cache.WritebackDirty_accesses::total 2350430 # number of WritebackDirty accesses(hits+misses)
1062system.cpu.l2cache.WritebackClean_accesses::writebacks 520007 # number of WritebackClean accesses(hits+misses)
1063system.cpu.l2cache.WritebackClean_accesses::total 520007 # number of WritebackClean accesses(hits+misses)
1064system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33 # number of UpgradeReq accesses(hits+misses)
1065system.cpu.l2cache.UpgradeReq_accesses::total 33 # number of UpgradeReq accesses(hits+misses)
1066system.cpu.l2cache.ReadExReq_accesses::cpu.data 522015 # number of ReadExReq accesses(hits+misses)
1067system.cpu.l2cache.ReadExReq_accesses::total 522015 # number of ReadExReq accesses(hits+misses)
1068system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77046 # number of ReadCleanReq accesses(hits+misses)
1069system.cpu.l2cache.ReadCleanReq_accesses::total 77046 # number of ReadCleanReq accesses(hits+misses)
1070system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295977 # number of ReadSharedReq accesses(hits+misses)
1071system.cpu.l2cache.ReadSharedReq_accesses::total 2295977 # number of ReadSharedReq accesses(hits+misses)
1072system.cpu.l2cache.demand_accesses::cpu.inst 77046 # number of demand (read+write) accesses
1073system.cpu.l2cache.demand_accesses::cpu.data 2817992 # number of demand (read+write) accesses
1074system.cpu.l2cache.demand_accesses::total 2895038 # number of demand (read+write) accesses
1075system.cpu.l2cache.overall_accesses::cpu.inst 77046 # number of overall (read+write) accesses
1076system.cpu.l2cache.overall_accesses::cpu.data 2817992 # number of overall (read+write) accesses
1077system.cpu.l2cache.overall_accesses::total 2895038 # number of overall (read+write) accesses
1078system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1079system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1080system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.010117 # miss rate for ReadExReq accesses
1081system.cpu.l2cache.ReadExReq_miss_rate::total 0.010117 # miss rate for ReadExReq accesses
1082system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.132220 # miss rate for ReadCleanReq accesses
1083system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.132220 # miss rate for ReadCleanReq accesses
1084system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071812 # miss rate for ReadSharedReq accesses
1085system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071812 # miss rate for ReadSharedReq accesses
1086system.cpu.l2cache.demand_miss_rate::cpu.inst 0.132220 # miss rate for demand accesses
1087system.cpu.l2cache.demand_miss_rate::cpu.data 0.060383 # miss rate for demand accesses
1088system.cpu.l2cache.demand_miss_rate::total 0.062295 # miss rate for demand accesses
1089system.cpu.l2cache.overall_miss_rate::cpu.inst 0.132220 # miss rate for overall accesses
1090system.cpu.l2cache.overall_miss_rate::cpu.data 0.060383 # miss rate for overall accesses
1091system.cpu.l2cache.overall_miss_rate::total 0.062295 # miss rate for overall accesses
1092system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2636.363636 # average UpgradeReq miss latency
1093system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2636.363636 # average UpgradeReq miss latency
1094system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127635.106987 # average ReadExReq miss latency
1095system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127635.106987 # average ReadExReq miss latency
1096system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101656.621184 # average ReadCleanReq miss latency
1097system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101656.621184 # average ReadCleanReq miss latency
1098system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92917.809424 # average ReadSharedReq miss latency
1099system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92917.809424 # average ReadSharedReq miss latency
1100system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101656.621184 # average overall miss latency
1101system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93995.277974 # average overall miss latency
1102system.cpu.l2cache.demand_avg_miss_latency::total 94428.033180 # average overall miss latency
1103system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101656.621184 # average overall miss latency
1104system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93995.277974 # average overall miss latency
1105system.cpu.l2cache.overall_avg_miss_latency::total 94428.033180 # average overall miss latency
1106system.cpu.l2cache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked
1107system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1108system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1109system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1110system.cpu.l2cache.avg_blocked_cycles::no_mshrs 349 # average number of cycles each access was blocked
1111system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1112system.cpu.l2cache.unused_prefetches 1991 # number of HardPF blocks evicted w/o reference
1113system.cpu.l2cache.writebacks::writebacks 291460 # number of writebacks
1114system.cpu.l2cache.writebacks::total 291460 # number of writebacks
1115system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1597 # number of ReadExReq MSHR hits
1116system.cpu.l2cache.ReadExReq_mshr_hits::total 1597 # number of ReadExReq MSHR hits
1117system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits
1118system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
1119system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4534 # number of ReadSharedReq MSHR hits
1120system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4534 # number of ReadSharedReq MSHR hits
1121system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
1122system.cpu.l2cache.demand_mshr_hits::cpu.data 6131 # number of demand (read+write) MSHR hits
1123system.cpu.l2cache.demand_mshr_hits::total 6142 # number of demand (read+write) MSHR hits
1124system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
1125system.cpu.l2cache.overall_mshr_hits::cpu.data 6131 # number of overall MSHR hits
1126system.cpu.l2cache.overall_mshr_hits::total 6142 # number of overall MSHR hits
1127system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356126 # number of HardPFReq MSHR misses
1128system.cpu.l2cache.HardPFReq_mshr_misses::total 356126 # number of HardPFReq MSHR misses
1129system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses
1130system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses
1131system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3684 # number of ReadExReq MSHR misses
1132system.cpu.l2cache.ReadExReq_mshr_misses::total 3684 # number of ReadExReq MSHR misses
1133system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10176 # number of ReadCleanReq MSHR misses
1134system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10176 # number of ReadCleanReq MSHR misses
1135system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160345 # number of ReadSharedReq MSHR misses
1136system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160345 # number of ReadSharedReq MSHR misses
1137system.cpu.l2cache.demand_mshr_misses::cpu.inst 10176 # number of demand (read+write) MSHR misses
1138system.cpu.l2cache.demand_mshr_misses::cpu.data 164029 # number of demand (read+write) MSHR misses
1139system.cpu.l2cache.demand_mshr_misses::total 174205 # number of demand (read+write) MSHR misses
1140system.cpu.l2cache.overall_mshr_misses::cpu.inst 10176 # number of overall MSHR misses
1141system.cpu.l2cache.overall_mshr_misses::cpu.data 164029 # number of overall MSHR misses
1142system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356126 # number of overall MSHR misses
1143system.cpu.l2cache.overall_mshr_misses::total 530331 # number of overall MSHR misses
1144system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of HardPFReq MSHR miss cycles
1145system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21400232213 # number of HardPFReq MSHR miss cycles
1146system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 517000 # number of UpgradeReq MSHR miss cycles
1147system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 517000 # number of UpgradeReq MSHR miss cycles
1148system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 462922500 # number of ReadExReq MSHR miss cycles
1149system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 462922500 # number of ReadExReq MSHR miss cycles
1150system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 973097500 # number of ReadCleanReq MSHR miss cycles
1151system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 973097500 # number of ReadCleanReq MSHR miss cycles
1152system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13944331500 # number of ReadSharedReq MSHR miss cycles
1153system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13944331500 # number of ReadSharedReq MSHR miss cycles
1154system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 973097500 # number of demand (read+write) MSHR miss cycles
1155system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14407254000 # number of demand (read+write) MSHR miss cycles
1156system.cpu.l2cache.demand_mshr_miss_latency::total 15380351500 # number of demand (read+write) MSHR miss cycles
1157system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 973097500 # number of overall MSHR miss cycles
1158system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14407254000 # number of overall MSHR miss cycles
1159system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of overall MSHR miss cycles
1160system.cpu.l2cache.overall_mshr_miss_latency::total 36780583713 # number of overall MSHR miss cycles
1161system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1162system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1163system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1164system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1165system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007057 # mshr miss rate for ReadExReq accesses
1166system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007057 # mshr miss rate for ReadExReq accesses
1167system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for ReadCleanReq accesses
1168system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.132077 # mshr miss rate for ReadCleanReq accesses
1169system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069837 # mshr miss rate for ReadSharedReq accesses
1170system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069837 # mshr miss rate for ReadSharedReq accesses
1171system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for demand accesses
1172system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for demand accesses
1173system.cpu.l2cache.demand_mshr_miss_rate::total 0.060174 # mshr miss rate for demand accesses
1174system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for overall accesses
1175system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for overall accesses
1176system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1177system.cpu.l2cache.overall_mshr_miss_rate::total 0.183186 # mshr miss rate for overall accesses
1178system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average HardPFReq mshr miss latency
1179system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60091.743408 # average HardPFReq mshr miss latency
1180system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15666.666667 # average UpgradeReq mshr miss latency
1181system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15666.666667 # average UpgradeReq mshr miss latency
1182system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 125657.573290 # average ReadExReq mshr miss latency
1183system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 125657.573290 # average ReadExReq mshr miss latency
1184system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95626.719733 # average ReadCleanReq mshr miss latency
1185system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95626.719733 # average ReadCleanReq mshr miss latency
1186system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 86964.554554 # average ReadSharedReq mshr miss latency
1187system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86964.554554 # average ReadSharedReq mshr miss latency
1188system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency
1189system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency
1190system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88288.806291 # average overall mshr miss latency
1191system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency
1192system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency
1193system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average overall mshr miss latency
1194system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69354.014216 # average overall mshr miss latency
1195system.cpu.toL2Bus.snoop_filter.tot_requests 5789124 # Total number of requests made to the snoop filter.
1196system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1197system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1198system.cpu.toL2Bus.snoop_filter.tot_snoops 99823 # Total number of snoops made to the snoop filter.
1199system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99226 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1200system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 597 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1201system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
1202system.cpu.toL2Bus.trans_dist::ReadResp 2373057 # Transaction distribution
1203system.cpu.toL2Bus.trans_dist::WritebackDirty 2641890 # Transaction distribution
1204system.cpu.toL2Bus.trans_dist::WritebackClean 543587 # Transaction distribution
1205system.cpu.toL2Bus.trans_dist::CleanEvict 98986 # Transaction distribution
1206system.cpu.toL2Bus.trans_dist::HardPFReq 403295 # Transaction distribution
1207system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
1208system.cpu.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution
1209system.cpu.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution
1210system.cpu.toL2Bus.trans_dist::ReadExReq 522015 # Transaction distribution
1211system.cpu.toL2Bus.trans_dist::ReadExResp 522015 # Transaction distribution
1212system.cpu.toL2Bus.trans_dist::ReadCleanReq 77082 # Transaction distribution
1213system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295977 # Transaction distribution
1214system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230663 # Packet count per connected master and slave (bytes)
1215system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453531 # Packet count per connected master and slave (bytes)
1216system.cpu.toL2Bus.pkt_count::total 8684194 # Packet count per connected master and slave (bytes)
1217system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9829184 # Cumulative packet size per connected master and slave (bytes)
1218system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272 # Cumulative packet size per connected master and slave (bytes)
1219system.cpu.toL2Bus.pkt_size::total 370499456 # Cumulative packet size per connected master and slave (bytes)
1220system.cpu.toL2Bus.snoops 793778 # Total snoops (count)
1221system.cpu.toL2Bus.snoopTraffic 18655808 # Total snoop traffic (bytes)
1222system.cpu.toL2Bus.snoop_fanout::samples 3688848 # Request fanout histogram
1223system.cpu.toL2Bus.snoop_fanout::mean 0.034290 # Request fanout histogram
1224system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 # Request fanout histogram
1225system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1226system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% # Request fanout histogram
1227system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% # Request fanout histogram
1228system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% # Request fanout histogram
1229system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1230system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1231system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1232system.cpu.toL2Bus.snoop_fanout::total 3688848 # Request fanout histogram
1233system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 # Layer occupancy (ticks)
1234system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%)
1235system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks)
1236system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1237system.cpu.toL2Bus.respLayer0.occupancy 115655928 # Layer occupancy (ticks)
1238system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1239system.cpu.toL2Bus.respLayer1.occupancy 4227026456 # Layer occupancy (ticks)
1240system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
1241system.membus.snoop_filter.tot_requests 821093 # Total number of requests made to the snoop filter.
1242system.membus.snoop_filter.hit_single_requests 414041 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1243system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1244system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1245system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1246system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1247system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
1248system.membus.trans_dist::ReadResp 426929 # Transaction distribution
1249system.membus.trans_dist::WritebackDirty 291460 # Transaction distribution
1250system.membus.trans_dist::CleanEvict 98986 # Transaction distribution
1251system.membus.trans_dist::UpgradeReq 36 # Transaction distribution
1252system.membus.trans_dist::ReadExReq 3681 # Transaction distribution
1253system.membus.trans_dist::ReadExResp 3681 # Transaction distribution
1254system.membus.trans_dist::ReadSharedReq 426930 # Transaction distribution
1255system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 # Packet count per connected master and slave (bytes)
1256system.membus.pkt_count::total 1251703 # Packet count per connected master and slave (bytes)
1257system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 # Cumulative packet size per connected master and slave (bytes)
1258system.membus.pkt_size::total 46212480 # Cumulative packet size per connected master and slave (bytes)
1259system.membus.snoops 0 # Total snoops (count)
1260system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1261system.membus.snoop_fanout::samples 430647 # Request fanout histogram
1262system.membus.snoop_fanout::mean 0 # Request fanout histogram
1263system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1264system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1265system.membus.snoop_fanout::0 430647 100.00% 100.00% # Request fanout histogram
1266system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1267system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1268system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1269system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1270system.membus.snoop_fanout::total 430647 # Request fanout histogram
1271system.membus.reqLayer0.occupancy 2213026745 # Layer occupancy (ticks)
1272system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
1273system.membus.respLayer1.occupancy 2279181090 # Layer occupancy (ticks)
1274system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
1275
1276---------- End Simulation Statistics ----------