1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.233306 # Number of seconds simulated
4sim_ticks 233306027000 # Number of ticks simulated
5final_tick 233306027000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 128535 # Simulator instruction rate (inst/s)
8host_op_rate 139249 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 59354207 # Simulator tick rate (ticks/s)
10host_mem_usage 322028 # Number of bytes of host memory used
11host_seconds 3930.74 # Real time elapsed on the host
12sim_insts 505237724 # Number of instructions simulated
13sim_ops 547350945 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 683648 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9174464 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 16490944 # Number of bytes read from this memory
19system.physmem.bytes_read::total 26349056 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 683648 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 683648 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 18702784 # Number of bytes written to this memory
23system.physmem.bytes_written::total 18702784 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 10682 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 143351 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.l2cache.prefetcher 257671 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 411704 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 292231 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 292231 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 2930263 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 39323733 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.l2cache.prefetcher 70683746 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 112937742 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 2930263 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 2930263 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 80164170 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 80164170 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 80164170 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 2930263 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 39323733 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.l2cache.prefetcher 70683746 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 193101912 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 411704 # Number of read requests accepted
44system.physmem.writeReqs 292231 # Number of write requests accepted
45system.physmem.readBursts 411704 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 292231 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 26211648 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 137408 # Total number of bytes read from write queue
49system.physmem.bytesWritten 18700672 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 26349056 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 18702784 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 2147 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 26604 # Per bank write bursts
56system.physmem.perBankRdBursts::1 25479 # Per bank write bursts
57system.physmem.perBankRdBursts::2 25122 # Per bank write bursts
58system.physmem.perBankRdBursts::3 24753 # Per bank write bursts
59system.physmem.perBankRdBursts::4 27168 # Per bank write bursts
60system.physmem.perBankRdBursts::5 26312 # Per bank write bursts
61system.physmem.perBankRdBursts::6 25243 # Per bank write bursts
62system.physmem.perBankRdBursts::7 24096 # Per bank write bursts
63system.physmem.perBankRdBursts::8 25848 # Per bank write bursts
64system.physmem.perBankRdBursts::9 24676 # Per bank write bursts
65system.physmem.perBankRdBursts::10 25150 # Per bank write bursts
66system.physmem.perBankRdBursts::11 26103 # Per bank write bursts
67system.physmem.perBankRdBursts::12 26513 # Per bank write bursts
68system.physmem.perBankRdBursts::13 25940 # Per bank write bursts
69system.physmem.perBankRdBursts::14 25062 # Per bank write bursts
70system.physmem.perBankRdBursts::15 25488 # Per bank write bursts
71system.physmem.perBankWrBursts::0 18828 # Per bank write bursts
72system.physmem.perBankWrBursts::1 18294 # Per bank write bursts
73system.physmem.perBankWrBursts::2 17806 # Per bank write bursts
74system.physmem.perBankWrBursts::3 17978 # Per bank write bursts
75system.physmem.perBankWrBursts::4 18719 # Per bank write bursts
76system.physmem.perBankWrBursts::5 18281 # Per bank write bursts
77system.physmem.perBankWrBursts::6 17995 # Per bank write bursts
78system.physmem.perBankWrBursts::7 17635 # Per bank write bursts
79system.physmem.perBankWrBursts::8 18144 # Per bank write bursts
80system.physmem.perBankWrBursts::9 17824 # Per bank write bursts
81system.physmem.perBankWrBursts::10 18107 # Per bank write bursts
82system.physmem.perBankWrBursts::11 18749 # Per bank write bursts
83system.physmem.perBankWrBursts::12 18847 # Per bank write bursts
84system.physmem.perBankWrBursts::13 18260 # Per bank write bursts
85system.physmem.perBankWrBursts::14 18418 # Per bank write bursts
86system.physmem.perBankWrBursts::15 18313 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89system.physmem.totGap 233306009000 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 411704 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 292231 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 311101 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 49294 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 13059 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 9199 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 7392 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 6207 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 5318 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 4408 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 3416 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 39 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 19 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see

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143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 6347 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 6612 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 13179 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 15360 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 16390 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 16942 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 17209 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 17386 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 17637 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 17840 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 18016 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 18369 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 18501 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 18840 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 20067 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 18284 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 17602 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 17448 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 42 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see

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192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 306850 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 146.361336 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 102.891492 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 182.277612 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 184544 60.14% 60.14% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 81708 26.63% 86.77% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 16503 5.38% 92.15% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 7231 2.36% 94.50% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 4881 1.59% 96.09% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 2237 0.73% 96.82% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 1756 0.57% 97.40% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 1532 0.50% 97.90% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 6458 2.10% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 306850 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 17319 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 23.647035 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::stdev 116.821350 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::0-511 17318 99.99% 99.99% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::total 17319 # Reads before turning the bus around for writes
220system.physmem.wrPerTurnAround::samples 17319 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::mean 16.871528 # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::gmean 16.829762 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::stdev 1.229266 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::16 10538 60.85% 60.85% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::17 299 1.73% 62.57% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::18 5524 31.90% 94.47% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::19 601 3.47% 97.94% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::20 136 0.79% 98.72% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::21 86 0.50% 99.22% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::22 52 0.30% 99.52% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::23 38 0.22% 99.74% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::24 24 0.14% 99.88% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::25 14 0.08% 99.96% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::27 1 0.01% 99.99% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::total 17319 # Writes before turning the bus around for reads
238system.physmem.totQLat 9105020732 # Total ticks spent queuing
239system.physmem.totMemAccLat 16784214482 # Total ticks spent from burst creation until serviced by the DRAM
240system.physmem.totBusLat 2047785000 # Total ticks spent in databus transfers
241system.physmem.avgQLat 22231.39 # Average queueing delay per DRAM burst
242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
243system.physmem.avgMemAccLat 40981.39 # Average memory access latency per DRAM burst
244system.physmem.avgRdBW 112.35 # Average DRAM read bandwidth in MiByte/s
245system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s
246system.physmem.avgRdBWSys 112.94 # Average system read bandwidth in MiByte/s
247system.physmem.avgWrBWSys 80.16 # Average system write bandwidth in MiByte/s
248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
249system.physmem.busUtil 1.50 # Data bus utilization in percentage
250system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads
251system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes
252system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
253system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing
254system.physmem.readRowHits 299267 # Number of row buffer hits during reads
255system.physmem.writeRowHits 95628 # Number of row buffer hits during writes
256system.physmem.readRowHitRate 73.07 # Row buffer hit rate for reads
257system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes
258system.physmem.avgGap 331431.18 # Average gap between requests
259system.physmem.pageHitRate 56.27 # Row buffer hit rate, read and write combined
260system.physmem_0.actEnergy 1155833280 # Energy for activate commands per rank (pJ)
261system.physmem_0.preEnergy 630663000 # Energy for precharge commands per rank (pJ)
262system.physmem_0.readEnergy 1596964200 # Energy for read commands per rank (pJ)
263system.physmem_0.writeEnergy 942956640 # Energy for write commands per rank (pJ)
264system.physmem_0.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ)
265system.physmem_0.actBackEnergy 74824379370 # Energy for active background per rank (pJ)
266system.physmem_0.preBackEnergy 74344372500 # Energy for precharge background per rank (pJ)
267system.physmem_0.totalEnergy 168733152270 # Total energy per rank (pJ)
268system.physmem_0.averagePower 723.246471 # Core power per rank (mW)
269system.physmem_0.memoryStateTime::IDLE 123152752220 # Time in different power states
270system.physmem_0.memoryStateTime::REF 7790380000 # Time in different power states
271system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
272system.physmem_0.memoryStateTime::ACT 102358687280 # Time in different power states
273system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
274system.physmem_1.actEnergy 1163673000 # Energy for activate commands per rank (pJ)
275system.physmem_1.preEnergy 634940625 # Energy for precharge commands per rank (pJ)
276system.physmem_1.readEnergy 1597073400 # Energy for read commands per rank (pJ)
277system.physmem_1.writeEnergy 950279040 # Energy for write commands per rank (pJ)
278system.physmem_1.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ)
279system.physmem_1.actBackEnergy 74177760825 # Energy for active background per rank (pJ)
280system.physmem_1.preBackEnergy 74911581750 # Energy for precharge background per rank (pJ)
281system.physmem_1.totalEnergy 168673291920 # Total energy per rank (pJ)
282system.physmem_1.averagePower 722.989890 # Core power per rank (mW)
283system.physmem_1.memoryStateTime::IDLE 124105976502 # Time in different power states
284system.physmem_1.memoryStateTime::REF 7790380000 # Time in different power states
285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
286system.physmem_1.memoryStateTime::ACT 101406021498 # Time in different power states
287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
288system.cpu.branchPred.lookups 175092094 # Number of BP lookups
289system.cpu.branchPred.condPredicted 131341607 # Number of conditional branches predicted
290system.cpu.branchPred.condIncorrect 7444018 # Number of conditional branches incorrect
291system.cpu.branchPred.BTBLookups 90535143 # Number of BTB lookups
292system.cpu.branchPred.BTBHits 83876326 # Number of BTB hits
293system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
294system.cpu.branchPred.BTBHitPct 92.645047 # BTB Hit Percentage
295system.cpu.branchPred.usedRAS 12109430 # Number of times the RAS was used to get a target.
296system.cpu.branchPred.RASInCorrect 104164 # Number of incorrect RAS predictions.
297system.cpu_clk_domain.clock 500 # Clock period in ticks
298system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

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407system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
408system.cpu.itb.read_accesses 0 # DTB read accesses
409system.cpu.itb.write_accesses 0 # DTB write accesses
410system.cpu.itb.inst_accesses 0 # ITB inst accesses
411system.cpu.itb.hits 0 # DTB hits
412system.cpu.itb.misses 0 # DTB misses
413system.cpu.itb.accesses 0 # DTB accesses
414system.cpu.workload.num_syscalls 548 # Number of system calls
415system.cpu.numCycles 466612055 # number of cpu cycles simulated
416system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
417system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
418system.cpu.fetch.icacheStallCycles 7841296 # Number of cycles fetch is stalled on an Icache miss
419system.cpu.fetch.Insts 731804732 # Number of instructions fetch has processed
420system.cpu.fetch.Branches 175092094 # Number of branches that fetch encountered
421system.cpu.fetch.predictedBranches 95985756 # Number of branches that fetch has predicted taken
422system.cpu.fetch.Cycles 450426990 # Number of cycles fetch has run and was not squashing or blocked
423system.cpu.fetch.SquashCycles 14940841 # Number of cycles fetch has spent squashing
424system.cpu.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
425system.cpu.fetch.PendingTrapStallCycles 183 # Number of stall cycles due to pending traps
426system.cpu.fetch.IcacheWaitRetryStallCycles 13996 # Number of stall cycles due to full MSHR
427system.cpu.fetch.CacheLines 236719309 # Number of cache lines fetched
428system.cpu.fetch.IcacheSquashes 34673 # Number of outstanding Icache misses that were squashed
429system.cpu.fetch.rateDist::samples 465758844 # Number of instructions fetched each cycle (Total)
430system.cpu.fetch.rateDist::mean 1.701594 # Number of instructions fetched each cycle (Total)
431system.cpu.fetch.rateDist::stdev 1.179451 # Number of instructions fetched each cycle (Total)
432system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
433system.cpu.fetch.rateDist::0 93829138 20.15% 20.15% # Number of instructions fetched each cycle (Total)
434system.cpu.fetch.rateDist::1 132701430 28.49% 48.64% # Number of instructions fetched each cycle (Total)
435system.cpu.fetch.rateDist::2 57853582 12.42% 61.06% # Number of instructions fetched each cycle (Total)
436system.cpu.fetch.rateDist::3 181374694 38.94% 100.00% # Number of instructions fetched each cycle (Total)
437system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
438system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
439system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
440system.cpu.fetch.rateDist::total 465758844 # Number of instructions fetched each cycle (Total)
441system.cpu.fetch.branchRate 0.375241 # Number of branch fetches per cycle
442system.cpu.fetch.rate 1.568337 # Number of inst fetches per cycle
443system.cpu.decode.IdleCycles 32366390 # Number of cycles decode is idle
444system.cpu.decode.BlockedCycles 117283842 # Number of cycles decode is blocked
445system.cpu.decode.RunCycles 287098365 # Number of cycles decode is running
446system.cpu.decode.UnblockCycles 22028374 # Number of cycles decode is unblocking
447system.cpu.decode.SquashCycles 6981873 # Number of cycles decode is squashing
448system.cpu.decode.BranchResolved 24050011 # Number of times decode resolved a branch
449system.cpu.decode.BranchMispred 496385 # Number of times decode detected a branch misprediction
450system.cpu.decode.DecodedInsts 715808617 # Number of instructions handled by decode
451system.cpu.decode.SquashedInsts 30003155 # Number of squashed instructions handled by decode
452system.cpu.rename.SquashCycles 6981873 # Number of cycles rename is squashing
453system.cpu.rename.IdleCycles 63420619 # Number of cycles rename is idle
454system.cpu.rename.BlockCycles 54156177 # Number of cycles rename is blocking
455system.cpu.rename.serializeStallCycles 40346363 # count of cycles rename stalled for serializing inst
456system.cpu.rename.RunCycles 276695654 # Number of cycles rename is running
457system.cpu.rename.UnblockCycles 24158158 # Number of cycles rename is unblocking
458system.cpu.rename.RenamedInsts 686602803 # Number of instructions processed by rename
459system.cpu.rename.SquashedInsts 13340804 # Number of squashed instructions processed by rename
460system.cpu.rename.ROBFullEvents 9402338 # Number of times rename has blocked due to ROB full
461system.cpu.rename.IQFullEvents 2387140 # Number of times rename has blocked due to IQ full
462system.cpu.rename.LQFullEvents 1669358 # Number of times rename has blocked due to LQ full
463system.cpu.rename.SQFullEvents 1928954 # Number of times rename has blocked due to SQ full
464system.cpu.rename.RenamedOperands 831026912 # Number of destination operands rename has renamed
465system.cpu.rename.RenameLookups 3019223277 # Number of register rename lookups that rename has made
466system.cpu.rename.int_rename_lookups 723937000 # Number of integer rename lookups
467system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
468system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
469system.cpu.rename.UndoneMaps 176903161 # Number of HB maps that are undone due to squashing
470system.cpu.rename.serializingInsts 1544702 # count of serializing insts renamed
471system.cpu.rename.tempSerializingInsts 1535188 # count of temporary serializing insts renamed
472system.cpu.rename.skidInsts 42285800 # count of insts added to the skid buffer
473system.cpu.memDep0.insertedLoads 143529225 # Number of loads inserted to the mem dependence unit.
474system.cpu.memDep0.insertedStores 67986348 # Number of stores inserted to the mem dependence unit.
475system.cpu.memDep0.conflictingLoads 12855797 # Number of conflicting loads.
476system.cpu.memDep0.conflictingStores 11202653 # Number of conflicting stores.
477system.cpu.iq.iqInstsAdded 668172379 # Number of instructions added to the IQ (excludes non-spec)
478system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ
479system.cpu.iq.iqInstsIssued 610256171 # Number of instructions issued
480system.cpu.iq.iqSquashedInstsIssued 5859842 # Number of squashed instructions issued
481system.cpu.iq.iqSquashedInstsExamined 123799764 # Number of squashed instructions iterated over during squash; mainly for profiling
482system.cpu.iq.iqSquashedOperandsExamined 319235639 # Number of squashed operands that are examined and possibly removed from graph
483system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed
484system.cpu.iq.issued_per_cycle::samples 465758844 # Number of insts issued each cycle
485system.cpu.iq.issued_per_cycle::mean 1.310241 # Number of insts issued each cycle
486system.cpu.iq.issued_per_cycle::stdev 1.101448 # Number of insts issued each cycle
487system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
488system.cpu.iq.issued_per_cycle::0 148618613 31.91% 31.91% # Number of insts issued each cycle
489system.cpu.iq.issued_per_cycle::1 101179975 21.72% 53.63% # Number of insts issued each cycle
490system.cpu.iq.issued_per_cycle::2 145721974 31.29% 84.92% # Number of insts issued each cycle
491system.cpu.iq.issued_per_cycle::3 63321350 13.60% 98.51% # Number of insts issued each cycle
492system.cpu.iq.issued_per_cycle::4 6916462 1.48% 100.00% # Number of insts issued each cycle
493system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle
494system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
495system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
496system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
497system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
498system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
499system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
500system.cpu.iq.issued_per_cycle::total 465758844 # Number of insts issued each cycle
501system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
502system.cpu.iq.fu_full::IntAlu 71923603 52.95% 52.95% # attempts to use FU when none available
503system.cpu.iq.fu_full::IntMult 30 0.00% 52.95% # attempts to use FU when none available
504system.cpu.iq.fu_full::IntDiv 0 0.00% 52.95% # attempts to use FU when none available
505system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.95% # attempts to use FU when none available
506system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.95% # attempts to use FU when none available
507system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.95% # attempts to use FU when none available
508system.cpu.iq.fu_full::FloatMult 0 0.00% 52.95% # attempts to use FU when none available
509system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.95% # attempts to use FU when none available
510system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.95% # attempts to use FU when none available
511system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.95% # attempts to use FU when none available
512system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.95% # attempts to use FU when none available
513system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.95% # attempts to use FU when none available
514system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.95% # attempts to use FU when none available
515system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.95% # attempts to use FU when none available
516system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.95% # attempts to use FU when none available
517system.cpu.iq.fu_full::SimdMult 0 0.00% 52.95% # attempts to use FU when none available
518system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.95% # attempts to use FU when none available
519system.cpu.iq.fu_full::SimdShift 0 0.00% 52.95% # attempts to use FU when none available
520system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.95% # attempts to use FU when none available
521system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.95% # attempts to use FU when none available
522system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.95% # attempts to use FU when none available
523system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.95% # attempts to use FU when none available
524system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.95% # attempts to use FU when none available
525system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.95% # attempts to use FU when none available
526system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.95% # attempts to use FU when none available
527system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.95% # attempts to use FU when none available
528system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.95% # attempts to use FU when none available
529system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.95% # attempts to use FU when none available
530system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.95% # attempts to use FU when none available
531system.cpu.iq.fu_full::MemRead 44560845 32.81% 85.75% # attempts to use FU when none available
532system.cpu.iq.fu_full::MemWrite 19351011 14.25% 100.00% # attempts to use FU when none available
533system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
534system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
535system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
536system.cpu.iq.FU_type_0::IntAlu 413149972 67.70% 67.70% # Type of FU issued
537system.cpu.iq.FU_type_0::IntMult 351777 0.06% 67.76% # Type of FU issued
538system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued
539system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued
540system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
541system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued
542system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued
543system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued
544system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued
545system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued

--- 11 unchanged lines hidden (view full) ---

557system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
558system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
559system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
560system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
561system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued
562system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
563system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
564system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
565system.cpu.iq.FU_type_0::MemRead 134213690 21.99% 89.75% # Type of FU issued
566system.cpu.iq.FU_type_0::MemWrite 62540729 10.25% 100.00% # Type of FU issued
567system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
568system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
569system.cpu.iq.FU_type_0::total 610256171 # Type of FU issued
570system.cpu.iq.rate 1.307845 # Inst issue rate
571system.cpu.iq.fu_busy_cnt 135835489 # FU busy when requested
572system.cpu.iq.fu_busy_rate 0.222588 # FU busy rate (busy events/executed inst)
573system.cpu.iq.int_inst_queue_reads 1827966224 # Number of integer instruction queue reads
574system.cpu.iq.int_inst_queue_writes 794978756 # Number of integer instruction queue writes
575system.cpu.iq.int_inst_queue_wakeup_accesses 594986581 # Number of integer instruction queue wakeup accesses
576system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
577system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
578system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
579system.cpu.iq.int_alu_accesses 746091483 # Number of integer alu accesses
580system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses
581system.cpu.iew.lsq.thread0.forwLoads 7271635 # Number of loads that had data forwarded from stores
582system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
583system.cpu.iew.lsq.thread0.squashedLoads 27644469 # Number of loads squashed
584system.cpu.iew.lsq.thread0.ignoredResponses 25562 # Number of memory responses ignored because the instruction is squashed
585system.cpu.iew.lsq.thread0.memOrderViolation 29008 # Number of memory ordering violations
586system.cpu.iew.lsq.thread0.squashedStores 11125871 # Number of stores squashed
587system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
588system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
589system.cpu.iew.lsq.thread0.rescheduledLoads 225728 # Number of loads that were rescheduled
590system.cpu.iew.lsq.thread0.cacheBlocked 22400 # Number of times an access to memory failed due to the cache being blocked
591system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
592system.cpu.iew.iewSquashCycles 6981873 # Number of cycles IEW is squashing
593system.cpu.iew.iewBlockCycles 22924718 # Number of cycles IEW is blocking
594system.cpu.iew.iewUnblockCycles 919849 # Number of cycles IEW is unblocking
595system.cpu.iew.iewDispatchedInsts 672638124 # Number of instructions dispatched to IQ
596system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
597system.cpu.iew.iewDispLoadInsts 143529225 # Number of dispatched load instructions
598system.cpu.iew.iewDispStoreInsts 67986348 # Number of dispatched store instructions
599system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions
600system.cpu.iew.iewIQFullEvents 258699 # Number of times the IQ has become full, causing a stall
601system.cpu.iew.iewLSQFullEvents 524927 # Number of times the LSQ has become full, causing a stall
602system.cpu.iew.memOrderViolationEvents 29008 # Number of memory order violations
603system.cpu.iew.predictedTakenIncorrect 3821848 # Number of branches that were predicted taken incorrectly
604system.cpu.iew.predictedNotTakenIncorrect 3731355 # Number of branches that were predicted not taken incorrectly
605system.cpu.iew.branchMispredicts 7553203 # Number of branch mispredicts detected at execute
606system.cpu.iew.iewExecutedInsts 599403304 # Number of executed instructions
607system.cpu.iew.iewExecLoadInsts 129574600 # Number of load instructions executed
608system.cpu.iew.iewExecSquashedInsts 10852867 # Number of squashed instructions skipped in execute
609system.cpu.iew.exec_swp 0 # number of swp insts executed
610system.cpu.iew.exec_nop 1487415 # number of nop insts executed
611system.cpu.iew.exec_refs 190539133 # number of memory reference insts executed
612system.cpu.iew.exec_branches 131373270 # Number of branches executed
613system.cpu.iew.exec_stores 60964533 # Number of stores executed
614system.cpu.iew.exec_rate 1.284586 # Inst execution rate
615system.cpu.iew.wb_sent 596281070 # cumulative count of insts sent to commit
616system.cpu.iew.wb_count 594986597 # cumulative count of insts written-back
617system.cpu.iew.wb_producers 349903865 # num instructions producing a value
618system.cpu.iew.wb_consumers 570650112 # num instructions consuming a value
619system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
620system.cpu.iew.wb_rate 1.275121 # insts written-back per cycle
621system.cpu.iew.wb_fanout 0.613167 # average fanout of values written-back
622system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
623system.cpu.commit.commitSquashedInsts 110031903 # The number of squashed insts skipped by commit
624system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
625system.cpu.commit.branchMispredicts 6955471 # The number of times a branch was mispredicted
626system.cpu.commit.committed_per_cycle::samples 448643201 # Number of insts commited each cycle
627system.cpu.commit.committed_per_cycle::mean 1.223009 # Number of insts commited each cycle
628system.cpu.commit.committed_per_cycle::stdev 1.887847 # Number of insts commited each cycle
629system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
630system.cpu.commit.committed_per_cycle::0 219610457 48.95% 48.95% # Number of insts commited each cycle
631system.cpu.commit.committed_per_cycle::1 116308832 25.92% 74.87% # Number of insts commited each cycle
632system.cpu.commit.committed_per_cycle::2 43746420 9.75% 84.63% # Number of insts commited each cycle
633system.cpu.commit.committed_per_cycle::3 23291517 5.19% 89.82% # Number of insts commited each cycle
634system.cpu.commit.committed_per_cycle::4 11578245 2.58% 92.40% # Number of insts commited each cycle
635system.cpu.commit.committed_per_cycle::5 7791027 1.74% 94.13% # Number of insts commited each cycle
636system.cpu.commit.committed_per_cycle::6 8269909 1.84% 95.98% # Number of insts commited each cycle
637system.cpu.commit.committed_per_cycle::7 4243315 0.95% 96.92% # Number of insts commited each cycle
638system.cpu.commit.committed_per_cycle::8 13803479 3.08% 100.00% # Number of insts commited each cycle
639system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
640system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
641system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
642system.cpu.commit.committed_per_cycle::total 448643201 # Number of insts commited each cycle
643system.cpu.commit.committedInsts 506581608 # Number of instructions committed
644system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed
645system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
646system.cpu.commit.refs 172745233 # Number of memory references committed
647system.cpu.commit.loads 115884756 # Number of loads committed
648system.cpu.commit.membars 1488542 # Number of memory barriers committed
649system.cpu.commit.branches 121548302 # Number of branches committed
650system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.

--- 29 unchanged lines hidden (view full) ---

680system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
681system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
682system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
683system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction
684system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction
685system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
686system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
687system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction
688system.cpu.commit.bw_lim_events 13803479 # number cycles where commit BW limit reached
689system.cpu.rob.rob_reads 1093559316 # The number of ROB reads
690system.cpu.rob.rob_writes 1334598854 # The number of ROB writes
691system.cpu.timesIdled 13995 # Number of times that the entire CPU went into an idle state and unscheduled itself
692system.cpu.idleCycles 853211 # Total number of cycles that the CPU has spent unscheduled due to idling
693system.cpu.committedInsts 505237724 # Number of Instructions Simulated
694system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated
695system.cpu.cpi 0.923550 # CPI: Cycles Per Instruction
696system.cpu.cpi_total 0.923550 # CPI: Total CPI of All Threads
697system.cpu.ipc 1.082779 # IPC: Instructions Per Cycle
698system.cpu.ipc_total 1.082779 # IPC: Total IPC of All Threads
699system.cpu.int_regfile_reads 611100755 # number of integer regfile reads
700system.cpu.int_regfile_writes 328116502 # number of integer regfile writes
701system.cpu.fp_regfile_reads 16 # number of floating regfile reads
702system.cpu.cc_regfile_reads 2170188783 # number of cc regfile reads
703system.cpu.cc_regfile_writes 376538117 # number of cc regfile writes
704system.cpu.misc_regfile_reads 217976814 # number of misc regfile reads
705system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
706system.cpu.dcache.tags.replacements 2820876 # number of replacements
707system.cpu.dcache.tags.tagsinuse 511.631746 # Cycle average of tags in use
708system.cpu.dcache.tags.total_refs 169355780 # Total number of references to valid blocks.
709system.cpu.dcache.tags.sampled_refs 2821388 # Sample count of references to valid blocks.
710system.cpu.dcache.tags.avg_refs 60.025697 # Average number of references to valid blocks.
711system.cpu.dcache.tags.warmup_cycle 498153000 # Cycle when the warmup percentage was hit.
712system.cpu.dcache.tags.occ_blocks::cpu.data 511.631746 # Average occupied blocks per requestor
713system.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy
714system.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy
715system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
716system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
717system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id
718system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
719system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
720system.cpu.dcache.tags.tag_accesses 356248226 # Number of tag accesses
721system.cpu.dcache.tags.data_accesses 356248226 # Number of data accesses
722system.cpu.dcache.ReadReq_hits::cpu.data 114651895 # number of ReadReq hits
723system.cpu.dcache.ReadReq_hits::total 114651895 # number of ReadReq hits
724system.cpu.dcache.WriteReq_hits::cpu.data 51723951 # number of WriteReq hits
725system.cpu.dcache.WriteReq_hits::total 51723951 # number of WriteReq hits
726system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits
727system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits
728system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits
729system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits
730system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
731system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
732system.cpu.dcache.demand_hits::cpu.data 166375846 # number of demand (read+write) hits
733system.cpu.dcache.demand_hits::total 166375846 # number of demand (read+write) hits
734system.cpu.dcache.overall_hits::cpu.data 166378633 # number of overall hits
735system.cpu.dcache.overall_hits::total 166378633 # number of overall hits
736system.cpu.dcache.ReadReq_misses::cpu.data 4842252 # number of ReadReq misses
737system.cpu.dcache.ReadReq_misses::total 4842252 # number of ReadReq misses
738system.cpu.dcache.WriteReq_misses::cpu.data 2515355 # number of WriteReq misses
739system.cpu.dcache.WriteReq_misses::total 2515355 # number of WriteReq misses
740system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses
741system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses
742system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses
743system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses
744system.cpu.dcache.demand_misses::cpu.data 7357607 # number of demand (read+write) misses
745system.cpu.dcache.demand_misses::total 7357607 # number of demand (read+write) misses
746system.cpu.dcache.overall_misses::cpu.data 7357619 # number of overall misses
747system.cpu.dcache.overall_misses::total 7357619 # number of overall misses
748system.cpu.dcache.ReadReq_miss_latency::cpu.data 56173880000 # number of ReadReq miss cycles
749system.cpu.dcache.ReadReq_miss_latency::total 56173880000 # number of ReadReq miss cycles
750system.cpu.dcache.WriteReq_miss_latency::cpu.data 19052445440 # number of WriteReq miss cycles
751system.cpu.dcache.WriteReq_miss_latency::total 19052445440 # number of WriteReq miss cycles
752system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1310000 # number of LoadLockedReq miss cycles
753system.cpu.dcache.LoadLockedReq_miss_latency::total 1310000 # number of LoadLockedReq miss cycles
754system.cpu.dcache.demand_miss_latency::cpu.data 75226325440 # number of demand (read+write) miss cycles
755system.cpu.dcache.demand_miss_latency::total 75226325440 # number of demand (read+write) miss cycles
756system.cpu.dcache.overall_miss_latency::cpu.data 75226325440 # number of overall miss cycles
757system.cpu.dcache.overall_miss_latency::total 75226325440 # number of overall miss cycles
758system.cpu.dcache.ReadReq_accesses::cpu.data 119494147 # number of ReadReq accesses(hits+misses)
759system.cpu.dcache.ReadReq_accesses::total 119494147 # number of ReadReq accesses(hits+misses)
760system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
761system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
762system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses)
763system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses)
764system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses)
765system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses)
766system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
767system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
768system.cpu.dcache.demand_accesses::cpu.data 173733453 # number of demand (read+write) accesses
769system.cpu.dcache.demand_accesses::total 173733453 # number of demand (read+write) accesses
770system.cpu.dcache.overall_accesses::cpu.data 173736252 # number of overall (read+write) accesses
771system.cpu.dcache.overall_accesses::total 173736252 # number of overall (read+write) accesses
772system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040523 # miss rate for ReadReq accesses
773system.cpu.dcache.ReadReq_miss_rate::total 0.040523 # miss rate for ReadReq accesses
774system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046375 # miss rate for WriteReq accesses
775system.cpu.dcache.WriteReq_miss_rate::total 0.046375 # miss rate for WriteReq accesses
776system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004287 # miss rate for SoftPFReq accesses
777system.cpu.dcache.SoftPFReq_miss_rate::total 0.004287 # miss rate for SoftPFReq accesses
778system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses
779system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses
780system.cpu.dcache.demand_miss_rate::cpu.data 0.042350 # miss rate for demand accesses
781system.cpu.dcache.demand_miss_rate::total 0.042350 # miss rate for demand accesses
782system.cpu.dcache.overall_miss_rate::cpu.data 0.042349 # miss rate for overall accesses
783system.cpu.dcache.overall_miss_rate::total 0.042349 # miss rate for overall accesses
784system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11600.775837 # average ReadReq miss latency
785system.cpu.dcache.ReadReq_avg_miss_latency::total 11600.775837 # average ReadReq miss latency
786system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7574.455868 # average WriteReq miss latency
787system.cpu.dcache.WriteReq_avg_miss_latency::total 7574.455868 # average WriteReq miss latency
788system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19848.484848 # average LoadLockedReq miss latency
789system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19848.484848 # average LoadLockedReq miss latency
790system.cpu.dcache.demand_avg_miss_latency::cpu.data 10224.292415 # average overall miss latency
791system.cpu.dcache.demand_avg_miss_latency::total 10224.292415 # average overall miss latency
792system.cpu.dcache.overall_avg_miss_latency::cpu.data 10224.275739 # average overall miss latency
793system.cpu.dcache.overall_avg_miss_latency::total 10224.275739 # average overall miss latency
794system.cpu.dcache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked
795system.cpu.dcache.blocked_cycles::no_targets 932011 # number of cycles access was blocked
796system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked
797system.cpu.dcache.blocked::no_targets 221163 # number of cycles access was blocked
798system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked
799system.cpu.dcache.avg_blocked_cycles::no_targets 4.214136 # average number of cycles each access was blocked
800system.cpu.dcache.fast_writes 0 # number of fast writes performed
801system.cpu.dcache.cache_copies 0 # number of cache copies performed
802system.cpu.dcache.writebacks::writebacks 2352880 # number of writebacks
803system.cpu.dcache.writebacks::total 2352880 # number of writebacks
804system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540436 # number of ReadReq MSHR hits
805system.cpu.dcache.ReadReq_mshr_hits::total 2540436 # number of ReadReq MSHR hits
806system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995769 # number of WriteReq MSHR hits
807system.cpu.dcache.WriteReq_mshr_hits::total 1995769 # number of WriteReq MSHR hits
808system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits
809system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits
810system.cpu.dcache.demand_mshr_hits::cpu.data 4536205 # number of demand (read+write) MSHR hits
811system.cpu.dcache.demand_mshr_hits::total 4536205 # number of demand (read+write) MSHR hits
812system.cpu.dcache.overall_mshr_hits::cpu.data 4536205 # number of overall MSHR hits
813system.cpu.dcache.overall_mshr_hits::total 4536205 # number of overall MSHR hits
814system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301816 # number of ReadReq MSHR misses
815system.cpu.dcache.ReadReq_mshr_misses::total 2301816 # number of ReadReq MSHR misses
816system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519586 # number of WriteReq MSHR misses
817system.cpu.dcache.WriteReq_mshr_misses::total 519586 # number of WriteReq MSHR misses
818system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses
819system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses
820system.cpu.dcache.demand_mshr_misses::cpu.data 2821402 # number of demand (read+write) MSHR misses
821system.cpu.dcache.demand_mshr_misses::total 2821402 # number of demand (read+write) MSHR misses
822system.cpu.dcache.overall_mshr_misses::cpu.data 2821412 # number of overall MSHR misses
823system.cpu.dcache.overall_mshr_misses::total 2821412 # number of overall MSHR misses
824system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28692574000 # number of ReadReq MSHR miss cycles
825system.cpu.dcache.ReadReq_mshr_miss_latency::total 28692574000 # number of ReadReq MSHR miss cycles
826system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4617588494 # number of WriteReq MSHR miss cycles
827system.cpu.dcache.WriteReq_mshr_miss_latency::total 4617588494 # number of WriteReq MSHR miss cycles
828system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 686000 # number of SoftPFReq MSHR miss cycles
829system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 686000 # number of SoftPFReq MSHR miss cycles
830system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33310162494 # number of demand (read+write) MSHR miss cycles
831system.cpu.dcache.demand_mshr_miss_latency::total 33310162494 # number of demand (read+write) MSHR miss cycles
832system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33310848494 # number of overall MSHR miss cycles
833system.cpu.dcache.overall_mshr_miss_latency::total 33310848494 # number of overall MSHR miss cycles
834system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019263 # mshr miss rate for ReadReq accesses
835system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019263 # mshr miss rate for ReadReq accesses
836system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses
837system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses
838system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003573 # mshr miss rate for SoftPFReq accesses
839system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003573 # mshr miss rate for SoftPFReq accesses
840system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for demand accesses
841system.cpu.dcache.demand_mshr_miss_rate::total 0.016240 # mshr miss rate for demand accesses
842system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for overall accesses
843system.cpu.dcache.overall_mshr_miss_rate::total 0.016240 # mshr miss rate for overall accesses
844system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12465.190093 # average ReadReq mshr miss latency
845system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12465.190093 # average ReadReq mshr miss latency
846system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8887.053335 # average WriteReq mshr miss latency
847system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8887.053335 # average WriteReq mshr miss latency
848system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68600 # average SoftPFReq mshr miss latency
849system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68600 # average SoftPFReq mshr miss latency
850system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11806.244730 # average overall mshr miss latency
851system.cpu.dcache.demand_avg_mshr_miss_latency::total 11806.244730 # average overall mshr miss latency
852system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11806.446026 # average overall mshr miss latency
853system.cpu.dcache.overall_avg_mshr_miss_latency::total 11806.446026 # average overall mshr miss latency
854system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
855system.cpu.icache.tags.replacements 73459 # number of replacements
856system.cpu.icache.tags.tagsinuse 466.213956 # Cycle average of tags in use
857system.cpu.icache.tags.total_refs 236636536 # Total number of references to valid blocks.
858system.cpu.icache.tags.sampled_refs 73971 # Sample count of references to valid blocks.
859system.cpu.icache.tags.avg_refs 3199.044707 # Average number of references to valid blocks.
860system.cpu.icache.tags.warmup_cycle 114942017500 # Cycle when the warmup percentage was hit.
861system.cpu.icache.tags.occ_blocks::cpu.inst 466.213956 # Average occupied blocks per requestor
862system.cpu.icache.tags.occ_percent::cpu.inst 0.910574 # Average percentage of cache occupancy
863system.cpu.icache.tags.occ_percent::total 0.910574 # Average percentage of cache occupancy
864system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
865system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
866system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
867system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id
868system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
869system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id
870system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
871system.cpu.icache.tags.tag_accesses 473512362 # Number of tag accesses
872system.cpu.icache.tags.data_accesses 473512362 # Number of data accesses
873system.cpu.icache.ReadReq_hits::cpu.inst 236636536 # number of ReadReq hits
874system.cpu.icache.ReadReq_hits::total 236636536 # number of ReadReq hits
875system.cpu.icache.demand_hits::cpu.inst 236636536 # number of demand (read+write) hits
876system.cpu.icache.demand_hits::total 236636536 # number of demand (read+write) hits
877system.cpu.icache.overall_hits::cpu.inst 236636536 # number of overall hits
878system.cpu.icache.overall_hits::total 236636536 # number of overall hits
879system.cpu.icache.ReadReq_misses::cpu.inst 82647 # number of ReadReq misses
880system.cpu.icache.ReadReq_misses::total 82647 # number of ReadReq misses
881system.cpu.icache.demand_misses::cpu.inst 82647 # number of demand (read+write) misses
882system.cpu.icache.demand_misses::total 82647 # number of demand (read+write) misses
883system.cpu.icache.overall_misses::cpu.inst 82647 # number of overall misses
884system.cpu.icache.overall_misses::total 82647 # number of overall misses
885system.cpu.icache.ReadReq_miss_latency::cpu.inst 1564864673 # number of ReadReq miss cycles
886system.cpu.icache.ReadReq_miss_latency::total 1564864673 # number of ReadReq miss cycles
887system.cpu.icache.demand_miss_latency::cpu.inst 1564864673 # number of demand (read+write) miss cycles
888system.cpu.icache.demand_miss_latency::total 1564864673 # number of demand (read+write) miss cycles
889system.cpu.icache.overall_miss_latency::cpu.inst 1564864673 # number of overall miss cycles
890system.cpu.icache.overall_miss_latency::total 1564864673 # number of overall miss cycles
891system.cpu.icache.ReadReq_accesses::cpu.inst 236719183 # number of ReadReq accesses(hits+misses)
892system.cpu.icache.ReadReq_accesses::total 236719183 # number of ReadReq accesses(hits+misses)
893system.cpu.icache.demand_accesses::cpu.inst 236719183 # number of demand (read+write) accesses
894system.cpu.icache.demand_accesses::total 236719183 # number of demand (read+write) accesses
895system.cpu.icache.overall_accesses::cpu.inst 236719183 # number of overall (read+write) accesses
896system.cpu.icache.overall_accesses::total 236719183 # number of overall (read+write) accesses
897system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000349 # miss rate for ReadReq accesses
898system.cpu.icache.ReadReq_miss_rate::total 0.000349 # miss rate for ReadReq accesses
899system.cpu.icache.demand_miss_rate::cpu.inst 0.000349 # miss rate for demand accesses
900system.cpu.icache.demand_miss_rate::total 0.000349 # miss rate for demand accesses
901system.cpu.icache.overall_miss_rate::cpu.inst 0.000349 # miss rate for overall accesses
902system.cpu.icache.overall_miss_rate::total 0.000349 # miss rate for overall accesses
903system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18934.319128 # average ReadReq miss latency
904system.cpu.icache.ReadReq_avg_miss_latency::total 18934.319128 # average ReadReq miss latency
905system.cpu.icache.demand_avg_miss_latency::cpu.inst 18934.319128 # average overall miss latency
906system.cpu.icache.demand_avg_miss_latency::total 18934.319128 # average overall miss latency
907system.cpu.icache.overall_avg_miss_latency::cpu.inst 18934.319128 # average overall miss latency
908system.cpu.icache.overall_avg_miss_latency::total 18934.319128 # average overall miss latency
909system.cpu.icache.blocked_cycles::no_mshrs 190768 # number of cycles access was blocked
910system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked
911system.cpu.icache.blocked::no_mshrs 6939 # number of cycles access was blocked
912system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
913system.cpu.icache.avg_blocked_cycles::no_mshrs 27.492146 # average number of cycles each access was blocked
914system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked
915system.cpu.icache.fast_writes 0 # number of fast writes performed
916system.cpu.icache.cache_copies 0 # number of cache copies performed
917system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8650 # number of ReadReq MSHR hits
918system.cpu.icache.ReadReq_mshr_hits::total 8650 # number of ReadReq MSHR hits
919system.cpu.icache.demand_mshr_hits::cpu.inst 8650 # number of demand (read+write) MSHR hits
920system.cpu.icache.demand_mshr_hits::total 8650 # number of demand (read+write) MSHR hits
921system.cpu.icache.overall_mshr_hits::cpu.inst 8650 # number of overall MSHR hits
922system.cpu.icache.overall_mshr_hits::total 8650 # number of overall MSHR hits
923system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73997 # number of ReadReq MSHR misses
924system.cpu.icache.ReadReq_mshr_misses::total 73997 # number of ReadReq MSHR misses
925system.cpu.icache.demand_mshr_misses::cpu.inst 73997 # number of demand (read+write) MSHR misses
926system.cpu.icache.demand_mshr_misses::total 73997 # number of demand (read+write) MSHR misses
927system.cpu.icache.overall_mshr_misses::cpu.inst 73997 # number of overall MSHR misses
928system.cpu.icache.overall_mshr_misses::total 73997 # number of overall MSHR misses
929system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1275745779 # number of ReadReq MSHR miss cycles
930system.cpu.icache.ReadReq_mshr_miss_latency::total 1275745779 # number of ReadReq MSHR miss cycles
931system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1275745779 # number of demand (read+write) MSHR miss cycles
932system.cpu.icache.demand_mshr_miss_latency::total 1275745779 # number of demand (read+write) MSHR miss cycles
933system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1275745779 # number of overall MSHR miss cycles
934system.cpu.icache.overall_mshr_miss_latency::total 1275745779 # number of overall MSHR miss cycles
935system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses
936system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses
937system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses
938system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses
939system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses
940system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses
941system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17240.506764 # average ReadReq mshr miss latency
942system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17240.506764 # average ReadReq mshr miss latency
943system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17240.506764 # average overall mshr miss latency
944system.cpu.icache.demand_avg_mshr_miss_latency::total 17240.506764 # average overall mshr miss latency
945system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17240.506764 # average overall mshr miss latency
946system.cpu.icache.overall_avg_mshr_miss_latency::total 17240.506764 # average overall mshr miss latency
947system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
948system.cpu.l2cache.prefetcher.num_hwpf_issued 8512194 # number of hwpf issued
949system.cpu.l2cache.prefetcher.pfIdentified 8513359 # number of prefetch candidates identified
950system.cpu.l2cache.prefetcher.pfBufferHit 195 # number of redundant prefetches already in prefetch queue
951system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
952system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
953system.cpu.l2cache.prefetcher.pfSpanPage 743225 # number of prefetches not generated due to page crossing
954system.cpu.l2cache.tags.replacements 400641 # number of replacements
955system.cpu.l2cache.tags.tagsinuse 15417.686844 # Cycle average of tags in use
956system.cpu.l2cache.tags.total_refs 5068283 # Total number of references to valid blocks.
957system.cpu.l2cache.tags.sampled_refs 416978 # Sample count of references to valid blocks.
958system.cpu.l2cache.tags.avg_refs 12.154797 # Average number of references to valid blocks.
959system.cpu.l2cache.tags.warmup_cycle 34590463000 # Cycle when the warmup percentage was hit.
960system.cpu.l2cache.tags.occ_blocks::writebacks 8465.103002 # Average occupied blocks per requestor
961system.cpu.l2cache.tags.occ_blocks::cpu.inst 476.521367 # Average occupied blocks per requestor
962system.cpu.l2cache.tags.occ_blocks::cpu.data 4913.026142 # Average occupied blocks per requestor
963system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1563.036333 # Average occupied blocks per requestor
964system.cpu.l2cache.tags.occ_percent::writebacks 0.516669 # Average percentage of cache occupancy
965system.cpu.l2cache.tags.occ_percent::cpu.inst 0.029085 # Average percentage of cache occupancy
966system.cpu.l2cache.tags.occ_percent::cpu.data 0.299867 # Average percentage of cache occupancy
967system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095400 # Average percentage of cache occupancy
968system.cpu.l2cache.tags.occ_percent::total 0.941021 # Average percentage of cache occupancy
969system.cpu.l2cache.tags.occ_task_id_blocks::1022 1142 # Occupied blocks per task id
970system.cpu.l2cache.tags.occ_task_id_blocks::1024 15195 # Occupied blocks per task id
971system.cpu.l2cache.tags.age_task_id_blocks_1022::2 26 # Occupied blocks per task id
972system.cpu.l2cache.tags.age_task_id_blocks_1022::3 276 # Occupied blocks per task id
973system.cpu.l2cache.tags.age_task_id_blocks_1022::4 840 # Occupied blocks per task id
974system.cpu.l2cache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
975system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
976system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1545 # Occupied blocks per task id
977system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9909 # Occupied blocks per task id
978system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3390 # Occupied blocks per task id
979system.cpu.l2cache.tags.occ_task_id_percent::1022 0.069702 # Percentage of cache occupancy per task id
980system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927429 # Percentage of cache occupancy per task id
981system.cpu.l2cache.tags.tag_accesses 93194547 # Number of tag accesses
982system.cpu.l2cache.tags.data_accesses 93194547 # Number of data accesses
983system.cpu.l2cache.Writeback_hits::writebacks 2352880 # number of Writeback hits
984system.cpu.l2cache.Writeback_hits::total 2352880 # number of Writeback hits
985system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits
986system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits
987system.cpu.l2cache.ReadExReq_hits::cpu.data 516809 # number of ReadExReq hits
988system.cpu.l2cache.ReadExReq_hits::total 516809 # number of ReadExReq hits
989system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 63278 # number of ReadCleanReq hits
990system.cpu.l2cache.ReadCleanReq_hits::total 63278 # number of ReadCleanReq hits
991system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2155693 # number of ReadSharedReq hits
992system.cpu.l2cache.ReadSharedReq_hits::total 2155693 # number of ReadSharedReq hits
993system.cpu.l2cache.demand_hits::cpu.inst 63278 # number of demand (read+write) hits
994system.cpu.l2cache.demand_hits::cpu.data 2672502 # number of demand (read+write) hits
995system.cpu.l2cache.demand_hits::total 2735780 # number of demand (read+write) hits
996system.cpu.l2cache.overall_hits::cpu.inst 63278 # number of overall hits
997system.cpu.l2cache.overall_hits::cpu.data 2672502 # number of overall hits
998system.cpu.l2cache.overall_hits::total 2735780 # number of overall hits
999system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
1000system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
1001system.cpu.l2cache.ReadExReq_misses::cpu.data 5137 # number of ReadExReq misses
1002system.cpu.l2cache.ReadExReq_misses::total 5137 # number of ReadExReq misses
1003system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10691 # number of ReadCleanReq misses
1004system.cpu.l2cache.ReadCleanReq_misses::total 10691 # number of ReadCleanReq misses
1005system.cpu.l2cache.ReadSharedReq_misses::cpu.data 143749 # number of ReadSharedReq misses
1006system.cpu.l2cache.ReadSharedReq_misses::total 143749 # number of ReadSharedReq misses
1007system.cpu.l2cache.demand_misses::cpu.inst 10691 # number of demand (read+write) misses
1008system.cpu.l2cache.demand_misses::cpu.data 148886 # number of demand (read+write) misses
1009system.cpu.l2cache.demand_misses::total 159577 # number of demand (read+write) misses
1010system.cpu.l2cache.overall_misses::cpu.inst 10691 # number of overall misses
1011system.cpu.l2cache.overall_misses::cpu.data 148886 # number of overall misses
1012system.cpu.l2cache.overall_misses::total 159577 # number of overall misses
1013system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 502200000 # number of ReadExReq miss cycles
1014system.cpu.l2cache.ReadExReq_miss_latency::total 502200000 # number of ReadExReq miss cycles
1015system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 787136500 # number of ReadCleanReq miss cycles
1016system.cpu.l2cache.ReadCleanReq_miss_latency::total 787136500 # number of ReadCleanReq miss cycles
1017system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11114003000 # number of ReadSharedReq miss cycles
1018system.cpu.l2cache.ReadSharedReq_miss_latency::total 11114003000 # number of ReadSharedReq miss cycles
1019system.cpu.l2cache.demand_miss_latency::cpu.inst 787136500 # number of demand (read+write) miss cycles
1020system.cpu.l2cache.demand_miss_latency::cpu.data 11616203000 # number of demand (read+write) miss cycles
1021system.cpu.l2cache.demand_miss_latency::total 12403339500 # number of demand (read+write) miss cycles
1022system.cpu.l2cache.overall_miss_latency::cpu.inst 787136500 # number of overall miss cycles
1023system.cpu.l2cache.overall_miss_latency::cpu.data 11616203000 # number of overall miss cycles
1024system.cpu.l2cache.overall_miss_latency::total 12403339500 # number of overall miss cycles
1025system.cpu.l2cache.Writeback_accesses::writebacks 2352880 # number of Writeback accesses(hits+misses)
1026system.cpu.l2cache.Writeback_accesses::total 2352880 # number of Writeback accesses(hits+misses)
1027system.cpu.l2cache.UpgradeReq_accesses::cpu.data 24 # number of UpgradeReq accesses(hits+misses)
1028system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses)
1029system.cpu.l2cache.ReadExReq_accesses::cpu.data 521946 # number of ReadExReq accesses(hits+misses)
1030system.cpu.l2cache.ReadExReq_accesses::total 521946 # number of ReadExReq accesses(hits+misses)
1031system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 73969 # number of ReadCleanReq accesses(hits+misses)
1032system.cpu.l2cache.ReadCleanReq_accesses::total 73969 # number of ReadCleanReq accesses(hits+misses)
1033system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299442 # number of ReadSharedReq accesses(hits+misses)
1034system.cpu.l2cache.ReadSharedReq_accesses::total 2299442 # number of ReadSharedReq accesses(hits+misses)
1035system.cpu.l2cache.demand_accesses::cpu.inst 73969 # number of demand (read+write) accesses
1036system.cpu.l2cache.demand_accesses::cpu.data 2821388 # number of demand (read+write) accesses
1037system.cpu.l2cache.demand_accesses::total 2895357 # number of demand (read+write) accesses
1038system.cpu.l2cache.overall_accesses::cpu.inst 73969 # number of overall (read+write) accesses
1039system.cpu.l2cache.overall_accesses::cpu.data 2821388 # number of overall (read+write) accesses
1040system.cpu.l2cache.overall_accesses::total 2895357 # number of overall (read+write) accesses
1041system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.041667 # miss rate for UpgradeReq accesses
1042system.cpu.l2cache.UpgradeReq_miss_rate::total 0.041667 # miss rate for UpgradeReq accesses
1043system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009842 # miss rate for ReadExReq accesses
1044system.cpu.l2cache.ReadExReq_miss_rate::total 0.009842 # miss rate for ReadExReq accesses
1045system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.144534 # miss rate for ReadCleanReq accesses
1046system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.144534 # miss rate for ReadCleanReq accesses
1047system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.062515 # miss rate for ReadSharedReq accesses
1048system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.062515 # miss rate for ReadSharedReq accesses
1049system.cpu.l2cache.demand_miss_rate::cpu.inst 0.144534 # miss rate for demand accesses
1050system.cpu.l2cache.demand_miss_rate::cpu.data 0.052770 # miss rate for demand accesses
1051system.cpu.l2cache.demand_miss_rate::total 0.055115 # miss rate for demand accesses
1052system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144534 # miss rate for overall accesses
1053system.cpu.l2cache.overall_miss_rate::cpu.data 0.052770 # miss rate for overall accesses
1054system.cpu.l2cache.overall_miss_rate::total 0.055115 # miss rate for overall accesses
1055system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97761.339303 # average ReadExReq miss latency
1056system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97761.339303 # average ReadExReq miss latency
1057system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73626.087363 # average ReadCleanReq miss latency
1058system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73626.087363 # average ReadCleanReq miss latency
1059system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77315.341324 # average ReadSharedReq miss latency
1060system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77315.341324 # average ReadSharedReq miss latency
1061system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73626.087363 # average overall miss latency
1062system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78020.787717 # average overall miss latency
1063system.cpu.l2cache.demand_avg_miss_latency::total 77726.360942 # average overall miss latency
1064system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73626.087363 # average overall miss latency
1065system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78020.787717 # average overall miss latency
1066system.cpu.l2cache.overall_avg_miss_latency::total 77726.360942 # average overall miss latency
1067system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1068system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1069system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1070system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1071system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1072system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1073system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1074system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1075system.cpu.l2cache.writebacks::writebacks 292231 # number of writebacks
1076system.cpu.l2cache.writebacks::total 292231 # number of writebacks
1077system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1476 # number of ReadExReq MSHR hits
1078system.cpu.l2cache.ReadExReq_mshr_hits::total 1476 # number of ReadExReq MSHR hits
1079system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 8 # number of ReadCleanReq MSHR hits
1080system.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits
1081system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4058 # number of ReadSharedReq MSHR hits
1082system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4058 # number of ReadSharedReq MSHR hits
1083system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
1084system.cpu.l2cache.demand_mshr_hits::cpu.data 5534 # number of demand (read+write) MSHR hits
1085system.cpu.l2cache.demand_mshr_hits::total 5542 # number of demand (read+write) MSHR hits
1086system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
1087system.cpu.l2cache.overall_mshr_hits::cpu.data 5534 # number of overall MSHR hits
1088system.cpu.l2cache.overall_mshr_hits::total 5542 # number of overall MSHR hits
1089system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6918 # number of CleanEvict MSHR misses
1090system.cpu.l2cache.CleanEvict_mshr_misses::total 6918 # number of CleanEvict MSHR misses
1091system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275358 # number of HardPFReq MSHR misses
1092system.cpu.l2cache.HardPFReq_mshr_misses::total 275358 # number of HardPFReq MSHR misses
1093system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
1094system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
1095system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3661 # number of ReadExReq MSHR misses
1096system.cpu.l2cache.ReadExReq_mshr_misses::total 3661 # number of ReadExReq MSHR misses
1097system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10683 # number of ReadCleanReq MSHR misses
1098system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10683 # number of ReadCleanReq MSHR misses
1099system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 139691 # number of ReadSharedReq MSHR misses
1100system.cpu.l2cache.ReadSharedReq_mshr_misses::total 139691 # number of ReadSharedReq MSHR misses
1101system.cpu.l2cache.demand_mshr_misses::cpu.inst 10683 # number of demand (read+write) MSHR misses
1102system.cpu.l2cache.demand_mshr_misses::cpu.data 143352 # number of demand (read+write) MSHR misses
1103system.cpu.l2cache.demand_mshr_misses::total 154035 # number of demand (read+write) MSHR misses
1104system.cpu.l2cache.overall_mshr_misses::cpu.inst 10683 # number of overall MSHR misses
1105system.cpu.l2cache.overall_mshr_misses::cpu.data 143352 # number of overall MSHR misses
1106system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275358 # number of overall MSHR misses
1107system.cpu.l2cache.overall_mshr_misses::total 429393 # number of overall MSHR misses
1108system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19097746561 # number of HardPFReq MSHR miss cycles
1109system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19097746561 # number of HardPFReq MSHR miss cycles
1110system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 17500 # number of UpgradeReq MSHR miss cycles
1111system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 17500 # number of UpgradeReq MSHR miss cycles
1112system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 337925500 # number of ReadExReq MSHR miss cycles
1113system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 337925500 # number of ReadExReq MSHR miss cycles
1114system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 722686500 # number of ReadCleanReq MSHR miss cycles
1115system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 722686500 # number of ReadCleanReq MSHR miss cycles
1116system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9966004000 # number of ReadSharedReq MSHR miss cycles
1117system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9966004000 # number of ReadSharedReq MSHR miss cycles
1118system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 722686500 # number of demand (read+write) MSHR miss cycles
1119system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10303929500 # number of demand (read+write) MSHR miss cycles
1120system.cpu.l2cache.demand_mshr_miss_latency::total 11026616000 # number of demand (read+write) MSHR miss cycles
1121system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 722686500 # number of overall MSHR miss cycles
1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10303929500 # number of overall MSHR miss cycles
1123system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19097746561 # number of overall MSHR miss cycles
1124system.cpu.l2cache.overall_mshr_miss_latency::total 30124362561 # number of overall MSHR miss cycles
1125system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1126system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1127system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1128system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1129system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for UpgradeReq accesses
1130system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.041667 # mshr miss rate for UpgradeReq accesses
1131system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007014 # mshr miss rate for ReadExReq accesses
1132system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007014 # mshr miss rate for ReadExReq accesses
1133system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for ReadCleanReq accesses
1134system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144425 # mshr miss rate for ReadCleanReq accesses
1135system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060750 # mshr miss rate for ReadSharedReq accesses
1136system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060750 # mshr miss rate for ReadSharedReq accesses
1137system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for demand accesses
1138system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for demand accesses
1139system.cpu.l2cache.demand_mshr_miss_rate::total 0.053201 # mshr miss rate for demand accesses
1140system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for overall accesses
1141system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for overall accesses
1142system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1143system.cpu.l2cache.overall_mshr_miss_rate::total 0.148304 # mshr miss rate for overall accesses
1144system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average HardPFReq mshr miss latency
1145system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69356.062148 # average HardPFReq mshr miss latency
1146system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17500 # average UpgradeReq mshr miss latency
1147system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17500 # average UpgradeReq mshr miss latency
1148system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92304.151871 # average ReadExReq mshr miss latency
1149system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92304.151871 # average ReadExReq mshr miss latency
1150system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67648.272957 # average ReadCleanReq mshr miss latency
1151system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67648.272957 # average ReadCleanReq mshr miss latency
1152system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71343.207508 # average ReadSharedReq mshr miss latency
1153system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71343.207508 # average ReadSharedReq mshr miss latency
1154system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency
1155system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency
1156system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71585.133249 # average overall mshr miss latency
1157system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency
1158system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency
1159system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average overall mshr miss latency
1160system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70155.690850 # average overall mshr miss latency
1161system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1162system.cpu.toL2Bus.snoop_filter.tot_requests 5789744 # Total number of requests made to the snoop filter.
1163system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894372 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1164system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23770 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1165system.cpu.toL2Bus.snoop_filter.tot_snoops 30234 # Total number of snoops made to the snoop filter.
1166system.cpu.toL2Bus.snoop_filter.hit_single_snoops 30144 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1167system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1168system.cpu.toL2Bus.trans_dist::ReadResp 2373438 # Transaction distribution
1169system.cpu.toL2Bus.trans_dist::Writeback 2645111 # Transaction distribution
1170system.cpu.toL2Bus.trans_dist::CleanEvict 626124 # Transaction distribution
1171system.cpu.toL2Bus.trans_dist::HardPFReq 317103 # Transaction distribution
1172system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution
1173system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution
1174system.cpu.toL2Bus.trans_dist::ReadExReq 521946 # Transaction distribution
1175system.cpu.toL2Bus.trans_dist::ReadExResp 521946 # Transaction distribution
1176system.cpu.toL2Bus.trans_dist::ReadCleanReq 73997 # Transaction distribution
1177system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299442 # Transaction distribution
1178system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220575 # Packet count per connected master and slave (bytes)
1179system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440808 # Packet count per connected master and slave (bytes)
1180system.cpu.toL2Bus.pkt_count::total 8661383 # Packet count per connected master and slave (bytes)
1181system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733952 # Cumulative packet size per connected master and slave (bytes)
1182system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331153152 # Cumulative packet size per connected master and slave (bytes)
1183system.cpu.toL2Bus.pkt_size::total 335887104 # Cumulative packet size per connected master and slave (bytes)
1184system.cpu.toL2Bus.snoops 717772 # Total snoops (count)
1185system.cpu.toL2Bus.snoop_fanout::samples 6507488 # Request fanout histogram
1186system.cpu.toL2Bus.snoop_fanout::mean 0.011967 # Request fanout histogram
1187system.cpu.toL2Bus.snoop_fanout::stdev 0.108866 # Request fanout histogram
1188system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1189system.cpu.toL2Bus.snoop_fanout::0 6429701 98.80% 98.80% # Request fanout histogram
1190system.cpu.toL2Bus.snoop_fanout::1 77697 1.19% 100.00% # Request fanout histogram
1191system.cpu.toL2Bus.snoop_fanout::2 90 0.00% 100.00% # Request fanout histogram
1192system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1193system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1194system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1195system.cpu.toL2Bus.snoop_fanout::total 6507488 # Request fanout histogram
1196system.cpu.toL2Bus.reqLayer0.occupancy 5247752000 # Layer occupancy (ticks)
1197system.cpu.toL2Bus.reqLayer0.utilization 2.2 # Layer utilization (%)
1198system.cpu.toL2Bus.respLayer0.occupancy 111080826 # Layer occupancy (ticks)
1199system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1200system.cpu.toL2Bus.respLayer1.occupancy 4232108471 # Layer occupancy (ticks)
1201system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
1202system.membus.trans_dist::ReadResp 408044 # Transaction distribution
1203system.membus.trans_dist::Writeback 292231 # Transaction distribution
1204system.membus.trans_dist::CleanEvict 102781 # Transaction distribution
1205system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
1206system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
1207system.membus.trans_dist::ReadExReq 3660 # Transaction distribution
1208system.membus.trans_dist::ReadExResp 3660 # Transaction distribution
1209system.membus.trans_dist::ReadSharedReq 408044 # Transaction distribution
1210system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1218424 # Packet count per connected master and slave (bytes)
1211system.membus.pkt_count::total 1218424 # Packet count per connected master and slave (bytes)
1212system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45051840 # Cumulative packet size per connected master and slave (bytes)
1213system.membus.pkt_size::total 45051840 # Cumulative packet size per connected master and slave (bytes)
1214system.membus.snoops 0 # Total snoops (count)
1215system.membus.snoop_fanout::samples 806718 # Request fanout histogram
1216system.membus.snoop_fanout::mean 0 # Request fanout histogram
1217system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1218system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1219system.membus.snoop_fanout::0 806718 100.00% 100.00% # Request fanout histogram
1220system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1221system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1222system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1223system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1224system.membus.snoop_fanout::total 806718 # Request fanout histogram
1225system.membus.reqLayer0.occupancy 2171550377 # Layer occupancy (ticks)
1226system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
1227system.membus.respLayer1.occupancy 2176359308 # Layer occupancy (ticks)
1228system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
1229
1230---------- End Simulation Statistics ----------