| config.ini (8835:7c68f84d7c4e) | config.ini (8893:e29c604a2582) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 12 unchanged lines hidden (view full) --- 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 12 unchanged lines hidden (view full) --- 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 |
| 29system_port=system.membus.port[0] | 29system_port=system.membus.slave[0] |
| 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 --- 84 unchanged lines hidden (view full) --- 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache | 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 --- 84 unchanged lines hidden (view full) --- 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache |
| 130addr_range=0:18446744073709551615 | 130addr_ranges=0:18446744073709551615 |
| 131assoc=2 132block_size=64 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=10 --- 4 unchanged lines hidden (view full) --- 143size=262144 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu.dcache_port | 131assoc=2 132block_size=64 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=10 --- 4 unchanged lines hidden (view full) --- 143size=262144 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu.dcache_port |
| 151mem_side=system.cpu.toL2Bus.port[1] | 151mem_side=system.cpu.toL2Bus.slave[1] |
| 152 153[system.cpu.dtb] 154type=ArmTLB 155children=walker 156size=64 157walker=system.cpu.dtb.walker 158 159[system.cpu.dtb.walker] 160type=ArmTableWalker 161max_backoff=100000 162min_backoff=0 163sys=system | 152 153[system.cpu.dtb] 154type=ArmTLB 155children=walker 156size=64 157walker=system.cpu.dtb.walker 158 159[system.cpu.dtb.walker] 160type=ArmTableWalker 161max_backoff=100000 162min_backoff=0 163sys=system |
| 164port=system.cpu.toL2Bus.port[3] | 164port=system.cpu.toL2Bus.slave[3] |
| 165 166[system.cpu.fuPool] 167type=FUPool 168children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 169FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 170 171[system.cpu.fuPool.FUList0] 172type=FUDesc --- 250 unchanged lines hidden (view full) --- 423[system.cpu.fuPool.FUList8.opList] 424type=OpDesc 425issueLat=3 426opClass=IprAccess 427opLat=3 428 429[system.cpu.icache] 430type=BaseCache | 165 166[system.cpu.fuPool] 167type=FUPool 168children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 169FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 170 171[system.cpu.fuPool.FUList0] 172type=FUDesc --- 250 unchanged lines hidden (view full) --- 423[system.cpu.fuPool.FUList8.opList] 424type=OpDesc 425issueLat=3 426opClass=IprAccess 427opLat=3 428 429[system.cpu.icache] 430type=BaseCache |
| 431addr_range=0:18446744073709551615 | 431addr_ranges=0:18446744073709551615 |
| 432assoc=2 433block_size=64 434forward_snoops=true 435hash_delay=1 436is_top_level=true 437latency=1000 438max_miss_count=0 439mshrs=10 --- 4 unchanged lines hidden (view full) --- 444size=131072 445subblock_size=0 446system=system 447tgts_per_mshr=20 448trace_addr=0 449two_queue=false 450write_buffers=8 451cpu_side=system.cpu.icache_port | 432assoc=2 433block_size=64 434forward_snoops=true 435hash_delay=1 436is_top_level=true 437latency=1000 438max_miss_count=0 439mshrs=10 --- 4 unchanged lines hidden (view full) --- 444size=131072 445subblock_size=0 446system=system 447tgts_per_mshr=20 448trace_addr=0 449two_queue=false 450write_buffers=8 451cpu_side=system.cpu.icache_port |
| 452mem_side=system.cpu.toL2Bus.port[0] | 452mem_side=system.cpu.toL2Bus.slave[0] |
| 453 454[system.cpu.interrupts] 455type=ArmInterrupts 456 457[system.cpu.itb] 458type=ArmTLB 459children=walker 460size=64 461walker=system.cpu.itb.walker 462 463[system.cpu.itb.walker] 464type=ArmTableWalker 465max_backoff=100000 466min_backoff=0 467sys=system | 453 454[system.cpu.interrupts] 455type=ArmInterrupts 456 457[system.cpu.itb] 458type=ArmTLB 459children=walker 460size=64 461walker=system.cpu.itb.walker 462 463[system.cpu.itb.walker] 464type=ArmTableWalker 465max_backoff=100000 466min_backoff=0 467sys=system |
| 468port=system.cpu.toL2Bus.port[2] | 468port=system.cpu.toL2Bus.slave[2] |
| 469 470[system.cpu.l2cache] 471type=BaseCache | 469 470[system.cpu.l2cache] 471type=BaseCache |
| 472addr_range=0:18446744073709551615 | 472addr_ranges=0:18446744073709551615 |
| 473assoc=2 474block_size=64 475forward_snoops=true 476hash_delay=1 477is_top_level=false 478latency=1000 479max_miss_count=0 480mshrs=10 481prefetch_on_access=false 482prefetcher=Null 483prioritizeRequests=false 484repl=Null 485size=2097152 486subblock_size=0 487system=system 488tgts_per_mshr=5 489trace_addr=0 490two_queue=false 491write_buffers=8 | 473assoc=2 474block_size=64 475forward_snoops=true 476hash_delay=1 477is_top_level=false 478latency=1000 479max_miss_count=0 480mshrs=10 481prefetch_on_access=false 482prefetcher=Null 483prioritizeRequests=false 484repl=Null 485size=2097152 486subblock_size=0 487system=system 488tgts_per_mshr=5 489trace_addr=0 490two_queue=false 491write_buffers=8 |
| 492cpu_side=system.cpu.toL2Bus.port[4] 493mem_side=system.membus.port[2] | 492cpu_side=system.cpu.toL2Bus.master[0] 493mem_side=system.membus.slave[1] |
| 494 495[system.cpu.toL2Bus] 496type=Bus 497block_size=64 498bus_id=0 499clock=1000 500header_cycles=1 501use_default_range=false 502width=64 | 494 495[system.cpu.toL2Bus] 496type=Bus 497block_size=64 498bus_id=0 499clock=1000 500header_cycles=1 501use_default_range=false 502width=64 |
| 503port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side | 503master=system.cpu.l2cache.cpu_side 504slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| 504 505[system.cpu.tracer] 506type=ExeTracer 507 508[system.cpu.workload] 509type=LiveProcess 510cmd=parser 2.1.dict -batch 511cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing --- 15 unchanged lines hidden (view full) --- 527[system.membus] 528type=Bus 529block_size=64 530bus_id=0 531clock=1000 532header_cycles=1 533use_default_range=false 534width=64 | 505 506[system.cpu.tracer] 507type=ExeTracer 508 509[system.cpu.workload] 510type=LiveProcess 511cmd=parser 2.1.dict -batch 512cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing --- 15 unchanged lines hidden (view full) --- 528[system.membus] 529type=Bus 530block_size=64 531bus_id=0 532clock=1000 533header_cycles=1 534use_default_range=false 535width=64 |
| 535port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side | 536master=system.physmem.port[0] 537slave=system.system_port system.cpu.l2cache.mem_side |
| 536 537[system.physmem] 538type=PhysicalMemory 539file= 540latency=30000 541latency_var=0 542null=false 543range=0:134217727 544zero=false | 538 539[system.physmem] 540type=PhysicalMemory 541file= 542latency=30000 543latency_var=0 544null=false 545range=0:134217727 546zero=false |
| 545port=system.membus.port[1] | 547port=system.membus.master[0] |
| 546 | 548 |