| config.ini (10636:9ac724889705) | config.ini (10798:74e3c7359393) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem |
| 26mmap_using_noreserve=false |
|
| 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 --- 96 unchanged lines hidden (view full) --- 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] | 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 --- 96 unchanged lines hidden (view full) --- 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.branchPred] |
| 138type=BranchPredictor | 139type=BiModeBP |
| 139BTBEntries=2048 140BTBTagSize=18 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 | 140BTBEntries=2048 141BTBTagSize=18 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 |
| 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 | |
| 151numThreads=1 | 149numThreads=1 |
| 152predType=bi-mode | |
| 153 154[system.cpu.dcache] 155type=BaseCache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=2 159clk_domain=system.cpu_clk_domain 160demand_mshr_reserve=1 --- 26 unchanged lines hidden (view full) --- 187sequential_access=false 188size=32768 189 190[system.cpu.dstage2_mmu] 191type=ArmStage2MMU 192children=stage2_tlb 193eventq_index=0 194stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb | 150 151[system.cpu.dcache] 152type=BaseCache 153children=tags 154addr_ranges=0:18446744073709551615 155assoc=2 156clk_domain=system.cpu_clk_domain 157demand_mshr_reserve=1 --- 26 unchanged lines hidden (view full) --- 184sequential_access=false 185size=32768 186 187[system.cpu.dstage2_mmu] 188type=ArmStage2MMU 189children=stage2_tlb 190eventq_index=0 191stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb |
| 192sys=system |
|
| 195tlb=system.cpu.dtb 196 197[system.cpu.dstage2_mmu.stage2_tlb] 198type=ArmTLB 199children=walker 200eventq_index=0 201is_stage2=true 202size=32 203walker=system.cpu.dstage2_mmu.stage2_tlb.walker 204 205[system.cpu.dstage2_mmu.stage2_tlb.walker] 206type=ArmTableWalker 207clk_domain=system.cpu_clk_domain 208eventq_index=0 209is_stage2=true 210num_squash_per_cycle=2 211sys=system | 193tlb=system.cpu.dtb 194 195[system.cpu.dstage2_mmu.stage2_tlb] 196type=ArmTLB 197children=walker 198eventq_index=0 199is_stage2=true 200size=32 201walker=system.cpu.dstage2_mmu.stage2_tlb.walker 202 203[system.cpu.dstage2_mmu.stage2_tlb.walker] 204type=ArmTableWalker 205clk_domain=system.cpu_clk_domain 206eventq_index=0 207is_stage2=true 208num_squash_per_cycle=2 209sys=system |
| 212port=system.cpu.toL2Bus.slave[5] | |
| 213 214[system.cpu.dtb] 215type=ArmTLB 216children=walker 217eventq_index=0 218is_stage2=false 219size=64 220walker=system.cpu.dtb.walker --- 275 unchanged lines hidden (view full) --- 496[system.cpu.icache] 497type=BaseCache 498children=tags 499addr_ranges=0:18446744073709551615 500assoc=2 501clk_domain=system.cpu_clk_domain 502demand_mshr_reserve=1 503eventq_index=0 | 210 211[system.cpu.dtb] 212type=ArmTLB 213children=walker 214eventq_index=0 215is_stage2=false 216size=64 217walker=system.cpu.dtb.walker --- 275 unchanged lines hidden (view full) --- 493[system.cpu.icache] 494type=BaseCache 495children=tags 496addr_ranges=0:18446744073709551615 497assoc=2 498clk_domain=system.cpu_clk_domain 499demand_mshr_reserve=1 500eventq_index=0 |
| 504forward_snoops=true | 501forward_snoops=false |
| 505hit_latency=1 506is_top_level=true 507max_miss_count=0 508mshrs=2 509prefetch_on_access=false 510prefetcher=Null 511response_latency=1 512sequential_access=false --- 50 unchanged lines hidden (view full) --- 563pmu=Null 564system=system 565 566[system.cpu.istage2_mmu] 567type=ArmStage2MMU 568children=stage2_tlb 569eventq_index=0 570stage2_tlb=system.cpu.istage2_mmu.stage2_tlb | 502hit_latency=1 503is_top_level=true 504max_miss_count=0 505mshrs=2 506prefetch_on_access=false 507prefetcher=Null 508response_latency=1 509sequential_access=false --- 50 unchanged lines hidden (view full) --- 560pmu=Null 561system=system 562 563[system.cpu.istage2_mmu] 564type=ArmStage2MMU 565children=stage2_tlb 566eventq_index=0 567stage2_tlb=system.cpu.istage2_mmu.stage2_tlb |
| 568sys=system |
|
| 571tlb=system.cpu.itb 572 573[system.cpu.istage2_mmu.stage2_tlb] 574type=ArmTLB 575children=walker 576eventq_index=0 577is_stage2=true 578size=32 579walker=system.cpu.istage2_mmu.stage2_tlb.walker 580 581[system.cpu.istage2_mmu.stage2_tlb.walker] 582type=ArmTableWalker 583clk_domain=system.cpu_clk_domain 584eventq_index=0 585is_stage2=true 586num_squash_per_cycle=2 587sys=system | 569tlb=system.cpu.itb 570 571[system.cpu.istage2_mmu.stage2_tlb] 572type=ArmTLB 573children=walker 574eventq_index=0 575is_stage2=true 576size=32 577walker=system.cpu.istage2_mmu.stage2_tlb.walker 578 579[system.cpu.istage2_mmu.stage2_tlb.walker] 580type=ArmTableWalker 581clk_domain=system.cpu_clk_domain 582eventq_index=0 583is_stage2=true 584num_squash_per_cycle=2 585sys=system |
| 588port=system.cpu.toL2Bus.slave[4] | |
| 589 590[system.cpu.itb] 591type=ArmTLB 592children=walker 593eventq_index=0 594is_stage2=false 595size=64 596walker=system.cpu.itb.walker --- 67 unchanged lines hidden (view full) --- 664hit_latency=12 665sequential_access=false 666size=1048576 667 668[system.cpu.toL2Bus] 669type=CoherentXBar 670clk_domain=system.cpu_clk_domain 671eventq_index=0 | 586 587[system.cpu.itb] 588type=ArmTLB 589children=walker 590eventq_index=0 591is_stage2=false 592size=64 593walker=system.cpu.itb.walker --- 67 unchanged lines hidden (view full) --- 661hit_latency=12 662sequential_access=false 663size=1048576 664 665[system.cpu.toL2Bus] 666type=CoherentXBar 667clk_domain=system.cpu_clk_domain 668eventq_index=0 |
| 672header_cycles=1 | 669forward_latency=0 670frontend_latency=1 671response_latency=1 |
| 673snoop_filter=Null | 672snoop_filter=Null |
| 673snoop_response_latency=1 |
|
| 674system=system 675use_default_range=false 676width=32 677master=system.cpu.l2cache.cpu_side | 674system=system 675use_default_range=false 676width=32 677master=system.cpu.l2cache.cpu_side |
| 678slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port | 678slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| 679 680[system.cpu.tracer] 681type=ExeTracer 682eventq_index=0 683 684[system.cpu.workload] 685type=LiveProcess 686cmd=parser 2.1.dict -batch 687cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing 688drivers= 689egid=100 690env= 691errout=cerr 692euid=100 693eventq_index=0 | 679 680[system.cpu.tracer] 681type=ExeTracer 682eventq_index=0 683 684[system.cpu.workload] 685type=LiveProcess 686cmd=parser 2.1.dict -batch 687cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing 688drivers= 689egid=100 690env= 691errout=cerr 692euid=100 693eventq_index=0 |
| 694executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser | 694executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser |
| 695gid=100 | 695gid=100 |
| 696input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in | 696input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in |
| 697kvmInSE=false 698max_stack_size=67108864 699output=cout 700pid=100 701ppid=99 702simpoint=114600000000 703system=system 704uid=100 --- 14 unchanged lines hidden (view full) --- 719eventq_index=0 720sys_clk_domain=system.clk_domain 721transition_latency=100000000 722 723[system.membus] 724type=CoherentXBar 725clk_domain=system.clk_domain 726eventq_index=0 | 697kvmInSE=false 698max_stack_size=67108864 699output=cout 700pid=100 701ppid=99 702simpoint=114600000000 703system=system 704uid=100 --- 14 unchanged lines hidden (view full) --- 719eventq_index=0 720sys_clk_domain=system.clk_domain 721transition_latency=100000000 722 723[system.membus] 724type=CoherentXBar 725clk_domain=system.clk_domain 726eventq_index=0 |
| 727header_cycles=1 | 727forward_latency=4 728frontend_latency=3 729response_latency=2 |
| 728snoop_filter=Null | 730snoop_filter=Null |
| 731snoop_response_latency=4 |
|
| 729system=system 730use_default_range=false | 732system=system 733use_default_range=false |
| 731width=8 | 734width=16 |
| 732master=system.physmem.port 733slave=system.system_port system.cpu.l2cache.mem_side 734 735[system.physmem] 736type=DRAMCtrl 737IDD0=0.075000 738IDD02=0.000000 739IDD2N=0.050000 --- 14 unchanged lines hidden (view full) --- 754IDD4W2=0.000000 755IDD5=0.220000 756IDD52=0.000000 757IDD6=0.000000 758IDD62=0.000000 759VDD=1.500000 760VDD2=0.000000 761activation_limit=4 | 735master=system.physmem.port 736slave=system.system_port system.cpu.l2cache.mem_side 737 738[system.physmem] 739type=DRAMCtrl 740IDD0=0.075000 741IDD02=0.000000 742IDD2N=0.050000 --- 14 unchanged lines hidden (view full) --- 757IDD4W2=0.000000 758IDD5=0.220000 759IDD52=0.000000 760IDD6=0.000000 761IDD62=0.000000 762VDD=1.500000 763VDD2=0.000000 764activation_limit=4 |
| 762addr_mapping=RoRaBaChCo | 765addr_mapping=RoRaBaCoCh |
| 763bank_groups_per_rank=0 764banks_per_rank=8 765burst_length=8 766channels=1 767clk_domain=system.clk_domain 768conf_table_reported=true 769device_bus_width=8 770device_rowbuffer_size=1024 --- 46 unchanged lines hidden --- | 766bank_groups_per_rank=0 767banks_per_rank=8 768burst_length=8 769channels=1 770clk_domain=system.clk_domain 771conf_table_reported=true 772device_bus_width=8 773device_rowbuffer_size=1024 --- 46 unchanged lines hidden --- |