1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 104 unchanged lines hidden (view full) --- 113smtFetchPolicy=SingleThread 114smtIQPolicy=Partitioned 115smtIQThreshold=100 116smtLSQPolicy=Partitioned 117smtLSQThreshold=100 118smtNumFetchingThreads=1 119smtROBPolicy=Partitioned 120smtROBThreshold=100 |
121socket_id=0 |
122squashWidth=8 123store_set_clear_period=250000 124switched_out=false 125system=system 126tracer=system.cpu.tracer 127trapLatency=13 128wbDepth=1 129wbWidth=8 --- 564 unchanged lines hidden (view full) --- 694type=LiveProcess 695cmd=parser 2.1.dict -batch 696cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing 697egid=100 698env= 699errout=cerr 700euid=100 701eventq_index=0 |
702executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser |
703gid=100 |
704input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in |
705max_stack_size=67108864 706output=cout 707pid=100 708ppid=99 709simpoint=114600000000 710system=system 711uid=100 712 --- 10 unchanged lines hidden (view full) --- 723header_cycles=1 724system=system 725use_default_range=false 726width=8 727master=system.physmem.port 728slave=system.system_port system.cpu.l2cache.mem_side 729 730[system.physmem] |
731type=DRAMCtrl |
732activation_limit=4 |
733addr_mapping=RoRaBaChCo |
734banks_per_rank=8 735burst_length=8 736channels=1 737clk_domain=system.clk_domain 738conf_table_reported=true 739device_bus_width=8 740device_rowbuffer_size=1024 741devices_per_rank=8 742eventq_index=0 743in_addr_map=true |
744max_accesses_per_row=16 |
745mem_sched_policy=frfcfs |
746min_writes_per_switch=16 |
747null=false |
748page_policy=open_adaptive |
749range=0:134217727 750ranks_per_channel=2 751read_buffer_size=32 752static_backend_latency=10000 753static_frontend_latency=10000 754tBURST=5000 |
755tCK=1250 |
756tCL=13750 757tRAS=35000 758tRCD=13750 759tREFI=7800000 |
760tRFC=260000 |
761tRP=13750 |
762tRRD=6000 763tRTP=7500 764tRTW=2500 765tWR=15000 |
766tWTR=7500 |
767tXAW=30000 768write_buffer_size=64 769write_high_thresh_perc=85 770write_low_thresh_perc=50 |
771port=system.membus.master[0] 772 773[system.voltage_domain] 774type=VoltageDomain 775eventq_index=0 776voltage=1.000000 777 |