13c13
< clock=1
---
> clock=1000
33c33
< children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
---
> children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
80a81
> isa=system.cpu.isa
132c133
< clock=1
---
> clock=500
135c136
< hit_latency=1000
---
> hit_latency=2
138c139
< mshrs=10
---
> mshrs=4
143c144
< response_latency=1000
---
> response_latency=2
162c163
< clock=1
---
> clock=500
435c436
< clock=1
---
> clock=500
438c439
< hit_latency=1000
---
> hit_latency=2
441c442
< mshrs=10
---
> mshrs=4
446c447
< response_latency=1000
---
> response_latency=2
459a461,477
> [system.cpu.isa]
> type=ArmISA
> fpsid=1090793632
> id_isar0=34607377
> id_isar1=34677009
> id_isar2=555950401
> id_isar3=17899825
> id_isar4=268501314
> id_isar5=0
> id_mmfr0=3
> id_mmfr1=0
> id_mmfr2=19070976
> id_mmfr3=4027589137
> id_pfr0=49
> id_pfr1=1
> midr=890224640
>
468c486
< clock=1
---
> clock=500
476c494
< assoc=2
---
> assoc=8
478c496
< clock=1
---
> clock=500
481c499
< hit_latency=1000
---
> hit_latency=20
484c502
< mshrs=10
---
> mshrs=20
489c507
< response_latency=1000
---
> response_latency=20
493c511
< tgts_per_mshr=5
---
> tgts_per_mshr=12
503c521
< clock=1000
---
> clock=500
506c524
< width=8
---
> width=32
543,545c561,564
< type=SimpleMemory
< bandwidth=73.000000
< clock=1
---
> type=SimpleDRAM
> addr_mapping=openmap
> banks_per_rank=8
> clock=1000
548,549c567,568
< latency=30000
< latency_var=0
---
> lines_per_rowbuffer=64
> mem_sched_policy=fcfs
550a570
> page_policy=open
551a572,582
> ranks_per_channel=2
> read_buffer_size=32
> tBURST=4000
> tCL=14000
> tRCD=14000
> tREFI=7800000
> tRFC=300000
> tRP=14000
> tWTR=1000
> write_buffer_size=32
> write_thresh_perc=70