1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 158 unchanged lines hidden (view full) ---

167indirectWays=2
168instShiftAmt=2
169numThreads=1
170useIndirect=true
171
172[system.cpu.dcache]
173type=Cache
174children=tags
175addr_ranges=0:18446744073709551615:0:0:0:0
176assoc=2
177clk_domain=system.cpu_clk_domain
178clusivity=mostly_incl
179default_p_state=UNDEFINED
180demand_mshr_reserve=1
181eventq_index=0
182hit_latency=2
183is_read_only=false

--- 345 unchanged lines hidden (view full) ---

529eventq_index=0
530opClass=FloatMult
531opLat=4
532pipelined=true
533
534[system.cpu.icache]
535type=Cache
536children=tags
537addr_ranges=0:18446744073709551615:0:0:0:0
538assoc=2
539clk_domain=system.cpu_clk_domain
540clusivity=mostly_incl
541default_p_state=UNDEFINED
542demand_mshr_reserve=1
543eventq_index=0
544hit_latency=1
545is_read_only=true

--- 115 unchanged lines hidden (view full) ---

661p_state_clk_gate_min=1000
662power_model=Null
663sys=system
664port=system.cpu.toL2Bus.slave[2]
665
666[system.cpu.l2cache]
667type=Cache
668children=prefetcher tags
669addr_ranges=0:18446744073709551615:0:0:0:0
670assoc=16
671clk_domain=system.cpu_clk_domain
672clusivity=mostly_excl
673default_p_state=UNDEFINED
674demand_mshr_reserve=1
675eventq_index=0
676hit_latency=12
677is_read_only=false

--- 130 unchanged lines hidden (view full) ---

808domains=
809enable=false
810eventq_index=0
811sys_clk_domain=system.clk_domain
812transition_latency=100000000
813
814[system.membus]
815type=CoherentXBar
816children=snoop_filter
817clk_domain=system.clk_domain
818default_p_state=UNDEFINED
819eventq_index=0
820forward_latency=4
821frontend_latency=3
822p_state_clk_gate_bins=20
823p_state_clk_gate_max=1000000000000
824p_state_clk_gate_min=1000
825point_of_coherency=true
826power_model=Null
827response_latency=2
828snoop_filter=system.membus.snoop_filter
829snoop_response_latency=4
830system=system
831use_default_range=false
832width=16
833master=system.physmem.port
834slave=system.system_port system.cpu.l2cache.mem_side
835
836[system.membus.snoop_filter]
837type=SnoopFilter
838eventq_index=0
839lookup_latency=1
840max_capacity=8388608
841system=system
842
843[system.physmem]
844type=DRAMCtrl
845IDD0=0.055000
846IDD02=0.000000
847IDD2N=0.032000
848IDD2N2=0.000000
849IDD2P0=0.000000
850IDD2P02=0.000000
851IDD2P1=0.032000
852IDD2P12=0.000000
853IDD3N=0.038000
854IDD3N2=0.000000
855IDD3P0=0.000000
856IDD3P02=0.000000
857IDD3P1=0.038000
858IDD3P12=0.000000
859IDD4R=0.157000
860IDD4R2=0.000000
861IDD4W=0.125000
862IDD4W2=0.000000
863IDD5=0.235000
864IDD52=0.000000
865IDD6=0.020000
866IDD62=0.000000
867VDD=1.500000
868VDD2=0.000000
869activation_limit=4
870addr_mapping=RoRaBaCoCh
871bank_groups_per_rank=0
872banks_per_rank=8
873burst_length=8
874channels=1
875clk_domain=system.clk_domain
876conf_table_reported=true
877default_p_state=UNDEFINED
878device_bus_width=8
879device_rowbuffer_size=1024
880device_size=536870912
881devices_per_rank=8
882dll=true
883eventq_index=0
884in_addr_map=true
885kvm_map=true
886max_accesses_per_row=16
887mem_sched_policy=frfcfs
888min_writes_per_switch=16
889null=false
890p_state_clk_gate_bins=20
891p_state_clk_gate_max=1000000000000
892p_state_clk_gate_min=1000
893page_policy=open_adaptive
894power_model=Null
895range=0:134217727:0:0:0:0
896ranks_per_channel=2
897read_buffer_size=32
898static_backend_latency=10000
899static_frontend_latency=10000
900tBURST=5000
901tCCD_L=0
902tCK=1250
903tCL=13750

--- 5 unchanged lines hidden (view full) ---

909tRP=13750
910tRRD=6000
911tRRD_L=0
912tRTP=7500
913tRTW=2500
914tWR=15000
915tWTR=7500
916tXAW=30000
917tXP=6000
918tXPDLL=0
919tXS=270000
920tXSDLL=0
921write_buffer_size=64
922write_high_thresh_perc=85
923write_low_thresh_perc=50
924port=system.membus.master[0]
925
926[system.voltage_domain]
927type=VoltageDomain
928eventq_index=0
929voltage=1.000000
930