| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.366632 # Number of seconds simulated 4sim_ticks 366631719500 # Number of ticks simulated 5final_tick 366631719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.368600 # Number of seconds simulated 4sim_ticks 368600034500 # Number of ticks simulated 5final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 211005 # Simulator instruction rate (inst/s) 8host_op_rate 228546 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 152712719 # Simulator tick rate (ticks/s) 10host_mem_usage 277288 # Number of bytes of host memory used 11host_seconds 2400.79 # Real time elapsed on the host | 7host_inst_rate 189198 # Simulator instruction rate (inst/s) 8host_op_rate 204927 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 137665575 # Simulator tick rate (ticks/s) 10host_mem_usage 274600 # Number of bytes of host memory used 11host_seconds 2677.50 # Real time elapsed on the host |
| 12sim_insts 506579366 # Number of instructions simulated 13sim_ops 548692589 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 506579366 # Number of instructions simulated 13sim_ops 548692589 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory |
| 29system.physmem.bw_read::cpu.inst 490519 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 24693379 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 25183898 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 490519 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 490519 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 17024692 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 17024692 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 17024692 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 490519 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 24693379 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 42208590 # Total bandwidth to/from this memory (bytes/s) | 29system.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 24561517 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 25049417 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 24561517 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 41983197 # Total bandwidth to/from this memory (bytes/s) |
| 40system.physmem.readReqs 144269 # Number of read requests accepted 41system.physmem.writeReqs 97528 # Number of write requests accepted 42system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue | 40system.physmem.readReqs 144269 # Number of read requests accepted 41system.physmem.writeReqs 97528 # Number of write requests accepted 42system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue |
| 44system.physmem.bytesReadDRAM 9226688 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue 46system.physmem.bytesWritten 6240064 # Total number of bytes written to DRAM | 44system.physmem.bytesReadDRAM 9225856 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue 46system.physmem.bytesWritten 6240448 # Total number of bytes written to DRAM |
| 47system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side | 47system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side |
| 49system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue | 49system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue |
| 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 52system.physmem.perBankRdBursts::0 9376 # Per bank write bursts | 52system.physmem.perBankRdBursts::0 9372 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::1 8929 # Per bank write bursts | 53system.physmem.perBankRdBursts::1 8929 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::2 8964 # Per bank write bursts 55system.physmem.perBankRdBursts::3 8666 # Per bank write bursts 56system.physmem.perBankRdBursts::4 9423 # Per bank write bursts 57system.physmem.perBankRdBursts::5 9371 # Per bank write bursts | 54system.physmem.perBankRdBursts::2 8963 # Per bank write bursts 55system.physmem.perBankRdBursts::3 8667 # Per bank write bursts 56system.physmem.perBankRdBursts::4 9424 # Per bank write bursts 57system.physmem.perBankRdBursts::5 9372 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::6 8974 # Per bank write bursts | 58system.physmem.perBankRdBursts::6 8974 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::7 8126 # Per bank write bursts 60system.physmem.perBankRdBursts::8 8634 # Per bank write bursts | 59system.physmem.perBankRdBursts::7 8127 # Per bank write bursts 60system.physmem.perBankRdBursts::8 8635 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::9 8697 # Per bank write bursts | 61system.physmem.perBankRdBursts::9 8697 # Per bank write bursts |
| 62system.physmem.perBankRdBursts::10 8760 # Per bank write bursts 63system.physmem.perBankRdBursts::11 9487 # Per bank write bursts 64system.physmem.perBankRdBursts::12 9347 # Per bank write bursts 65system.physmem.perBankRdBursts::13 9550 # Per bank write bursts 66system.physmem.perBankRdBursts::14 8728 # Per bank write bursts 67system.physmem.perBankRdBursts::15 9135 # Per bank write bursts 68system.physmem.perBankWrBursts::0 6252 # Per bank write bursts | 62system.physmem.perBankRdBursts::10 8761 # Per bank write bursts 63system.physmem.perBankRdBursts::11 9485 # Per bank write bursts 64system.physmem.perBankRdBursts::12 9346 # Per bank write bursts 65system.physmem.perBankRdBursts::13 9545 # Per bank write bursts 66system.physmem.perBankRdBursts::14 8729 # Per bank write bursts 67system.physmem.perBankRdBursts::15 9128 # Per bank write bursts 68system.physmem.perBankWrBursts::0 6253 # Per bank write bursts |
| 69system.physmem.perBankWrBursts::1 6118 # Per bank write bursts 70system.physmem.perBankWrBursts::2 6042 # Per bank write bursts 71system.physmem.perBankWrBursts::3 5901 # Per bank write bursts 72system.physmem.perBankWrBursts::4 6273 # Per bank write bursts 73system.physmem.perBankWrBursts::5 6263 # Per bank write bursts 74system.physmem.perBankWrBursts::6 6069 # Per bank write bursts | 69system.physmem.perBankWrBursts::1 6118 # Per bank write bursts 70system.physmem.perBankWrBursts::2 6042 # Per bank write bursts 71system.physmem.perBankWrBursts::3 5901 # Per bank write bursts 72system.physmem.perBankWrBursts::4 6273 # Per bank write bursts 73system.physmem.perBankWrBursts::5 6263 # Per bank write bursts 74system.physmem.perBankWrBursts::6 6069 # Per bank write bursts |
| 75system.physmem.perBankWrBursts::7 5534 # Per bank write bursts 76system.physmem.perBankWrBursts::8 5815 # Per bank write bursts | 75system.physmem.perBankWrBursts::7 5535 # Per bank write bursts 76system.physmem.perBankWrBursts::8 5819 # Per bank write bursts |
| 77system.physmem.perBankWrBursts::9 5920 # Per bank write bursts 78system.physmem.perBankWrBursts::10 5985 # Per bank write bursts 79system.physmem.perBankWrBursts::11 6510 # Per bank write bursts 80system.physmem.perBankWrBursts::12 6360 # Per bank write bursts 81system.physmem.perBankWrBursts::13 6344 # Per bank write bursts 82system.physmem.perBankWrBursts::14 6013 # Per bank write bursts 83system.physmem.perBankWrBursts::15 6102 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 77system.physmem.perBankWrBursts::9 5920 # Per bank write bursts 78system.physmem.perBankWrBursts::10 5985 # Per bank write bursts 79system.physmem.perBankWrBursts::11 6510 # Per bank write bursts 80system.physmem.perBankWrBursts::12 6360 # Per bank write bursts 81system.physmem.perBankWrBursts::13 6344 # Per bank write bursts 82system.physmem.perBankWrBursts::14 6013 # Per bank write bursts 83system.physmem.perBankWrBursts::15 6102 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 86system.physmem.totGap 366631694000 # Total gap between requests | 86system.physmem.totGap 368600009000 # Total gap between requests |
| 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 144269 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 97528 # Write request sizes (log2) | 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 144269 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 97528 # Write request sizes (log2) |
| 101system.physmem.rdQLenPdf::0 143840 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 311 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::0 143801 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 333 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::15 2842 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 2979 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 5670 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 5725 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 5731 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 5730 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 5730 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 5734 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 5731 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 5736 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 5741 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 5739 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 5754 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 5737 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 5732 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 5729 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 5727 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::15 2730 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 5701 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 5739 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 5742 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 5743 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 5741 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 5741 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 5741 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 5744 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 5746 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 5749 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 5745 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 5752 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 5747 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 5741 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see |
| 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see --- 7 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see --- 7 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 197system.physmem.bytesPerActivate::samples 63306 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 244.314283 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 163.017060 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 244.594379 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 22538 35.60% 35.60% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 17961 28.37% 63.97% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 7327 11.57% 75.55% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 7996 12.63% 88.18% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 2051 3.24% 91.42% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 1180 1.86% 93.28% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 835 1.32% 94.60% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 660 1.04% 95.64% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 2758 4.36% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 63306 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 5727 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 25.172342 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 18.597400 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 376.088417 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 5724 99.95% 99.95% # Reads before turning the bus around for writes | 197system.physmem.bytesPerActivate::samples 63970 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 241.763327 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 162.115864 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 241.210402 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 22774 35.60% 35.60% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 18302 28.61% 64.21% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 7461 11.66% 75.87% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 8049 12.58% 88.46% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 2117 3.31% 91.77% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 1180 1.84% 93.61% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 776 1.21% 94.82% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 623 0.97% 95.80% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 2688 4.20% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 63970 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 5740 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 25.113240 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 375.658190 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 5737 99.95% 99.95% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes | 215system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::total 5727 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 5727 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 17.024795 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.995243 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 1.004050 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 2743 47.90% 47.90% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 142 2.48% 50.38% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 2814 49.14% 99.51% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 20 0.35% 99.86% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 6 0.10% 99.97% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::total 5727 # Writes before turning the bus around for reads 231system.physmem.totQLat 1581653750 # Total ticks spent queuing 232system.physmem.totMemAccLat 4284785000 # Total ticks spent from burst creation until serviced by the DRAM 233system.physmem.totBusLat 720835000 # Total ticks spent in databus transfers 234system.physmem.avgQLat 10970.98 # Average queueing delay per DRAM burst | 217system.physmem.rdPerTurnAround::total 5740 # Reads before turning the bus around for writes 218system.physmem.wrPerTurnAround::samples 5740 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::mean 16.987282 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::gmean 16.957535 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::stdev 1.009458 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::16 2852 49.69% 49.69% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::17 159 2.77% 52.46% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 2701 47.06% 99.51% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::19 19 0.33% 99.84% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::20 6 0.10% 99.95% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads 231system.physmem.totQLat 3577413000 # Total ticks spent queuing 232system.physmem.totMemAccLat 6280300500 # Total ticks spent from burst creation until serviced by the DRAM 233system.physmem.totBusLat 720770000 # Total ticks spent in databus transfers 234system.physmem.avgQLat 24816.61 # Average queueing delay per DRAM burst |
| 235system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 235system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 236system.physmem.avgMemAccLat 29720.98 # Average memory access latency per DRAM burst 237system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s 238system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s 239system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s 240system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s | 236system.physmem.avgMemAccLat 43566.61 # Average memory access latency per DRAM burst 237system.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s 238system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s 239system.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s 240system.physmem.avgWrBWSys 16.93 # Average system write bandwidth in MiByte/s |
| 241system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 242system.physmem.busUtil 0.33 # Data bus utilization in percentage 243system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 244system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 245system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing | 241system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 242system.physmem.busUtil 0.33 # Data bus utilization in percentage 243system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 244system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 245system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| 246system.physmem.avgWrQLen 20.20 # Average write queue length when enqueuing 247system.physmem.readRowHits 110439 # Number of row buffer hits during reads 248system.physmem.writeRowHits 67921 # Number of row buffer hits during writes 249system.physmem.readRowHitRate 76.60 # Row buffer hit rate for reads 250system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes 251system.physmem.avgGap 1516278.92 # Average gap between requests 252system.physmem.pageHitRate 73.80 # Row buffer hit rate, read and write combined 253system.physmem_0.actEnergy 239652000 # Energy for activate commands per rank (pJ) 254system.physmem_0.preEnergy 130762500 # Energy for precharge commands per rank (pJ) 255system.physmem_0.readEnergy 560266200 # Energy for read commands per rank (pJ) 256system.physmem_0.writeEnergy 313968960 # Energy for write commands per rank (pJ) 257system.physmem_0.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) 258system.physmem_0.actBackEnergy 47282173740 # Energy for active background per rank (pJ) 259system.physmem_0.preBackEnergy 178503263250 # Energy for precharge background per rank (pJ) 260system.physmem_0.totalEnergy 250976651370 # Total energy per rank (pJ) 261system.physmem_0.averagePower 684.547573 # Core power per rank (mW) 262system.physmem_0.memoryStateTime::IDLE 296644648000 # Time in different power states 263system.physmem_0.memoryStateTime::REF 12242620000 # Time in different power states 264system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 265system.physmem_0.memoryStateTime::ACT 57744168750 # Time in different power states 266system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 267system.physmem_1.actEnergy 238941360 # Energy for activate commands per rank (pJ) 268system.physmem_1.preEnergy 130374750 # Energy for precharge commands per rank (pJ) 269system.physmem_1.readEnergy 564213000 # Energy for read commands per rank (pJ) 270system.physmem_1.writeEnergy 317837520 # Energy for write commands per rank (pJ) 271system.physmem_1.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) 272system.physmem_1.actBackEnergy 47121480765 # Energy for active background per rank (pJ) 273system.physmem_1.preBackEnergy 178644216000 # Energy for precharge background per rank (pJ) 274system.physmem_1.totalEnergy 250963628115 # Total energy per rank (pJ) 275system.physmem_1.averagePower 684.512070 # Core power per rank (mW) 276system.physmem_1.memoryStateTime::IDLE 296880094250 # Time in different power states 277system.physmem_1.memoryStateTime::REF 12242620000 # Time in different power states 278system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 279system.physmem_1.memoryStateTime::ACT 57508713250 # Time in different power states 280system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 281system.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 282system.cpu.branchPred.lookups 132103795 # Number of BP lookups 283system.cpu.branchPred.condPredicted 98193288 # Number of conditional branches predicted | 246system.physmem.avgWrQLen 20.06 # Average write queue length when enqueuing 247system.physmem.readRowHits 110541 # Number of row buffer hits during reads 248system.physmem.writeRowHits 67141 # Number of row buffer hits during writes 249system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads 250system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes 251system.physmem.avgGap 1524419.28 # Average gap between requests 252system.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined 253system.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ) 254system.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ) 255system.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ) 256system.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ) 257system.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ) 258system.physmem_0.actBackEnergy 3985238790 # Energy for active background per rank (pJ) 259system.physmem_0.preBackEnergy 353652480 # Energy for precharge background per rank (pJ) 260system.physmem_0.actPowerDownEnergy 24742370760 # Energy for active power-down per rank (pJ) 261system.physmem_0.prePowerDownEnergy 8329193280 # Energy for precharge power-down per rank (pJ) 262system.physmem_0.selfRefreshEnergy 68838779610 # Energy for self refresh per rank (pJ) 263system.physmem_0.totalEnergy 115080424995 # Total energy per rank (pJ) 264system.physmem_0.averagePower 312.209476 # Core power per rank (mW) 265system.physmem_0.totalIdleTime 358934915250 # Total Idle time Per DRAM Rank 266system.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states 267system.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states 268system.physmem_0.memoryStateTime::SREF 282985145000 # Time in different power states 269system.physmem_0.memoryStateTime::PRE_PDN 21690770000 # Time in different power states 270system.physmem_0.memoryStateTime::ACT 5858999750 # Time in different power states 271system.physmem_0.memoryStateTime::ACT_PDN 54259446500 # Time in different power states 272system.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ) 273system.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ) 274system.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ) 275system.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ) 276system.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ) 277system.physmem_1.actBackEnergy 3990658350 # Energy for active background per rank (pJ) 278system.physmem_1.preBackEnergy 342745440 # Energy for precharge background per rank (pJ) 279system.physmem_1.actPowerDownEnergy 24389253480 # Energy for active power-down per rank (pJ) 280system.physmem_1.prePowerDownEnergy 8128930080 # Energy for precharge power-down per rank (pJ) 281system.physmem_1.selfRefreshEnergy 69135041760 # Energy for self refresh per rank (pJ) 282system.physmem_1.totalEnergy 114698280525 # Total energy per rank (pJ) 283system.physmem_1.averagePower 311.172732 # Core power per rank (mW) 284system.physmem_1.totalIdleTime 358951286500 # Total Idle time Per DRAM Rank 285system.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states 286system.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states 287system.physmem_1.memoryStateTime::SREF 284296674500 # Time in different power states 288system.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states 289system.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states 290system.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states 291system.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 292system.cpu.branchPred.lookups 132103819 # Number of BP lookups 293system.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted |
| 284system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect | 294system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect |
| 285system.cpu.branchPred.BTBLookups 68601542 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 60590460 # Number of BTB hits | 295system.cpu.branchPred.BTBLookups 68601561 # Number of BTB lookups 296system.cpu.branchPred.BTBHits 60590477 # Number of BTB hits |
| 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 297system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 288system.cpu.branchPred.BTBHitPct 88.322300 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target. | 298system.cpu.branchPred.BTBHitPct 88.322301 # BTB Hit Percentage 299system.cpu.branchPred.usedRAS 10017121 # Number of times the RAS was used to get a target. |
| 290system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. | 300system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. |
| 291system.cpu.branchPred.indirectLookups 3891574 # Number of indirect predictor lookups. 292system.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits. | 301system.cpu.branchPred.indirectLookups 3891575 # Number of indirect predictor lookups. 302system.cpu.branchPred.indirectHits 3883028 # Number of indirect target hits. |
| 293system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. 294system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. 295system.cpu_clk_domain.clock 500 # Clock period in ticks | 303system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. 304system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. 305system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 296system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states | 306system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states |
| 297system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 318system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 319system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 320system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 321system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 322system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 323system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 324system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 325system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 307system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 328system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 329system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 330system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 331system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 332system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 333system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 334system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 335system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 326system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states | 336system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states |
| 327system.cpu.dtb.walker.walks 0 # Table walker walks requested 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 348system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 349system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 350system.cpu.dtb.read_accesses 0 # DTB read accesses 351system.cpu.dtb.write_accesses 0 # DTB write accesses 352system.cpu.dtb.inst_accesses 0 # ITB inst accesses 353system.cpu.dtb.hits 0 # DTB hits 354system.cpu.dtb.misses 0 # DTB misses 355system.cpu.dtb.accesses 0 # DTB accesses | 337system.cpu.dtb.walker.walks 0 # Table walker walks requested 338system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 358system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 359system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 360system.cpu.dtb.read_accesses 0 # DTB read accesses 361system.cpu.dtb.write_accesses 0 # DTB write accesses 362system.cpu.dtb.inst_accesses 0 # ITB inst accesses 363system.cpu.dtb.hits 0 # DTB hits 364system.cpu.dtb.misses 0 # DTB misses 365system.cpu.dtb.accesses 0 # DTB accesses |
| 356system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states | 366system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states |
| 357system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 378system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 367system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 388system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 389system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 390system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 391system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 392system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 393system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 394system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 395system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 386system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states | 396system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states |
| 387system.cpu.itb.walker.walks 0 # Table walker walks requested 388system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 409system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 410system.cpu.itb.read_accesses 0 # DTB read accesses 411system.cpu.itb.write_accesses 0 # DTB write accesses 412system.cpu.itb.inst_accesses 0 # ITB inst accesses 413system.cpu.itb.hits 0 # DTB hits 414system.cpu.itb.misses 0 # DTB misses 415system.cpu.itb.accesses 0 # DTB accesses 416system.cpu.workload.num_syscalls 548 # Number of system calls | 397system.cpu.itb.walker.walks 0 # Table walker walks requested 398system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 419system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 420system.cpu.itb.read_accesses 0 # DTB read accesses 421system.cpu.itb.write_accesses 0 # DTB write accesses 422system.cpu.itb.inst_accesses 0 # ITB inst accesses 423system.cpu.itb.hits 0 # DTB hits 424system.cpu.itb.misses 0 # DTB misses 425system.cpu.itb.accesses 0 # DTB accesses 426system.cpu.workload.num_syscalls 548 # Number of system calls |
| 417system.cpu.pwrStateResidencyTicks::ON 366631719500 # Cumulative time (in ticks) in various power states 418system.cpu.numCycles 733263439 # number of cpu cycles simulated | 427system.cpu.pwrStateResidencyTicks::ON 368600034500 # Cumulative time (in ticks) in various power states 428system.cpu.numCycles 737200069 # number of cpu cycles simulated |
| 419system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 420system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 421system.cpu.committedInsts 506579366 # Number of instructions committed 422system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed | 429system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 430system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 431system.cpu.committedInsts 506579366 # Number of instructions committed 432system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed |
| 423system.cpu.discardedOps 12939754 # Number of ops (including micro ops) which were discarded before commit | 433system.cpu.discardedOps 12939783 # Number of ops (including micro ops) which were discarded before commit |
| 424system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 434system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 425system.cpu.cpi 1.447480 # CPI: cycles per instruction 426system.cpu.ipc 0.690856 # IPC: instructions per cycle | 435system.cpu.cpi 1.455251 # CPI: cycles per instruction 436system.cpu.ipc 0.687167 # IPC: instructions per cycle |
| 427system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 428system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction 429system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 430system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 431system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 432system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 433system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 434system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 454system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 455system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 456system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 457system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 458system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction 459system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 460system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 461system.cpu.op_class_0::total 548692589 # Class of committed instruction | 437system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 438system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction 439system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 440system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 441system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 442system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 443system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 444system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 464system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 465system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 466system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 467system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 468system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction 469system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 470system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 471system.cpu.op_class_0::total 548692589 # Class of committed instruction |
| 462system.cpu.tickCycles 694072576 # Number of cycles that the object actually ticked 463system.cpu.idleCycles 39190863 # Total number of cycles that the object has spent stopped 464system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states | 472system.cpu.tickCycles 694074439 # Number of cycles that the object actually ticked 473system.cpu.idleCycles 43125630 # Total number of cycles that the object has spent stopped 474system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states |
| 465system.cpu.dcache.tags.replacements 1141337 # number of replacements | 475system.cpu.dcache.tags.replacements 1141337 # number of replacements |
| 466system.cpu.dcache.tags.tagsinuse 4070.301946 # Cycle average of tags in use 467system.cpu.dcache.tags.total_refs 171083822 # Total number of references to valid blocks. | 476system.cpu.dcache.tags.tagsinuse 4070.214597 # Cycle average of tags in use 477system.cpu.dcache.tags.total_refs 171083824 # Total number of references to valid blocks. |
| 468system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. | 478system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. |
| 469system.cpu.dcache.tags.avg_refs 149.361702 # Average number of references to valid blocks. 470system.cpu.dcache.tags.warmup_cycle 5036525500 # Cycle when the warmup percentage was hit. 471system.cpu.dcache.tags.occ_blocks::cpu.data 4070.301946 # Average occupied blocks per requestor 472system.cpu.dcache.tags.occ_percent::cpu.data 0.993726 # Average percentage of cache occupancy 473system.cpu.dcache.tags.occ_percent::total 0.993726 # Average percentage of cache occupancy | 479system.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks. 480system.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit. 481system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214597 # Average occupied blocks per requestor 482system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy 483system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy |
| 474system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 484system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 475system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 476system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 477system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id 478system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id | 485system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 486system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 487system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id 488system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id |
| 479system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 489system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 480system.cpu.dcache.tags.tag_accesses 346338109 # Number of tag accesses 481system.cpu.dcache.tags.data_accesses 346338109 # Number of data accesses 482system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 483system.cpu.dcache.ReadReq_hits::cpu.data 114566017 # number of ReadReq hits 484system.cpu.dcache.ReadReq_hits::total 114566017 # number of ReadReq hits 485system.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits 486system.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits | 490system.cpu.dcache.tags.tag_accesses 346338045 # Number of tag accesses 491system.cpu.dcache.tags.data_accesses 346338045 # Number of data accesses 492system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 493system.cpu.dcache.ReadReq_hits::cpu.data 114566013 # number of ReadReq hits 494system.cpu.dcache.ReadReq_hits::total 114566013 # number of ReadReq hits 495system.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits 496system.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits |
| 487system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits 488system.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits 489system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 490system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 491system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 492system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits | 497system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits 498system.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits 499system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 500system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 501system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 502system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits |
| 493system.cpu.dcache.demand_hits::cpu.data 168103946 # number of demand (read+write) hits 494system.cpu.dcache.demand_hits::total 168103946 # number of demand (read+write) hits 495system.cpu.dcache.overall_hits::cpu.data 168106740 # number of overall hits 496system.cpu.dcache.overall_hits::total 168106740 # number of overall hits 497system.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses 498system.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses 499system.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses 500system.cpu.dcache.WriteReq_misses::total 701120 # number of WriteReq misses | 503system.cpu.dcache.demand_hits::cpu.data 168103948 # number of demand (read+write) hits 504system.cpu.dcache.demand_hits::total 168103948 # number of demand (read+write) hits 505system.cpu.dcache.overall_hits::cpu.data 168106742 # number of overall hits 506system.cpu.dcache.overall_hits::total 168106742 # number of overall hits 507system.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses 508system.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses 509system.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses 510system.cpu.dcache.WriteReq_misses::total 701114 # number of WriteReq misses |
| 501system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 502system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses | 511system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 512system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses |
| 503system.cpu.dcache.demand_misses::cpu.data 1512501 # number of demand (read+write) misses 504system.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses 505system.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses 506system.cpu.dcache.overall_misses::total 1512516 # number of overall misses 507system.cpu.dcache.ReadReq_miss_latency::cpu.data 13515584500 # number of ReadReq miss cycles 508system.cpu.dcache.ReadReq_miss_latency::total 13515584500 # number of ReadReq miss cycles 509system.cpu.dcache.WriteReq_miss_latency::cpu.data 22200332500 # number of WriteReq miss cycles 510system.cpu.dcache.WriteReq_miss_latency::total 22200332500 # number of WriteReq miss cycles 511system.cpu.dcache.demand_miss_latency::cpu.data 35715917000 # number of demand (read+write) miss cycles 512system.cpu.dcache.demand_miss_latency::total 35715917000 # number of demand (read+write) miss cycles 513system.cpu.dcache.overall_miss_latency::cpu.data 35715917000 # number of overall miss cycles 514system.cpu.dcache.overall_miss_latency::total 35715917000 # number of overall miss cycles 515system.cpu.dcache.ReadReq_accesses::cpu.data 115377398 # number of ReadReq accesses(hits+misses) 516system.cpu.dcache.ReadReq_accesses::total 115377398 # number of ReadReq accesses(hits+misses) | 513system.cpu.dcache.demand_misses::cpu.data 1512467 # number of demand (read+write) misses 514system.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses 515system.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses 516system.cpu.dcache.overall_misses::total 1512482 # number of overall misses 517system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511838000 # number of ReadReq miss cycles 518system.cpu.dcache.ReadReq_miss_latency::total 14511838000 # number of ReadReq miss cycles 519system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015669000 # number of WriteReq miss cycles 520system.cpu.dcache.WriteReq_miss_latency::total 24015669000 # number of WriteReq miss cycles 521system.cpu.dcache.demand_miss_latency::cpu.data 38527507000 # number of demand (read+write) miss cycles 522system.cpu.dcache.demand_miss_latency::total 38527507000 # number of demand (read+write) miss cycles 523system.cpu.dcache.overall_miss_latency::cpu.data 38527507000 # number of overall miss cycles 524system.cpu.dcache.overall_miss_latency::total 38527507000 # number of overall miss cycles 525system.cpu.dcache.ReadReq_accesses::cpu.data 115377366 # number of ReadReq accesses(hits+misses) 526system.cpu.dcache.ReadReq_accesses::total 115377366 # number of ReadReq accesses(hits+misses) |
| 517system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 518system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 519system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) 520system.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses) 521system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 522system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 523system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 524system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) | 527system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 528system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 529system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) 530system.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses) 531system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 532system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 533system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 534system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) |
| 525system.cpu.dcache.demand_accesses::cpu.data 169616447 # number of demand (read+write) accesses 526system.cpu.dcache.demand_accesses::total 169616447 # number of demand (read+write) accesses 527system.cpu.dcache.overall_accesses::cpu.data 169619256 # number of overall (read+write) accesses 528system.cpu.dcache.overall_accesses::total 169619256 # number of overall (read+write) accesses | 535system.cpu.dcache.demand_accesses::cpu.data 169616415 # number of demand (read+write) accesses 536system.cpu.dcache.demand_accesses::total 169616415 # number of demand (read+write) accesses 537system.cpu.dcache.overall_accesses::cpu.data 169619224 # number of overall (read+write) accesses 538system.cpu.dcache.overall_accesses::total 169619224 # number of overall (read+write) accesses |
| 529system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses 530system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses 531system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses 532system.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses 533system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses 534system.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses 535system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses 536system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses 537system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses 538system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses | 539system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses 540system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses 541system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses 542system.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses 543system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses 544system.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses 545system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses 546system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses 547system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses 548system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses |
| 539system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769 # average ReadReq miss latency 540system.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769 # average ReadReq miss latency 541system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157 # average WriteReq miss latency 542system.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157 # average WriteReq miss latency 543system.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809 # average overall miss latency 544system.cpu.dcache.demand_avg_miss_latency::total 23613.813809 # average overall miss latency 545system.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625 # average overall miss latency 546system.cpu.dcache.overall_avg_miss_latency::total 23613.579625 # average overall miss latency | 549system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183 # average ReadReq miss latency 550system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183 # average ReadReq miss latency 551system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435 # average WriteReq miss latency 552system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435 # average WriteReq miss latency 553system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682 # average overall miss latency 554system.cpu.dcache.demand_avg_miss_latency::total 25473.287682 # average overall miss latency 555system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051 # average overall miss latency 556system.cpu.dcache.overall_avg_miss_latency::total 25473.035051 # average overall miss latency |
| 547system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks 554system.cpu.dcache.writebacks::total 1068942 # number of writebacks | 557system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 558system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 559system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 562system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 563system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks 564system.cpu.dcache.writebacks::total 1068942 # number of writebacks |
| 555system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits 556system.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits 557system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits 558system.cpu.dcache.WriteReq_mshr_hits::total 344732 # number of WriteReq MSHR hits 559system.cpu.dcache.demand_mshr_hits::cpu.data 367080 # number of demand (read+write) MSHR hits 560system.cpu.dcache.demand_mshr_hits::total 367080 # number of demand (read+write) MSHR hits 561system.cpu.dcache.overall_mshr_hits::cpu.data 367080 # number of overall MSHR hits 562system.cpu.dcache.overall_mshr_hits::total 367080 # number of overall MSHR hits | 565system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22320 # number of ReadReq MSHR hits 566system.cpu.dcache.ReadReq_mshr_hits::total 22320 # number of ReadReq MSHR hits 567system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344726 # number of WriteReq MSHR hits 568system.cpu.dcache.WriteReq_mshr_hits::total 344726 # number of WriteReq MSHR hits 569system.cpu.dcache.demand_mshr_hits::cpu.data 367046 # number of demand (read+write) MSHR hits 570system.cpu.dcache.demand_mshr_hits::total 367046 # number of demand (read+write) MSHR hits 571system.cpu.dcache.overall_mshr_hits::cpu.data 367046 # number of overall MSHR hits 572system.cpu.dcache.overall_mshr_hits::total 367046 # number of overall MSHR hits |
| 563system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses 564system.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses 565system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses 566system.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses 567system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 568system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 569system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses 570system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses 571system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses 572system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses | 573system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses 574system.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses 575system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses 576system.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses 577system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 578system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 579system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses 580system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses 581system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses 582system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses |
| 573system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12423186500 # number of ReadReq MSHR miss cycles 574system.cpu.dcache.ReadReq_mshr_miss_latency::total 12423186500 # number of ReadReq MSHR miss cycles 575system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11274063500 # number of WriteReq MSHR miss cycles 576system.cpu.dcache.WriteReq_mshr_miss_latency::total 11274063500 # number of WriteReq MSHR miss cycles 577system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 942500 # number of SoftPFReq MSHR miss cycles 578system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 942500 # number of SoftPFReq MSHR miss cycles 579system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23697250000 # number of demand (read+write) MSHR miss cycles 580system.cpu.dcache.demand_mshr_miss_latency::total 23697250000 # number of demand (read+write) MSHR miss cycles 581system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23698192500 # number of overall MSHR miss cycles 582system.cpu.dcache.overall_mshr_miss_latency::total 23698192500 # number of overall MSHR miss cycles | 583system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416891000 # number of ReadReq MSHR miss cycles 584system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416891000 # number of ReadReq MSHR miss cycles 585system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191000 # number of WriteReq MSHR miss cycles 586system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191000 # number of WriteReq MSHR miss cycles 587system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles 588system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles 589system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613082000 # number of demand (read+write) MSHR miss cycles 590system.cpu.dcache.demand_mshr_miss_latency::total 25613082000 # number of demand (read+write) MSHR miss cycles 591system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617379000 # number of overall MSHR miss cycles 592system.cpu.dcache.overall_mshr_miss_latency::total 25617379000 # number of overall MSHR miss cycles |
| 583system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses 584system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses 585system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses 586system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses 587system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses 588system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses 589system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses 590system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses 591system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses 592system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses | 593system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses 594system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses 595system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses 596system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses 597system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses 598system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses 599system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses 600system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses 601system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses 602system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses |
| 593system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995 # average ReadReq mshr miss latency 594system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995 # average ReadReq mshr miss latency 595system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930 # average WriteReq mshr miss latency 596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930 # average WriteReq mshr miss latency 597system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667 # average SoftPFReq mshr miss latency 598system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667 # average SoftPFReq mshr miss latency 599system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280 # average overall mshr miss latency 600system.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280 # average overall mshr miss latency 601system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370 # average overall mshr miss latency 602system.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370 # average overall mshr miss latency 603system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 604system.cpu.icache.tags.replacements 18175 # number of replacements 605system.cpu.icache.tags.tagsinuse 1187.102530 # Cycle average of tags in use 606system.cpu.icache.tags.total_refs 199148962 # Total number of references to valid blocks. 607system.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks. 608system.cpu.icache.tags.avg_refs 9934.102958 # Average number of references to valid blocks. | 603system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356 # average ReadReq mshr miss latency 604system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356 # average ReadReq mshr miss latency 605system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713 # average WriteReq mshr miss latency 606system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713 # average WriteReq mshr miss latency 607system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency 608system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency 609system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009 # average overall mshr miss latency 610system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009 # average overall mshr miss latency 611system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163 # average overall mshr miss latency 612system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163 # average overall mshr miss latency 613system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 614system.cpu.icache.tags.replacements 18178 # number of replacements 615system.cpu.icache.tags.tagsinuse 1186.508914 # Cycle average of tags in use 616system.cpu.icache.tags.total_refs 199149017 # Total number of references to valid blocks. 617system.cpu.icache.tags.sampled_refs 20050 # Sample count of references to valid blocks. 618system.cpu.icache.tags.avg_refs 9932.619302 # Average number of references to valid blocks. |
| 609system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 619system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 610system.cpu.icache.tags.occ_blocks::cpu.inst 1187.102530 # Average occupied blocks per requestor 611system.cpu.icache.tags.occ_percent::cpu.inst 0.579640 # Average percentage of cache occupancy 612system.cpu.icache.tags.occ_percent::total 0.579640 # Average percentage of cache occupancy | 620system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508914 # Average occupied blocks per requestor 621system.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy 622system.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy |
| 613system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 614system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 615system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 616system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 617system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id 618system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id 619system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id | 623system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 624system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 625system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 626system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 627system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id 628system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id 629system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id |
| 620system.cpu.icache.tags.tag_accesses 398358065 # Number of tag accesses 621system.cpu.icache.tags.data_accesses 398358065 # Number of data accesses 622system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 623system.cpu.icache.ReadReq_hits::cpu.inst 199148962 # number of ReadReq hits 624system.cpu.icache.ReadReq_hits::total 199148962 # number of ReadReq hits 625system.cpu.icache.demand_hits::cpu.inst 199148962 # number of demand (read+write) hits 626system.cpu.icache.demand_hits::total 199148962 # number of demand (read+write) hits 627system.cpu.icache.overall_hits::cpu.inst 199148962 # number of overall hits 628system.cpu.icache.overall_hits::total 199148962 # number of overall hits 629system.cpu.icache.ReadReq_misses::cpu.inst 20047 # number of ReadReq misses 630system.cpu.icache.ReadReq_misses::total 20047 # number of ReadReq misses 631system.cpu.icache.demand_misses::cpu.inst 20047 # number of demand (read+write) misses 632system.cpu.icache.demand_misses::total 20047 # number of demand (read+write) misses 633system.cpu.icache.overall_misses::cpu.inst 20047 # number of overall misses 634system.cpu.icache.overall_misses::total 20047 # number of overall misses 635system.cpu.icache.ReadReq_miss_latency::cpu.inst 467837000 # number of ReadReq miss cycles 636system.cpu.icache.ReadReq_miss_latency::total 467837000 # number of ReadReq miss cycles 637system.cpu.icache.demand_miss_latency::cpu.inst 467837000 # number of demand (read+write) miss cycles 638system.cpu.icache.demand_miss_latency::total 467837000 # number of demand (read+write) miss cycles 639system.cpu.icache.overall_miss_latency::cpu.inst 467837000 # number of overall miss cycles 640system.cpu.icache.overall_miss_latency::total 467837000 # number of overall miss cycles 641system.cpu.icache.ReadReq_accesses::cpu.inst 199169009 # number of ReadReq accesses(hits+misses) 642system.cpu.icache.ReadReq_accesses::total 199169009 # number of ReadReq accesses(hits+misses) 643system.cpu.icache.demand_accesses::cpu.inst 199169009 # number of demand (read+write) accesses 644system.cpu.icache.demand_accesses::total 199169009 # number of demand (read+write) accesses 645system.cpu.icache.overall_accesses::cpu.inst 199169009 # number of overall (read+write) accesses 646system.cpu.icache.overall_accesses::total 199169009 # number of overall (read+write) accesses | 630system.cpu.icache.tags.tag_accesses 398358184 # Number of tag accesses 631system.cpu.icache.tags.data_accesses 398358184 # Number of data accesses 632system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 633system.cpu.icache.ReadReq_hits::cpu.inst 199149017 # number of ReadReq hits 634system.cpu.icache.ReadReq_hits::total 199149017 # number of ReadReq hits 635system.cpu.icache.demand_hits::cpu.inst 199149017 # number of demand (read+write) hits 636system.cpu.icache.demand_hits::total 199149017 # number of demand (read+write) hits 637system.cpu.icache.overall_hits::cpu.inst 199149017 # number of overall hits 638system.cpu.icache.overall_hits::total 199149017 # number of overall hits 639system.cpu.icache.ReadReq_misses::cpu.inst 20050 # number of ReadReq misses 640system.cpu.icache.ReadReq_misses::total 20050 # number of ReadReq misses 641system.cpu.icache.demand_misses::cpu.inst 20050 # number of demand (read+write) misses 642system.cpu.icache.demand_misses::total 20050 # number of demand (read+write) misses 643system.cpu.icache.overall_misses::cpu.inst 20050 # number of overall misses 644system.cpu.icache.overall_misses::total 20050 # number of overall misses 645system.cpu.icache.ReadReq_miss_latency::cpu.inst 544281000 # number of ReadReq miss cycles 646system.cpu.icache.ReadReq_miss_latency::total 544281000 # number of ReadReq miss cycles 647system.cpu.icache.demand_miss_latency::cpu.inst 544281000 # number of demand (read+write) miss cycles 648system.cpu.icache.demand_miss_latency::total 544281000 # number of demand (read+write) miss cycles 649system.cpu.icache.overall_miss_latency::cpu.inst 544281000 # number of overall miss cycles 650system.cpu.icache.overall_miss_latency::total 544281000 # number of overall miss cycles 651system.cpu.icache.ReadReq_accesses::cpu.inst 199169067 # number of ReadReq accesses(hits+misses) 652system.cpu.icache.ReadReq_accesses::total 199169067 # number of ReadReq accesses(hits+misses) 653system.cpu.icache.demand_accesses::cpu.inst 199169067 # number of demand (read+write) accesses 654system.cpu.icache.demand_accesses::total 199169067 # number of demand (read+write) accesses 655system.cpu.icache.overall_accesses::cpu.inst 199169067 # number of overall (read+write) accesses 656system.cpu.icache.overall_accesses::total 199169067 # number of overall (read+write) accesses |
| 647system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses 648system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses 649system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses 650system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses 651system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses 652system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses | 657system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses 658system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses 659system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses 660system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses 661system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses 662system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses |
| 653system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23337.008031 # average ReadReq miss latency 654system.cpu.icache.ReadReq_avg_miss_latency::total 23337.008031 # average ReadReq miss latency 655system.cpu.icache.demand_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency 656system.cpu.icache.demand_avg_miss_latency::total 23337.008031 # average overall miss latency 657system.cpu.icache.overall_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency 658system.cpu.icache.overall_avg_miss_latency::total 23337.008031 # average overall miss latency | 663system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539 # average ReadReq miss latency 664system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539 # average ReadReq miss latency 665system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency 666system.cpu.icache.demand_avg_miss_latency::total 27146.184539 # average overall miss latency 667system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency 668system.cpu.icache.overall_avg_miss_latency::total 27146.184539 # average overall miss latency |
| 659system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 660system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 661system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 662system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 663system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 664system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 669system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 670system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 671system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 672system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 673system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 674system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 665system.cpu.icache.writebacks::writebacks 18175 # number of writebacks 666system.cpu.icache.writebacks::total 18175 # number of writebacks 667system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20047 # number of ReadReq MSHR misses 668system.cpu.icache.ReadReq_mshr_misses::total 20047 # number of ReadReq MSHR misses 669system.cpu.icache.demand_mshr_misses::cpu.inst 20047 # number of demand (read+write) MSHR misses 670system.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses 671system.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses 672system.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses 673system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 447790000 # number of ReadReq MSHR miss cycles 674system.cpu.icache.ReadReq_mshr_miss_latency::total 447790000 # number of ReadReq MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::cpu.inst 447790000 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.demand_mshr_miss_latency::total 447790000 # number of demand (read+write) MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::cpu.inst 447790000 # number of overall MSHR miss cycles 678system.cpu.icache.overall_mshr_miss_latency::total 447790000 # number of overall MSHR miss cycles | 675system.cpu.icache.writebacks::writebacks 18178 # number of writebacks 676system.cpu.icache.writebacks::total 18178 # number of writebacks 677system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20050 # number of ReadReq MSHR misses 678system.cpu.icache.ReadReq_mshr_misses::total 20050 # number of ReadReq MSHR misses 679system.cpu.icache.demand_mshr_misses::cpu.inst 20050 # number of demand (read+write) MSHR misses 680system.cpu.icache.demand_mshr_misses::total 20050 # number of demand (read+write) MSHR misses 681system.cpu.icache.overall_mshr_misses::cpu.inst 20050 # number of overall MSHR misses 682system.cpu.icache.overall_mshr_misses::total 20050 # number of overall MSHR misses 683system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524231000 # number of ReadReq MSHR miss cycles 684system.cpu.icache.ReadReq_mshr_miss_latency::total 524231000 # number of ReadReq MSHR miss cycles 685system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524231000 # number of demand (read+write) MSHR miss cycles 686system.cpu.icache.demand_mshr_miss_latency::total 524231000 # number of demand (read+write) MSHR miss cycles 687system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524231000 # number of overall MSHR miss cycles 688system.cpu.icache.overall_mshr_miss_latency::total 524231000 # number of overall MSHR miss cycles |
| 679system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses 680system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses 681system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses 682system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses 683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 684system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses | 689system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses 690system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses 691system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses 692system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses 693system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 694system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses |
| 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031 # average ReadReq mshr miss latency 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031 # average ReadReq mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency 691system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states | 695system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539 # average ReadReq mshr miss latency 696system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539 # average ReadReq mshr miss latency 697system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency 698system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency 699system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency 700system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency 701system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states |
| 692system.cpu.l2cache.tags.replacements 112761 # number of replacements | 702system.cpu.l2cache.tags.replacements 112761 # number of replacements |
| 693system.cpu.l2cache.tags.tagsinuse 29068.883602 # Cycle average of tags in use 694system.cpu.l2cache.tags.total_refs 2174452 # Total number of references to valid blocks. | 703system.cpu.l2cache.tags.tagsinuse 29076.847904 # Cycle average of tags in use 704system.cpu.l2cache.tags.total_refs 2174458 # Total number of references to valid blocks. |
| 695system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. | 705system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. |
| 696system.cpu.l2cache.tags.avg_refs 14.941709 # Average number of references to valid blocks. 697system.cpu.l2cache.tags.warmup_cycle 101788000000 # Cycle when the warmup percentage was hit. 698system.cpu.l2cache.tags.occ_blocks::writebacks 134.067060 # Average occupied blocks per requestor 699system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.855024 # Average occupied blocks per requestor 700system.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519 # Average occupied blocks per requestor 701system.cpu.l2cache.tags.occ_percent::writebacks 0.004091 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009395 # Average percentage of cache occupancy 703system.cpu.l2cache.tags.occ_percent::cpu.data 0.873626 # Average percentage of cache occupancy 704system.cpu.l2cache.tags.occ_percent::total 0.887112 # Average percentage of cache occupancy | 706system.cpu.l2cache.tags.avg_refs 14.941750 # Average number of references to valid blocks. 707system.cpu.l2cache.tags.warmup_cycle 102118428000 # Cycle when the warmup percentage was hit. 708system.cpu.l2cache.tags.occ_blocks::writebacks 133.889042 # Average occupied blocks per requestor 709system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541070 # Average occupied blocks per requestor 710system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793 # Average occupied blocks per requestor 711system.cpu.l2cache.tags.occ_percent::writebacks 0.004086 # Average percentage of cache occupancy 712system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009385 # Average percentage of cache occupancy 713system.cpu.l2cache.tags.occ_percent::cpu.data 0.873884 # Average percentage of cache occupancy 714system.cpu.l2cache.tags.occ_percent::total 0.887355 # Average percentage of cache occupancy |
| 705system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id 708system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id 709system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id 710system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 715system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 716system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 717system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id 718system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id 719system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id 720system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 711system.cpu.l2cache.tags.tag_accesses 18705497 # Number of tag accesses 712system.cpu.l2cache.tags.data_accesses 18705497 # Number of data accesses 713system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states | 721system.cpu.l2cache.tags.tag_accesses 18705537 # Number of tag accesses 722system.cpu.l2cache.tags.data_accesses 18705537 # Number of data accesses 723system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states |
| 714system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits 715system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits | 724system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits 725system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits |
| 716system.cpu.l2cache.WritebackClean_hits::writebacks 17938 # number of WritebackClean hits 717system.cpu.l2cache.WritebackClean_hits::total 17938 # number of WritebackClean hits | 726system.cpu.l2cache.WritebackClean_hits::writebacks 17940 # number of WritebackClean hits 727system.cpu.l2cache.WritebackClean_hits::total 17940 # number of WritebackClean hits |
| 718system.cpu.l2cache.ReadExReq_hits::cpu.data 255660 # number of ReadExReq hits 719system.cpu.l2cache.ReadExReq_hits::total 255660 # number of ReadExReq hits | 728system.cpu.l2cache.ReadExReq_hits::cpu.data 255660 # number of ReadExReq hits 729system.cpu.l2cache.ReadExReq_hits::total 255660 # number of ReadExReq hits |
| 720system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17235 # number of ReadCleanReq hits 721system.cpu.l2cache.ReadCleanReq_hits::total 17235 # number of ReadCleanReq hits | 730system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17239 # number of ReadCleanReq hits 731system.cpu.l2cache.ReadCleanReq_hits::total 17239 # number of ReadCleanReq hits |
| 722system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748301 # number of ReadSharedReq hits 723system.cpu.l2cache.ReadSharedReq_hits::total 748301 # number of ReadSharedReq hits | 732system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748301 # number of ReadSharedReq hits 733system.cpu.l2cache.ReadSharedReq_hits::total 748301 # number of ReadSharedReq hits |
| 724system.cpu.l2cache.demand_hits::cpu.inst 17235 # number of demand (read+write) hits | 734system.cpu.l2cache.demand_hits::cpu.inst 17239 # number of demand (read+write) hits |
| 725system.cpu.l2cache.demand_hits::cpu.data 1003961 # number of demand (read+write) hits | 735system.cpu.l2cache.demand_hits::cpu.data 1003961 # number of demand (read+write) hits |
| 726system.cpu.l2cache.demand_hits::total 1021196 # number of demand (read+write) hits 727system.cpu.l2cache.overall_hits::cpu.inst 17235 # number of overall hits | 736system.cpu.l2cache.demand_hits::total 1021200 # number of demand (read+write) hits 737system.cpu.l2cache.overall_hits::cpu.inst 17239 # number of overall hits |
| 728system.cpu.l2cache.overall_hits::cpu.data 1003961 # number of overall hits | 738system.cpu.l2cache.overall_hits::cpu.data 1003961 # number of overall hits |
| 729system.cpu.l2cache.overall_hits::total 1021196 # number of overall hits | 739system.cpu.l2cache.overall_hits::total 1021200 # number of overall hits |
| 730system.cpu.l2cache.ReadExReq_misses::cpu.data 100978 # number of ReadExReq misses 731system.cpu.l2cache.ReadExReq_misses::total 100978 # number of ReadExReq misses | 740system.cpu.l2cache.ReadExReq_misses::cpu.data 100978 # number of ReadExReq misses 741system.cpu.l2cache.ReadExReq_misses::total 100978 # number of ReadExReq misses |
| 732system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2812 # number of ReadCleanReq misses 733system.cpu.l2cache.ReadCleanReq_misses::total 2812 # number of ReadCleanReq misses | 742system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses 743system.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses |
| 734system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40494 # number of ReadSharedReq misses 735system.cpu.l2cache.ReadSharedReq_misses::total 40494 # number of ReadSharedReq misses | 744system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40494 # number of ReadSharedReq misses 745system.cpu.l2cache.ReadSharedReq_misses::total 40494 # number of ReadSharedReq misses |
| 736system.cpu.l2cache.demand_misses::cpu.inst 2812 # number of demand (read+write) misses | 746system.cpu.l2cache.demand_misses::cpu.inst 2811 # number of demand (read+write) misses |
| 737system.cpu.l2cache.demand_misses::cpu.data 141472 # number of demand (read+write) misses | 747system.cpu.l2cache.demand_misses::cpu.data 141472 # number of demand (read+write) misses |
| 738system.cpu.l2cache.demand_misses::total 144284 # number of demand (read+write) misses 739system.cpu.l2cache.overall_misses::cpu.inst 2812 # number of overall misses | 748system.cpu.l2cache.demand_misses::total 144283 # number of demand (read+write) misses 749system.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses |
| 740system.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses | 750system.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses |
| 741system.cpu.l2cache.overall_misses::total 144284 # number of overall misses 742system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8057525500 # number of ReadExReq miss cycles 743system.cpu.l2cache.ReadExReq_miss_latency::total 8057525500 # number of ReadExReq miss cycles 744system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236084500 # number of ReadCleanReq miss cycles 745system.cpu.l2cache.ReadCleanReq_miss_latency::total 236084500 # number of ReadCleanReq miss cycles 746system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3363607000 # number of ReadSharedReq miss cycles 747system.cpu.l2cache.ReadSharedReq_miss_latency::total 3363607000 # number of ReadSharedReq miss cycles 748system.cpu.l2cache.demand_miss_latency::cpu.inst 236084500 # number of demand (read+write) miss cycles 749system.cpu.l2cache.demand_miss_latency::cpu.data 11421132500 # number of demand (read+write) miss cycles 750system.cpu.l2cache.demand_miss_latency::total 11657217000 # number of demand (read+write) miss cycles 751system.cpu.l2cache.overall_miss_latency::cpu.inst 236084500 # number of overall miss cycles 752system.cpu.l2cache.overall_miss_latency::cpu.data 11421132500 # number of overall miss cycles 753system.cpu.l2cache.overall_miss_latency::total 11657217000 # number of overall miss cycles | 751system.cpu.l2cache.overall_misses::total 144283 # number of overall misses 752system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653000 # number of ReadExReq miss cycles 753system.cpu.l2cache.ReadExReq_miss_latency::total 8979653000 # number of ReadExReq miss cycles 754system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312477500 # number of ReadCleanReq miss cycles 755system.cpu.l2cache.ReadCleanReq_miss_latency::total 312477500 # number of ReadCleanReq miss cycles 756system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360667500 # number of ReadSharedReq miss cycles 757system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360667500 # number of ReadSharedReq miss cycles 758system.cpu.l2cache.demand_miss_latency::cpu.inst 312477500 # number of demand (read+write) miss cycles 759system.cpu.l2cache.demand_miss_latency::cpu.data 13340320500 # number of demand (read+write) miss cycles 760system.cpu.l2cache.demand_miss_latency::total 13652798000 # number of demand (read+write) miss cycles 761system.cpu.l2cache.overall_miss_latency::cpu.inst 312477500 # number of overall miss cycles 762system.cpu.l2cache.overall_miss_latency::cpu.data 13340320500 # number of overall miss cycles 763system.cpu.l2cache.overall_miss_latency::total 13652798000 # number of overall miss cycles |
| 754system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) 755system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) | 764system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) 765system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) |
| 756system.cpu.l2cache.WritebackClean_accesses::writebacks 17938 # number of WritebackClean accesses(hits+misses) 757system.cpu.l2cache.WritebackClean_accesses::total 17938 # number of WritebackClean accesses(hits+misses) | 766system.cpu.l2cache.WritebackClean_accesses::writebacks 17940 # number of WritebackClean accesses(hits+misses) 767system.cpu.l2cache.WritebackClean_accesses::total 17940 # number of WritebackClean accesses(hits+misses) |
| 758system.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) 759system.cpu.l2cache.ReadExReq_accesses::total 356638 # number of ReadExReq accesses(hits+misses) | 768system.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) 769system.cpu.l2cache.ReadExReq_accesses::total 356638 # number of ReadExReq accesses(hits+misses) |
| 760system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20047 # number of ReadCleanReq accesses(hits+misses) 761system.cpu.l2cache.ReadCleanReq_accesses::total 20047 # number of ReadCleanReq accesses(hits+misses) | 770system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20050 # number of ReadCleanReq accesses(hits+misses) 771system.cpu.l2cache.ReadCleanReq_accesses::total 20050 # number of ReadCleanReq accesses(hits+misses) |
| 762system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788795 # number of ReadSharedReq accesses(hits+misses) 763system.cpu.l2cache.ReadSharedReq_accesses::total 788795 # number of ReadSharedReq accesses(hits+misses) | 772system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788795 # number of ReadSharedReq accesses(hits+misses) 773system.cpu.l2cache.ReadSharedReq_accesses::total 788795 # number of ReadSharedReq accesses(hits+misses) |
| 764system.cpu.l2cache.demand_accesses::cpu.inst 20047 # number of demand (read+write) accesses | 774system.cpu.l2cache.demand_accesses::cpu.inst 20050 # number of demand (read+write) accesses |
| 765system.cpu.l2cache.demand_accesses::cpu.data 1145433 # number of demand (read+write) accesses | 775system.cpu.l2cache.demand_accesses::cpu.data 1145433 # number of demand (read+write) accesses |
| 766system.cpu.l2cache.demand_accesses::total 1165480 # number of demand (read+write) accesses 767system.cpu.l2cache.overall_accesses::cpu.inst 20047 # number of overall (read+write) accesses | 776system.cpu.l2cache.demand_accesses::total 1165483 # number of demand (read+write) accesses 777system.cpu.l2cache.overall_accesses::cpu.inst 20050 # number of overall (read+write) accesses |
| 768system.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses | 778system.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses |
| 769system.cpu.l2cache.overall_accesses::total 1165480 # number of overall (read+write) accesses | 779system.cpu.l2cache.overall_accesses::total 1165483 # number of overall (read+write) accesses |
| 770system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses 771system.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses | 780system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses 781system.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses |
| 772system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140270 # miss rate for ReadCleanReq accesses 773system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140270 # miss rate for ReadCleanReq accesses | 782system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140200 # miss rate for ReadCleanReq accesses 783system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140200 # miss rate for ReadCleanReq accesses |
| 774system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses 775system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses | 784system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses 785system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses |
| 776system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140270 # miss rate for demand accesses | 786system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140200 # miss rate for demand accesses |
| 777system.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses | 787system.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses |
| 778system.cpu.l2cache.demand_miss_rate::total 0.123798 # miss rate for demand accesses 779system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140270 # miss rate for overall accesses | 788system.cpu.l2cache.demand_miss_rate::total 0.123797 # miss rate for demand accesses 789system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140200 # miss rate for overall accesses |
| 780system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses | 790system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses |
| 781system.cpu.l2cache.overall_miss_rate::total 0.123798 # miss rate for overall accesses 782system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79794.861257 # average ReadExReq miss latency 783system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79794.861257 # average ReadExReq miss latency 784system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83956.081081 # average ReadCleanReq miss latency 785system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83956.081081 # average ReadCleanReq miss latency 786system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83064.330518 # average ReadSharedReq miss latency 787system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83064.330518 # average ReadSharedReq miss latency 788system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency 789system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency 790system.cpu.l2cache.demand_avg_miss_latency::total 80793.552993 # average overall miss latency 791system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency 792system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency 793system.cpu.l2cache.overall_avg_miss_latency::total 80793.552993 # average overall miss latency | 791system.cpu.l2cache.overall_miss_rate::total 0.123797 # miss rate for overall accesses 792system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645 # average ReadExReq miss latency 793system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645 # average ReadExReq miss latency 794system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723 # average ReadCleanReq miss latency 795system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723 # average ReadCleanReq miss latency 796system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063 # average ReadSharedReq miss latency 797system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063 # average ReadSharedReq miss latency 798system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency 799system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency 800system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552 # average overall miss latency 801system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency 802system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552 # average overall miss latency |
| 794system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 795system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 796system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 797system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 798system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 799system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 800system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks 801system.cpu.l2cache.writebacks::total 97528 # number of writebacks | 804system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 805system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 806system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 808system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 809system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 810system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks 811system.cpu.l2cache.writebacks::total 97528 # number of writebacks |
| 802system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 803system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits | 812system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 813system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits |
| 804system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits 805system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits | 814system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits 815system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits |
| 806system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits | 816system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits |
| 807system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits | 817system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits |
| 808system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 809system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits | 818system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 819system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits |
| 810system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits | 820system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits |
| 811system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits | 821system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits |
| 812system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses 813system.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses 814system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses 815system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses 816system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses 817system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses 818system.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses 819system.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses 820system.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses 821system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses 822system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses 823system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses | 822system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses 823system.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses 824system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses 825system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses 826system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses 827system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses 828system.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses 829system.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses 830system.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses 831system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses 832system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses 833system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses |
| 824system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7047745500 # number of ReadExReq MSHR miss cycles 825system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7047745500 # number of ReadExReq MSHR miss cycles 826system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207624000 # number of ReadCleanReq MSHR miss cycles 827system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207624000 # number of ReadCleanReq MSHR miss cycles 828system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2957433000 # number of ReadSharedReq MSHR miss cycles 829system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2957433000 # number of ReadSharedReq MSHR miss cycles 830system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207624000 # number of demand (read+write) MSHR miss cycles 831system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10005178500 # number of demand (read+write) MSHR miss cycles 832system.cpu.l2cache.demand_mshr_miss_latency::total 10212802500 # number of demand (read+write) MSHR miss cycles 833system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207624000 # number of overall MSHR miss cycles 834system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10005178500 # number of overall MSHR miss cycles 835system.cpu.l2cache.overall_mshr_miss_latency::total 10212802500 # number of overall MSHR miss cycles | 834system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873000 # number of ReadExReq MSHR miss cycles 835system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873000 # number of ReadExReq MSHR miss cycles 836system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284302500 # number of ReadCleanReq MSHR miss cycles 837system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284302500 # number of ReadCleanReq MSHR miss cycles 838system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953965500 # number of ReadSharedReq MSHR miss cycles 839system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953965500 # number of ReadSharedReq MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284302500 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923838500 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.demand_mshr_miss_latency::total 12208141000 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284302500 # number of overall MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923838500 # number of overall MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::total 12208141000 # number of overall MSHR miss cycles |
| 836system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses 837system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses | 846system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses 847system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses |
| 838system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for ReadCleanReq accesses 839system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140171 # mshr miss rate for ReadCleanReq accesses | 848system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for ReadCleanReq accesses 849system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140150 # mshr miss rate for ReadCleanReq accesses |
| 840system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses 841system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses | 850system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses 851system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses |
| 842system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for demand accesses | 852system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for demand accesses |
| 843system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses 844system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses | 853system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses 854system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses |
| 845system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for overall accesses | 855system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for overall accesses |
| 846system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses 847system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses | 856system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses 857system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses |
| 848system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.861257 # average ReadExReq mshr miss latency 849system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.861257 # average ReadExReq mshr miss latency 850system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73887.544484 # average ReadCleanReq mshr miss latency 851system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484 # average ReadCleanReq mshr miss latency 852system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837 # average ReadSharedReq mshr miss latency 853system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837 # average ReadSharedReq mshr miss latency 854system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency 855system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency 856system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency 857system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency 858system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency 859system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency 860system.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter. 861system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data. 862system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 858system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645 # average ReadExReq mshr miss latency 859system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645 # average ReadExReq mshr miss latency 860system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904 # average ReadCleanReq mshr miss latency 861system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904 # average ReadCleanReq mshr miss latency 862system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430 # average ReadSharedReq mshr miss latency 863system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430 # average ReadSharedReq mshr miss latency 864system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency 865system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency 866system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency 867system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency 868system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency 869system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency 870system.cpu.toL2Bus.snoop_filter.tot_requests 2324998 # Total number of requests made to the snoop filter. 871system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159585 # Number of requests hitting in the snoop filter with a single holder of the requested data. 872system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 863system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. 864system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 865system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 873system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. 874system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 875system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 866system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 867system.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution | 876system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 877system.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution |
| 868system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution | 878system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution |
| 869system.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution | 879system.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution |
| 870system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution 871system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution | 880system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution 881system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution 882system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution |
| 873system.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution | 883system.cpu.toL2Bus.trans_dist::ReadCleanReq 20050 # Transaction distribution |
| 874system.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution | 884system.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution |
| 875system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58269 # Packet count per connected master and slave (bytes) | 885system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58278 # Packet count per connected master and slave (bytes) |
| 876system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) | 886system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) |
| 877system.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes) 878system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes) | 887system.cpu.toL2Bus.pkt_count::total 3490481 # Packet count per connected master and slave (bytes) 888system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446592 # Cumulative packet size per connected master and slave (bytes) |
| 879system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) | 889system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) |
| 880system.cpu.toL2Bus.pkt_size::total 144166208 # Cumulative packet size per connected master and slave (bytes) | 890system.cpu.toL2Bus.pkt_size::total 144166592 # Cumulative packet size per connected master and slave (bytes) |
| 881system.cpu.toL2Bus.snoops 112761 # Total snoops (count) 882system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) | 891system.cpu.toL2Bus.snoops 112761 # Total snoops (count) 892system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) |
| 883system.cpu.toL2Bus.snoop_fanout::samples 1278241 # Request fanout histogram 884system.cpu.toL2Bus.snoop_fanout::mean 0.006014 # Request fanout histogram 885system.cpu.toL2Bus.snoop_fanout::stdev 0.077345 # Request fanout histogram | 893system.cpu.toL2Bus.snoop_fanout::samples 1278244 # Request fanout histogram 894system.cpu.toL2Bus.snoop_fanout::mean 0.006015 # Request fanout histogram 895system.cpu.toL2Bus.snoop_fanout::stdev 0.077350 # Request fanout histogram |
| 886system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 896system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 887system.cpu.toL2Bus.snoop_fanout::0 1270557 99.40% 99.40% # Request fanout histogram 888system.cpu.toL2Bus.snoop_fanout::1 7681 0.60% 100.00% # Request fanout histogram | 897system.cpu.toL2Bus.snoop_fanout::0 1270559 99.40% 99.40% # Request fanout histogram 898system.cpu.toL2Bus.snoop_fanout::1 7682 0.60% 100.00% # Request fanout histogram |
| 889system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 890system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 891system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 892system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 899system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 900system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 901system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 902system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 893system.cpu.toL2Bus.snoop_fanout::total 1278241 # Request fanout histogram 894system.cpu.toL2Bus.reqLayer0.occupancy 2249613000 # Layer occupancy (ticks) | 903system.cpu.toL2Bus.snoop_fanout::total 1278244 # Request fanout histogram 904system.cpu.toL2Bus.reqLayer0.occupancy 2249619000 # Layer occupancy (ticks) |
| 895system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) | 905system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 896system.cpu.toL2Bus.respLayer0.occupancy 30094452 # Layer occupancy (ticks) | 906system.cpu.toL2Bus.respLayer0.occupancy 30098453 # Layer occupancy (ticks) |
| 897system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 898system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) 899system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 900system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. 901system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 902system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 903system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 904system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 905system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 907system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 908system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) 909system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 910system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. 911system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 912system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 913system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 914system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 915system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 906system.membus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states | 916system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states |
| 907system.membus.trans_dist::ReadResp 43291 # Transaction distribution 908system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution 909system.membus.trans_dist::CleanEvict 12615 # Transaction distribution 910system.membus.trans_dist::ReadExReq 100978 # Transaction distribution 911system.membus.trans_dist::ReadExResp 100978 # Transaction distribution 912system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution 913system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) 914system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 921system.membus.snoop_fanout::stdev 0 # Request fanout histogram 922system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 923system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram 924system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 925system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 926system.membus.snoop_fanout::min_value 0 # Request fanout histogram 927system.membus.snoop_fanout::max_value 0 # Request fanout histogram 928system.membus.snoop_fanout::total 144269 # Request fanout histogram | 917system.membus.trans_dist::ReadResp 43291 # Transaction distribution 918system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution 919system.membus.trans_dist::CleanEvict 12615 # Transaction distribution 920system.membus.trans_dist::ReadExReq 100978 # Transaction distribution 921system.membus.trans_dist::ReadExResp 100978 # Transaction distribution 922system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution 923system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) 924system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 931system.membus.snoop_fanout::stdev 0 # Request fanout histogram 932system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 933system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram 934system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 935system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 936system.membus.snoop_fanout::min_value 0 # Request fanout histogram 937system.membus.snoop_fanout::max_value 0 # Request fanout histogram 938system.membus.snoop_fanout::total 144269 # Request fanout histogram |
| 929system.membus.reqLayer0.occupancy 685129000 # Layer occupancy (ticks) | 939system.membus.reqLayer0.occupancy 685124000 # Layer occupancy (ticks) |
| 930system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) | 940system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 931system.membus.respLayer1.occupancy 765930250 # Layer occupancy (ticks) | 941system.membus.respLayer1.occupancy 765885250 # Layer occupancy (ticks) |
| 932system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 933 934---------- End Simulation Statistics ---------- | 942system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 943 944---------- End Simulation Statistics ---------- |