Cross Reference: /gem5/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

stats.txt (11507:be6065c1d8d2)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362632 # Number of seconds simulated 4sim_ticks 362631828500 # Number of ticks simulated 5final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362632 # Number of seconds simulated 4sim_ticks 362631828500 # Number of ticks simulated 5final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 177215 # Simulator instruction rate (inst/s) 8host_op_rate 191948 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 126858592 # Simulator tick rate (ticks/s) 10host_mem_usage 271160 # Number of bytes of host memory used 11host_seconds 2858.55 # Real time elapsed on the host	7host_inst_rate 379372 # Simulator instruction rate (inst/s) 8host_op_rate 410911 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 271571493 # Simulator tick rate (ticks/s) 10host_mem_usage 317732 # Number of bytes of host memory used 11host_seconds 1335.31 # Real time elapsed on the host
12sim_insts 506579366 # Number of instructions simulated 13sim_ops 548692589 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 506579366 # Number of instructions simulated 13sim_ops 548692589 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6221440 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory --- 257 unchanged lines hidden (view full) --- 281system.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ) 282system.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ) 283system.physmem_1.averagePower 684.623774 # Core power per rank (mW) 284system.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states 285system.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states 286system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 287system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states 288system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states	17system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6221440 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory --- 257 unchanged lines hidden (view full) --- 282system.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ) 283system.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ) 284system.physmem_1.averagePower 684.623774 # Core power per rank (mW) 285system.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states 286system.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states 287system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 288system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states 289system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
	290system.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
289system.cpu.branchPred.lookups 131880511 # Number of BP lookups 290system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted 291system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect 292system.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups 293system.cpu.branchPred.BTBHits 60518878 # Number of BTB hits 294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 295system.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage 296system.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target. 297system.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions. 298system.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups. 299system.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits. 300system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses. 301system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. 302system.cpu_clk_domain.clock 500 # Clock period in ticks	291system.cpu.branchPred.lookups 131880511 # Number of BP lookups 292system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted 293system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect 294system.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups 295system.cpu.branchPred.BTBHits 60518878 # Number of BTB hits 296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 297system.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage 298system.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target. 299system.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions. 300system.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups. 301system.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits. 302system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses. 303system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. 304system.cpu_clk_domain.clock 500 # Clock period in ticks
	305system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
303system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 324system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 325system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 326system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 327system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 328system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 329system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 330system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 331system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	306system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 327system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 328system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 329system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 330system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 331system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 332system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 333system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 334system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	335system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
332system.cpu.dtb.walker.walks 0 # Table walker walks requested 333system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 353system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 354system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.dtb.read_accesses 0 # DTB read accesses 356system.cpu.dtb.write_accesses 0 # DTB write accesses 357system.cpu.dtb.inst_accesses 0 # ITB inst accesses 358system.cpu.dtb.hits 0 # DTB hits 359system.cpu.dtb.misses 0 # DTB misses 360system.cpu.dtb.accesses 0 # DTB accesses	336system.cpu.dtb.walker.walks 0 # Table walker walks requested 337system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 357system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 358system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 359system.cpu.dtb.read_accesses 0 # DTB read accesses 360system.cpu.dtb.write_accesses 0 # DTB write accesses 361system.cpu.dtb.inst_accesses 0 # ITB inst accesses 362system.cpu.dtb.hits 0 # DTB hits 363system.cpu.dtb.misses 0 # DTB misses 364system.cpu.dtb.accesses 0 # DTB accesses
	365system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
361system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 382system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 383system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 384system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 385system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 386system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 387system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 388system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 389system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	366system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 387system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 388system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 389system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 390system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 391system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 392system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 393system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 394system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	395system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
390system.cpu.itb.walker.walks 0 # Table walker walks requested 391system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 412system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 413system.cpu.itb.read_accesses 0 # DTB read accesses 414system.cpu.itb.write_accesses 0 # DTB write accesses 415system.cpu.itb.inst_accesses 0 # ITB inst accesses 416system.cpu.itb.hits 0 # DTB hits 417system.cpu.itb.misses 0 # DTB misses 418system.cpu.itb.accesses 0 # DTB accesses 419system.cpu.workload.num_syscalls 548 # Number of system calls	396system.cpu.itb.walker.walks 0 # Table walker walks requested 397system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 418system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 419system.cpu.itb.read_accesses 0 # DTB read accesses 420system.cpu.itb.write_accesses 0 # DTB write accesses 421system.cpu.itb.inst_accesses 0 # ITB inst accesses 422system.cpu.itb.hits 0 # DTB hits 423system.cpu.itb.misses 0 # DTB misses 424system.cpu.itb.accesses 0 # DTB accesses 425system.cpu.workload.num_syscalls 548 # Number of system calls
	426system.cpu.pwrStateResidencyTicks::ON 362631828500 # Cumulative time (in ticks) in various power states
420system.cpu.numCycles 725263657 # number of cpu cycles simulated 421system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 422system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 423system.cpu.committedInsts 506579366 # Number of instructions committed 424system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed 425system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit 426system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 427system.cpu.cpi 1.431688 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 458system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 459system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 460system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction 461system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 462system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 463system.cpu.op_class_0::total 548692589 # Class of committed instruction 464system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked 465system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped	427system.cpu.numCycles 725263657 # number of cpu cycles simulated 428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 430system.cpu.committedInsts 506579366 # Number of instructions committed 431system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed 432system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit 433system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 434system.cpu.cpi 1.431688 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 465system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 466system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 467system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction 468system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 469system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 470system.cpu.op_class_0::total 548692589 # Class of committed instruction 471system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked 472system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped
	473system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
466system.cpu.dcache.tags.replacements 1141477 # number of replacements 467system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use 468system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks. 469system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks. 470system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks. 471system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. 472system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor 473system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy 474system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy 475system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 476system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 477system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 478system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id 479system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id 480system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 481system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses 482system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses	474system.cpu.dcache.tags.replacements 1141477 # number of replacements 475system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use 476system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks. 477system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks. 478system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks. 479system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. 480system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor 481system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy 482system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy 483system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 484system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 485system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 486system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id 487system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id 488system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 489system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses 490system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses
	491system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
483system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits 484system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits 485system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits 486system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits 487system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits 488system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits 489system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 490system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 595system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency 596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency 597system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency 598system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency 599system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency 600system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency 601system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency 602system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency	492system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits 493system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits 494system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits 495system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits 496system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits 497system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits 498system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 499system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 604system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency 605system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency 606system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency 607system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency 608system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency 609system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency 610system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency 611system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency
	612system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
603system.cpu.icache.tags.replacements 18130 # number of replacements 604system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use 605system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. 606system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks. 607system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks. 608system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 609system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor 610system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy 611system.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy 612system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 614system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 615system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id 616system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id 617system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id 618system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id 619system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses 620system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses	613system.cpu.icache.tags.replacements 18130 # number of replacements 614system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use 615system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. 616system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks. 617system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks. 618system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 619system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor 620system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy 621system.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy 622system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id 623system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 624system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 625system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id 626system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id 627system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id 628system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id 629system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses 630system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses
	631system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
621system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits 622system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits 623system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits 624system.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits 625system.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits 626system.cpu.icache.overall_hits::total 198770599 # number of overall hits 627system.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses 628system.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 681system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 682system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency 684system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 686system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 688system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency	632system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits 633system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits 634system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits 635system.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits 636system.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits 637system.cpu.icache.overall_hits::total 198770599 # number of overall hits 638system.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses 639system.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 692system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 693system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 694system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency 695system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency 696system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 697system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency 698system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 699system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
	700system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
689system.cpu.l2cache.tags.replacements 112376 # number of replacements 690system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use 691system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks. 692system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks. 693system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks. 694system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit. 695system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id 708system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id 709system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses 710system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses	701system.cpu.l2cache.tags.replacements 112376 # number of replacements 702system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use 703system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks. 704system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks. 705system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks. 706system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit. 707system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor 708system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 715system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 716system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 717system.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id 718system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id 719system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id 720system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id 721system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses 722system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses
	723system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
711system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits 712system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits 713system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits 714system.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits 715system.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits 716system.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits 717system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits 718system.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits --- 136 unchanged lines hidden (view full) --- 855system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency 856system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency 857system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter. 858system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data. 859system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 860system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. 861system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 862system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	724system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits 725system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits 726system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits 727system.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits 728system.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits 729system.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits 730system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits 731system.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits --- 136 unchanged lines hidden (view full) --- 868system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency 869system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency 870system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter. 871system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data. 872system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 873system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. 874system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 875system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	876system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
863system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution 867system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution 870system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 887system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 888system.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram 889system.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks) 890system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 891system.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks) 892system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 893system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks) 894system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)	877system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution 879system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution 880system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution 881system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution 882system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution 883system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution 884system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 901system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 902system.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram 903system.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks) 904system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 905system.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks) 906system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 907system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks) 908system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
	909system.membus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
895system.membus.trans_dist::ReadResp 42981 # Transaction distribution 896system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution 897system.membus.trans_dist::CleanEvict 12558 # Transaction distribution 898system.membus.trans_dist::ReadExReq 100949 # Transaction distribution 899system.membus.trans_dist::ReadExResp 100949 # Transaction distribution 900system.membus.trans_dist::ReadSharedReq 42981 # Transaction distribution 901system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397628 # Packet count per connected master and slave (bytes) 902system.membus.pkt_count::total 397628 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden ---	910system.membus.trans_dist::ReadResp 42981 # Transaction distribution 911system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution 912system.membus.trans_dist::CleanEvict 12558 # Transaction distribution 913system.membus.trans_dist::ReadExReq 100949 # Transaction distribution 914system.membus.trans_dist::ReadExResp 100949 # Transaction distribution 915system.membus.trans_dist::ReadSharedReq 42981 # Transaction distribution 916system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397628 # Packet count per connected master and slave (bytes) 917system.membus.pkt_count::total 397628 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.362632 # Number of seconds simulated
4sim_ticks 362631828500 # Number of ticks simulated
5final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 177215 # Simulator instruction rate (inst/s)
8host_op_rate 191948 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 126858592 # Simulator tick rate (ticks/s)
10host_mem_usage 271160 # Number of bytes of host memory used
11host_seconds 2858.55 # Real time elapsed on the host

7host_inst_rate 379372 # Simulator instruction rate (inst/s)
8host_op_rate 410911 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 271571493 # Simulator tick rate (ticks/s)
10host_mem_usage 317732 # Number of bytes of host memory used
11host_seconds 1335.31 # Real time elapsed on the host

12sim_insts 506579366 # Number of instructions simulated
13sim_ops 548692589 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory
22system.physmem.bytes_written::total 6221440 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory

--- 257 unchanged lines hidden (view full) ---

281system.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ)
282system.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ)
283system.physmem_1.averagePower 684.623774 # Core power per rank (mW)
284system.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states
285system.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states
286system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
287system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states
288system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

17system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory
19system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory
23system.physmem.bytes_written::total 6221440 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory

--- 257 unchanged lines hidden (view full) ---

282system.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ)
283system.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ)
284system.physmem_1.averagePower 684.623774 # Core power per rank (mW)
285system.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states
286system.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states
287system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
288system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states
289system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

290system.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

289system.cpu.branchPred.lookups 131880511 # Number of BP lookups
290system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted
291system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect
292system.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups
293system.cpu.branchPred.BTBHits 60518878 # Number of BTB hits
294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
295system.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage
296system.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target.
297system.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions.
298system.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups.
299system.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits.
300system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses.
301system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches.
302system.cpu_clk_domain.clock 500 # Clock period in ticks

291system.cpu.branchPred.lookups 131880511 # Number of BP lookups
292system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted
293system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect
294system.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups
295system.cpu.branchPred.BTBHits 60518878 # Number of BTB hits
296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
297system.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage
298system.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target.
299system.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions.
300system.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups.
301system.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits.
302system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses.
303system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches.
304system.cpu_clk_domain.clock 500 # Clock period in ticks

305system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

303system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

324system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
325system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
326system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
327system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
328system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
329system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
330system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
331system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

306system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

327system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
328system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
329system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
330system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
331system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
332system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
333system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
334system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

335system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

332system.cpu.dtb.walker.walks 0 # Table walker walks requested
333system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
334system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
335system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
336system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
337system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
338system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
339system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

353system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
354system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
355system.cpu.dtb.read_accesses 0 # DTB read accesses
356system.cpu.dtb.write_accesses 0 # DTB write accesses
357system.cpu.dtb.inst_accesses 0 # ITB inst accesses
358system.cpu.dtb.hits 0 # DTB hits
359system.cpu.dtb.misses 0 # DTB misses
360system.cpu.dtb.accesses 0 # DTB accesses

336system.cpu.dtb.walker.walks 0 # Table walker walks requested
337system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
338system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
339system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
340system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
341system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
342system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
343system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

357system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
358system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
359system.cpu.dtb.read_accesses 0 # DTB read accesses
360system.cpu.dtb.write_accesses 0 # DTB write accesses
361system.cpu.dtb.inst_accesses 0 # ITB inst accesses
362system.cpu.dtb.hits 0 # DTB hits
363system.cpu.dtb.misses 0 # DTB misses
364system.cpu.dtb.accesses 0 # DTB accesses

365system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

361system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

382system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
383system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
384system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
385system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
386system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
387system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
388system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
389system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

366system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

387system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
388system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
389system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
390system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
391system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
392system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
393system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
394system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

395system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

390system.cpu.itb.walker.walks 0 # Table walker walks requested
391system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
392system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
393system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
394system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
395system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
396system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
397system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

412system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
413system.cpu.itb.read_accesses 0 # DTB read accesses
414system.cpu.itb.write_accesses 0 # DTB write accesses
415system.cpu.itb.inst_accesses 0 # ITB inst accesses
416system.cpu.itb.hits 0 # DTB hits
417system.cpu.itb.misses 0 # DTB misses
418system.cpu.itb.accesses 0 # DTB accesses
419system.cpu.workload.num_syscalls 548 # Number of system calls

396system.cpu.itb.walker.walks 0 # Table walker walks requested
397system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
398system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
399system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
400system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
401system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
402system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
403system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

418system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
419system.cpu.itb.read_accesses 0 # DTB read accesses
420system.cpu.itb.write_accesses 0 # DTB write accesses
421system.cpu.itb.inst_accesses 0 # ITB inst accesses
422system.cpu.itb.hits 0 # DTB hits
423system.cpu.itb.misses 0 # DTB misses
424system.cpu.itb.accesses 0 # DTB accesses
425system.cpu.workload.num_syscalls 548 # Number of system calls

426system.cpu.pwrStateResidencyTicks::ON 362631828500 # Cumulative time (in ticks) in various power states

420system.cpu.numCycles 725263657 # number of cpu cycles simulated
421system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
422system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
423system.cpu.committedInsts 506579366 # Number of instructions committed
424system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed
425system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit
426system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
427system.cpu.cpi 1.431688 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

458system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
459system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
460system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction
461system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
462system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
463system.cpu.op_class_0::total 548692589 # Class of committed instruction
464system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked
465system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped

427system.cpu.numCycles 725263657 # number of cpu cycles simulated
428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
430system.cpu.committedInsts 506579366 # Number of instructions committed
431system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed
432system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit
433system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
434system.cpu.cpi 1.431688 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

465system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
466system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
467system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction
468system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
469system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
470system.cpu.op_class_0::total 548692589 # Class of committed instruction
471system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked
472system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped

473system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

466system.cpu.dcache.tags.replacements 1141477 # number of replacements
467system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use
468system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks.
469system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks.
470system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks.
471system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit.
472system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor
473system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy
474system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy
475system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
476system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
477system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
478system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id
479system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id
480system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
481system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses
482system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses

474system.cpu.dcache.tags.replacements 1141477 # number of replacements
475system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use
476system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks.
477system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks.
478system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks.
479system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit.
480system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor
481system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy
482system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy
483system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
484system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
485system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
486system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id
487system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id
488system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
489system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses
490system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses

491system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

483system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits
484system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits
485system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits
486system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits
487system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits
488system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits
489system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
490system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

595system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency
596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency
597system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency
598system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency
599system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency
600system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency
601system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency
602system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency

492system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits
493system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits
494system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits
495system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits
496system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits
497system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits
498system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
499system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

604system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency
605system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency
606system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency
607system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency
608system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency
609system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency
610system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency
611system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency

612system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

603system.cpu.icache.tags.replacements 18130 # number of replacements
604system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use
605system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks.
606system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks.
607system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks.
608system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
609system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor
610system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy
611system.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy
612system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id
613system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
614system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
615system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
616system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id
617system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id
618system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id
619system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses
620system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses

613system.cpu.icache.tags.replacements 18130 # number of replacements
614system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use
615system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks.
616system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks.
617system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks.
618system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
619system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor
620system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy
621system.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy
622system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id
623system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
624system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
625system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
626system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id
627system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id
628system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id
629system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses
630system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses

631system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

621system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits
622system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits
623system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits
624system.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits
625system.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits
626system.cpu.icache.overall_hits::total 198770599 # number of overall hits
627system.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses
628system.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

681system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses
682system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses
683system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency
684system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency
685system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
686system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
687system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
688system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency

632system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits
633system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits
634system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits
635system.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits
636system.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits
637system.cpu.icache.overall_hits::total 198770599 # number of overall hits
638system.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses
639system.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

692system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses
693system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses
694system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency
695system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency
696system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
697system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
698system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
699system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency

700system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

689system.cpu.l2cache.tags.replacements 112376 # number of replacements
690system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use
691system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks.
692system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks.
693system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks.
694system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit.
695system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor
696system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor

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703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
705system.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id
706system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id
707system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id
708system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id
709system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses
710system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses

701system.cpu.l2cache.tags.replacements 112376 # number of replacements
702system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use
703system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks.
704system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks.
705system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks.
706system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit.
707system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor
708system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

715system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
716system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
717system.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id
718system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id
719system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id
720system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id
721system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses
722system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses

723system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

711system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits
712system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits
713system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits
714system.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits
715system.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits
716system.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits
717system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits
718system.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits

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855system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
856system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
857system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter.
858system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
859system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
860system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter.
861system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
862system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

724system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits
725system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits
726system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits
727system.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits
728system.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits
729system.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits
730system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits
731system.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits

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868system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
869system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
870system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter.
871system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
872system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
873system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter.
874system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
875system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

876system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states

863system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution
864system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution
865system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution
866system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution
867system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution
868system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution
869system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution
870system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution

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887system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
888system.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram
889system.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks)
890system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
891system.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks)
892system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
893system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks)
894system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)

877system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution
878system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution
879system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution
880system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution
881system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution
882system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution
883system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution
884system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution

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901system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
902system.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram
903system.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks)
904system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
905system.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks)
906system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
907system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks)
908system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)

909system.membus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states