| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362632 # Number of seconds simulated 4sim_ticks 362631828500 # Number of ticks simulated 5final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362632 # Number of seconds simulated 4sim_ticks 362631828500 # Number of ticks simulated 5final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 285981 # Simulator instruction rate (inst/s) 8host_op_rate 309756 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 204718125 # Simulator tick rate (ticks/s) 10host_mem_usage 275016 # Number of bytes of host memory used 11host_seconds 1771.37 # Real time elapsed on the host | 7host_inst_rate 263885 # Simulator instruction rate (inst/s) 8host_op_rate 285822 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 188900227 # Simulator tick rate (ticks/s) 10host_mem_usage 275012 # Number of bytes of host memory used 11host_seconds 1919.70 # Real time elapsed on the host |
| 12sim_insts 506579366 # Number of instructions simulated 13sim_ops 548692589 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory --- 525 unchanged lines hidden (view full) --- 545system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755 # average overall miss latency 546system.cpu.dcache.overall_avg_miss_latency::total 23108.545755 # average overall miss latency 547system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 506579366 # Number of instructions simulated 13sim_ops 548692589 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory --- 525 unchanged lines hidden (view full) --- 545system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755 # average overall miss latency 546system.cpu.dcache.overall_avg_miss_latency::total 23108.545755 # average overall miss latency 547system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 553system.cpu.dcache.fast_writes 0 # number of fast writes performed 554system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 555system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks 556system.cpu.dcache.writebacks::total 1069336 # number of writebacks 557system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits 558system.cpu.dcache.ReadReq_mshr_hits::total 66650 # number of ReadReq MSHR hits 559system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344781 # number of WriteReq MSHR hits 560system.cpu.dcache.WriteReq_mshr_hits::total 344781 # number of WriteReq MSHR hits 561system.cpu.dcache.demand_mshr_hits::cpu.data 411431 # number of demand (read+write) MSHR hits 562system.cpu.dcache.demand_mshr_hits::total 411431 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 597system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency 598system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency 599system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency 600system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency 601system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency 602system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency 603system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency 604system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency | 553system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks 554system.cpu.dcache.writebacks::total 1069336 # number of writebacks 555system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits 556system.cpu.dcache.ReadReq_mshr_hits::total 66650 # number of ReadReq MSHR hits 557system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344781 # number of WriteReq MSHR hits 558system.cpu.dcache.WriteReq_mshr_hits::total 344781 # number of WriteReq MSHR hits 559system.cpu.dcache.demand_mshr_hits::cpu.data 411431 # number of demand (read+write) MSHR hits 560system.cpu.dcache.demand_mshr_hits::total 411431 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 595system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency 596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency 597system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency 598system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency 599system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency 600system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency 601system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency 602system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency |
| 605system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 606system.cpu.icache.tags.replacements 18130 # number of replacements 607system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use 608system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. 609system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks. 610system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks. 611system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 612system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor 613system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 658system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency 659system.cpu.icache.overall_avg_miss_latency::total 22750.787461 # average overall miss latency 660system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 661system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 662system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 663system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 664system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 665system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 603system.cpu.icache.tags.replacements 18130 # number of replacements 604system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use 605system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. 606system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks. 607system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks. 608system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 609system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor 610system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 655system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency 656system.cpu.icache.overall_avg_miss_latency::total 22750.787461 # average overall miss latency 657system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 658system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 659system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 660system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 661system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 662system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 666system.cpu.icache.fast_writes 0 # number of fast writes performed 667system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 668system.cpu.icache.writebacks::writebacks 18130 # number of writebacks 669system.cpu.icache.writebacks::total 18130 # number of writebacks 670system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses 671system.cpu.icache.ReadReq_mshr_misses::total 20001 # number of ReadReq MSHR misses 672system.cpu.icache.demand_mshr_misses::cpu.inst 20001 # number of demand (read+write) MSHR misses 673system.cpu.icache.demand_mshr_misses::total 20001 # number of demand (read+write) MSHR misses 674system.cpu.icache.overall_mshr_misses::cpu.inst 20001 # number of overall MSHR misses 675system.cpu.icache.overall_mshr_misses::total 20001 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 686system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 687system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 688system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency 689system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency 690system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 691system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency 692system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 693system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency | 663system.cpu.icache.writebacks::writebacks 18130 # number of writebacks 664system.cpu.icache.writebacks::total 18130 # number of writebacks 665system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses 666system.cpu.icache.ReadReq_mshr_misses::total 20001 # number of ReadReq MSHR misses 667system.cpu.icache.demand_mshr_misses::cpu.inst 20001 # number of demand (read+write) MSHR misses 668system.cpu.icache.demand_mshr_misses::total 20001 # number of demand (read+write) MSHR misses 669system.cpu.icache.overall_mshr_misses::cpu.inst 20001 # number of overall MSHR misses 670system.cpu.icache.overall_mshr_misses::total 20001 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 681system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 682system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency 684system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 686system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 688system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency |
| 694system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 695system.cpu.l2cache.tags.replacements 112376 # number of replacements 696system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use 697system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks. 698system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks. 699system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks. 700system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit. 701system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor 702system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 795system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency 796system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617 # average overall miss latency 797system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 798system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 799system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 800system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 801system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 802system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 689system.cpu.l2cache.tags.replacements 112376 # number of replacements 690system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use 691system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks. 692system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks. 693system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks. 694system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit. 695system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 789system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency 790system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617 # average overall miss latency 791system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 792system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 793system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 794system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 795system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 796system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 803system.cpu.l2cache.fast_writes 0 # number of fast writes performed 804system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 805system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks 806system.cpu.l2cache.writebacks::total 97210 # number of writebacks 807system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 808system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 809system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 810system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 811system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 812system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits --- 44 unchanged lines hidden (view full) --- 857system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357 # average ReadSharedReq mshr miss latency 858system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357 # average ReadSharedReq mshr miss latency 859system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency 860system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency 861system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency 862system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency 863system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency 864system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency | 797system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks 798system.cpu.l2cache.writebacks::total 97210 # number of writebacks 799system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 800system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 801system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 802system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 803system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 804system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits --- 44 unchanged lines hidden (view full) --- 849system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357 # average ReadSharedReq mshr miss latency 850system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357 # average ReadSharedReq mshr miss latency 851system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency 852system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency 853system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency 854system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency 855system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency 856system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency |
| 865system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 866system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter. 867system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data. 868system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 869system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. 870system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 871system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 872system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution --- 57 unchanged lines hidden --- | 857system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter. 858system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data. 859system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 860system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. 861system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 862system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 863system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution --- 57 unchanged lines hidden --- |