| stats.txt (11336:b318499f676c) | stats.txt (11388:bd4125134e77) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.363578 # Number of seconds simulated 4sim_ticks 363578056500 # Number of ticks simulated 5final_tick 363578056500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.363609 # Number of seconds simulated 4sim_ticks 363608804500 # Number of ticks simulated 5final_tick 363608804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 233007 # Simulator instruction rate (inst/s) 8host_op_rate 252377 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 167231069 # Simulator tick rate (ticks/s) 10host_mem_usage 322224 # Number of bytes of host memory used 11host_seconds 2174.11 # Real time elapsed on the host 12sim_insts 506582156 # Number of instructions simulated 13sim_ops 548695379 # Number of ops (including micro ops) simulated | 7host_inst_rate 100066 # Simulator instruction rate (inst/s) 8host_op_rate 108385 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 71824585 # Simulator tick rate (ticks/s) 10host_mem_usage 304984 # Number of bytes of host memory used 11host_seconds 5062.46 # Real time elapsed on the host 12sim_insts 506579366 # Number of instructions simulated 13sim_ops 548692589 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 179648 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9032384 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9212032 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 179648 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 179648 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6219008 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6219008 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2807 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 141131 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 143938 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 97172 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 97172 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 494111 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 24843039 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 25337151 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 494111 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 494111 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17105015 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17105015 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17105015 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 494111 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 24843039 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 42442165 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 143938 # Number of read requests accepted 40system.physmem.writeReqs 97172 # Number of write requests accepted 41system.physmem.readBursts 143938 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 97172 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 9204928 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue 45system.physmem.bytesWritten 6217152 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 9212032 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 6219008 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 179584 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9028480 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9208064 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 179584 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 179584 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6218624 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6218624 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2806 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 141070 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 143876 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 97166 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 97166 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 493893 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 24830202 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 25324095 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 493893 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 493893 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17102512 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17102512 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17102512 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 493893 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 24830202 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 42426607 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 143876 # Number of read requests accepted 40system.physmem.writeReqs 97166 # Number of write requests accepted 41system.physmem.readBursts 143876 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 97166 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 9201472 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue 45system.physmem.bytesWritten 6217344 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 9208064 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 6218624 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 51system.physmem.perBankRdBursts::0 9337 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8920 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8993 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8670 # Per bank write bursts 55system.physmem.perBankRdBursts::4 9385 # Per bank write bursts | 51system.physmem.perBankRdBursts::0 9345 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8917 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8955 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8654 # Per bank write bursts 55system.physmem.perBankRdBursts::4 9386 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::5 9354 # Per bank write bursts | 56system.physmem.perBankRdBursts::5 9354 # Per bank write bursts |
| 57system.physmem.perBankRdBursts::6 8954 # Per bank write bursts | 57system.physmem.perBankRdBursts::6 8955 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::7 8104 # Per bank write bursts | 58system.physmem.perBankRdBursts::7 8104 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::8 8602 # Per bank write bursts | 59system.physmem.perBankRdBursts::8 8603 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::9 8629 # Per bank write bursts | 60system.physmem.perBankRdBursts::9 8629 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::10 8738 # Per bank write bursts 62system.physmem.perBankRdBursts::11 9458 # Per bank write bursts 63system.physmem.perBankRdBursts::12 9338 # Per bank write bursts 64system.physmem.perBankRdBursts::13 9514 # Per bank write bursts 65system.physmem.perBankRdBursts::14 8722 # Per bank write bursts 66system.physmem.perBankRdBursts::15 9109 # Per bank write bursts 67system.physmem.perBankWrBursts::0 6210 # Per bank write bursts 68system.physmem.perBankWrBursts::1 6096 # Per bank write bursts | 61system.physmem.perBankRdBursts::10 8742 # Per bank write bursts 62system.physmem.perBankRdBursts::11 9454 # Per bank write bursts 63system.physmem.perBankRdBursts::12 9335 # Per bank write bursts 64system.physmem.perBankRdBursts::13 9509 # Per bank write bursts 65system.physmem.perBankRdBursts::14 8712 # Per bank write bursts 66system.physmem.perBankRdBursts::15 9119 # Per bank write bursts 67system.physmem.perBankWrBursts::0 6212 # Per bank write bursts 68system.physmem.perBankWrBursts::1 6095 # Per bank write bursts |
| 69system.physmem.perBankWrBursts::2 6031 # Per bank write bursts | 69system.physmem.perBankWrBursts::2 6031 # Per bank write bursts |
| 70system.physmem.perBankWrBursts::3 5885 # Per bank write bursts 71system.physmem.perBankWrBursts::4 6239 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6240 # Per bank write bursts 73system.physmem.perBankWrBursts::6 6045 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5507 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5786 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5860 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5977 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6497 # Per bank write bursts 79system.physmem.perBankWrBursts::12 6353 # Per bank write bursts 80system.physmem.perBankWrBursts::13 6323 # Per bank write bursts 81system.physmem.perBankWrBursts::14 6005 # Per bank write bursts 82system.physmem.perBankWrBursts::15 6089 # Per bank write bursts | 70system.physmem.perBankWrBursts::3 5882 # Per bank write bursts 71system.physmem.perBankWrBursts::4 6240 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6242 # Per bank write bursts 73system.physmem.perBankWrBursts::6 6046 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5509 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5790 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5862 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5980 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6494 # Per bank write bursts 79system.physmem.perBankWrBursts::12 6352 # Per bank write bursts 80system.physmem.perBankWrBursts::13 6321 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5998 # Per bank write bursts 82system.physmem.perBankWrBursts::15 6092 # Per bank write bursts |
| 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 363578030500 # Total gap between requests | 85system.physmem.totGap 363608778500 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 143938 # Read request sizes (log2) | 92system.physmem.readPktSize::6 143876 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 99system.physmem.writePktSize::6 97172 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 143477 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 330 # What read queue length does an incoming req see | 99system.physmem.writePktSize::6 97166 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 143433 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 320 # What read queue length does an incoming req see |
| 102system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 102system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 2944 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 3098 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5669 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5692 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5696 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5718 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5719 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5721 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5717 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5713 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5750 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5692 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5700 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5635 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 2923 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 3110 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5563 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5694 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5686 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5706 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5721 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5699 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5724 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5731 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5734 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5734 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5738 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5711 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5678 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5681 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5643 # What write queue length does an incoming req see |
| 164system.physmem.wrQLenPdf::32 5621 # What write queue length does an incoming req see | 164system.physmem.wrQLenPdf::32 5621 # What write queue length does an incoming req see |
| 165system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see | 165system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see |
| 168system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see | 168system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see |
| 173system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see | 173system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see |
| 174system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see | 174system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see |
| 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 65452 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 235.611563 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 156.275569 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 241.348204 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 24841 37.95% 37.95% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 18422 28.15% 66.10% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 6870 10.50% 76.60% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7970 12.18% 88.77% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2117 3.23% 92.01% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1100 1.68% 93.69% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 791 1.21% 94.90% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 584 0.89% 95.79% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 2757 4.21% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65452 # Bytes accessed per row activation | 196system.physmem.bytesPerActivate::samples 65427 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 235.654638 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 156.256012 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 241.782834 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 24843 37.97% 37.97% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 18425 28.16% 66.13% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 6952 10.63% 76.76% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7899 12.07% 88.83% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2020 3.09% 91.92% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1104 1.69% 93.61% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 778 1.19% 94.79% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 662 1.01% 95.81% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 2744 4.19% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65427 # Bytes accessed per row activation |
| 210system.physmem.rdPerTurnAround::samples 5612 # Reads before turning the bus around for writes | 210system.physmem.rdPerTurnAround::samples 5612 # Reads before turning the bus around for writes |
| 211system.physmem.rdPerTurnAround::mean 25.626515 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 380.491009 # Reads before turning the bus around for writes | 211system.physmem.rdPerTurnAround::mean 25.618496 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 380.574654 # Reads before turning the bus around for writes |
| 213system.physmem.rdPerTurnAround::0-1023 5610 99.96% 99.96% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5612 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5612 # Writes before turning the bus around for reads | 213system.physmem.rdPerTurnAround::0-1023 5610 99.96% 99.96% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5612 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5612 # Writes before turning the bus around for reads |
| 218system.physmem.wrPerTurnAround::mean 17.309872 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.213078 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 2.394006 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16-17 2658 47.36% 47.36% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18-19 2810 50.07% 97.43% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::20-21 50 0.89% 98.33% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::22-23 29 0.52% 98.84% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-25 20 0.36% 99.20% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::26-27 11 0.20% 99.39% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::28-29 6 0.11% 99.50% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::30-31 6 0.11% 99.61% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-33 3 0.05% 99.66% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::34-35 7 0.12% 99.79% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-37 1 0.02% 99.80% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::44-45 1 0.02% 99.86% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::46-47 1 0.02% 99.88% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::48-49 1 0.02% 99.89% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::50-51 1 0.02% 99.91% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::52-53 2 0.04% 99.95% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::56-57 1 0.02% 99.96% # Writes before turning the bus around for reads | 218system.physmem.wrPerTurnAround::mean 17.310406 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.214262 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 2.369355 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16-17 2682 47.79% 47.79% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18-19 2777 49.48% 97.27% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::20-21 56 1.00% 98.27% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::22-23 33 0.59% 98.86% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-25 17 0.30% 99.16% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::26-27 10 0.18% 99.34% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::28-29 7 0.12% 99.47% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::30-31 5 0.09% 99.55% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-33 7 0.12% 99.68% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::34-35 4 0.07% 99.75% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-37 3 0.05% 99.80% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::40-41 2 0.04% 99.84% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::42-43 4 0.07% 99.91% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::50-51 1 0.02% 99.95% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::52-53 1 0.02% 99.96% # Writes before turning the bus around for reads |
| 240system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads | 237system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads |
| 241system.physmem.wrPerTurnAround::96-97 1 0.02% 100.00% # Writes before turning the bus around for reads | 238system.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads |
| 242system.physmem.wrPerTurnAround::total 5612 # Writes before turning the bus around for reads | 239system.physmem.wrPerTurnAround::total 5612 # Writes before turning the bus around for reads |
| 243system.physmem.totQLat 1537591000 # Total ticks spent queuing 244system.physmem.totMemAccLat 4234347250 # Total ticks spent from burst creation until serviced by the DRAM 245system.physmem.totBusLat 719135000 # Total ticks spent in databus transfers 246system.physmem.avgQLat 10690.56 # Average queueing delay per DRAM burst | 240system.physmem.totQLat 1539890250 # Total ticks spent queuing 241system.physmem.totMemAccLat 4235634000 # Total ticks spent from burst creation until serviced by the DRAM 242system.physmem.totBusLat 718865000 # Total ticks spent in databus transfers 243system.physmem.avgQLat 10710.57 # Average queueing delay per DRAM burst |
| 247system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 244system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 248system.physmem.avgMemAccLat 29440.56 # Average memory access latency per DRAM burst 249system.physmem.avgRdBW 25.32 # Average DRAM read bandwidth in MiByte/s | 245system.physmem.avgMemAccLat 29460.57 # Average memory access latency per DRAM burst 246system.physmem.avgRdBW 25.31 # Average DRAM read bandwidth in MiByte/s |
| 250system.physmem.avgWrBW 17.10 # Average achieved write bandwidth in MiByte/s | 247system.physmem.avgWrBW 17.10 # Average achieved write bandwidth in MiByte/s |
| 251system.physmem.avgRdBWSys 25.34 # Average system read bandwidth in MiByte/s 252system.physmem.avgWrBWSys 17.11 # Average system write bandwidth in MiByte/s | 248system.physmem.avgRdBWSys 25.32 # Average system read bandwidth in MiByte/s 249system.physmem.avgWrBWSys 17.10 # Average system write bandwidth in MiByte/s |
| 253system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 254system.physmem.busUtil 0.33 # Data bus utilization in percentage 255system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 256system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes | 250system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 251system.physmem.busUtil 0.33 # Data bus utilization in percentage 252system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 253system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes |
| 257system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 258system.physmem.avgWrQLen 19.82 # Average write queue length when enqueuing 259system.physmem.readRowHits 110822 # Number of row buffer hits during reads 260system.physmem.writeRowHits 64690 # Number of row buffer hits during writes | 254system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 255system.physmem.avgWrQLen 19.45 # Average write queue length when enqueuing 256system.physmem.readRowHits 110770 # Number of row buffer hits during reads 257system.physmem.writeRowHits 64716 # Number of row buffer hits during writes |
| 261system.physmem.readRowHitRate 77.05 # Row buffer hit rate for reads | 258system.physmem.readRowHitRate 77.05 # Row buffer hit rate for reads |
| 262system.physmem.writeRowHitRate 66.57 # Row buffer hit rate for writes 263system.physmem.avgGap 1507934.26 # Average gap between requests | 259system.physmem.writeRowHitRate 66.60 # Row buffer hit rate for writes 260system.physmem.avgGap 1508487.23 # Average gap between requests |
| 264system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined | 261system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined |
| 265system.physmem_0.actEnergy 249245640 # Energy for activate commands per rank (pJ) 266system.physmem_0.preEnergy 135997125 # Energy for precharge commands per rank (pJ) 267system.physmem_0.readEnergy 559174200 # Energy for read commands per rank (pJ) 268system.physmem_0.writeEnergy 312459120 # Energy for write commands per rank (pJ) 269system.physmem_0.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ) 270system.physmem_0.actBackEnergy 47224643355 # Energy for active background per rank (pJ) 271system.physmem_0.preBackEnergy 176717716500 # Energy for precharge background per rank (pJ) 272system.physmem_0.totalEnergy 248945936580 # Total energy per rank (pJ) 273system.physmem_0.averagePower 684.723644 # Core power per rank (mW) 274system.physmem_0.memoryStateTime::IDLE 293681207750 # Time in different power states 275system.physmem_0.memoryStateTime::REF 12140440000 # Time in different power states | 262system.physmem_0.actEnergy 249041520 # Energy for activate commands per rank (pJ) 263system.physmem_0.preEnergy 135885750 # Energy for precharge commands per rank (pJ) 264system.physmem_0.readEnergy 558807600 # Energy for read commands per rank (pJ) 265system.physmem_0.writeEnergy 312407280 # Energy for write commands per rank (pJ) 266system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) 267system.physmem_0.actBackEnergy 47272879035 # Energy for active background per rank (pJ) 268system.physmem_0.preBackEnergy 176694091500 # Energy for precharge background per rank (pJ) 269system.physmem_0.totalEnergy 248971847565 # Total energy per rank (pJ) 270system.physmem_0.averagePower 684.736255 # Core power per rank (mW) 271system.physmem_0.memoryStateTime::IDLE 293641319750 # Time in different power states 272system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states |
| 276system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 273system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 277system.physmem_0.memoryStateTime::ACT 57750923750 # Time in different power states | 274system.physmem_0.memoryStateTime::ACT 57820495250 # Time in different power states |
| 278system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 275system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 279system.physmem_1.actEnergy 245314440 # Energy for activate commands per rank (pJ) 280system.physmem_1.preEnergy 133852125 # Energy for precharge commands per rank (pJ) 281system.physmem_1.readEnergy 562247400 # Energy for read commands per rank (pJ) 282system.physmem_1.writeEnergy 316716480 # Energy for write commands per rank (pJ) 283system.physmem_1.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ) 284system.physmem_1.actBackEnergy 46957257495 # Energy for active background per rank (pJ) 285system.physmem_1.preBackEnergy 176952265500 # Energy for precharge background per rank (pJ) 286system.physmem_1.totalEnergy 248914354080 # Total energy per rank (pJ) 287system.physmem_1.averagePower 684.636777 # Core power per rank (mW) 288system.physmem_1.memoryStateTime::IDLE 294072895750 # Time in different power states 289system.physmem_1.memoryStateTime::REF 12140440000 # Time in different power states | 276system.physmem_1.actEnergy 245269080 # Energy for activate commands per rank (pJ) 277system.physmem_1.preEnergy 133827375 # Energy for precharge commands per rank (pJ) 278system.physmem_1.readEnergy 562192800 # Energy for read commands per rank (pJ) 279system.physmem_1.writeEnergy 316684080 # Energy for write commands per rank (pJ) 280system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) 281system.physmem_1.actBackEnergy 46853247600 # Energy for active background per rank (pJ) 282system.physmem_1.preBackEnergy 177062189250 # Energy for precharge background per rank (pJ) 283system.physmem_1.totalEnergy 248922145065 # Total energy per rank (pJ) 284system.physmem_1.averagePower 684.599560 # Core power per rank (mW) 285system.physmem_1.memoryStateTime::IDLE 294255473500 # Time in different power states 286system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states |
| 290system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 287system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 291system.physmem_1.memoryStateTime::ACT 57359475250 # Time in different power states | 288system.physmem_1.memoryStateTime::ACT 57206580500 # Time in different power states |
| 292system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 289system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 293system.cpu.branchPred.lookups 131892190 # Number of BP lookups 294system.cpu.branchPred.condPredicted 98029664 # Number of conditional branches predicted 295system.cpu.branchPred.condIncorrect 6137262 # Number of conditional branches incorrect 296system.cpu.branchPred.BTBLookups 68271020 # Number of BTB lookups 297system.cpu.branchPred.BTBHits 64393265 # Number of BTB hits | 290system.cpu.branchPred.lookups 131890227 # Number of BP lookups 291system.cpu.branchPred.condPredicted 98029520 # Number of conditional branches predicted 292system.cpu.branchPred.condIncorrect 6134595 # Number of conditional branches incorrect 293system.cpu.branchPred.BTBLookups 68518889 # Number of BTB lookups 294system.cpu.branchPred.BTBHits 64416393 # Number of BTB hits |
| 298system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 295system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 299system.cpu.branchPred.BTBHitPct 94.320057 # BTB Hit Percentage 300system.cpu.branchPred.usedRAS 9980136 # Number of times the RAS was used to get a target. 301system.cpu.branchPred.RASInCorrect 17826 # Number of incorrect RAS predictions. | 296system.cpu.branchPred.BTBHitPct 94.012606 # BTB Hit Percentage 297system.cpu.branchPred.usedRAS 9980436 # Number of times the RAS was used to get a target. 298system.cpu.branchPred.RASInCorrect 18277 # Number of incorrect RAS predictions. |
| 302system.cpu_clk_domain.clock 500 # Clock period in ticks 303system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 412system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 413system.cpu.itb.read_accesses 0 # DTB read accesses 414system.cpu.itb.write_accesses 0 # DTB write accesses 415system.cpu.itb.inst_accesses 0 # ITB inst accesses 416system.cpu.itb.hits 0 # DTB hits 417system.cpu.itb.misses 0 # DTB misses 418system.cpu.itb.accesses 0 # DTB accesses 419system.cpu.workload.num_syscalls 548 # Number of system calls | 299system.cpu_clk_domain.clock 500 # Clock period in ticks 300system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 409system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 410system.cpu.itb.read_accesses 0 # DTB read accesses 411system.cpu.itb.write_accesses 0 # DTB write accesses 412system.cpu.itb.inst_accesses 0 # ITB inst accesses 413system.cpu.itb.hits 0 # DTB hits 414system.cpu.itb.misses 0 # DTB misses 415system.cpu.itb.accesses 0 # DTB accesses 416system.cpu.workload.num_syscalls 548 # Number of system calls |
| 420system.cpu.numCycles 727156113 # number of cpu cycles simulated | 417system.cpu.numCycles 727217609 # number of cpu cycles simulated |
| 421system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 422system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 418system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 419system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 423system.cpu.committedInsts 506582156 # Number of instructions committed 424system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed 425system.cpu.discardedOps 13195789 # Number of ops (including micro ops) which were discarded before commit | 420system.cpu.committedInsts 506579366 # Number of instructions committed 421system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed 422system.cpu.discardedOps 13188504 # Number of ops (including micro ops) which were discarded before commit |
| 426system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 423system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 427system.cpu.cpi 1.435416 # CPI: cycles per instruction 428system.cpu.ipc 0.696662 # IPC: instructions per cycle 429system.cpu.tickCycles 690690437 # Number of cycles that the object actually ticked 430system.cpu.idleCycles 36465676 # Total number of cycles that the object has spent stopped 431system.cpu.dcache.tags.replacements 1139983 # number of replacements 432system.cpu.dcache.tags.tagsinuse 4070.787946 # Cycle average of tags in use 433system.cpu.dcache.tags.total_refs 171168228 # Total number of references to valid blocks. 434system.cpu.dcache.tags.sampled_refs 1144079 # Sample count of references to valid blocks. 435system.cpu.dcache.tags.avg_refs 149.612245 # Average number of references to valid blocks. | 424system.cpu.cpi 1.435545 # CPI: cycles per instruction 425system.cpu.ipc 0.696599 # IPC: instructions per cycle 426system.cpu.tickCycles 690736700 # Number of cycles that the object actually ticked 427system.cpu.idleCycles 36480909 # Total number of cycles that the object has spent stopped 428system.cpu.dcache.tags.replacements 1141376 # number of replacements 429system.cpu.dcache.tags.tagsinuse 4070.790078 # Cycle average of tags in use 430system.cpu.dcache.tags.total_refs 171162589 # Total number of references to valid blocks. 431system.cpu.dcache.tags.sampled_refs 1145472 # Sample count of references to valid blocks. 432system.cpu.dcache.tags.avg_refs 149.425380 # Average number of references to valid blocks. |
| 436system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. | 433system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. |
| 437system.cpu.dcache.tags.occ_blocks::cpu.data 4070.787946 # Average occupied blocks per requestor | 434system.cpu.dcache.tags.occ_blocks::cpu.data 4070.790078 # Average occupied blocks per requestor |
| 438system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy 439system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy 440system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 441system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 442system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id 445system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 435system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy 436system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy 437system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 438system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 439system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 440system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id 441system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id 442system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 446system.cpu.dcache.tags.tag_accesses 346591347 # Number of tag accesses 447system.cpu.dcache.tags.data_accesses 346591347 # Number of data accesses 448system.cpu.dcache.ReadReq_hits::cpu.data 114649758 # number of ReadReq hits 449system.cpu.dcache.ReadReq_hits::total 114649758 # number of ReadReq hits 450system.cpu.dcache.WriteReq_hits::cpu.data 53538635 # number of WriteReq hits 451system.cpu.dcache.WriteReq_hits::total 53538635 # number of WriteReq hits 452system.cpu.dcache.SoftPFReq_hits::cpu.data 2753 # number of SoftPFReq hits 453system.cpu.dcache.SoftPFReq_hits::total 2753 # number of SoftPFReq hits | 443system.cpu.dcache.tags.tag_accesses 346584178 # Number of tag accesses 444system.cpu.dcache.tags.data_accesses 346584178 # Number of data accesses 445system.cpu.dcache.ReadReq_hits::cpu.data 114644865 # number of ReadReq hits 446system.cpu.dcache.ReadReq_hits::total 114644865 # number of ReadReq hits 447system.cpu.dcache.WriteReq_hits::cpu.data 53537898 # number of WriteReq hits 448system.cpu.dcache.WriteReq_hits::total 53537898 # number of WriteReq hits 449system.cpu.dcache.SoftPFReq_hits::cpu.data 2744 # number of SoftPFReq hits 450system.cpu.dcache.SoftPFReq_hits::total 2744 # number of SoftPFReq hits |
| 454system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 455system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 456system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 457system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits | 451system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 452system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 453system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 454system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits |
| 458system.cpu.dcache.demand_hits::cpu.data 168188393 # number of demand (read+write) hits 459system.cpu.dcache.demand_hits::total 168188393 # number of demand (read+write) hits 460system.cpu.dcache.overall_hits::cpu.data 168191146 # number of overall hits 461system.cpu.dcache.overall_hits::total 168191146 # number of overall hits 462system.cpu.dcache.ReadReq_misses::cpu.data 854719 # number of ReadReq misses 463system.cpu.dcache.ReadReq_misses::total 854719 # number of ReadReq misses 464system.cpu.dcache.WriteReq_misses::cpu.data 700671 # number of WriteReq misses 465system.cpu.dcache.WriteReq_misses::total 700671 # number of WriteReq misses 466system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses 467system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses 468system.cpu.dcache.demand_misses::cpu.data 1555390 # number of demand (read+write) misses 469system.cpu.dcache.demand_misses::total 1555390 # number of demand (read+write) misses 470system.cpu.dcache.overall_misses::cpu.data 1555406 # number of overall misses 471system.cpu.dcache.overall_misses::total 1555406 # number of overall misses 472system.cpu.dcache.ReadReq_miss_latency::cpu.data 14046321000 # number of ReadReq miss cycles 473system.cpu.dcache.ReadReq_miss_latency::total 14046321000 # number of ReadReq miss cycles 474system.cpu.dcache.WriteReq_miss_latency::cpu.data 21904504500 # number of WriteReq miss cycles 475system.cpu.dcache.WriteReq_miss_latency::total 21904504500 # number of WriteReq miss cycles 476system.cpu.dcache.demand_miss_latency::cpu.data 35950825500 # number of demand (read+write) miss cycles 477system.cpu.dcache.demand_miss_latency::total 35950825500 # number of demand (read+write) miss cycles 478system.cpu.dcache.overall_miss_latency::cpu.data 35950825500 # number of overall miss cycles 479system.cpu.dcache.overall_miss_latency::total 35950825500 # number of overall miss cycles 480system.cpu.dcache.ReadReq_accesses::cpu.data 115504477 # number of ReadReq accesses(hits+misses) 481system.cpu.dcache.ReadReq_accesses::total 115504477 # number of ReadReq accesses(hits+misses) 482system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 483system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 484system.cpu.dcache.SoftPFReq_accesses::cpu.data 2769 # number of SoftPFReq accesses(hits+misses) 485system.cpu.dcache.SoftPFReq_accesses::total 2769 # number of SoftPFReq accesses(hits+misses) | 455system.cpu.dcache.demand_hits::cpu.data 168182763 # number of demand (read+write) hits 456system.cpu.dcache.demand_hits::total 168182763 # number of demand (read+write) hits 457system.cpu.dcache.overall_hits::cpu.data 168185507 # number of overall hits 458system.cpu.dcache.overall_hits::total 168185507 # number of overall hits 459system.cpu.dcache.ReadReq_misses::cpu.data 855598 # number of ReadReq misses 460system.cpu.dcache.ReadReq_misses::total 855598 # number of ReadReq misses 461system.cpu.dcache.WriteReq_misses::cpu.data 701151 # number of WriteReq misses 462system.cpu.dcache.WriteReq_misses::total 701151 # number of WriteReq misses 463system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 464system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses 465system.cpu.dcache.demand_misses::cpu.data 1556749 # number of demand (read+write) misses 466system.cpu.dcache.demand_misses::total 1556749 # number of demand (read+write) misses 467system.cpu.dcache.overall_misses::cpu.data 1556764 # number of overall misses 468system.cpu.dcache.overall_misses::total 1556764 # number of overall misses 469system.cpu.dcache.ReadReq_miss_latency::cpu.data 14056066500 # number of ReadReq miss cycles 470system.cpu.dcache.ReadReq_miss_latency::total 14056066500 # number of ReadReq miss cycles 471system.cpu.dcache.WriteReq_miss_latency::cpu.data 21917357000 # number of WriteReq miss cycles 472system.cpu.dcache.WriteReq_miss_latency::total 21917357000 # number of WriteReq miss cycles 473system.cpu.dcache.demand_miss_latency::cpu.data 35973423500 # number of demand (read+write) miss cycles 474system.cpu.dcache.demand_miss_latency::total 35973423500 # number of demand (read+write) miss cycles 475system.cpu.dcache.overall_miss_latency::cpu.data 35973423500 # number of overall miss cycles 476system.cpu.dcache.overall_miss_latency::total 35973423500 # number of overall miss cycles 477system.cpu.dcache.ReadReq_accesses::cpu.data 115500463 # number of ReadReq accesses(hits+misses) 478system.cpu.dcache.ReadReq_accesses::total 115500463 # number of ReadReq accesses(hits+misses) 479system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 480system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 481system.cpu.dcache.SoftPFReq_accesses::cpu.data 2759 # number of SoftPFReq accesses(hits+misses) 482system.cpu.dcache.SoftPFReq_accesses::total 2759 # number of SoftPFReq accesses(hits+misses) |
| 486system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 487system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 488system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 489system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) | 483system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 484system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 485system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 486system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) |
| 490system.cpu.dcache.demand_accesses::cpu.data 169743783 # number of demand (read+write) accesses 491system.cpu.dcache.demand_accesses::total 169743783 # number of demand (read+write) accesses 492system.cpu.dcache.overall_accesses::cpu.data 169746552 # number of overall (read+write) accesses 493system.cpu.dcache.overall_accesses::total 169746552 # number of overall (read+write) accesses 494system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses 496system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses 498system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005778 # miss rate for SoftPFReq accesses 499system.cpu.dcache.SoftPFReq_miss_rate::total 0.005778 # miss rate for SoftPFReq accesses 500system.cpu.dcache.demand_miss_rate::cpu.data 0.009163 # miss rate for demand accesses 501system.cpu.dcache.demand_miss_rate::total 0.009163 # miss rate for demand accesses 502system.cpu.dcache.overall_miss_rate::cpu.data 0.009163 # miss rate for overall accesses 503system.cpu.dcache.overall_miss_rate::total 0.009163 # miss rate for overall accesses 504system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16433.846679 # average ReadReq miss latency 505system.cpu.dcache.ReadReq_avg_miss_latency::total 16433.846679 # average ReadReq miss latency 506system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31262.182251 # average WriteReq miss latency 507system.cpu.dcache.WriteReq_avg_miss_latency::total 31262.182251 # average WriteReq miss latency 508system.cpu.dcache.demand_avg_miss_latency::cpu.data 23113.704923 # average overall miss latency 509system.cpu.dcache.demand_avg_miss_latency::total 23113.704923 # average overall miss latency 510system.cpu.dcache.overall_avg_miss_latency::cpu.data 23113.467159 # average overall miss latency 511system.cpu.dcache.overall_avg_miss_latency::total 23113.467159 # average overall miss latency | 487system.cpu.dcache.demand_accesses::cpu.data 169739512 # number of demand (read+write) accesses 488system.cpu.dcache.demand_accesses::total 169739512 # number of demand (read+write) accesses 489system.cpu.dcache.overall_accesses::cpu.data 169742271 # number of overall (read+write) accesses 490system.cpu.dcache.overall_accesses::total 169742271 # number of overall (read+write) accesses 491system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007408 # miss rate for ReadReq accesses 492system.cpu.dcache.ReadReq_miss_rate::total 0.007408 # miss rate for ReadReq accesses 493system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012927 # miss rate for WriteReq accesses 494system.cpu.dcache.WriteReq_miss_rate::total 0.012927 # miss rate for WriteReq accesses 495system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005437 # miss rate for SoftPFReq accesses 496system.cpu.dcache.SoftPFReq_miss_rate::total 0.005437 # miss rate for SoftPFReq accesses 497system.cpu.dcache.demand_miss_rate::cpu.data 0.009171 # miss rate for demand accesses 498system.cpu.dcache.demand_miss_rate::total 0.009171 # miss rate for demand accesses 499system.cpu.dcache.overall_miss_rate::cpu.data 0.009171 # miss rate for overall accesses 500system.cpu.dcache.overall_miss_rate::total 0.009171 # miss rate for overall accesses 501system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.353619 # average ReadReq miss latency 502system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.353619 # average ReadReq miss latency 503system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31259.111090 # average WriteReq miss latency 504system.cpu.dcache.WriteReq_avg_miss_latency::total 31259.111090 # average WriteReq miss latency 505system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.043429 # average overall miss latency 506system.cpu.dcache.demand_avg_miss_latency::total 23108.043429 # average overall miss latency 507system.cpu.dcache.overall_avg_miss_latency::cpu.data 23107.820774 # average overall miss latency 508system.cpu.dcache.overall_avg_miss_latency::total 23107.820774 # average overall miss latency |
| 512system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 517system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 518system.cpu.dcache.fast_writes 0 # number of fast writes performed 519system.cpu.dcache.cache_copies 0 # number of cache copies performed | 509system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 510system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 511system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 512system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 513system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 514system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 515system.cpu.dcache.fast_writes 0 # number of fast writes performed 516system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 520system.cpu.dcache.writebacks::writebacks 1068257 # number of writebacks 521system.cpu.dcache.writebacks::total 1068257 # number of writebacks 522system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66817 # number of ReadReq MSHR hits 523system.cpu.dcache.ReadReq_mshr_hits::total 66817 # number of ReadReq MSHR hits 524system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344507 # number of WriteReq MSHR hits 525system.cpu.dcache.WriteReq_mshr_hits::total 344507 # number of WriteReq MSHR hits 526system.cpu.dcache.demand_mshr_hits::cpu.data 411324 # number of demand (read+write) MSHR hits 527system.cpu.dcache.demand_mshr_hits::total 411324 # number of demand (read+write) MSHR hits 528system.cpu.dcache.overall_mshr_hits::cpu.data 411324 # number of overall MSHR hits 529system.cpu.dcache.overall_mshr_hits::total 411324 # number of overall MSHR hits 530system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787902 # number of ReadReq MSHR misses 531system.cpu.dcache.ReadReq_mshr_misses::total 787902 # number of ReadReq MSHR misses 532system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356164 # number of WriteReq MSHR misses 533system.cpu.dcache.WriteReq_mshr_misses::total 356164 # number of WriteReq MSHR misses 534system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses 535system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses 536system.cpu.dcache.demand_mshr_misses::cpu.data 1144066 # number of demand (read+write) MSHR misses 537system.cpu.dcache.demand_mshr_misses::total 1144066 # number of demand (read+write) MSHR misses 538system.cpu.dcache.overall_mshr_misses::cpu.data 1144079 # number of overall MSHR misses 539system.cpu.dcache.overall_mshr_misses::total 1144079 # number of overall MSHR misses 540system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12362476000 # number of ReadReq MSHR miss cycles 541system.cpu.dcache.ReadReq_mshr_miss_latency::total 12362476000 # number of ReadReq MSHR miss cycles 542system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11126251500 # number of WriteReq MSHR miss cycles 543system.cpu.dcache.WriteReq_mshr_miss_latency::total 11126251500 # number of WriteReq MSHR miss cycles 544system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1030500 # number of SoftPFReq MSHR miss cycles 545system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1030500 # number of SoftPFReq MSHR miss cycles 546system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23488727500 # number of demand (read+write) MSHR miss cycles 547system.cpu.dcache.demand_mshr_miss_latency::total 23488727500 # number of demand (read+write) MSHR miss cycles 548system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23489758000 # number of overall MSHR miss cycles 549system.cpu.dcache.overall_mshr_miss_latency::total 23489758000 # number of overall MSHR miss cycles 550system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses 551system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses 552system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses 553system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses 554system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004695 # mshr miss rate for SoftPFReq accesses 555system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004695 # mshr miss rate for SoftPFReq accesses 556system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses 557system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses 558system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses 559system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses 560system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15690.372661 # average ReadReq mshr miss latency 561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15690.372661 # average ReadReq mshr miss latency 562system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.124392 # average WriteReq mshr miss latency 563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.124392 # average WriteReq mshr miss latency 564system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79269.230769 # average SoftPFReq mshr miss latency 565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79269.230769 # average SoftPFReq mshr miss latency 566system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20530.919982 # average overall mshr miss latency 567system.cpu.dcache.demand_avg_mshr_miss_latency::total 20530.919982 # average overall mshr miss latency 568system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20531.587417 # average overall mshr miss latency 569system.cpu.dcache.overall_avg_mshr_miss_latency::total 20531.587417 # average overall mshr miss latency | 517system.cpu.dcache.writebacks::writebacks 1069283 # number of writebacks 518system.cpu.dcache.writebacks::total 1069283 # number of writebacks 519system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66543 # number of ReadReq MSHR hits 520system.cpu.dcache.ReadReq_mshr_hits::total 66543 # number of ReadReq MSHR hits 521system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344746 # number of WriteReq MSHR hits 522system.cpu.dcache.WriteReq_mshr_hits::total 344746 # number of WriteReq MSHR hits 523system.cpu.dcache.demand_mshr_hits::cpu.data 411289 # number of demand (read+write) MSHR hits 524system.cpu.dcache.demand_mshr_hits::total 411289 # number of demand (read+write) MSHR hits 525system.cpu.dcache.overall_mshr_hits::cpu.data 411289 # number of overall MSHR hits 526system.cpu.dcache.overall_mshr_hits::total 411289 # number of overall MSHR hits 527system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789055 # number of ReadReq MSHR misses 528system.cpu.dcache.ReadReq_mshr_misses::total 789055 # number of ReadReq MSHR misses 529system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356405 # number of WriteReq MSHR misses 530system.cpu.dcache.WriteReq_mshr_misses::total 356405 # number of WriteReq MSHR misses 531system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 532system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 533system.cpu.dcache.demand_mshr_misses::cpu.data 1145460 # number of demand (read+write) MSHR misses 534system.cpu.dcache.demand_mshr_misses::total 1145460 # number of demand (read+write) MSHR misses 535system.cpu.dcache.overall_mshr_misses::cpu.data 1145472 # number of overall MSHR misses 536system.cpu.dcache.overall_mshr_misses::total 1145472 # number of overall MSHR misses 537system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372636000 # number of ReadReq MSHR miss cycles 538system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372636000 # number of ReadReq MSHR miss cycles 539system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11132196500 # number of WriteReq MSHR miss cycles 540system.cpu.dcache.WriteReq_mshr_miss_latency::total 11132196500 # number of WriteReq MSHR miss cycles 541system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 944000 # number of SoftPFReq MSHR miss cycles 542system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 944000 # number of SoftPFReq MSHR miss cycles 543system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23504832500 # number of demand (read+write) MSHR miss cycles 544system.cpu.dcache.demand_mshr_miss_latency::total 23504832500 # number of demand (read+write) MSHR miss cycles 545system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23505776500 # number of overall MSHR miss cycles 546system.cpu.dcache.overall_mshr_miss_latency::total 23505776500 # number of overall MSHR miss cycles 547system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006832 # mshr miss rate for ReadReq accesses 548system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006832 # mshr miss rate for ReadReq accesses 549system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses 550system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses 551system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004349 # mshr miss rate for SoftPFReq accesses 552system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004349 # mshr miss rate for SoftPFReq accesses 553system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006748 # mshr miss rate for demand accesses 554system.cpu.dcache.demand_mshr_miss_rate::total 0.006748 # mshr miss rate for demand accesses 555system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006748 # mshr miss rate for overall accesses 556system.cpu.dcache.overall_mshr_miss_rate::total 0.006748 # mshr miss rate for overall accesses 557system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15680.321397 # average ReadReq mshr miss latency 558system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15680.321397 # average ReadReq mshr miss latency 559system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31234.681051 # average WriteReq mshr miss latency 560system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31234.681051 # average WriteReq mshr miss latency 561system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78666.666667 # average SoftPFReq mshr miss latency 562system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78666.666667 # average SoftPFReq mshr miss latency 563system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20519.994151 # average overall mshr miss latency 564system.cpu.dcache.demand_avg_mshr_miss_latency::total 20519.994151 # average overall mshr miss latency 565system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20520.603297 # average overall mshr miss latency 566system.cpu.dcache.overall_avg_mshr_miss_latency::total 20520.603297 # average overall mshr miss latency |
| 570system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 567system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 571system.cpu.icache.tags.replacements 17711 # number of replacements 572system.cpu.icache.tags.tagsinuse 1188.286888 # Cycle average of tags in use 573system.cpu.icache.tags.total_refs 199302654 # Total number of references to valid blocks. 574system.cpu.icache.tags.sampled_refs 19583 # Sample count of references to valid blocks. 575system.cpu.icache.tags.avg_refs 10177.330031 # Average number of references to valid blocks. | 568system.cpu.icache.tags.replacements 17687 # number of replacements 569system.cpu.icache.tags.tagsinuse 1188.299437 # Cycle average of tags in use 570system.cpu.icache.tags.total_refs 199347924 # Total number of references to valid blocks. 571system.cpu.icache.tags.sampled_refs 19559 # Sample count of references to valid blocks. 572system.cpu.icache.tags.avg_refs 10192.132727 # Average number of references to valid blocks. |
| 576system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 573system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 577system.cpu.icache.tags.occ_blocks::cpu.inst 1188.286888 # Average occupied blocks per requestor 578system.cpu.icache.tags.occ_percent::cpu.inst 0.580218 # Average percentage of cache occupancy 579system.cpu.icache.tags.occ_percent::total 0.580218 # Average percentage of cache occupancy | 574system.cpu.icache.tags.occ_blocks::cpu.inst 1188.299437 # Average occupied blocks per requestor 575system.cpu.icache.tags.occ_percent::cpu.inst 0.580224 # Average percentage of cache occupancy 576system.cpu.icache.tags.occ_percent::total 0.580224 # Average percentage of cache occupancy |
| 580system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 581system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id | 577system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 578system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id |
| 582system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 583system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 584system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id 585system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id | 579system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 580system.cpu.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 581system.cpu.icache.tags.age_task_id_blocks_1024::3 305 # Occupied blocks per task id 582system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id |
| 586system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id | 583system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id |
| 587system.cpu.icache.tags.tag_accesses 398664057 # Number of tag accesses 588system.cpu.icache.tags.data_accesses 398664057 # Number of data accesses 589system.cpu.icache.ReadReq_hits::cpu.inst 199302654 # number of ReadReq hits 590system.cpu.icache.ReadReq_hits::total 199302654 # number of ReadReq hits 591system.cpu.icache.demand_hits::cpu.inst 199302654 # number of demand (read+write) hits 592system.cpu.icache.demand_hits::total 199302654 # number of demand (read+write) hits 593system.cpu.icache.overall_hits::cpu.inst 199302654 # number of overall hits 594system.cpu.icache.overall_hits::total 199302654 # number of overall hits 595system.cpu.icache.ReadReq_misses::cpu.inst 19583 # number of ReadReq misses 596system.cpu.icache.ReadReq_misses::total 19583 # number of ReadReq misses 597system.cpu.icache.demand_misses::cpu.inst 19583 # number of demand (read+write) misses 598system.cpu.icache.demand_misses::total 19583 # number of demand (read+write) misses 599system.cpu.icache.overall_misses::cpu.inst 19583 # number of overall misses 600system.cpu.icache.overall_misses::total 19583 # number of overall misses 601system.cpu.icache.ReadReq_miss_latency::cpu.inst 449788500 # number of ReadReq miss cycles 602system.cpu.icache.ReadReq_miss_latency::total 449788500 # number of ReadReq miss cycles 603system.cpu.icache.demand_miss_latency::cpu.inst 449788500 # number of demand (read+write) miss cycles 604system.cpu.icache.demand_miss_latency::total 449788500 # number of demand (read+write) miss cycles 605system.cpu.icache.overall_miss_latency::cpu.inst 449788500 # number of overall miss cycles 606system.cpu.icache.overall_miss_latency::total 449788500 # number of overall miss cycles 607system.cpu.icache.ReadReq_accesses::cpu.inst 199322237 # number of ReadReq accesses(hits+misses) 608system.cpu.icache.ReadReq_accesses::total 199322237 # number of ReadReq accesses(hits+misses) 609system.cpu.icache.demand_accesses::cpu.inst 199322237 # number of demand (read+write) accesses 610system.cpu.icache.demand_accesses::total 199322237 # number of demand (read+write) accesses 611system.cpu.icache.overall_accesses::cpu.inst 199322237 # number of overall (read+write) accesses 612system.cpu.icache.overall_accesses::total 199322237 # number of overall (read+write) accesses | 584system.cpu.icache.tags.tag_accesses 398754525 # Number of tag accesses 585system.cpu.icache.tags.data_accesses 398754525 # Number of data accesses 586system.cpu.icache.ReadReq_hits::cpu.inst 199347924 # number of ReadReq hits 587system.cpu.icache.ReadReq_hits::total 199347924 # number of ReadReq hits 588system.cpu.icache.demand_hits::cpu.inst 199347924 # number of demand (read+write) hits 589system.cpu.icache.demand_hits::total 199347924 # number of demand (read+write) hits 590system.cpu.icache.overall_hits::cpu.inst 199347924 # number of overall hits 591system.cpu.icache.overall_hits::total 199347924 # number of overall hits 592system.cpu.icache.ReadReq_misses::cpu.inst 19559 # number of ReadReq misses 593system.cpu.icache.ReadReq_misses::total 19559 # number of ReadReq misses 594system.cpu.icache.demand_misses::cpu.inst 19559 # number of demand (read+write) misses 595system.cpu.icache.demand_misses::total 19559 # number of demand (read+write) misses 596system.cpu.icache.overall_misses::cpu.inst 19559 # number of overall misses 597system.cpu.icache.overall_misses::total 19559 # number of overall misses 598system.cpu.icache.ReadReq_miss_latency::cpu.inst 449446000 # number of ReadReq miss cycles 599system.cpu.icache.ReadReq_miss_latency::total 449446000 # number of ReadReq miss cycles 600system.cpu.icache.demand_miss_latency::cpu.inst 449446000 # number of demand (read+write) miss cycles 601system.cpu.icache.demand_miss_latency::total 449446000 # number of demand (read+write) miss cycles 602system.cpu.icache.overall_miss_latency::cpu.inst 449446000 # number of overall miss cycles 603system.cpu.icache.overall_miss_latency::total 449446000 # number of overall miss cycles 604system.cpu.icache.ReadReq_accesses::cpu.inst 199367483 # number of ReadReq accesses(hits+misses) 605system.cpu.icache.ReadReq_accesses::total 199367483 # number of ReadReq accesses(hits+misses) 606system.cpu.icache.demand_accesses::cpu.inst 199367483 # number of demand (read+write) accesses 607system.cpu.icache.demand_accesses::total 199367483 # number of demand (read+write) accesses 608system.cpu.icache.overall_accesses::cpu.inst 199367483 # number of overall (read+write) accesses 609system.cpu.icache.overall_accesses::total 199367483 # number of overall (read+write) accesses |
| 613system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses 614system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses 615system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses 616system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses 617system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses 618system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses | 610system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses 611system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses 612system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses 613system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses 614system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses 615system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses |
| 619system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22968.314354 # average ReadReq miss latency 620system.cpu.icache.ReadReq_avg_miss_latency::total 22968.314354 # average ReadReq miss latency 621system.cpu.icache.demand_avg_miss_latency::cpu.inst 22968.314354 # average overall miss latency 622system.cpu.icache.demand_avg_miss_latency::total 22968.314354 # average overall miss latency 623system.cpu.icache.overall_avg_miss_latency::cpu.inst 22968.314354 # average overall miss latency 624system.cpu.icache.overall_avg_miss_latency::total 22968.314354 # average overall miss latency | 616system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22978.986656 # average ReadReq miss latency 617system.cpu.icache.ReadReq_avg_miss_latency::total 22978.986656 # average ReadReq miss latency 618system.cpu.icache.demand_avg_miss_latency::cpu.inst 22978.986656 # average overall miss latency 619system.cpu.icache.demand_avg_miss_latency::total 22978.986656 # average overall miss latency 620system.cpu.icache.overall_avg_miss_latency::cpu.inst 22978.986656 # average overall miss latency 621system.cpu.icache.overall_avg_miss_latency::total 22978.986656 # average overall miss latency |
| 625system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 626system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 627system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 628system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 629system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 630system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 631system.cpu.icache.fast_writes 0 # number of fast writes performed 632system.cpu.icache.cache_copies 0 # number of cache copies performed | 622system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 623system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 624system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 625system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 626system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 627system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 628system.cpu.icache.fast_writes 0 # number of fast writes performed 629system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 633system.cpu.icache.writebacks::writebacks 17711 # number of writebacks 634system.cpu.icache.writebacks::total 17711 # number of writebacks 635system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19583 # number of ReadReq MSHR misses 636system.cpu.icache.ReadReq_mshr_misses::total 19583 # number of ReadReq MSHR misses 637system.cpu.icache.demand_mshr_misses::cpu.inst 19583 # number of demand (read+write) MSHR misses 638system.cpu.icache.demand_mshr_misses::total 19583 # number of demand (read+write) MSHR misses 639system.cpu.icache.overall_mshr_misses::cpu.inst 19583 # number of overall MSHR misses 640system.cpu.icache.overall_mshr_misses::total 19583 # number of overall MSHR misses 641system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 430205500 # number of ReadReq MSHR miss cycles 642system.cpu.icache.ReadReq_mshr_miss_latency::total 430205500 # number of ReadReq MSHR miss cycles 643system.cpu.icache.demand_mshr_miss_latency::cpu.inst 430205500 # number of demand (read+write) MSHR miss cycles 644system.cpu.icache.demand_mshr_miss_latency::total 430205500 # number of demand (read+write) MSHR miss cycles 645system.cpu.icache.overall_mshr_miss_latency::cpu.inst 430205500 # number of overall MSHR miss cycles 646system.cpu.icache.overall_mshr_miss_latency::total 430205500 # number of overall MSHR miss cycles | 630system.cpu.icache.writebacks::writebacks 17687 # number of writebacks 631system.cpu.icache.writebacks::total 17687 # number of writebacks 632system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19559 # number of ReadReq MSHR misses 633system.cpu.icache.ReadReq_mshr_misses::total 19559 # number of ReadReq MSHR misses 634system.cpu.icache.demand_mshr_misses::cpu.inst 19559 # number of demand (read+write) MSHR misses 635system.cpu.icache.demand_mshr_misses::total 19559 # number of demand (read+write) MSHR misses 636system.cpu.icache.overall_mshr_misses::cpu.inst 19559 # number of overall MSHR misses 637system.cpu.icache.overall_mshr_misses::total 19559 # number of overall MSHR misses 638system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429887000 # number of ReadReq MSHR miss cycles 639system.cpu.icache.ReadReq_mshr_miss_latency::total 429887000 # number of ReadReq MSHR miss cycles 640system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429887000 # number of demand (read+write) MSHR miss cycles 641system.cpu.icache.demand_mshr_miss_latency::total 429887000 # number of demand (read+write) MSHR miss cycles 642system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429887000 # number of overall MSHR miss cycles 643system.cpu.icache.overall_mshr_miss_latency::total 429887000 # number of overall MSHR miss cycles |
| 647system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses 648system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses 649system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses 650system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses 651system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses 652system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses | 644system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses 645system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses 646system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses 647system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses 648system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses 649system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses |
| 653system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21968.314354 # average ReadReq mshr miss latency 654system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21968.314354 # average ReadReq mshr miss latency 655system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21968.314354 # average overall mshr miss latency 656system.cpu.icache.demand_avg_mshr_miss_latency::total 21968.314354 # average overall mshr miss latency 657system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21968.314354 # average overall mshr miss latency 658system.cpu.icache.overall_avg_mshr_miss_latency::total 21968.314354 # average overall mshr miss latency | 650system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21978.986656 # average ReadReq mshr miss latency 651system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21978.986656 # average ReadReq mshr miss latency 652system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21978.986656 # average overall mshr miss latency 653system.cpu.icache.demand_avg_mshr_miss_latency::total 21978.986656 # average overall mshr miss latency 654system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21978.986656 # average overall mshr miss latency 655system.cpu.icache.overall_avg_mshr_miss_latency::total 21978.986656 # average overall mshr miss latency |
| 659system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 656system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 660system.cpu.l2cache.tags.replacements 112366 # number of replacements 661system.cpu.l2cache.tags.tagsinuse 27636.027175 # Cycle average of tags in use 662system.cpu.l2cache.tags.total_refs 1768435 # Total number of references to valid blocks. 663system.cpu.l2cache.tags.sampled_refs 143575 # Sample count of references to valid blocks. 664system.cpu.l2cache.tags.avg_refs 12.317151 # Average number of references to valid blocks. 665system.cpu.l2cache.tags.warmup_cycle 163253484000 # Cycle when the warmup percentage was hit. 666system.cpu.l2cache.tags.occ_blocks::writebacks 23509.918170 # Average occupied blocks per requestor 667system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.069777 # Average occupied blocks per requestor 668system.cpu.l2cache.tags.occ_blocks::cpu.data 3818.039228 # Average occupied blocks per requestor 669system.cpu.l2cache.tags.occ_percent::writebacks 0.717466 # Average percentage of cache occupancy 670system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009402 # Average percentage of cache occupancy 671system.cpu.l2cache.tags.occ_percent::cpu.data 0.116517 # Average percentage of cache occupancy 672system.cpu.l2cache.tags.occ_percent::total 0.843385 # Average percentage of cache occupancy 673system.cpu.l2cache.tags.occ_task_id_blocks::1024 31209 # Occupied blocks per task id | 657system.cpu.l2cache.tags.replacements 112304 # number of replacements 658system.cpu.l2cache.tags.tagsinuse 27637.803257 # Cycle average of tags in use 659system.cpu.l2cache.tags.total_refs 1771245 # Total number of references to valid blocks. 660system.cpu.l2cache.tags.sampled_refs 143514 # Sample count of references to valid blocks. 661system.cpu.l2cache.tags.avg_refs 12.341967 # Average number of references to valid blocks. 662system.cpu.l2cache.tags.warmup_cycle 163256914000 # Cycle when the warmup percentage was hit. 663system.cpu.l2cache.tags.occ_blocks::writebacks 23514.215736 # Average occupied blocks per requestor 664system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.353699 # Average occupied blocks per requestor 665system.cpu.l2cache.tags.occ_blocks::cpu.data 3816.233823 # Average occupied blocks per requestor 666system.cpu.l2cache.tags.occ_percent::writebacks 0.717597 # Average percentage of cache occupancy 667system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009380 # Average percentage of cache occupancy 668system.cpu.l2cache.tags.occ_percent::cpu.data 0.116462 # Average percentage of cache occupancy 669system.cpu.l2cache.tags.occ_percent::total 0.843439 # Average percentage of cache occupancy 670system.cpu.l2cache.tags.occ_task_id_blocks::1024 31210 # Occupied blocks per task id |
| 674system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 675system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id | 671system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 672system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id |
| 676system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4938 # Occupied blocks per task id 677system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25851 # Occupied blocks per task id 678system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952423 # Percentage of cache occupancy per task id 679system.cpu.l2cache.tags.tag_accesses 19031534 # Number of tag accesses 680system.cpu.l2cache.tags.data_accesses 19031534 # Number of data accesses 681system.cpu.l2cache.WritebackDirty_hits::writebacks 1068257 # number of WritebackDirty hits 682system.cpu.l2cache.WritebackDirty_hits::total 1068257 # number of WritebackDirty hits 683system.cpu.l2cache.WritebackClean_hits::writebacks 17475 # number of WritebackClean hits 684system.cpu.l2cache.WritebackClean_hits::total 17475 # number of WritebackClean hits 685system.cpu.l2cache.ReadExReq_hits::cpu.data 255492 # number of ReadExReq hits 686system.cpu.l2cache.ReadExReq_hits::total 255492 # number of ReadExReq hits 687system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16775 # number of ReadCleanReq hits 688system.cpu.l2cache.ReadCleanReq_hits::total 16775 # number of ReadCleanReq hits 689system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747442 # number of ReadSharedReq hits 690system.cpu.l2cache.ReadSharedReq_hits::total 747442 # number of ReadSharedReq hits 691system.cpu.l2cache.demand_hits::cpu.inst 16775 # number of demand (read+write) hits 692system.cpu.l2cache.demand_hits::cpu.data 1002934 # number of demand (read+write) hits 693system.cpu.l2cache.demand_hits::total 1019709 # number of demand (read+write) hits 694system.cpu.l2cache.overall_hits::cpu.inst 16775 # number of overall hits 695system.cpu.l2cache.overall_hits::cpu.data 1002934 # number of overall hits 696system.cpu.l2cache.overall_hits::total 1019709 # number of overall hits 697system.cpu.l2cache.ReadExReq_misses::cpu.data 100923 # number of ReadExReq misses 698system.cpu.l2cache.ReadExReq_misses::total 100923 # number of ReadExReq misses 699system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2808 # number of ReadCleanReq misses 700system.cpu.l2cache.ReadCleanReq_misses::total 2808 # number of ReadCleanReq misses 701system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40222 # number of ReadSharedReq misses 702system.cpu.l2cache.ReadSharedReq_misses::total 40222 # number of ReadSharedReq misses 703system.cpu.l2cache.demand_misses::cpu.inst 2808 # number of demand (read+write) misses 704system.cpu.l2cache.demand_misses::cpu.data 141145 # number of demand (read+write) misses 705system.cpu.l2cache.demand_misses::total 143953 # number of demand (read+write) misses 706system.cpu.l2cache.overall_misses::cpu.inst 2808 # number of overall misses 707system.cpu.l2cache.overall_misses::cpu.data 141145 # number of overall misses 708system.cpu.l2cache.overall_misses::total 143953 # number of overall misses 709system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7911788000 # number of ReadExReq miss cycles 710system.cpu.l2cache.ReadExReq_miss_latency::total 7911788000 # number of ReadExReq miss cycles 711system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 224015500 # number of ReadCleanReq miss cycles 712system.cpu.l2cache.ReadCleanReq_miss_latency::total 224015500 # number of ReadCleanReq miss cycles 713system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3310285500 # number of ReadSharedReq miss cycles 714system.cpu.l2cache.ReadSharedReq_miss_latency::total 3310285500 # number of ReadSharedReq miss cycles 715system.cpu.l2cache.demand_miss_latency::cpu.inst 224015500 # number of demand (read+write) miss cycles 716system.cpu.l2cache.demand_miss_latency::cpu.data 11222073500 # number of demand (read+write) miss cycles 717system.cpu.l2cache.demand_miss_latency::total 11446089000 # number of demand (read+write) miss cycles 718system.cpu.l2cache.overall_miss_latency::cpu.inst 224015500 # number of overall miss cycles 719system.cpu.l2cache.overall_miss_latency::cpu.data 11222073500 # number of overall miss cycles 720system.cpu.l2cache.overall_miss_latency::total 11446089000 # number of overall miss cycles 721system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068257 # number of WritebackDirty accesses(hits+misses) 722system.cpu.l2cache.WritebackDirty_accesses::total 1068257 # number of WritebackDirty accesses(hits+misses) 723system.cpu.l2cache.WritebackClean_accesses::writebacks 17475 # number of WritebackClean accesses(hits+misses) 724system.cpu.l2cache.WritebackClean_accesses::total 17475 # number of WritebackClean accesses(hits+misses) 725system.cpu.l2cache.ReadExReq_accesses::cpu.data 356415 # number of ReadExReq accesses(hits+misses) 726system.cpu.l2cache.ReadExReq_accesses::total 356415 # number of ReadExReq accesses(hits+misses) 727system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19583 # number of ReadCleanReq accesses(hits+misses) 728system.cpu.l2cache.ReadCleanReq_accesses::total 19583 # number of ReadCleanReq accesses(hits+misses) 729system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 787664 # number of ReadSharedReq accesses(hits+misses) 730system.cpu.l2cache.ReadSharedReq_accesses::total 787664 # number of ReadSharedReq accesses(hits+misses) 731system.cpu.l2cache.demand_accesses::cpu.inst 19583 # number of demand (read+write) accesses 732system.cpu.l2cache.demand_accesses::cpu.data 1144079 # number of demand (read+write) accesses 733system.cpu.l2cache.demand_accesses::total 1163662 # number of demand (read+write) accesses 734system.cpu.l2cache.overall_accesses::cpu.inst 19583 # number of overall (read+write) accesses 735system.cpu.l2cache.overall_accesses::cpu.data 1144079 # number of overall (read+write) accesses 736system.cpu.l2cache.overall_accesses::total 1163662 # number of overall (read+write) accesses 737system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283161 # miss rate for ReadExReq accesses 738system.cpu.l2cache.ReadExReq_miss_rate::total 0.283161 # miss rate for ReadExReq accesses 739system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.143390 # miss rate for ReadCleanReq accesses 740system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.143390 # miss rate for ReadCleanReq accesses 741system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051065 # miss rate for ReadSharedReq accesses 742system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051065 # miss rate for ReadSharedReq accesses 743system.cpu.l2cache.demand_miss_rate::cpu.inst 0.143390 # miss rate for demand accesses 744system.cpu.l2cache.demand_miss_rate::cpu.data 0.123370 # miss rate for demand accesses 745system.cpu.l2cache.demand_miss_rate::total 0.123707 # miss rate for demand accesses 746system.cpu.l2cache.overall_miss_rate::cpu.inst 0.143390 # miss rate for overall accesses 747system.cpu.l2cache.overall_miss_rate::cpu.data 0.123370 # miss rate for overall accesses 748system.cpu.l2cache.overall_miss_rate::total 0.123707 # miss rate for overall accesses 749system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78394.300605 # average ReadExReq miss latency 750system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78394.300605 # average ReadExReq miss latency 751system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79777.599715 # average ReadCleanReq miss latency 752system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79777.599715 # average ReadCleanReq miss latency 753system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82300.370444 # average ReadSharedReq miss latency 754system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82300.370444 # average ReadSharedReq miss latency 755system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79777.599715 # average overall miss latency 756system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79507.410819 # average overall miss latency 757system.cpu.l2cache.demand_avg_miss_latency::total 79512.681222 # average overall miss latency 758system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79777.599715 # average overall miss latency 759system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79507.410819 # average overall miss latency 760system.cpu.l2cache.overall_avg_miss_latency::total 79512.681222 # average overall miss latency | 673system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4944 # Occupied blocks per task id 674system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25846 # Occupied blocks per task id 675system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952454 # Percentage of cache occupancy per task id 676system.cpu.l2cache.tags.tag_accesses 19053033 # Number of tag accesses 677system.cpu.l2cache.tags.data_accesses 19053033 # Number of data accesses 678system.cpu.l2cache.WritebackDirty_hits::writebacks 1069283 # number of WritebackDirty hits 679system.cpu.l2cache.WritebackDirty_hits::total 1069283 # number of WritebackDirty hits 680system.cpu.l2cache.WritebackClean_hits::writebacks 17449 # number of WritebackClean hits 681system.cpu.l2cache.WritebackClean_hits::total 17449 # number of WritebackClean hits 682system.cpu.l2cache.ReadExReq_hits::cpu.data 255738 # number of ReadExReq hits 683system.cpu.l2cache.ReadExReq_hits::total 255738 # number of ReadExReq hits 684system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16752 # number of ReadCleanReq hits 685system.cpu.l2cache.ReadCleanReq_hits::total 16752 # number of ReadCleanReq hits 686system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748650 # number of ReadSharedReq hits 687system.cpu.l2cache.ReadSharedReq_hits::total 748650 # number of ReadSharedReq hits 688system.cpu.l2cache.demand_hits::cpu.inst 16752 # number of demand (read+write) hits 689system.cpu.l2cache.demand_hits::cpu.data 1004388 # number of demand (read+write) hits 690system.cpu.l2cache.demand_hits::total 1021140 # number of demand (read+write) hits 691system.cpu.l2cache.overall_hits::cpu.inst 16752 # number of overall hits 692system.cpu.l2cache.overall_hits::cpu.data 1004388 # number of overall hits 693system.cpu.l2cache.overall_hits::total 1021140 # number of overall hits 694system.cpu.l2cache.ReadExReq_misses::cpu.data 100917 # number of ReadExReq misses 695system.cpu.l2cache.ReadExReq_misses::total 100917 # number of ReadExReq misses 696system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2807 # number of ReadCleanReq misses 697system.cpu.l2cache.ReadCleanReq_misses::total 2807 # number of ReadCleanReq misses 698system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40167 # number of ReadSharedReq misses 699system.cpu.l2cache.ReadSharedReq_misses::total 40167 # number of ReadSharedReq misses 700system.cpu.l2cache.demand_misses::cpu.inst 2807 # number of demand (read+write) misses 701system.cpu.l2cache.demand_misses::cpu.data 141084 # number of demand (read+write) misses 702system.cpu.l2cache.demand_misses::total 143891 # number of demand (read+write) misses 703system.cpu.l2cache.overall_misses::cpu.inst 2807 # number of overall misses 704system.cpu.l2cache.overall_misses::cpu.data 141084 # number of overall misses 705system.cpu.l2cache.overall_misses::total 143891 # number of overall misses 706system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7914773500 # number of ReadExReq miss cycles 707system.cpu.l2cache.ReadExReq_miss_latency::total 7914773500 # number of ReadExReq miss cycles 708system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 223970500 # number of ReadCleanReq miss cycles 709system.cpu.l2cache.ReadCleanReq_miss_latency::total 223970500 # number of ReadCleanReq miss cycles 710system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3305851000 # number of ReadSharedReq miss cycles 711system.cpu.l2cache.ReadSharedReq_miss_latency::total 3305851000 # number of ReadSharedReq miss cycles 712system.cpu.l2cache.demand_miss_latency::cpu.inst 223970500 # number of demand (read+write) miss cycles 713system.cpu.l2cache.demand_miss_latency::cpu.data 11220624500 # number of demand (read+write) miss cycles 714system.cpu.l2cache.demand_miss_latency::total 11444595000 # number of demand (read+write) miss cycles 715system.cpu.l2cache.overall_miss_latency::cpu.inst 223970500 # number of overall miss cycles 716system.cpu.l2cache.overall_miss_latency::cpu.data 11220624500 # number of overall miss cycles 717system.cpu.l2cache.overall_miss_latency::total 11444595000 # number of overall miss cycles 718system.cpu.l2cache.WritebackDirty_accesses::writebacks 1069283 # number of WritebackDirty accesses(hits+misses) 719system.cpu.l2cache.WritebackDirty_accesses::total 1069283 # number of WritebackDirty accesses(hits+misses) 720system.cpu.l2cache.WritebackClean_accesses::writebacks 17449 # number of WritebackClean accesses(hits+misses) 721system.cpu.l2cache.WritebackClean_accesses::total 17449 # number of WritebackClean accesses(hits+misses) 722system.cpu.l2cache.ReadExReq_accesses::cpu.data 356655 # number of ReadExReq accesses(hits+misses) 723system.cpu.l2cache.ReadExReq_accesses::total 356655 # number of ReadExReq accesses(hits+misses) 724system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19559 # number of ReadCleanReq accesses(hits+misses) 725system.cpu.l2cache.ReadCleanReq_accesses::total 19559 # number of ReadCleanReq accesses(hits+misses) 726system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788817 # number of ReadSharedReq accesses(hits+misses) 727system.cpu.l2cache.ReadSharedReq_accesses::total 788817 # number of ReadSharedReq accesses(hits+misses) 728system.cpu.l2cache.demand_accesses::cpu.inst 19559 # number of demand (read+write) accesses 729system.cpu.l2cache.demand_accesses::cpu.data 1145472 # number of demand (read+write) accesses 730system.cpu.l2cache.demand_accesses::total 1165031 # number of demand (read+write) accesses 731system.cpu.l2cache.overall_accesses::cpu.inst 19559 # number of overall (read+write) accesses 732system.cpu.l2cache.overall_accesses::cpu.data 1145472 # number of overall (read+write) accesses 733system.cpu.l2cache.overall_accesses::total 1165031 # number of overall (read+write) accesses 734system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282954 # miss rate for ReadExReq accesses 735system.cpu.l2cache.ReadExReq_miss_rate::total 0.282954 # miss rate for ReadExReq accesses 736system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.143514 # miss rate for ReadCleanReq accesses 737system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.143514 # miss rate for ReadCleanReq accesses 738system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050921 # miss rate for ReadSharedReq accesses 739system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050921 # miss rate for ReadSharedReq accesses 740system.cpu.l2cache.demand_miss_rate::cpu.inst 0.143514 # miss rate for demand accesses 741system.cpu.l2cache.demand_miss_rate::cpu.data 0.123167 # miss rate for demand accesses 742system.cpu.l2cache.demand_miss_rate::total 0.123508 # miss rate for demand accesses 743system.cpu.l2cache.overall_miss_rate::cpu.inst 0.143514 # miss rate for overall accesses 744system.cpu.l2cache.overall_miss_rate::cpu.data 0.123167 # miss rate for overall accesses 745system.cpu.l2cache.overall_miss_rate::total 0.123508 # miss rate for overall accesses 746system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78428.545240 # average ReadExReq miss latency 747system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78428.545240 # average ReadExReq miss latency 748system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79789.989312 # average ReadCleanReq miss latency 749system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79789.989312 # average ReadCleanReq miss latency 750system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82302.661389 # average ReadSharedReq miss latency 751system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82302.661389 # average ReadSharedReq miss latency 752system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79789.989312 # average overall miss latency 753system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79531.516685 # average overall miss latency 754system.cpu.l2cache.demand_avg_miss_latency::total 79536.558923 # average overall miss latency 755system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79789.989312 # average overall miss latency 756system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79531.516685 # average overall miss latency 757system.cpu.l2cache.overall_avg_miss_latency::total 79536.558923 # average overall miss latency |
| 761system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 762system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 763system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 764system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 765system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 766system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 767system.cpu.l2cache.fast_writes 0 # number of fast writes performed 768system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 758system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 759system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 760system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 761system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 762system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 763system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 764system.cpu.l2cache.fast_writes 0 # number of fast writes performed 765system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 769system.cpu.l2cache.writebacks::writebacks 97172 # number of writebacks 770system.cpu.l2cache.writebacks::total 97172 # number of writebacks | 766system.cpu.l2cache.writebacks::writebacks 97166 # number of writebacks 767system.cpu.l2cache.writebacks::total 97166 # number of writebacks |
| 771system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 772system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 773system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 774system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 775system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 776system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 777system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 778system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 779system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits 780system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits | 768system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 769system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 770system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 771system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 772system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 773system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 774system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 775system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 776system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits 777system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits |
| 781system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100923 # number of ReadExReq MSHR misses 782system.cpu.l2cache.ReadExReq_mshr_misses::total 100923 # number of ReadExReq MSHR misses 783system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2807 # number of ReadCleanReq MSHR misses 784system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2807 # number of ReadCleanReq MSHR misses 785system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40208 # number of ReadSharedReq MSHR misses 786system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40208 # number of ReadSharedReq MSHR misses 787system.cpu.l2cache.demand_mshr_misses::cpu.inst 2807 # number of demand (read+write) MSHR misses 788system.cpu.l2cache.demand_mshr_misses::cpu.data 141131 # number of demand (read+write) MSHR misses 789system.cpu.l2cache.demand_mshr_misses::total 143938 # number of demand (read+write) MSHR misses 790system.cpu.l2cache.overall_mshr_misses::cpu.inst 2807 # number of overall MSHR misses 791system.cpu.l2cache.overall_mshr_misses::cpu.data 141131 # number of overall MSHR misses 792system.cpu.l2cache.overall_mshr_misses::total 143938 # number of overall MSHR misses 793system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6902558000 # number of ReadExReq MSHR miss cycles 794system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6902558000 # number of ReadExReq MSHR miss cycles 795system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195877500 # number of ReadCleanReq MSHR miss cycles 796system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195877500 # number of ReadCleanReq MSHR miss cycles 797system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2907247000 # number of ReadSharedReq MSHR miss cycles 798system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2907247000 # number of ReadSharedReq MSHR miss cycles 799system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195877500 # number of demand (read+write) MSHR miss cycles 800system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9809805000 # number of demand (read+write) MSHR miss cycles 801system.cpu.l2cache.demand_mshr_miss_latency::total 10005682500 # number of demand (read+write) MSHR miss cycles 802system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195877500 # number of overall MSHR miss cycles 803system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9809805000 # number of overall MSHR miss cycles 804system.cpu.l2cache.overall_mshr_miss_latency::total 10005682500 # number of overall MSHR miss cycles 805system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283161 # mshr miss rate for ReadExReq accesses 806system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283161 # mshr miss rate for ReadExReq accesses 807system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for ReadCleanReq accesses 808system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.143339 # mshr miss rate for ReadCleanReq accesses 809system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051047 # mshr miss rate for ReadSharedReq accesses 810system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051047 # mshr miss rate for ReadSharedReq accesses 811system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for demand accesses 812system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for demand accesses 813system.cpu.l2cache.demand_mshr_miss_rate::total 0.123694 # mshr miss rate for demand accesses 814system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for overall accesses 815system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for overall accesses 816system.cpu.l2cache.overall_mshr_miss_rate::total 0.123694 # mshr miss rate for overall accesses 817system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68394.300605 # average ReadExReq mshr miss latency 818system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68394.300605 # average ReadExReq mshr miss latency 819system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69781.795511 # average ReadCleanReq mshr miss latency 820system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69781.795511 # average ReadCleanReq mshr miss latency 821system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72305.188022 # average ReadSharedReq mshr miss latency 822system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72305.188022 # average ReadSharedReq mshr miss latency 823system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency 824system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency 825system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency 826system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency 827system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency 828system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency | 778system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100917 # number of ReadExReq MSHR misses 779system.cpu.l2cache.ReadExReq_mshr_misses::total 100917 # number of ReadExReq MSHR misses 780system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2806 # number of ReadCleanReq MSHR misses 781system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2806 # number of ReadCleanReq MSHR misses 782system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40153 # number of ReadSharedReq MSHR misses 783system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40153 # number of ReadSharedReq MSHR misses 784system.cpu.l2cache.demand_mshr_misses::cpu.inst 2806 # number of demand (read+write) MSHR misses 785system.cpu.l2cache.demand_mshr_misses::cpu.data 141070 # number of demand (read+write) MSHR misses 786system.cpu.l2cache.demand_mshr_misses::total 143876 # number of demand (read+write) MSHR misses 787system.cpu.l2cache.overall_mshr_misses::cpu.inst 2806 # number of overall MSHR misses 788system.cpu.l2cache.overall_mshr_misses::cpu.data 141070 # number of overall MSHR misses 789system.cpu.l2cache.overall_mshr_misses::total 143876 # number of overall MSHR misses 790system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6905603500 # number of ReadExReq MSHR miss cycles 791system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6905603500 # number of ReadExReq MSHR miss cycles 792system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles 793system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles 794system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2903188500 # number of ReadSharedReq MSHR miss cycles 795system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2903188500 # number of ReadSharedReq MSHR miss cycles 796system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles 797system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9808792000 # number of demand (read+write) MSHR miss cycles 798system.cpu.l2cache.demand_mshr_miss_latency::total 10004462500 # number of demand (read+write) MSHR miss cycles 799system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles 800system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9808792000 # number of overall MSHR miss cycles 801system.cpu.l2cache.overall_mshr_miss_latency::total 10004462500 # number of overall MSHR miss cycles 802system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282954 # mshr miss rate for ReadExReq accesses 803system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282954 # mshr miss rate for ReadExReq accesses 804system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for ReadCleanReq accesses 805system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.143463 # mshr miss rate for ReadCleanReq accesses 806system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050903 # mshr miss rate for ReadSharedReq accesses 807system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050903 # mshr miss rate for ReadSharedReq accesses 808system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for demand accesses 809system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123154 # mshr miss rate for demand accesses 810system.cpu.l2cache.demand_mshr_miss_rate::total 0.123495 # mshr miss rate for demand accesses 811system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for overall accesses 812system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123154 # mshr miss rate for overall accesses 813system.cpu.l2cache.overall_mshr_miss_rate::total 0.123495 # mshr miss rate for overall accesses 814system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68428.545240 # average ReadExReq mshr miss latency 815system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68428.545240 # average ReadExReq mshr miss latency 816system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69732.893799 # average ReadCleanReq mshr miss latency 817system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69732.893799 # average ReadCleanReq mshr miss latency 818system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.152940 # average ReadSharedReq mshr miss latency 819system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.152940 # average ReadSharedReq mshr miss latency 820system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69732.893799 # average overall mshr miss latency 821system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.381584 # average overall mshr miss latency 822system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69535.311657 # average overall mshr miss latency 823system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69732.893799 # average overall mshr miss latency 824system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.381584 # average overall mshr miss latency 825system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69535.311657 # average overall mshr miss latency |
| 829system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 826system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 830system.cpu.toL2Bus.snoop_filter.tot_requests 2321356 # Total number of requests made to the snoop filter. 831system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157764 # Number of requests hitting in the snoop filter with a single holder of the requested data. 832system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 833system.cpu.toL2Bus.snoop_filter.tot_snoops 2623 # Total number of snoops made to the snoop filter. 834system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 827system.cpu.toL2Bus.snoop_filter.tot_requests 2324094 # Total number of requests made to the snoop filter. 828system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159133 # Number of requests hitting in the snoop filter with a single holder of the requested data. 829system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4986 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 830system.cpu.toL2Bus.snoop_filter.tot_snoops 2609 # Total number of snoops made to the snoop filter. 831system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2606 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 835system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 832system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 836system.cpu.toL2Bus.trans_dist::ReadResp 807247 # Transaction distribution 837system.cpu.toL2Bus.trans_dist::WritebackDirty 1165429 # Transaction distribution 838system.cpu.toL2Bus.trans_dist::WritebackClean 17711 # Transaction distribution 839system.cpu.toL2Bus.trans_dist::CleanEvict 86920 # Transaction distribution 840system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution 841system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution 842system.cpu.toL2Bus.trans_dist::ReadCleanReq 19583 # Transaction distribution 843system.cpu.toL2Bus.trans_dist::ReadSharedReq 787664 # Transaction distribution 844system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56877 # Packet count per connected master and slave (bytes) 845system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3428141 # Packet count per connected master and slave (bytes) 846system.cpu.toL2Bus.pkt_count::total 3485018 # Packet count per connected master and slave (bytes) 847system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2386816 # Cumulative packet size per connected master and slave (bytes) 848system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589504 # Cumulative packet size per connected master and slave (bytes) 849system.cpu.toL2Bus.pkt_size::total 143976320 # Cumulative packet size per connected master and slave (bytes) 850system.cpu.toL2Bus.snoops 112366 # Total snoops (count) 851system.cpu.toL2Bus.snoop_fanout::samples 1276028 # Request fanout histogram 852system.cpu.toL2Bus.snoop_fanout::mean 0.005963 # Request fanout histogram 853system.cpu.toL2Bus.snoop_fanout::stdev 0.077021 # Request fanout histogram | 833system.cpu.toL2Bus.trans_dist::ReadResp 808376 # Transaction distribution 834system.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution 835system.cpu.toL2Bus.trans_dist::WritebackClean 17687 # Transaction distribution 836system.cpu.toL2Bus.trans_dist::CleanEvict 87231 # Transaction distribution 837system.cpu.toL2Bus.trans_dist::ReadExReq 356655 # Transaction distribution 838system.cpu.toL2Bus.trans_dist::ReadExResp 356655 # Transaction distribution 839system.cpu.toL2Bus.trans_dist::ReadCleanReq 19559 # Transaction distribution 840system.cpu.toL2Bus.trans_dist::ReadSharedReq 788817 # Transaction distribution 841system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56805 # Packet count per connected master and slave (bytes) 842system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432320 # Packet count per connected master and slave (bytes) 843system.cpu.toL2Bus.pkt_count::total 3489125 # Packet count per connected master and slave (bytes) 844system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2383744 # Cumulative packet size per connected master and slave (bytes) 845system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141744320 # Cumulative packet size per connected master and slave (bytes) 846system.cpu.toL2Bus.pkt_size::total 144128064 # Cumulative packet size per connected master and slave (bytes) 847system.cpu.toL2Bus.snoops 112304 # Total snoops (count) 848system.cpu.toL2Bus.snoop_fanout::samples 1277335 # Request fanout histogram 849system.cpu.toL2Bus.snoop_fanout::mean 0.006003 # Request fanout histogram 850system.cpu.toL2Bus.snoop_fanout::stdev 0.077277 # Request fanout histogram |
| 854system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 851system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 855system.cpu.toL2Bus.snoop_fanout::0 1268422 99.40% 99.40% # Request fanout histogram 856system.cpu.toL2Bus.snoop_fanout::1 7603 0.60% 100.00% # Request fanout histogram | 852system.cpu.toL2Bus.snoop_fanout::0 1269670 99.40% 99.40% # Request fanout histogram 853system.cpu.toL2Bus.snoop_fanout::1 7662 0.60% 100.00% # Request fanout histogram |
| 857system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 858system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 859system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 860system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 854system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 855system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 856system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 857system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 861system.cpu.toL2Bus.snoop_fanout::total 1276028 # Request fanout histogram 862system.cpu.toL2Bus.reqLayer0.occupancy 2246646000 # Layer occupancy (ticks) | 858system.cpu.toL2Bus.snoop_fanout::total 1277335 # Request fanout histogram 859system.cpu.toL2Bus.reqLayer0.occupancy 2249017000 # Layer occupancy (ticks) |
| 863system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) | 860system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 864system.cpu.toL2Bus.respLayer0.occupancy 29392963 # Layer occupancy (ticks) | 861system.cpu.toL2Bus.respLayer0.occupancy 29357961 # Layer occupancy (ticks) |
| 865system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 862system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 866system.cpu.toL2Bus.respLayer1.occupancy 1716126983 # Layer occupancy (ticks) | 863system.cpu.toL2Bus.respLayer1.occupancy 1718215984 # Layer occupancy (ticks) |
| 867system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) | 864system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) |
| 868system.membus.trans_dist::ReadResp 43015 # Transaction distribution 869system.membus.trans_dist::WritebackDirty 97172 # Transaction distribution 870system.membus.trans_dist::CleanEvict 12571 # Transaction distribution 871system.membus.trans_dist::ReadExReq 100923 # Transaction distribution 872system.membus.trans_dist::ReadExResp 100923 # Transaction distribution 873system.membus.trans_dist::ReadSharedReq 43015 # Transaction distribution 874system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397619 # Packet count per connected master and slave (bytes) 875system.membus.pkt_count::total 397619 # Packet count per connected master and slave (bytes) 876system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15431040 # Cumulative packet size per connected master and slave (bytes) 877system.membus.pkt_size::total 15431040 # Cumulative packet size per connected master and slave (bytes) | 865system.membus.trans_dist::ReadResp 42959 # Transaction distribution 866system.membus.trans_dist::WritebackDirty 97166 # Transaction distribution 867system.membus.trans_dist::CleanEvict 12529 # Transaction distribution 868system.membus.trans_dist::ReadExReq 100917 # Transaction distribution 869system.membus.trans_dist::ReadExResp 100917 # Transaction distribution 870system.membus.trans_dist::ReadSharedReq 42959 # Transaction distribution 871system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397447 # Packet count per connected master and slave (bytes) 872system.membus.pkt_count::total 397447 # Packet count per connected master and slave (bytes) 873system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15426688 # Cumulative packet size per connected master and slave (bytes) 874system.membus.pkt_size::total 15426688 # Cumulative packet size per connected master and slave (bytes) |
| 878system.membus.snoops 0 # Total snoops (count) | 875system.membus.snoops 0 # Total snoops (count) |
| 879system.membus.snoop_fanout::samples 253681 # Request fanout histogram | 876system.membus.snoop_fanout::samples 253571 # Request fanout histogram |
| 880system.membus.snoop_fanout::mean 0 # Request fanout histogram 881system.membus.snoop_fanout::stdev 0 # Request fanout histogram 882system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 877system.membus.snoop_fanout::mean 0 # Request fanout histogram 878system.membus.snoop_fanout::stdev 0 # Request fanout histogram 879system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 883system.membus.snoop_fanout::0 253681 100.00% 100.00% # Request fanout histogram | 880system.membus.snoop_fanout::0 253571 100.00% 100.00% # Request fanout histogram |
| 884system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 885system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 886system.membus.snoop_fanout::min_value 0 # Request fanout histogram 887system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 881system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 882system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 883system.membus.snoop_fanout::min_value 0 # Request fanout histogram 884system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 888system.membus.snoop_fanout::total 253681 # Request fanout histogram 889system.membus.reqLayer0.occupancy 685231500 # Layer occupancy (ticks) | 885system.membus.snoop_fanout::total 253571 # Request fanout histogram 886system.membus.reqLayer0.occupancy 685058500 # Layer occupancy (ticks) |
| 890system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) | 887system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 891system.membus.respLayer1.occupancy 764006500 # Layer occupancy (ticks) | 888system.membus.respLayer1.occupancy 763682500 # Layer occupancy (ticks) |
| 892system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 893 894---------- End Simulation Statistics ---------- | 889system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 890 891---------- End Simulation Statistics ---------- |