| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.363605 # Number of seconds simulated 4sim_ticks 363605295500 # Number of ticks simulated 5final_tick 363605295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.363600 # Number of seconds simulated 4sim_ticks 363599502500 # Number of ticks simulated 5final_tick 363599502500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 163495 # Simulator instruction rate (inst/s) 8host_op_rate 177087 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 117350463 # Simulator tick rate (ticks/s) 10host_mem_usage 312624 # Number of bytes of host memory used 11host_seconds 3098.46 # Real time elapsed on the host | 7host_inst_rate 226144 # Simulator instruction rate (inst/s) 8host_op_rate 244944 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 162315109 # Simulator tick rate (ticks/s) 10host_mem_usage 321124 # Number of bytes of host memory used 11host_seconds 2240.08 # Real time elapsed on the host |
| 12sim_insts 506582156 # Number of instructions simulated 13sim_ops 548695379 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 506582156 # Number of instructions simulated 13sim_ops 548695379 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 219264 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 219456 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 9004480 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 9004480 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::total 9223744 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 219264 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 219264 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6189056 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6189056 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3426 # Number of read requests responded to by this memory | 18system.physmem.bytes_read::total 9223936 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 219456 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 219456 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6189376 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6189376 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3429 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::cpu.data 140695 # Number of read requests responded to by this memory | 24system.physmem.num_reads::cpu.data 140695 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::total 144121 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 96704 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 96704 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 603028 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 24764436 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 25367463 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 603028 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 603028 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17021358 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17021358 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17021358 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 603028 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 24764436 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 42388822 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 144121 # Number of read requests accepted 40system.physmem.writeReqs 96704 # Number of write requests accepted 41system.physmem.readBursts 144121 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 96704 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 9217792 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue 45system.physmem.bytesWritten 6187328 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 9223744 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 6189056 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue | 25system.physmem.num_reads::total 144124 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 96709 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 96709 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 603565 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 24764830 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 25368396 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 603565 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 603565 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17022510 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17022510 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17022510 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 603565 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 24764830 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 42390905 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 144124 # Number of read requests accepted 40system.physmem.writeReqs 96709 # Number of write requests accepted 41system.physmem.readBursts 144124 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 96709 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 9217920 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue 45system.physmem.bytesWritten 6188224 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 9223936 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 6189376 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 51system.physmem.perBankRdBursts::0 9327 # Per bank write bursts | 51system.physmem.perBankRdBursts::0 9331 # Per bank write bursts |
| 52system.physmem.perBankRdBursts::1 8969 # Per bank write bursts | 52system.physmem.perBankRdBursts::1 8969 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::2 9002 # Per bank write bursts | 53system.physmem.perBankRdBursts::2 9003 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::3 8675 # Per bank write bursts | 54system.physmem.perBankRdBursts::3 8675 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::4 9455 # Per bank write bursts | 55system.physmem.perBankRdBursts::4 9453 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::5 9352 # Per bank write bursts | 56system.physmem.perBankRdBursts::5 9352 # Per bank write bursts |
| 57system.physmem.perBankRdBursts::6 8946 # Per bank write bursts | 57system.physmem.perBankRdBursts::6 8945 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::7 8102 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8582 # Per bank write bursts | 58system.physmem.perBankRdBursts::7 8102 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8582 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::9 8671 # Per bank write bursts | 60system.physmem.perBankRdBursts::9 8674 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::10 8765 # Per bank write bursts | 61system.physmem.perBankRdBursts::10 8765 # Per bank write bursts |
| 62system.physmem.perBankRdBursts::11 9475 # Per bank write bursts 63system.physmem.perBankRdBursts::12 9349 # Per bank write bursts 64system.physmem.perBankRdBursts::13 9515 # Per bank write bursts 65system.physmem.perBankRdBursts::14 8723 # Per bank write bursts 66system.physmem.perBankRdBursts::15 9120 # Per bank write bursts 67system.physmem.perBankWrBursts::0 6189 # Per bank write bursts | 62system.physmem.perBankRdBursts::11 9476 # Per bank write bursts 63system.physmem.perBankRdBursts::12 9348 # Per bank write bursts 64system.physmem.perBankRdBursts::13 9513 # Per bank write bursts 65system.physmem.perBankRdBursts::14 8719 # Per bank write bursts 66system.physmem.perBankRdBursts::15 9123 # Per bank write bursts 67system.physmem.perBankWrBursts::0 6195 # Per bank write bursts |
| 68system.physmem.perBankWrBursts::1 6094 # Per bank write bursts | 68system.physmem.perBankWrBursts::1 6094 # Per bank write bursts |
| 69system.physmem.perBankWrBursts::2 6010 # Per bank write bursts | 69system.physmem.perBankWrBursts::2 6011 # Per bank write bursts |
| 70system.physmem.perBankWrBursts::3 5821 # Per bank write bursts | 70system.physmem.perBankWrBursts::3 5821 # Per bank write bursts |
| 71system.physmem.perBankWrBursts::4 6183 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6186 # Per bank write bursts | 71system.physmem.perBankWrBursts::4 6181 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6188 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::6 6015 # Per bank write bursts | 73system.physmem.perBankWrBursts::6 6015 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::7 5498 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5738 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5829 # Per bank write bursts | 74system.physmem.perBankWrBursts::7 5499 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5743 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5830 # Per bank write bursts |
| 77system.physmem.perBankWrBursts::10 5965 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6463 # Per bank write bursts | 77system.physmem.perBankWrBursts::10 5965 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6463 # Per bank write bursts |
| 79system.physmem.perBankWrBursts::12 6313 # Per bank write bursts | 79system.physmem.perBankWrBursts::12 6312 # Per bank write bursts |
| 80system.physmem.perBankWrBursts::13 6285 # Per bank write bursts | 80system.physmem.perBankWrBursts::13 6285 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::14 6005 # Per bank write bursts 82system.physmem.perBankWrBursts::15 6083 # Per bank write bursts | 81system.physmem.perBankWrBursts::14 6003 # Per bank write bursts 82system.physmem.perBankWrBursts::15 6086 # Per bank write bursts |
| 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 363605269500 # Total gap between requests | 85system.physmem.totGap 363599476500 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 144121 # Read request sizes (log2) | 92system.physmem.readPktSize::6 144124 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 99system.physmem.writePktSize::6 96704 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 143663 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 343 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see | 99system.physmem.writePktSize::6 96709 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 349 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 2949 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 3103 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5548 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 3131 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see |
| 150system.physmem.wrQLenPdf::18 5659 # What write queue length does an incoming req see | 150system.physmem.wrQLenPdf::18 5659 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5668 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5673 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5682 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5670 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5674 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5686 # What write queue length does an incoming req see | 151system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5666 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5668 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5670 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5680 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5666 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see | 159system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see |
| 160system.physmem.wrQLenPdf::28 5716 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5669 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5677 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5614 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see | 160system.physmem.wrQLenPdf::28 5712 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5670 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5613 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see | 166system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see |
| 167system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see | 167system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see |
| 168system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see | 168system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see |
| 173system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see | 173system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see |
| 174system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see | 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see |
| 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see --- 5 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see --- 5 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 65251 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 236.074482 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 156.620272 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 241.651300 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 24697 37.85% 37.85% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 18374 28.16% 66.01% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 6917 10.60% 76.61% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7938 12.17% 88.77% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2038 3.12% 91.90% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1147 1.76% 93.66% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 769 1.18% 94.83% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 621 0.95% 95.79% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 2750 4.21% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65251 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5585 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 25.786571 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 381.841879 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5581 99.93% 99.93% # Reads before turning the bus around for writes | 196system.physmem.bytesPerActivate::samples 65302 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 235.912652 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 156.372535 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 241.914583 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 24788 37.96% 37.96% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 18406 28.19% 66.14% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 6849 10.49% 76.63% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7905 12.11% 88.74% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2084 3.19% 91.93% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1111 1.70% 93.63% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 761 1.17% 94.80% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 643 0.98% 95.78% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 2755 4.22% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65302 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5583 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 25.797421 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 381.883100 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5579 99.93% 99.93% # Reads before turning the bus around for writes |
| 214system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes | 214system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::total 5585 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5585 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.310116 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.217866 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 2.213646 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 2534 45.37% 45.37% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 92 1.65% 47.02% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 2660 47.63% 94.65% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 156 2.79% 97.44% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20 36 0.64% 98.08% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::21 18 0.32% 98.41% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::22 16 0.29% 98.69% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::23 9 0.16% 98.85% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::24 7 0.13% 98.98% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::25 10 0.18% 99.16% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::26 4 0.07% 99.23% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::27 4 0.07% 99.30% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::28 4 0.07% 99.37% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::29 6 0.11% 99.48% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::30 2 0.04% 99.52% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::31 4 0.07% 99.59% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::32 3 0.05% 99.64% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::33 4 0.07% 99.71% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::35 2 0.04% 99.75% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::37 2 0.04% 99.79% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::39 1 0.02% 99.80% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40 1 0.02% 99.82% # Writes before turning the bus around for reads | 216system.physmem.rdPerTurnAround::total 5583 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5583 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.318825 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.224966 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 2.238810 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 2516 45.07% 45.07% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 99 1.77% 46.84% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 2663 47.70% 94.54% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 163 2.92% 97.46% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20 38 0.68% 98.14% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::21 18 0.32% 98.46% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::22 14 0.25% 98.71% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::23 8 0.14% 98.85% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::24 6 0.11% 98.96% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::25 9 0.16% 99.12% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::26 5 0.09% 99.21% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::27 4 0.07% 99.28% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::28 4 0.07% 99.36% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::29 6 0.11% 99.46% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::30 2 0.04% 99.50% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::31 3 0.05% 99.55% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::32 2 0.04% 99.59% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::33 4 0.07% 99.66% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::34 2 0.04% 99.70% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::35 2 0.04% 99.73% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::37 2 0.04% 99.77% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::39 1 0.02% 99.79% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40 1 0.02% 99.80% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::41 1 0.02% 99.82% # Writes before turning the bus around for reads |
| 243system.physmem.wrPerTurnAround::43 1 0.02% 99.84% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44 1 0.02% 99.86% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::47 1 0.02% 99.87% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::50 2 0.04% 99.91% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::52 1 0.02% 99.93% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::53 1 0.02% 99.95% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::55 1 0.02% 99.96% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::61 1 0.02% 99.98% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::62 1 0.02% 100.00% # Writes before turning the bus around for reads | 245system.physmem.wrPerTurnAround::43 1 0.02% 99.84% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::44 1 0.02% 99.86% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::47 1 0.02% 99.87% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::50 2 0.04% 99.91% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::52 1 0.02% 99.93% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::53 1 0.02% 99.95% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::55 1 0.02% 99.96% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::61 1 0.02% 99.98% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::62 1 0.02% 100.00% # Writes before turning the bus around for reads |
| 252system.physmem.wrPerTurnAround::total 5585 # Writes before turning the bus around for reads 253system.physmem.totQLat 1541292750 # Total ticks spent queuing 254system.physmem.totMemAccLat 4241817750 # Total ticks spent from burst creation until serviced by the DRAM 255system.physmem.totBusLat 720140000 # Total ticks spent in databus transfers 256system.physmem.avgQLat 10701.34 # Average queueing delay per DRAM burst | 254system.physmem.wrPerTurnAround::total 5583 # Writes before turning the bus around for reads 255system.physmem.totQLat 1538433000 # Total ticks spent queuing 256system.physmem.totMemAccLat 4238995500 # Total ticks spent from burst creation until serviced by the DRAM 257system.physmem.totBusLat 720150000 # Total ticks spent in databus transfers 258system.physmem.avgQLat 10681.34 # Average queueing delay per DRAM burst |
| 257system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 259system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 258system.physmem.avgMemAccLat 29451.34 # Average memory access latency per DRAM burst | 260system.physmem.avgMemAccLat 29431.34 # Average memory access latency per DRAM burst |
| 259system.physmem.avgRdBW 25.35 # Average DRAM read bandwidth in MiByte/s 260system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s 261system.physmem.avgRdBWSys 25.37 # Average system read bandwidth in MiByte/s 262system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s 263system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 264system.physmem.busUtil 0.33 # Data bus utilization in percentage 265system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 266system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 267system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing | 261system.physmem.avgRdBW 25.35 # Average DRAM read bandwidth in MiByte/s 262system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s 263system.physmem.avgRdBWSys 25.37 # Average system read bandwidth in MiByte/s 264system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s 265system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 266system.physmem.busUtil 0.33 # Data bus utilization in percentage 267system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 268system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 269system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing |
| 268system.physmem.avgWrQLen 19.51 # Average write queue length when enqueuing 269system.physmem.readRowHits 110876 # Number of row buffer hits during reads 270system.physmem.writeRowHits 64571 # Number of row buffer hits during writes | 270system.physmem.avgWrQLen 19.80 # Average write queue length when enqueuing 271system.physmem.readRowHits 110870 # Number of row buffer hits during reads 272system.physmem.writeRowHits 64542 # Number of row buffer hits during writes |
| 271system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads | 273system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads |
| 272system.physmem.writeRowHitRate 66.77 # Row buffer hit rate for writes 273system.physmem.avgGap 1509831.91 # Average gap between requests 274system.physmem.pageHitRate 72.88 # Row buffer hit rate, read and write combined 275system.physmem_0.actEnergy 248028480 # Energy for activate commands per rank (pJ) 276system.physmem_0.preEnergy 135333000 # Energy for precharge commands per rank (pJ) 277system.physmem_0.readEnergy 560164800 # Energy for read commands per rank (pJ) 278system.physmem_0.writeEnergy 310884480 # Energy for write commands per rank (pJ) 279system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) 280system.physmem_0.actBackEnergy 47382783300 # Energy for active background per rank (pJ) 281system.physmem_0.preBackEnergy 176597692500 # Energy for precharge background per rank (pJ) 282system.physmem_0.totalEnergy 248983621440 # Total energy per rank (pJ) 283system.physmem_0.averagePower 684.768610 # Core power per rank (mW) 284system.physmem_0.memoryStateTime::IDLE 293478926000 # Time in different power states 285system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states | 274system.physmem.writeRowHitRate 66.74 # Row buffer hit rate for writes 275system.physmem.avgGap 1509757.70 # Average gap between requests 276system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined 277system.physmem_0.actEnergy 248293080 # Energy for activate commands per rank (pJ) 278system.physmem_0.preEnergy 135477375 # Energy for precharge commands per rank (pJ) 279system.physmem_0.readEnergy 560086800 # Energy for read commands per rank (pJ) 280system.physmem_0.writeEnergy 310832640 # Energy for write commands per rank (pJ) 281system.physmem_0.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ) 282system.physmem_0.actBackEnergy 47486002320 # Energy for active background per rank (pJ) 283system.physmem_0.preBackEnergy 176502477750 # Energy for precharge background per rank (pJ) 284system.physmem_0.totalEnergy 248991396285 # Total energy per rank (pJ) 285system.physmem_0.averagePower 684.804658 # Core power per rank (mW) 286system.physmem_0.memoryStateTime::IDLE 293320694250 # Time in different power states 287system.physmem_0.memoryStateTime::REF 12141220000 # Time in different power states |
| 286system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 288system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 287system.physmem_0.memoryStateTime::ACT 57982170250 # Time in different power states | 289system.physmem_0.memoryStateTime::ACT 58133810750 # Time in different power states |
| 288system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 290system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 289system.physmem_1.actEnergy 245080080 # Energy for activate commands per rank (pJ) 290system.physmem_1.preEnergy 133724250 # Energy for precharge commands per rank (pJ) 291system.physmem_1.readEnergy 563004000 # Energy for read commands per rank (pJ) 292system.physmem_1.writeEnergy 315375120 # Energy for write commands per rank (pJ) 293system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) 294system.physmem_1.actBackEnergy 46983341835 # Energy for active background per rank (pJ) 295system.physmem_1.preBackEnergy 176948079750 # Energy for precharge background per rank (pJ) 296system.physmem_1.totalEnergy 248937339915 # Total energy per rank (pJ) 297system.physmem_1.averagePower 684.641324 # Core power per rank (mW) 298system.physmem_1.memoryStateTime::IDLE 294063578500 # Time in different power states 299system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states | 291system.physmem_1.actEnergy 245148120 # Energy for activate commands per rank (pJ) 292system.physmem_1.preEnergy 133761375 # Energy for precharge commands per rank (pJ) 293system.physmem_1.readEnergy 562957200 # Energy for read commands per rank (pJ) 294system.physmem_1.writeEnergy 315401040 # Energy for write commands per rank (pJ) 295system.physmem_1.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ) 296system.physmem_1.actBackEnergy 46957937220 # Energy for active background per rank (pJ) 297system.physmem_1.preBackEnergy 176965692750 # Energy for precharge background per rank (pJ) 298system.physmem_1.totalEnergy 248929124025 # Total energy per rank (pJ) 299system.physmem_1.averagePower 684.633389 # Core power per rank (mW) 300system.physmem_1.memoryStateTime::IDLE 294092512000 # Time in different power states 301system.physmem_1.memoryStateTime::REF 12141220000 # Time in different power states |
| 300system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 302system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 301system.physmem_1.memoryStateTime::ACT 57397836750 # Time in different power states | 303system.physmem_1.memoryStateTime::ACT 57361058000 # Time in different power states |
| 302system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 304system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 303system.cpu.branchPred.lookups 131896308 # Number of BP lookups 304system.cpu.branchPred.condPredicted 98031712 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 6139352 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 68410049 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 64397752 # Number of BTB hits | 305system.cpu.branchPred.lookups 131895360 # Number of BP lookups 306system.cpu.branchPred.condPredicted 98029927 # Number of conditional branches predicted 307system.cpu.branchPred.condIncorrect 6139026 # Number of conditional branches incorrect 308system.cpu.branchPred.BTBLookups 68388068 # Number of BTB lookups 309system.cpu.branchPred.BTBHits 64396789 # Number of BTB hits |
| 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 310system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 309system.cpu.branchPred.BTBHitPct 94.134930 # BTB Hit Percentage 310system.cpu.branchPred.usedRAS 9981293 # Number of times the RAS was used to get a target. 311system.cpu.branchPred.RASInCorrect 18014 # Number of incorrect RAS predictions. | 311system.cpu.branchPred.BTBHitPct 94.163779 # BTB Hit Percentage 312system.cpu.branchPred.usedRAS 9981632 # Number of times the RAS was used to get a target. 313system.cpu.branchPred.RASInCorrect 18119 # Number of incorrect RAS predictions. |
| 312system.cpu_clk_domain.clock 500 # Clock period in ticks 313system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 422system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 423system.cpu.itb.read_accesses 0 # DTB read accesses 424system.cpu.itb.write_accesses 0 # DTB write accesses 425system.cpu.itb.inst_accesses 0 # ITB inst accesses 426system.cpu.itb.hits 0 # DTB hits 427system.cpu.itb.misses 0 # DTB misses 428system.cpu.itb.accesses 0 # DTB accesses 429system.cpu.workload.num_syscalls 548 # Number of system calls | 314system.cpu_clk_domain.clock 500 # Clock period in ticks 315system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 424system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 425system.cpu.itb.read_accesses 0 # DTB read accesses 426system.cpu.itb.write_accesses 0 # DTB write accesses 427system.cpu.itb.inst_accesses 0 # ITB inst accesses 428system.cpu.itb.hits 0 # DTB hits 429system.cpu.itb.misses 0 # DTB misses 430system.cpu.itb.accesses 0 # DTB accesses 431system.cpu.workload.num_syscalls 548 # Number of system calls |
| 430system.cpu.numCycles 727210591 # number of cpu cycles simulated | 432system.cpu.numCycles 727199005 # number of cpu cycles simulated |
| 431system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 432system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 433system.cpu.committedInsts 506582156 # Number of instructions committed 434system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed | 433system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 434system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 435system.cpu.committedInsts 506582156 # Number of instructions committed 436system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed |
| 435system.cpu.discardedOps 13199856 # Number of ops (including micro ops) which were discarded before commit | 437system.cpu.discardedOps 13199573 # Number of ops (including micro ops) which were discarded before commit |
| 436system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 438system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 437system.cpu.cpi 1.435524 # CPI: cycles per instruction 438system.cpu.ipc 0.696610 # IPC: instructions per cycle 439system.cpu.tickCycles 690727435 # Number of cycles that the object actually ticked 440system.cpu.idleCycles 36483156 # Total number of cycles that the object has spent stopped 441system.cpu.dcache.tags.replacements 1139971 # number of replacements 442system.cpu.dcache.tags.tagsinuse 4070.789837 # Cycle average of tags in use 443system.cpu.dcache.tags.total_refs 171168979 # Total number of references to valid blocks. 444system.cpu.dcache.tags.sampled_refs 1144067 # Sample count of references to valid blocks. 445system.cpu.dcache.tags.avg_refs 149.614471 # Average number of references to valid blocks. | 439system.cpu.cpi 1.435501 # CPI: cycles per instruction 440system.cpu.ipc 0.696621 # IPC: instructions per cycle 441system.cpu.tickCycles 690715590 # Number of cycles that the object actually ticked 442system.cpu.idleCycles 36483415 # Total number of cycles that the object has spent stopped 443system.cpu.dcache.tags.replacements 1139984 # number of replacements 444system.cpu.dcache.tags.tagsinuse 4070.789434 # Cycle average of tags in use 445system.cpu.dcache.tags.total_refs 171168644 # Total number of references to valid blocks. 446system.cpu.dcache.tags.sampled_refs 1144080 # Sample count of references to valid blocks. 447system.cpu.dcache.tags.avg_refs 149.612478 # Average number of references to valid blocks. |
| 446system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. | 448system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. |
| 447system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789837 # Average occupied blocks per requestor | 449system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789434 # Average occupied blocks per requestor |
| 448system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy 449system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy 450system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 451system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id | 450system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy 451system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy 452system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 453system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id |
| 452system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id | 454system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id |
| 453system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id | 455system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id |
| 454system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id | 456system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id |
| 455system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 457system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 456system.cpu.dcache.tags.tag_accesses 346593001 # Number of tag accesses 457system.cpu.dcache.tags.data_accesses 346593001 # Number of data accesses 458system.cpu.dcache.ReadReq_hits::cpu.data 114650515 # number of ReadReq hits 459system.cpu.dcache.ReadReq_hits::total 114650515 # number of ReadReq hits 460system.cpu.dcache.WriteReq_hits::cpu.data 53538628 # number of WriteReq hits 461system.cpu.dcache.WriteReq_hits::total 53538628 # number of WriteReq hits 462system.cpu.dcache.SoftPFReq_hits::cpu.data 2754 # number of SoftPFReq hits 463system.cpu.dcache.SoftPFReq_hits::total 2754 # number of SoftPFReq hits | 458system.cpu.dcache.tags.tag_accesses 346592332 # Number of tag accesses 459system.cpu.dcache.tags.data_accesses 346592332 # Number of data accesses 460system.cpu.dcache.ReadReq_hits::cpu.data 114650184 # number of ReadReq hits 461system.cpu.dcache.ReadReq_hits::total 114650184 # number of ReadReq hits 462system.cpu.dcache.WriteReq_hits::cpu.data 53538625 # number of WriteReq hits 463system.cpu.dcache.WriteReq_hits::total 53538625 # number of WriteReq hits 464system.cpu.dcache.SoftPFReq_hits::cpu.data 2753 # number of SoftPFReq hits 465system.cpu.dcache.SoftPFReq_hits::total 2753 # number of SoftPFReq hits |
| 464system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 465system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 466system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 467system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits | 466system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 467system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 468system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 469system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits |
| 468system.cpu.dcache.demand_hits::cpu.data 168189143 # number of demand (read+write) hits 469system.cpu.dcache.demand_hits::total 168189143 # number of demand (read+write) hits 470system.cpu.dcache.overall_hits::cpu.data 168191897 # number of overall hits 471system.cpu.dcache.overall_hits::total 168191897 # number of overall hits 472system.cpu.dcache.ReadReq_misses::cpu.data 854793 # number of ReadReq misses 473system.cpu.dcache.ReadReq_misses::total 854793 # number of ReadReq misses 474system.cpu.dcache.WriteReq_misses::cpu.data 700678 # number of WriteReq misses 475system.cpu.dcache.WriteReq_misses::total 700678 # number of WriteReq misses 476system.cpu.dcache.SoftPFReq_misses::cpu.data 17 # number of SoftPFReq misses 477system.cpu.dcache.SoftPFReq_misses::total 17 # number of SoftPFReq misses 478system.cpu.dcache.demand_misses::cpu.data 1555471 # number of demand (read+write) misses 479system.cpu.dcache.demand_misses::total 1555471 # number of demand (read+write) misses 480system.cpu.dcache.overall_misses::cpu.data 1555488 # number of overall misses 481system.cpu.dcache.overall_misses::total 1555488 # number of overall misses 482system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024452000 # number of ReadReq miss cycles 483system.cpu.dcache.ReadReq_miss_latency::total 14024452000 # number of ReadReq miss cycles 484system.cpu.dcache.WriteReq_miss_latency::cpu.data 21892214000 # number of WriteReq miss cycles 485system.cpu.dcache.WriteReq_miss_latency::total 21892214000 # number of WriteReq miss cycles 486system.cpu.dcache.demand_miss_latency::cpu.data 35916666000 # number of demand (read+write) miss cycles 487system.cpu.dcache.demand_miss_latency::total 35916666000 # number of demand (read+write) miss cycles 488system.cpu.dcache.overall_miss_latency::cpu.data 35916666000 # number of overall miss cycles 489system.cpu.dcache.overall_miss_latency::total 35916666000 # number of overall miss cycles 490system.cpu.dcache.ReadReq_accesses::cpu.data 115505308 # number of ReadReq accesses(hits+misses) 491system.cpu.dcache.ReadReq_accesses::total 115505308 # number of ReadReq accesses(hits+misses) | 470system.cpu.dcache.demand_hits::cpu.data 168188809 # number of demand (read+write) hits 471system.cpu.dcache.demand_hits::total 168188809 # number of demand (read+write) hits 472system.cpu.dcache.overall_hits::cpu.data 168191562 # number of overall hits 473system.cpu.dcache.overall_hits::total 168191562 # number of overall hits 474system.cpu.dcache.ReadReq_misses::cpu.data 854786 # number of ReadReq misses 475system.cpu.dcache.ReadReq_misses::total 854786 # number of ReadReq misses 476system.cpu.dcache.WriteReq_misses::cpu.data 700681 # number of WriteReq misses 477system.cpu.dcache.WriteReq_misses::total 700681 # number of WriteReq misses 478system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 479system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses 480system.cpu.dcache.demand_misses::cpu.data 1555467 # number of demand (read+write) misses 481system.cpu.dcache.demand_misses::total 1555467 # number of demand (read+write) misses 482system.cpu.dcache.overall_misses::cpu.data 1555482 # number of overall misses 483system.cpu.dcache.overall_misses::total 1555482 # number of overall misses 484system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024022500 # number of ReadReq miss cycles 485system.cpu.dcache.ReadReq_miss_latency::total 14024022500 # number of ReadReq miss cycles 486system.cpu.dcache.WriteReq_miss_latency::cpu.data 21893600500 # number of WriteReq miss cycles 487system.cpu.dcache.WriteReq_miss_latency::total 21893600500 # number of WriteReq miss cycles 488system.cpu.dcache.demand_miss_latency::cpu.data 35917623000 # number of demand (read+write) miss cycles 489system.cpu.dcache.demand_miss_latency::total 35917623000 # number of demand (read+write) miss cycles 490system.cpu.dcache.overall_miss_latency::cpu.data 35917623000 # number of overall miss cycles 491system.cpu.dcache.overall_miss_latency::total 35917623000 # number of overall miss cycles 492system.cpu.dcache.ReadReq_accesses::cpu.data 115504970 # number of ReadReq accesses(hits+misses) 493system.cpu.dcache.ReadReq_accesses::total 115504970 # number of ReadReq accesses(hits+misses) |
| 492system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 493system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) | 494system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 495system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) |
| 494system.cpu.dcache.SoftPFReq_accesses::cpu.data 2771 # number of SoftPFReq accesses(hits+misses) 495system.cpu.dcache.SoftPFReq_accesses::total 2771 # number of SoftPFReq accesses(hits+misses) | 496system.cpu.dcache.SoftPFReq_accesses::cpu.data 2768 # number of SoftPFReq accesses(hits+misses) 497system.cpu.dcache.SoftPFReq_accesses::total 2768 # number of SoftPFReq accesses(hits+misses) |
| 496system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 497system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 498system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 499system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) | 498system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 499system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 500system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 501system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) |
| 500system.cpu.dcache.demand_accesses::cpu.data 169744614 # number of demand (read+write) accesses 501system.cpu.dcache.demand_accesses::total 169744614 # number of demand (read+write) accesses 502system.cpu.dcache.overall_accesses::cpu.data 169747385 # number of overall (read+write) accesses 503system.cpu.dcache.overall_accesses::total 169747385 # number of overall (read+write) accesses | 502system.cpu.dcache.demand_accesses::cpu.data 169744276 # number of demand (read+write) accesses 503system.cpu.dcache.demand_accesses::total 169744276 # number of demand (read+write) accesses 504system.cpu.dcache.overall_accesses::cpu.data 169747044 # number of overall (read+write) accesses 505system.cpu.dcache.overall_accesses::total 169747044 # number of overall (read+write) accesses |
| 504system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses 505system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses 506system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses 507system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses | 506system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses 507system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses 508system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses 509system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses |
| 508system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.006135 # miss rate for SoftPFReq accesses 509system.cpu.dcache.SoftPFReq_miss_rate::total 0.006135 # miss rate for SoftPFReq accesses | 510system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005419 # miss rate for SoftPFReq accesses 511system.cpu.dcache.SoftPFReq_miss_rate::total 0.005419 # miss rate for SoftPFReq accesses |
| 510system.cpu.dcache.demand_miss_rate::cpu.data 0.009164 # miss rate for demand accesses 511system.cpu.dcache.demand_miss_rate::total 0.009164 # miss rate for demand accesses 512system.cpu.dcache.overall_miss_rate::cpu.data 0.009164 # miss rate for overall accesses 513system.cpu.dcache.overall_miss_rate::total 0.009164 # miss rate for overall accesses | 512system.cpu.dcache.demand_miss_rate::cpu.data 0.009164 # miss rate for demand accesses 513system.cpu.dcache.demand_miss_rate::total 0.009164 # miss rate for demand accesses 514system.cpu.dcache.overall_miss_rate::cpu.data 0.009164 # miss rate for overall accesses 515system.cpu.dcache.overall_miss_rate::total 0.009164 # miss rate for overall accesses |
| 514system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.840019 # average ReadReq miss latency 515system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.840019 # average ReadReq miss latency 516system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31244.329064 # average WriteReq miss latency 517system.cpu.dcache.WriteReq_avg_miss_latency::total 31244.329064 # average WriteReq miss latency 518system.cpu.dcache.demand_avg_miss_latency::cpu.data 23090.540422 # average overall miss latency 519system.cpu.dcache.demand_avg_miss_latency::total 23090.540422 # average overall miss latency 520system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.288064 # average overall miss latency 521system.cpu.dcache.overall_avg_miss_latency::total 23090.288064 # average overall miss latency | 516system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.471912 # average ReadReq miss latency 517system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.471912 # average ReadReq miss latency 518system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31246.174079 # average WriteReq miss latency 519system.cpu.dcache.WriteReq_avg_miss_latency::total 31246.174079 # average WriteReq miss latency 520system.cpu.dcache.demand_avg_miss_latency::cpu.data 23091.215050 # average overall miss latency 521system.cpu.dcache.demand_avg_miss_latency::total 23091.215050 # average overall miss latency 522system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.992374 # average overall miss latency 523system.cpu.dcache.overall_avg_miss_latency::total 23090.992374 # average overall miss latency |
| 522system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 523system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 524system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 525system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 526system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 527system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 528system.cpu.dcache.fast_writes 0 # number of fast writes performed 529system.cpu.dcache.cache_copies 0 # number of cache copies performed | 524system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 525system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 526system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 527system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 528system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 529system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 530system.cpu.dcache.fast_writes 0 # number of fast writes performed 531system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 530system.cpu.dcache.writebacks::writebacks 1068574 # number of writebacks 531system.cpu.dcache.writebacks::total 1068574 # number of writebacks 532system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66907 # number of ReadReq MSHR hits 533system.cpu.dcache.ReadReq_mshr_hits::total 66907 # number of ReadReq MSHR hits 534system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344511 # number of WriteReq MSHR hits 535system.cpu.dcache.WriteReq_mshr_hits::total 344511 # number of WriteReq MSHR hits 536system.cpu.dcache.demand_mshr_hits::cpu.data 411418 # number of demand (read+write) MSHR hits 537system.cpu.dcache.demand_mshr_hits::total 411418 # number of demand (read+write) MSHR hits 538system.cpu.dcache.overall_mshr_hits::cpu.data 411418 # number of overall MSHR hits 539system.cpu.dcache.overall_mshr_hits::total 411418 # number of overall MSHR hits 540system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787886 # number of ReadReq MSHR misses 541system.cpu.dcache.ReadReq_mshr_misses::total 787886 # number of ReadReq MSHR misses 542system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356167 # number of WriteReq MSHR misses 543system.cpu.dcache.WriteReq_mshr_misses::total 356167 # number of WriteReq MSHR misses 544system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 14 # number of SoftPFReq MSHR misses 545system.cpu.dcache.SoftPFReq_mshr_misses::total 14 # number of SoftPFReq MSHR misses 546system.cpu.dcache.demand_mshr_misses::cpu.data 1144053 # number of demand (read+write) MSHR misses 547system.cpu.dcache.demand_mshr_misses::total 1144053 # number of demand (read+write) MSHR misses 548system.cpu.dcache.overall_mshr_misses::cpu.data 1144067 # number of overall MSHR misses 549system.cpu.dcache.overall_mshr_misses::total 1144067 # number of overall MSHR misses 550system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337562000 # number of ReadReq MSHR miss cycles 551system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337562000 # number of ReadReq MSHR miss cycles 552system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11120015500 # number of WriteReq MSHR miss cycles 553system.cpu.dcache.WriteReq_mshr_miss_latency::total 11120015500 # number of WriteReq MSHR miss cycles 554system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1028000 # number of SoftPFReq MSHR miss cycles 555system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1028000 # number of SoftPFReq MSHR miss cycles 556system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23457577500 # number of demand (read+write) MSHR miss cycles 557system.cpu.dcache.demand_mshr_miss_latency::total 23457577500 # number of demand (read+write) MSHR miss cycles 558system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23458605500 # number of overall MSHR miss cycles 559system.cpu.dcache.overall_mshr_miss_latency::total 23458605500 # number of overall MSHR miss cycles | 532system.cpu.dcache.writebacks::writebacks 1068583 # number of writebacks 533system.cpu.dcache.writebacks::total 1068583 # number of writebacks 534system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66886 # number of ReadReq MSHR hits 535system.cpu.dcache.ReadReq_mshr_hits::total 66886 # number of ReadReq MSHR hits 536system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344513 # number of WriteReq MSHR hits 537system.cpu.dcache.WriteReq_mshr_hits::total 344513 # number of WriteReq MSHR hits 538system.cpu.dcache.demand_mshr_hits::cpu.data 411399 # number of demand (read+write) MSHR hits 539system.cpu.dcache.demand_mshr_hits::total 411399 # number of demand (read+write) MSHR hits 540system.cpu.dcache.overall_mshr_hits::cpu.data 411399 # number of overall MSHR hits 541system.cpu.dcache.overall_mshr_hits::total 411399 # number of overall MSHR hits 542system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787900 # number of ReadReq MSHR misses 543system.cpu.dcache.ReadReq_mshr_misses::total 787900 # number of ReadReq MSHR misses 544system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356168 # number of WriteReq MSHR misses 545system.cpu.dcache.WriteReq_mshr_misses::total 356168 # number of WriteReq MSHR misses 546system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 547system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 548system.cpu.dcache.demand_mshr_misses::cpu.data 1144068 # number of demand (read+write) MSHR misses 549system.cpu.dcache.demand_mshr_misses::total 1144068 # number of demand (read+write) MSHR misses 550system.cpu.dcache.overall_mshr_misses::cpu.data 1144080 # number of overall MSHR misses 551system.cpu.dcache.overall_mshr_misses::total 1144080 # number of overall MSHR misses 552system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337991000 # number of ReadReq MSHR miss cycles 553system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337991000 # number of ReadReq MSHR miss cycles 554system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11121217500 # number of WriteReq MSHR miss cycles 555system.cpu.dcache.WriteReq_mshr_miss_latency::total 11121217500 # number of WriteReq MSHR miss cycles 556system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 946000 # number of SoftPFReq MSHR miss cycles 557system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 946000 # number of SoftPFReq MSHR miss cycles 558system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23459208500 # number of demand (read+write) MSHR miss cycles 559system.cpu.dcache.demand_mshr_miss_latency::total 23459208500 # number of demand (read+write) MSHR miss cycles 560system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23460154500 # number of overall MSHR miss cycles 561system.cpu.dcache.overall_mshr_miss_latency::total 23460154500 # number of overall MSHR miss cycles |
| 560system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses 561system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses 562system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses 563system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses | 562system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses 563system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses 564system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses 565system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses |
| 564system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005052 # mshr miss rate for SoftPFReq accesses 565system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005052 # mshr miss rate for SoftPFReq accesses | 566system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004335 # mshr miss rate for SoftPFReq accesses 567system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004335 # mshr miss rate for SoftPFReq accesses |
| 566system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses 567system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses 568system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses 569system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses | 568system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses 569system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses 570system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses 571system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses |
| 570system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.069967 # average ReadReq mshr miss latency 571system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.069967 # average ReadReq mshr miss latency 572system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31221.352624 # average WriteReq mshr miss latency 573system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31221.352624 # average WriteReq mshr miss latency 574system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73428.571429 # average SoftPFReq mshr miss latency 575system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73428.571429 # average SoftPFReq mshr miss latency 576system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20503.925517 # average overall mshr miss latency 577system.cpu.dcache.demand_avg_mshr_miss_latency::total 20503.925517 # average overall mshr miss latency 578system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20504.573159 # average overall mshr miss latency 579system.cpu.dcache.overall_avg_mshr_miss_latency::total 20504.573159 # average overall mshr miss latency | 572system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.336210 # average ReadReq mshr miss latency 573system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.336210 # average ReadReq mshr miss latency 574system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31224.639777 # average WriteReq mshr miss latency 575system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31224.639777 # average WriteReq mshr miss latency 576system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78833.333333 # average SoftPFReq mshr miss latency 577system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78833.333333 # average SoftPFReq mshr miss latency 578system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20505.082303 # average overall mshr miss latency 579system.cpu.dcache.demand_avg_mshr_miss_latency::total 20505.082303 # average overall mshr miss latency 580system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20505.694095 # average overall mshr miss latency 581system.cpu.dcache.overall_avg_mshr_miss_latency::total 20505.694095 # average overall mshr miss latency |
| 580system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 582system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 581system.cpu.icache.tags.replacements 17719 # number of replacements 582system.cpu.icache.tags.tagsinuse 1188.326281 # Cycle average of tags in use 583system.cpu.icache.tags.total_refs 199317838 # Total number of references to valid blocks. 584system.cpu.icache.tags.sampled_refs 19591 # Sample count of references to valid blocks. 585system.cpu.icache.tags.avg_refs 10173.949160 # Average number of references to valid blocks. | 583system.cpu.icache.tags.replacements 17702 # number of replacements 584system.cpu.icache.tags.tagsinuse 1188.317648 # Cycle average of tags in use 585system.cpu.icache.tags.total_refs 199314883 # Total number of references to valid blocks. 586system.cpu.icache.tags.sampled_refs 19574 # Sample count of references to valid blocks. 587system.cpu.icache.tags.avg_refs 10182.634260 # Average number of references to valid blocks. |
| 586system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 588system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 587system.cpu.icache.tags.occ_blocks::cpu.inst 1188.326281 # Average occupied blocks per requestor 588system.cpu.icache.tags.occ_percent::cpu.inst 0.580237 # Average percentage of cache occupancy 589system.cpu.icache.tags.occ_percent::total 0.580237 # Average percentage of cache occupancy | 589system.cpu.icache.tags.occ_blocks::cpu.inst 1188.317648 # Average occupied blocks per requestor 590system.cpu.icache.tags.occ_percent::cpu.inst 0.580233 # Average percentage of cache occupancy 591system.cpu.icache.tags.occ_percent::total 0.580233 # Average percentage of cache occupancy |
| 590system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 591system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id | 592system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 593system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id |
| 592system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 593system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id 594system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id 595system.cpu.icache.tags.age_task_id_blocks_1024::4 1407 # Occupied blocks per task id | 594system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 595system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id 596system.cpu.icache.tags.age_task_id_blocks_1024::3 306 # Occupied blocks per task id 597system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id |
| 596system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id | 598system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id |
| 597system.cpu.icache.tags.tag_accesses 398694449 # Number of tag accesses 598system.cpu.icache.tags.data_accesses 398694449 # Number of data accesses 599system.cpu.icache.ReadReq_hits::cpu.inst 199317838 # number of ReadReq hits 600system.cpu.icache.ReadReq_hits::total 199317838 # number of ReadReq hits 601system.cpu.icache.demand_hits::cpu.inst 199317838 # number of demand (read+write) hits 602system.cpu.icache.demand_hits::total 199317838 # number of demand (read+write) hits 603system.cpu.icache.overall_hits::cpu.inst 199317838 # number of overall hits 604system.cpu.icache.overall_hits::total 199317838 # number of overall hits 605system.cpu.icache.ReadReq_misses::cpu.inst 19591 # number of ReadReq misses 606system.cpu.icache.ReadReq_misses::total 19591 # number of ReadReq misses 607system.cpu.icache.demand_misses::cpu.inst 19591 # number of demand (read+write) misses 608system.cpu.icache.demand_misses::total 19591 # number of demand (read+write) misses 609system.cpu.icache.overall_misses::cpu.inst 19591 # number of overall misses 610system.cpu.icache.overall_misses::total 19591 # number of overall misses 611system.cpu.icache.ReadReq_miss_latency::cpu.inst 490899000 # number of ReadReq miss cycles 612system.cpu.icache.ReadReq_miss_latency::total 490899000 # number of ReadReq miss cycles 613system.cpu.icache.demand_miss_latency::cpu.inst 490899000 # number of demand (read+write) miss cycles 614system.cpu.icache.demand_miss_latency::total 490899000 # number of demand (read+write) miss cycles 615system.cpu.icache.overall_miss_latency::cpu.inst 490899000 # number of overall miss cycles 616system.cpu.icache.overall_miss_latency::total 490899000 # number of overall miss cycles 617system.cpu.icache.ReadReq_accesses::cpu.inst 199337429 # number of ReadReq accesses(hits+misses) 618system.cpu.icache.ReadReq_accesses::total 199337429 # number of ReadReq accesses(hits+misses) 619system.cpu.icache.demand_accesses::cpu.inst 199337429 # number of demand (read+write) accesses 620system.cpu.icache.demand_accesses::total 199337429 # number of demand (read+write) accesses 621system.cpu.icache.overall_accesses::cpu.inst 199337429 # number of overall (read+write) accesses 622system.cpu.icache.overall_accesses::total 199337429 # number of overall (read+write) accesses | 599system.cpu.icache.tags.tag_accesses 398688488 # Number of tag accesses 600system.cpu.icache.tags.data_accesses 398688488 # Number of data accesses 601system.cpu.icache.ReadReq_hits::cpu.inst 199314883 # number of ReadReq hits 602system.cpu.icache.ReadReq_hits::total 199314883 # number of ReadReq hits 603system.cpu.icache.demand_hits::cpu.inst 199314883 # number of demand (read+write) hits 604system.cpu.icache.demand_hits::total 199314883 # number of demand (read+write) hits 605system.cpu.icache.overall_hits::cpu.inst 199314883 # number of overall hits 606system.cpu.icache.overall_hits::total 199314883 # number of overall hits 607system.cpu.icache.ReadReq_misses::cpu.inst 19574 # number of ReadReq misses 608system.cpu.icache.ReadReq_misses::total 19574 # number of ReadReq misses 609system.cpu.icache.demand_misses::cpu.inst 19574 # number of demand (read+write) misses 610system.cpu.icache.demand_misses::total 19574 # number of demand (read+write) misses 611system.cpu.icache.overall_misses::cpu.inst 19574 # number of overall misses 612system.cpu.icache.overall_misses::total 19574 # number of overall misses 613system.cpu.icache.ReadReq_miss_latency::cpu.inst 491333500 # number of ReadReq miss cycles 614system.cpu.icache.ReadReq_miss_latency::total 491333500 # number of ReadReq miss cycles 615system.cpu.icache.demand_miss_latency::cpu.inst 491333500 # number of demand (read+write) miss cycles 616system.cpu.icache.demand_miss_latency::total 491333500 # number of demand (read+write) miss cycles 617system.cpu.icache.overall_miss_latency::cpu.inst 491333500 # number of overall miss cycles 618system.cpu.icache.overall_miss_latency::total 491333500 # number of overall miss cycles 619system.cpu.icache.ReadReq_accesses::cpu.inst 199334457 # number of ReadReq accesses(hits+misses) 620system.cpu.icache.ReadReq_accesses::total 199334457 # number of ReadReq accesses(hits+misses) 621system.cpu.icache.demand_accesses::cpu.inst 199334457 # number of demand (read+write) accesses 622system.cpu.icache.demand_accesses::total 199334457 # number of demand (read+write) accesses 623system.cpu.icache.overall_accesses::cpu.inst 199334457 # number of overall (read+write) accesses 624system.cpu.icache.overall_accesses::total 199334457 # number of overall (read+write) accesses |
| 623system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses 624system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses 625system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses 626system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses 627system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses 628system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses | 625system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses 626system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses 627system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses 628system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses 629system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses 630system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses |
| 629system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25057.373284 # average ReadReq miss latency 630system.cpu.icache.ReadReq_avg_miss_latency::total 25057.373284 # average ReadReq miss latency 631system.cpu.icache.demand_avg_miss_latency::cpu.inst 25057.373284 # average overall miss latency 632system.cpu.icache.demand_avg_miss_latency::total 25057.373284 # average overall miss latency 633system.cpu.icache.overall_avg_miss_latency::cpu.inst 25057.373284 # average overall miss latency 634system.cpu.icache.overall_avg_miss_latency::total 25057.373284 # average overall miss latency | 631system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25101.333401 # average ReadReq miss latency 632system.cpu.icache.ReadReq_avg_miss_latency::total 25101.333401 # average ReadReq miss latency 633system.cpu.icache.demand_avg_miss_latency::cpu.inst 25101.333401 # average overall miss latency 634system.cpu.icache.demand_avg_miss_latency::total 25101.333401 # average overall miss latency 635system.cpu.icache.overall_avg_miss_latency::cpu.inst 25101.333401 # average overall miss latency 636system.cpu.icache.overall_avg_miss_latency::total 25101.333401 # average overall miss latency |
| 635system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 636system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 637system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 638system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 639system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 640system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 641system.cpu.icache.fast_writes 0 # number of fast writes performed 642system.cpu.icache.cache_copies 0 # number of cache copies performed | 637system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 638system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 640system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 641system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 642system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.icache.fast_writes 0 # number of fast writes performed 644system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 643system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19591 # number of ReadReq MSHR misses 644system.cpu.icache.ReadReq_mshr_misses::total 19591 # number of ReadReq MSHR misses 645system.cpu.icache.demand_mshr_misses::cpu.inst 19591 # number of demand (read+write) MSHR misses 646system.cpu.icache.demand_mshr_misses::total 19591 # number of demand (read+write) MSHR misses 647system.cpu.icache.overall_mshr_misses::cpu.inst 19591 # number of overall MSHR misses 648system.cpu.icache.overall_mshr_misses::total 19591 # number of overall MSHR misses 649system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 471308000 # number of ReadReq MSHR miss cycles 650system.cpu.icache.ReadReq_mshr_miss_latency::total 471308000 # number of ReadReq MSHR miss cycles 651system.cpu.icache.demand_mshr_miss_latency::cpu.inst 471308000 # number of demand (read+write) MSHR miss cycles 652system.cpu.icache.demand_mshr_miss_latency::total 471308000 # number of demand (read+write) MSHR miss cycles 653system.cpu.icache.overall_mshr_miss_latency::cpu.inst 471308000 # number of overall MSHR miss cycles 654system.cpu.icache.overall_mshr_miss_latency::total 471308000 # number of overall MSHR miss cycles | 645system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19574 # number of ReadReq MSHR misses 646system.cpu.icache.ReadReq_mshr_misses::total 19574 # number of ReadReq MSHR misses 647system.cpu.icache.demand_mshr_misses::cpu.inst 19574 # number of demand (read+write) MSHR misses 648system.cpu.icache.demand_mshr_misses::total 19574 # number of demand (read+write) MSHR misses 649system.cpu.icache.overall_mshr_misses::cpu.inst 19574 # number of overall MSHR misses 650system.cpu.icache.overall_mshr_misses::total 19574 # number of overall MSHR misses 651system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 471759500 # number of ReadReq MSHR miss cycles 652system.cpu.icache.ReadReq_mshr_miss_latency::total 471759500 # number of ReadReq MSHR miss cycles 653system.cpu.icache.demand_mshr_miss_latency::cpu.inst 471759500 # number of demand (read+write) MSHR miss cycles 654system.cpu.icache.demand_mshr_miss_latency::total 471759500 # number of demand (read+write) MSHR miss cycles 655system.cpu.icache.overall_mshr_miss_latency::cpu.inst 471759500 # number of overall MSHR miss cycles 656system.cpu.icache.overall_mshr_miss_latency::total 471759500 # number of overall MSHR miss cycles |
| 655system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses 656system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses 657system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses 658system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses 659system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses 660system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses | 657system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses 658system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses 659system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses 660system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses 661system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses 662system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses |
| 661system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24057.373284 # average ReadReq mshr miss latency 662system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24057.373284 # average ReadReq mshr miss latency 663system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24057.373284 # average overall mshr miss latency 664system.cpu.icache.demand_avg_mshr_miss_latency::total 24057.373284 # average overall mshr miss latency 665system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24057.373284 # average overall mshr miss latency 666system.cpu.icache.overall_avg_mshr_miss_latency::total 24057.373284 # average overall mshr miss latency | 663system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24101.333401 # average ReadReq mshr miss latency 664system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24101.333401 # average ReadReq mshr miss latency 665system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24101.333401 # average overall mshr miss latency 666system.cpu.icache.demand_avg_mshr_miss_latency::total 24101.333401 # average overall mshr miss latency 667system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24101.333401 # average overall mshr miss latency 668system.cpu.icache.overall_avg_mshr_miss_latency::total 24101.333401 # average overall mshr miss latency |
| 667system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 669system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 668system.cpu.l2cache.tags.replacements 111367 # number of replacements 669system.cpu.l2cache.tags.tagsinuse 27634.082837 # Cycle average of tags in use 670system.cpu.l2cache.tags.total_refs 1767150 # Total number of references to valid blocks. 671system.cpu.l2cache.tags.sampled_refs 142553 # Sample count of references to valid blocks. 672system.cpu.l2cache.tags.avg_refs 12.396442 # Average number of references to valid blocks. 673system.cpu.l2cache.tags.warmup_cycle 163253470000 # Cycle when the warmup percentage was hit. 674system.cpu.l2cache.tags.occ_blocks::writebacks 23457.963317 # Average occupied blocks per requestor 675system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.755870 # Average occupied blocks per requestor 676system.cpu.l2cache.tags.occ_blocks::cpu.data 3786.363650 # Average occupied blocks per requestor 677system.cpu.l2cache.tags.occ_percent::writebacks 0.715880 # Average percentage of cache occupancy 678system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011894 # Average percentage of cache occupancy 679system.cpu.l2cache.tags.occ_percent::cpu.data 0.115551 # Average percentage of cache occupancy 680system.cpu.l2cache.tags.occ_percent::total 0.843325 # Average percentage of cache occupancy 681system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id 682system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id | 670system.cpu.l2cache.tags.replacements 111370 # number of replacements 671system.cpu.l2cache.tags.tagsinuse 27634.033642 # Cycle average of tags in use 672system.cpu.l2cache.tags.total_refs 1767249 # Total number of references to valid blocks. 673system.cpu.l2cache.tags.sampled_refs 142558 # Sample count of references to valid blocks. 674system.cpu.l2cache.tags.avg_refs 12.396702 # Average number of references to valid blocks. 675system.cpu.l2cache.tags.warmup_cycle 163253473000 # Cycle when the warmup percentage was hit. 676system.cpu.l2cache.tags.occ_blocks::writebacks 23457.713364 # Average occupied blocks per requestor 677system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.652620 # Average occupied blocks per requestor 678system.cpu.l2cache.tags.occ_blocks::cpu.data 3786.667658 # Average occupied blocks per requestor 679system.cpu.l2cache.tags.occ_percent::writebacks 0.715873 # Average percentage of cache occupancy 680system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011891 # Average percentage of cache occupancy 681system.cpu.l2cache.tags.occ_percent::cpu.data 0.115560 # Average percentage of cache occupancy 682system.cpu.l2cache.tags.occ_percent::total 0.843324 # Average percentage of cache occupancy 683system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id 684system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id |
| 683system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id | 685system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id |
| 684system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4935 # Occupied blocks per task id 685system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25860 # Occupied blocks per task id 686system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id 687system.cpu.l2cache.tags.tag_accesses 19030386 # Number of tag accesses 688system.cpu.l2cache.tags.data_accesses 19030386 # Number of data accesses 689system.cpu.l2cache.Writeback_hits::writebacks 1068574 # number of Writeback hits 690system.cpu.l2cache.Writeback_hits::total 1068574 # number of Writeback hits 691system.cpu.l2cache.ReadExReq_hits::cpu.data 255588 # number of ReadExReq hits 692system.cpu.l2cache.ReadExReq_hits::total 255588 # number of ReadExReq hits 693system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16163 # number of ReadCleanReq hits 694system.cpu.l2cache.ReadCleanReq_hits::total 16163 # number of ReadCleanReq hits 695system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747770 # number of ReadSharedReq hits 696system.cpu.l2cache.ReadSharedReq_hits::total 747770 # number of ReadSharedReq hits 697system.cpu.l2cache.demand_hits::cpu.inst 16163 # number of demand (read+write) hits 698system.cpu.l2cache.demand_hits::cpu.data 1003358 # number of demand (read+write) hits 699system.cpu.l2cache.demand_hits::total 1019521 # number of demand (read+write) hits 700system.cpu.l2cache.overall_hits::cpu.inst 16163 # number of overall hits 701system.cpu.l2cache.overall_hits::cpu.data 1003358 # number of overall hits 702system.cpu.l2cache.overall_hits::total 1019521 # number of overall hits | 686system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id 687system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25857 # Occupied blocks per task id 688system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id 689system.cpu.l2cache.tags.tag_accesses 19030322 # Number of tag accesses 690system.cpu.l2cache.tags.data_accesses 19030322 # Number of data accesses 691system.cpu.l2cache.Writeback_hits::writebacks 1068583 # number of Writeback hits 692system.cpu.l2cache.Writeback_hits::total 1068583 # number of Writeback hits 693system.cpu.l2cache.ReadExReq_hits::cpu.data 255591 # number of ReadExReq hits 694system.cpu.l2cache.ReadExReq_hits::total 255591 # number of ReadExReq hits 695system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16143 # number of ReadCleanReq hits 696system.cpu.l2cache.ReadCleanReq_hits::total 16143 # number of ReadCleanReq hits 697system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747780 # number of ReadSharedReq hits 698system.cpu.l2cache.ReadSharedReq_hits::total 747780 # number of ReadSharedReq hits 699system.cpu.l2cache.demand_hits::cpu.inst 16143 # number of demand (read+write) hits 700system.cpu.l2cache.demand_hits::cpu.data 1003371 # number of demand (read+write) hits 701system.cpu.l2cache.demand_hits::total 1019514 # number of demand (read+write) hits 702system.cpu.l2cache.overall_hits::cpu.inst 16143 # number of overall hits 703system.cpu.l2cache.overall_hits::cpu.data 1003371 # number of overall hits 704system.cpu.l2cache.overall_hits::total 1019514 # number of overall hits |
| 703system.cpu.l2cache.ReadExReq_misses::cpu.data 100829 # number of ReadExReq misses 704system.cpu.l2cache.ReadExReq_misses::total 100829 # number of ReadExReq misses | 705system.cpu.l2cache.ReadExReq_misses::cpu.data 100829 # number of ReadExReq misses 706system.cpu.l2cache.ReadExReq_misses::total 100829 # number of ReadExReq misses |
| 705system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3428 # number of ReadCleanReq misses 706system.cpu.l2cache.ReadCleanReq_misses::total 3428 # number of ReadCleanReq misses | 707system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3431 # number of ReadCleanReq misses 708system.cpu.l2cache.ReadCleanReq_misses::total 3431 # number of ReadCleanReq misses |
| 707system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39880 # number of ReadSharedReq misses 708system.cpu.l2cache.ReadSharedReq_misses::total 39880 # number of ReadSharedReq misses | 709system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39880 # number of ReadSharedReq misses 710system.cpu.l2cache.ReadSharedReq_misses::total 39880 # number of ReadSharedReq misses |
| 709system.cpu.l2cache.demand_misses::cpu.inst 3428 # number of demand (read+write) misses | 711system.cpu.l2cache.demand_misses::cpu.inst 3431 # number of demand (read+write) misses |
| 710system.cpu.l2cache.demand_misses::cpu.data 140709 # number of demand (read+write) misses | 712system.cpu.l2cache.demand_misses::cpu.data 140709 # number of demand (read+write) misses |
| 711system.cpu.l2cache.demand_misses::total 144137 # number of demand (read+write) misses 712system.cpu.l2cache.overall_misses::cpu.inst 3428 # number of overall misses | 713system.cpu.l2cache.demand_misses::total 144140 # number of demand (read+write) misses 714system.cpu.l2cache.overall_misses::cpu.inst 3431 # number of overall misses |
| 713system.cpu.l2cache.overall_misses::cpu.data 140709 # number of overall misses | 715system.cpu.l2cache.overall_misses::cpu.data 140709 # number of overall misses |
| 714system.cpu.l2cache.overall_misses::total 144137 # number of overall misses 715system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7904552500 # number of ReadExReq miss cycles 716system.cpu.l2cache.ReadExReq_miss_latency::total 7904552500 # number of ReadExReq miss cycles 717system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 272166000 # number of ReadCleanReq miss cycles 718system.cpu.l2cache.ReadCleanReq_miss_latency::total 272166000 # number of ReadCleanReq miss cycles 719system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3286207500 # number of ReadSharedReq miss cycles 720system.cpu.l2cache.ReadSharedReq_miss_latency::total 3286207500 # number of ReadSharedReq miss cycles 721system.cpu.l2cache.demand_miss_latency::cpu.inst 272166000 # number of demand (read+write) miss cycles 722system.cpu.l2cache.demand_miss_latency::cpu.data 11190760000 # number of demand (read+write) miss cycles 723system.cpu.l2cache.demand_miss_latency::total 11462926000 # number of demand (read+write) miss cycles 724system.cpu.l2cache.overall_miss_latency::cpu.inst 272166000 # number of overall miss cycles 725system.cpu.l2cache.overall_miss_latency::cpu.data 11190760000 # number of overall miss cycles 726system.cpu.l2cache.overall_miss_latency::total 11462926000 # number of overall miss cycles 727system.cpu.l2cache.Writeback_accesses::writebacks 1068574 # number of Writeback accesses(hits+misses) 728system.cpu.l2cache.Writeback_accesses::total 1068574 # number of Writeback accesses(hits+misses) 729system.cpu.l2cache.ReadExReq_accesses::cpu.data 356417 # number of ReadExReq accesses(hits+misses) 730system.cpu.l2cache.ReadExReq_accesses::total 356417 # number of ReadExReq accesses(hits+misses) 731system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19591 # number of ReadCleanReq accesses(hits+misses) 732system.cpu.l2cache.ReadCleanReq_accesses::total 19591 # number of ReadCleanReq accesses(hits+misses) 733system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 787650 # number of ReadSharedReq accesses(hits+misses) 734system.cpu.l2cache.ReadSharedReq_accesses::total 787650 # number of ReadSharedReq accesses(hits+misses) 735system.cpu.l2cache.demand_accesses::cpu.inst 19591 # number of demand (read+write) accesses 736system.cpu.l2cache.demand_accesses::cpu.data 1144067 # number of demand (read+write) accesses 737system.cpu.l2cache.demand_accesses::total 1163658 # number of demand (read+write) accesses 738system.cpu.l2cache.overall_accesses::cpu.inst 19591 # number of overall (read+write) accesses 739system.cpu.l2cache.overall_accesses::cpu.data 1144067 # number of overall (read+write) accesses 740system.cpu.l2cache.overall_accesses::total 1163658 # number of overall (read+write) accesses 741system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282896 # miss rate for ReadExReq accesses 742system.cpu.l2cache.ReadExReq_miss_rate::total 0.282896 # miss rate for ReadExReq accesses 743system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.174978 # miss rate for ReadCleanReq accesses 744system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.174978 # miss rate for ReadCleanReq accesses 745system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050632 # miss rate for ReadSharedReq accesses 746system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050632 # miss rate for ReadSharedReq accesses 747system.cpu.l2cache.demand_miss_rate::cpu.inst 0.174978 # miss rate for demand accesses 748system.cpu.l2cache.demand_miss_rate::cpu.data 0.122990 # miss rate for demand accesses 749system.cpu.l2cache.demand_miss_rate::total 0.123865 # miss rate for demand accesses 750system.cpu.l2cache.overall_miss_rate::cpu.inst 0.174978 # miss rate for overall accesses 751system.cpu.l2cache.overall_miss_rate::cpu.data 0.122990 # miss rate for overall accesses 752system.cpu.l2cache.overall_miss_rate::total 0.123865 # miss rate for overall accesses 753system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78395.625267 # average ReadExReq miss latency 754system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78395.625267 # average ReadExReq miss latency 755system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79394.982497 # average ReadCleanReq miss latency 756system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79394.982497 # average ReadCleanReq miss latency 757system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82402.394684 # average ReadSharedReq miss latency 758system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82402.394684 # average ReadSharedReq miss latency 759system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79394.982497 # average overall miss latency 760system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79531.231122 # average overall miss latency 761system.cpu.l2cache.demand_avg_miss_latency::total 79527.990731 # average overall miss latency 762system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79394.982497 # average overall miss latency 763system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79531.231122 # average overall miss latency 764system.cpu.l2cache.overall_avg_miss_latency::total 79527.990731 # average overall miss latency | 716system.cpu.l2cache.overall_misses::total 144140 # number of overall misses 717system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7905743000 # number of ReadExReq miss cycles 718system.cpu.l2cache.ReadExReq_miss_latency::total 7905743000 # number of ReadExReq miss cycles 719system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 272299500 # number of ReadCleanReq miss cycles 720system.cpu.l2cache.ReadCleanReq_miss_latency::total 272299500 # number of ReadCleanReq miss cycles 721system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3282195500 # number of ReadSharedReq miss cycles 722system.cpu.l2cache.ReadSharedReq_miss_latency::total 3282195500 # number of ReadSharedReq miss cycles 723system.cpu.l2cache.demand_miss_latency::cpu.inst 272299500 # number of demand (read+write) miss cycles 724system.cpu.l2cache.demand_miss_latency::cpu.data 11187938500 # number of demand (read+write) miss cycles 725system.cpu.l2cache.demand_miss_latency::total 11460238000 # number of demand (read+write) miss cycles 726system.cpu.l2cache.overall_miss_latency::cpu.inst 272299500 # number of overall miss cycles 727system.cpu.l2cache.overall_miss_latency::cpu.data 11187938500 # number of overall miss cycles 728system.cpu.l2cache.overall_miss_latency::total 11460238000 # number of overall miss cycles 729system.cpu.l2cache.Writeback_accesses::writebacks 1068583 # number of Writeback accesses(hits+misses) 730system.cpu.l2cache.Writeback_accesses::total 1068583 # number of Writeback accesses(hits+misses) 731system.cpu.l2cache.ReadExReq_accesses::cpu.data 356420 # number of ReadExReq accesses(hits+misses) 732system.cpu.l2cache.ReadExReq_accesses::total 356420 # number of ReadExReq accesses(hits+misses) 733system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19574 # number of ReadCleanReq accesses(hits+misses) 734system.cpu.l2cache.ReadCleanReq_accesses::total 19574 # number of ReadCleanReq accesses(hits+misses) 735system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 787660 # number of ReadSharedReq accesses(hits+misses) 736system.cpu.l2cache.ReadSharedReq_accesses::total 787660 # number of ReadSharedReq accesses(hits+misses) 737system.cpu.l2cache.demand_accesses::cpu.inst 19574 # number of demand (read+write) accesses 738system.cpu.l2cache.demand_accesses::cpu.data 1144080 # number of demand (read+write) accesses 739system.cpu.l2cache.demand_accesses::total 1163654 # number of demand (read+write) accesses 740system.cpu.l2cache.overall_accesses::cpu.inst 19574 # number of overall (read+write) accesses 741system.cpu.l2cache.overall_accesses::cpu.data 1144080 # number of overall (read+write) accesses 742system.cpu.l2cache.overall_accesses::total 1163654 # number of overall (read+write) accesses 743system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282894 # miss rate for ReadExReq accesses 744system.cpu.l2cache.ReadExReq_miss_rate::total 0.282894 # miss rate for ReadExReq accesses 745system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.175284 # miss rate for ReadCleanReq accesses 746system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.175284 # miss rate for ReadCleanReq accesses 747system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050631 # miss rate for ReadSharedReq accesses 748system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050631 # miss rate for ReadSharedReq accesses 749system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175284 # miss rate for demand accesses 750system.cpu.l2cache.demand_miss_rate::cpu.data 0.122989 # miss rate for demand accesses 751system.cpu.l2cache.demand_miss_rate::total 0.123868 # miss rate for demand accesses 752system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175284 # miss rate for overall accesses 753system.cpu.l2cache.overall_miss_rate::cpu.data 0.122989 # miss rate for overall accesses 754system.cpu.l2cache.overall_miss_rate::total 0.123868 # miss rate for overall accesses 755system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78407.432386 # average ReadExReq miss latency 756system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78407.432386 # average ReadExReq miss latency 757system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79364.471000 # average ReadCleanReq miss latency 758system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79364.471000 # average ReadCleanReq miss latency 759system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82301.792879 # average ReadSharedReq miss latency 760system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82301.792879 # average ReadSharedReq miss latency 761system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79364.471000 # average overall miss latency 762system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79511.179100 # average overall miss latency 763system.cpu.l2cache.demand_avg_miss_latency::total 79507.686971 # average overall miss latency 764system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79364.471000 # average overall miss latency 765system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79511.179100 # average overall miss latency 766system.cpu.l2cache.overall_avg_miss_latency::total 79507.686971 # average overall miss latency |
| 765system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 766system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 767system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 768system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 769system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 770system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 771system.cpu.l2cache.fast_writes 0 # number of fast writes performed 772system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 767system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 768system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 769system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 770system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 771system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 772system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 773system.cpu.l2cache.fast_writes 0 # number of fast writes performed 774system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 773system.cpu.l2cache.writebacks::writebacks 96704 # number of writebacks 774system.cpu.l2cache.writebacks::total 96704 # number of writebacks | 775system.cpu.l2cache.writebacks::writebacks 96709 # number of writebacks 776system.cpu.l2cache.writebacks::total 96709 # number of writebacks |
| 775system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 776system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 777system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 778system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 779system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 780system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 781system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 782system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 783system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits 784system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits | 777system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 778system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 779system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 780system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 781system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 782system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 783system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 784system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 785system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits 786system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits |
| 785system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1193 # number of CleanEvict MSHR misses 786system.cpu.l2cache.CleanEvict_mshr_misses::total 1193 # number of CleanEvict MSHR misses | 787system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1197 # number of CleanEvict MSHR misses 788system.cpu.l2cache.CleanEvict_mshr_misses::total 1197 # number of CleanEvict MSHR misses |
| 787system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100829 # number of ReadExReq MSHR misses 788system.cpu.l2cache.ReadExReq_mshr_misses::total 100829 # number of ReadExReq MSHR misses | 789system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100829 # number of ReadExReq MSHR misses 790system.cpu.l2cache.ReadExReq_mshr_misses::total 100829 # number of ReadExReq MSHR misses |
| 789system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3426 # number of ReadCleanReq MSHR misses 790system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3426 # number of ReadCleanReq MSHR misses | 791system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3429 # number of ReadCleanReq MSHR misses 792system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3429 # number of ReadCleanReq MSHR misses |
| 791system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39866 # number of ReadSharedReq MSHR misses 792system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39866 # number of ReadSharedReq MSHR misses | 793system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39866 # number of ReadSharedReq MSHR misses 794system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39866 # number of ReadSharedReq MSHR misses |
| 793system.cpu.l2cache.demand_mshr_misses::cpu.inst 3426 # number of demand (read+write) MSHR misses | 795system.cpu.l2cache.demand_mshr_misses::cpu.inst 3429 # number of demand (read+write) MSHR misses |
| 794system.cpu.l2cache.demand_mshr_misses::cpu.data 140695 # number of demand (read+write) MSHR misses | 796system.cpu.l2cache.demand_mshr_misses::cpu.data 140695 # number of demand (read+write) MSHR misses |
| 795system.cpu.l2cache.demand_mshr_misses::total 144121 # number of demand (read+write) MSHR misses 796system.cpu.l2cache.overall_mshr_misses::cpu.inst 3426 # number of overall MSHR misses | 797system.cpu.l2cache.demand_mshr_misses::total 144124 # number of demand (read+write) MSHR misses 798system.cpu.l2cache.overall_mshr_misses::cpu.inst 3429 # number of overall MSHR misses |
| 797system.cpu.l2cache.overall_mshr_misses::cpu.data 140695 # number of overall MSHR misses | 799system.cpu.l2cache.overall_mshr_misses::cpu.data 140695 # number of overall MSHR misses |
| 798system.cpu.l2cache.overall_mshr_misses::total 144121 # number of overall MSHR misses 799system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6896262500 # number of ReadExReq MSHR miss cycles 800system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6896262500 # number of ReadExReq MSHR miss cycles 801system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 237598000 # number of ReadCleanReq MSHR miss cycles 802system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 237598000 # number of ReadCleanReq MSHR miss cycles 803system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2886048500 # number of ReadSharedReq MSHR miss cycles 804system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2886048500 # number of ReadSharedReq MSHR miss cycles 805system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 237598000 # number of demand (read+write) MSHR miss cycles 806system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9782311000 # number of demand (read+write) MSHR miss cycles 807system.cpu.l2cache.demand_mshr_miss_latency::total 10019909000 # number of demand (read+write) MSHR miss cycles 808system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 237598000 # number of overall MSHR miss cycles 809system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9782311000 # number of overall MSHR miss cycles 810system.cpu.l2cache.overall_mshr_miss_latency::total 10019909000 # number of overall MSHR miss cycles | 800system.cpu.l2cache.overall_mshr_misses::total 144124 # number of overall MSHR misses 801system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6897453000 # number of ReadExReq MSHR miss cycles 802system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6897453000 # number of ReadExReq MSHR miss cycles 803system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 237701500 # number of ReadCleanReq MSHR miss cycles 804system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 237701500 # number of ReadCleanReq MSHR miss cycles 805system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2882229000 # number of ReadSharedReq MSHR miss cycles 806system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2882229000 # number of ReadSharedReq MSHR miss cycles 807system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 237701500 # number of demand (read+write) MSHR miss cycles 808system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9779682000 # number of demand (read+write) MSHR miss cycles 809system.cpu.l2cache.demand_mshr_miss_latency::total 10017383500 # number of demand (read+write) MSHR miss cycles 810system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 237701500 # number of overall MSHR miss cycles 811system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9779682000 # number of overall MSHR miss cycles 812system.cpu.l2cache.overall_mshr_miss_latency::total 10017383500 # number of overall MSHR miss cycles |
| 811system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 812system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 813system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 814system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 813system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282896 # mshr miss rate for ReadExReq accesses 814system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282896 # mshr miss rate for ReadExReq accesses 815system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for ReadCleanReq accesses 816system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.174876 # mshr miss rate for ReadCleanReq accesses 817system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050614 # mshr miss rate for ReadSharedReq accesses 818system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050614 # mshr miss rate for ReadSharedReq accesses 819system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for demand accesses 820system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for demand accesses 821system.cpu.l2cache.demand_mshr_miss_rate::total 0.123852 # mshr miss rate for demand accesses 822system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for overall accesses 823system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for overall accesses 824system.cpu.l2cache.overall_mshr_miss_rate::total 0.123852 # mshr miss rate for overall accesses 825system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68395.625267 # average ReadExReq mshr miss latency 826system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68395.625267 # average ReadExReq mshr miss latency 827system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69351.430239 # average ReadCleanReq mshr miss latency 828system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69351.430239 # average ReadCleanReq mshr miss latency 829system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72393.731501 # average ReadSharedReq mshr miss latency 830system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72393.731501 # average ReadSharedReq mshr miss latency 831system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency 832system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency 833system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency 834system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency 835system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency 836system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency | 815system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282894 # mshr miss rate for ReadExReq accesses 816system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282894 # mshr miss rate for ReadExReq accesses 817system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for ReadCleanReq accesses 818system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.175181 # mshr miss rate for ReadCleanReq accesses 819system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050613 # mshr miss rate for ReadSharedReq accesses 820system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050613 # mshr miss rate for ReadSharedReq accesses 821system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for demand accesses 822system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses 823system.cpu.l2cache.demand_mshr_miss_rate::total 0.123855 # mshr miss rate for demand accesses 824system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for overall accesses 825system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses 826system.cpu.l2cache.overall_mshr_miss_rate::total 0.123855 # mshr miss rate for overall accesses 827system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68407.432386 # average ReadExReq mshr miss latency 828system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68407.432386 # average ReadExReq mshr miss latency 829system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69320.939049 # average ReadCleanReq mshr miss latency 830system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69320.939049 # average ReadCleanReq mshr miss latency 831system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72297.923042 # average ReadSharedReq mshr miss latency 832system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72297.923042 # average ReadSharedReq mshr miss latency 833system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69320.939049 # average overall mshr miss latency 834system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69509.804897 # average overall mshr miss latency 835system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69505.311399 # average overall mshr miss latency 836system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69320.939049 # average overall mshr miss latency 837system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69509.804897 # average overall mshr miss latency 838system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69505.311399 # average overall mshr miss latency |
| 837system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 839system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 838system.cpu.toL2Bus.trans_dist::ReadResp 807241 # Transaction distribution 839system.cpu.toL2Bus.trans_dist::Writeback 1165278 # Transaction distribution 840system.cpu.toL2Bus.trans_dist::CleanEvict 98858 # Transaction distribution 841system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution 842system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution 843system.cpu.toL2Bus.trans_dist::ReadCleanReq 19591 # Transaction distribution 844system.cpu.toL2Bus.trans_dist::ReadSharedReq 787650 # Transaction distribution 845system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56664 # Packet count per connected master and slave (bytes) 846system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423421 # Packet count per connected master and slave (bytes) 847system.cpu.toL2Bus.pkt_count::total 3480085 # Packet count per connected master and slave (bytes) 848system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253824 # Cumulative packet size per connected master and slave (bytes) 849system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141609024 # Cumulative packet size per connected master and slave (bytes) 850system.cpu.toL2Bus.pkt_size::total 142862848 # Cumulative packet size per connected master and slave (bytes) 851system.cpu.toL2Bus.snoops 111367 # Total snoops (count) 852system.cpu.toL2Bus.snoop_fanout::samples 2432715 # Request fanout histogram 853system.cpu.toL2Bus.snoop_fanout::mean 1.045779 # Request fanout histogram 854system.cpu.toL2Bus.snoop_fanout::stdev 0.209005 # Request fanout histogram | 840system.cpu.toL2Bus.snoop_filter.tot_requests 2321340 # Total number of requests made to the snoop filter. 841system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157756 # Number of requests hitting in the snoop filter with a single holder of the requested data. 842system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4922 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 843system.cpu.toL2Bus.snoop_filter.tot_snoops 2616 # Total number of snoops made to the snoop filter. 844system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 845system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 846system.cpu.toL2Bus.trans_dist::ReadResp 807234 # Transaction distribution 847system.cpu.toL2Bus.trans_dist::Writeback 1165292 # Transaction distribution 848system.cpu.toL2Bus.trans_dist::CleanEvict 98842 # Transaction distribution 849system.cpu.toL2Bus.trans_dist::ReadExReq 356420 # Transaction distribution 850system.cpu.toL2Bus.trans_dist::ReadExResp 356420 # Transaction distribution 851system.cpu.toL2Bus.trans_dist::ReadCleanReq 19574 # Transaction distribution 852system.cpu.toL2Bus.trans_dist::ReadSharedReq 787660 # Transaction distribution 853system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56613 # Packet count per connected master and slave (bytes) 854system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423459 # Packet count per connected master and slave (bytes) 855system.cpu.toL2Bus.pkt_count::total 3480072 # Packet count per connected master and slave (bytes) 856system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252736 # Cumulative packet size per connected master and slave (bytes) 857system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141610432 # Cumulative packet size per connected master and slave (bytes) 858system.cpu.toL2Bus.pkt_size::total 142863168 # Cumulative packet size per connected master and slave (bytes) 859system.cpu.toL2Bus.snoops 111370 # Total snoops (count) 860system.cpu.toL2Bus.snoop_fanout::samples 2432710 # Request fanout histogram 861system.cpu.toL2Bus.snoop_fanout::mean 0.005152 # Request fanout histogram 862system.cpu.toL2Bus.snoop_fanout::stdev 0.071609 # Request fanout histogram |
| 855system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 863system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 856system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 857system.cpu.toL2Bus.snoop_fanout::1 2321348 95.42% 95.42% # Request fanout histogram 858system.cpu.toL2Bus.snoop_fanout::2 111367 4.58% 100.00% # Request fanout histogram | 864system.cpu.toL2Bus.snoop_fanout::0 2420180 99.48% 99.48% # Request fanout histogram 865system.cpu.toL2Bus.snoop_fanout::1 12527 0.51% 100.00% # Request fanout histogram 866system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram |
| 859system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 867system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 860system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 868system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 861system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 869system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 862system.cpu.toL2Bus.snoop_fanout::total 2432715 # Request fanout histogram 863system.cpu.toL2Bus.reqLayer0.occupancy 2229248000 # Layer occupancy (ticks) | 870system.cpu.toL2Bus.snoop_fanout::total 2432710 # Request fanout histogram 871system.cpu.toL2Bus.reqLayer0.occupancy 2229253000 # Layer occupancy (ticks) |
| 864system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) | 872system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 865system.cpu.toL2Bus.respLayer0.occupancy 29387997 # Layer occupancy (ticks) | 873system.cpu.toL2Bus.respLayer0.occupancy 29379463 # Layer occupancy (ticks) |
| 866system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 874system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 867system.cpu.toL2Bus.respLayer1.occupancy 1716107486 # Layer occupancy (ticks) | 875system.cpu.toL2Bus.respLayer1.occupancy 1716126986 # Layer occupancy (ticks) |
| 868system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) | 876system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) |
| 869system.membus.trans_dist::ReadResp 43292 # Transaction distribution 870system.membus.trans_dist::Writeback 96704 # Transaction distribution 871system.membus.trans_dist::CleanEvict 13244 # Transaction distribution | 877system.membus.trans_dist::ReadResp 43295 # Transaction distribution 878system.membus.trans_dist::Writeback 96709 # Transaction distribution 879system.membus.trans_dist::CleanEvict 13242 # Transaction distribution |
| 872system.membus.trans_dist::ReadExReq 100829 # Transaction distribution 873system.membus.trans_dist::ReadExResp 100829 # Transaction distribution | 880system.membus.trans_dist::ReadExReq 100829 # Transaction distribution 881system.membus.trans_dist::ReadExResp 100829 # Transaction distribution |
| 874system.membus.trans_dist::ReadSharedReq 43292 # Transaction distribution 875system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398190 # Packet count per connected master and slave (bytes) 876system.membus.pkt_count::total 398190 # Packet count per connected master and slave (bytes) 877system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15412800 # Cumulative packet size per connected master and slave (bytes) 878system.membus.pkt_size::total 15412800 # Cumulative packet size per connected master and slave (bytes) | 882system.membus.trans_dist::ReadSharedReq 43295 # Transaction distribution 883system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398199 # Packet count per connected master and slave (bytes) 884system.membus.pkt_count::total 398199 # Packet count per connected master and slave (bytes) 885system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15413312 # Cumulative packet size per connected master and slave (bytes) 886system.membus.pkt_size::total 15413312 # Cumulative packet size per connected master and slave (bytes) |
| 879system.membus.snoops 0 # Total snoops (count) | 887system.membus.snoops 0 # Total snoops (count) |
| 880system.membus.snoop_fanout::samples 254069 # Request fanout histogram | 888system.membus.snoop_fanout::samples 254075 # Request fanout histogram |
| 881system.membus.snoop_fanout::mean 0 # Request fanout histogram 882system.membus.snoop_fanout::stdev 0 # Request fanout histogram 883system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 889system.membus.snoop_fanout::mean 0 # Request fanout histogram 890system.membus.snoop_fanout::stdev 0 # Request fanout histogram 891system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 884system.membus.snoop_fanout::0 254069 100.00% 100.00% # Request fanout histogram | 892system.membus.snoop_fanout::0 254075 100.00% 100.00% # Request fanout histogram |
| 885system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 886system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 887system.membus.snoop_fanout::min_value 0 # Request fanout histogram 888system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 893system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 894system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 895system.membus.snoop_fanout::min_value 0 # Request fanout histogram 896system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 889system.membus.snoop_fanout::total 254069 # Request fanout histogram 890system.membus.reqLayer0.occupancy 683631500 # Layer occupancy (ticks) | 897system.membus.snoop_fanout::total 254075 # Request fanout histogram 898system.membus.reqLayer0.occupancy 683661500 # Layer occupancy (ticks) |
| 891system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) | 899system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 892system.membus.respLayer1.occupancy 765040250 # Layer occupancy (ticks) | 900system.membus.respLayer1.occupancy 765035500 # Layer occupancy (ticks) |
| 893system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 894 895---------- End Simulation Statistics ---------- | 901system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 902 903---------- End Simulation Statistics ---------- |