| stats.txt (10433:821cbe4a183b) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.361881 # Number of seconds simulated 4sim_ticks 361880862500 # Number of ticks simulated 5final_tick 361880862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.365348 # Number of seconds simulated 4sim_ticks 365347511000 # Number of ticks simulated 5final_tick 365347511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 214559 # Simulator instruction rate (inst/s) 8host_op_rate 232396 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 153272119 # Simulator tick rate (ticks/s) 10host_mem_usage 259716 # Number of bytes of host memory used 11host_seconds 2361.04 # Real time elapsed on the host | 7host_inst_rate 224796 # Simulator instruction rate (inst/s) 8host_op_rate 243484 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 162123009 # Simulator tick rate (ticks/s) 10host_mem_usage 256924 # Number of bytes of host memory used 11host_seconds 2253.52 # Real time elapsed on the host |
| 12sim_insts 506582155 # Number of instructions simulated 13sim_ops 548695378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 506582155 # Number of instructions simulated 13sim_ops 548695378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 9221824 # Number of bytes read from this memory 17system.physmem.bytes_read::total 9221824 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 6177344 # Number of bytes written to this memory 21system.physmem.bytes_written::total 6177344 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 144091 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 144091 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 96521 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 96521 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 25483039 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 25483039 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 612622 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 612622 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 17070104 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 17070104 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 17070104 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 25483039 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 42553143 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 144091 # Number of read requests accepted 36system.physmem.writeReqs 96521 # Number of write requests accepted 37system.physmem.readBursts 144091 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 96521 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 9215168 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue 41system.physmem.bytesWritten 6176128 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 9221824 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 6177344 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 9224896 # Number of bytes read from this memory 17system.physmem.bytes_read::total 9224896 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 221312 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 221312 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 6179008 # Number of bytes written to this memory 21system.physmem.bytes_written::total 6179008 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 144139 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 144139 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 96547 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 96547 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 25249648 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 25249648 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 605758 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 605758 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 16912687 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 16912687 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 16912687 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 25249648 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 42162335 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 144139 # Number of read requests accepted 36system.physmem.writeReqs 96547 # Number of write requests accepted 37system.physmem.readBursts 144139 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 96547 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 9218048 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue 41system.physmem.bytesWritten 6177856 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 9224896 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 6179008 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue |
| 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 47system.physmem.perBankRdBursts::0 9338 # Per bank write bursts 48system.physmem.perBankRdBursts::1 8967 # Per bank write bursts 49system.physmem.perBankRdBursts::2 9003 # Per bank write bursts 50system.physmem.perBankRdBursts::3 8705 # Per bank write bursts 51system.physmem.perBankRdBursts::4 9445 # Per bank write bursts 52system.physmem.perBankRdBursts::5 9343 # Per bank write bursts 53system.physmem.perBankRdBursts::6 8943 # Per bank write bursts 54system.physmem.perBankRdBursts::7 8100 # Per bank write bursts 55system.physmem.perBankRdBursts::8 8560 # Per bank write bursts 56system.physmem.perBankRdBursts::9 8672 # Per bank write bursts 57system.physmem.perBankRdBursts::10 8773 # Per bank write bursts 58system.physmem.perBankRdBursts::11 9480 # Per bank write bursts 59system.physmem.perBankRdBursts::12 9371 # Per bank write bursts 60system.physmem.perBankRdBursts::13 9512 # Per bank write bursts 61system.physmem.perBankRdBursts::14 8706 # Per bank write bursts 62system.physmem.perBankRdBursts::15 9069 # Per bank write bursts 63system.physmem.perBankWrBursts::0 6189 # Per bank write bursts | 47system.physmem.perBankRdBursts::0 9344 # Per bank write bursts 48system.physmem.perBankRdBursts::1 8969 # Per bank write bursts 49system.physmem.perBankRdBursts::2 8998 # Per bank write bursts 50system.physmem.perBankRdBursts::3 8704 # Per bank write bursts 51system.physmem.perBankRdBursts::4 9453 # Per bank write bursts 52system.physmem.perBankRdBursts::5 9341 # Per bank write bursts 53system.physmem.perBankRdBursts::6 8940 # Per bank write bursts 54system.physmem.perBankRdBursts::7 8101 # Per bank write bursts 55system.physmem.perBankRdBursts::8 8571 # Per bank write bursts 56system.physmem.perBankRdBursts::9 8677 # Per bank write bursts 57system.physmem.perBankRdBursts::10 8772 # Per bank write bursts 58system.physmem.perBankRdBursts::11 9476 # Per bank write bursts 59system.physmem.perBankRdBursts::12 9379 # Per bank write bursts 60system.physmem.perBankRdBursts::13 9523 # Per bank write bursts 61system.physmem.perBankRdBursts::14 8710 # Per bank write bursts 62system.physmem.perBankRdBursts::15 9074 # Per bank write bursts 63system.physmem.perBankWrBursts::0 6191 # Per bank write bursts |
| 64system.physmem.perBankWrBursts::1 6093 # Per bank write bursts | 64system.physmem.perBankWrBursts::1 6093 # Per bank write bursts |
| 65system.physmem.perBankWrBursts::2 6008 # Per bank write bursts 66system.physmem.perBankWrBursts::3 5816 # Per bank write bursts 67system.physmem.perBankWrBursts::4 6159 # Per bank write bursts 68system.physmem.perBankWrBursts::5 6173 # Per bank write bursts 69system.physmem.perBankWrBursts::6 6014 # Per bank write bursts | 65system.physmem.perBankWrBursts::2 6006 # Per bank write bursts 66system.physmem.perBankWrBursts::3 5817 # Per bank write bursts 67system.physmem.perBankWrBursts::4 6161 # Per bank write bursts 68system.physmem.perBankWrBursts::5 6171 # Per bank write bursts 69system.physmem.perBankWrBursts::6 6013 # Per bank write bursts |
| 70system.physmem.perBankWrBursts::7 5494 # Per bank write bursts | 70system.physmem.perBankWrBursts::7 5494 # Per bank write bursts |
| 71system.physmem.perBankWrBursts::8 5724 # Per bank write bursts 72system.physmem.perBankWrBursts::9 5818 # Per bank write bursts | 71system.physmem.perBankWrBursts::8 5728 # Per bank write bursts 72system.physmem.perBankWrBursts::9 5821 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::10 5961 # Per bank write bursts | 73system.physmem.perBankWrBursts::10 5961 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::11 6447 # Per bank write bursts 75system.physmem.perBankWrBursts::12 6306 # Per bank write bursts 76system.physmem.perBankWrBursts::13 6267 # Per bank write bursts 77system.physmem.perBankWrBursts::14 5992 # Per bank write bursts 78system.physmem.perBankWrBursts::15 6041 # Per bank write bursts | 74system.physmem.perBankWrBursts::11 6446 # Per bank write bursts 75system.physmem.perBankWrBursts::12 6308 # Per bank write bursts 76system.physmem.perBankWrBursts::13 6280 # Per bank write bursts 77system.physmem.perBankWrBursts::14 5994 # Per bank write bursts 78system.physmem.perBankWrBursts::15 6045 # Per bank write bursts |
| 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 81system.physmem.totGap 361880833500 # Total gap between requests | 81system.physmem.totGap 365347483000 # Total gap between requests |
| 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) | 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 88system.physmem.readPktSize::6 144091 # Read request sizes (log2) | 88system.physmem.readPktSize::6 144139 # Read request sizes (log2) |
| 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) | 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 95system.physmem.writePktSize::6 96521 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 143620 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 348 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see | 95system.physmem.writePktSize::6 96547 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 143system.physmem.wrQLenPdf::15 2769 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 2939 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 5678 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 5669 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 5685 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 5687 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 5701 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 5699 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 5689 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 5716 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 5703 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 5641 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 5637 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::15 2861 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 3022 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 5536 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 5697 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 5670 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 5682 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 5668 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 5678 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 5702 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 5698 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 5672 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 5626 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 5701 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 5628 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 5584 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see |
| 172system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see | 172system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see |
| 173system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see | 173system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see |
| 175system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 175system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 192system.physmem.bytesPerActivate::samples 64681 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 237.949073 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 157.463319 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 243.404639 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 24397 37.72% 37.72% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 18169 28.09% 65.81% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 6808 10.53% 76.33% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 7802 12.06% 88.40% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 2168 3.35% 91.75% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1166 1.80% 93.55% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 777 1.20% 94.75% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 613 0.95% 95.70% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 2781 4.30% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 64681 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 5584 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 25.784921 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 381.788967 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 5580 99.93% 99.93% # Reads before turning the bus around for writes | 192system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 237.344433 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 157.101707 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 243.291878 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 24488 37.75% 37.75% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 18300 28.21% 65.96% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 6859 10.57% 76.54% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 7791 12.01% 88.55% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 2064 3.18% 91.73% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1161 1.79% 93.52% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 764 1.18% 94.70% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 681 1.05% 95.75% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 2758 4.25% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 5569 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 25.862992 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 382.285392 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 5565 99.93% 99.93% # Reads before turning the bus around for writes |
| 210system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes | 210system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 212system.physmem.rdPerTurnAround::total 5584 # Reads before turning the bus around for writes 213system.physmem.wrPerTurnAround::samples 5584 # Writes before turning the bus around for reads 214system.physmem.wrPerTurnAround::mean 17.281877 # Writes before turning the bus around for reads 215system.physmem.wrPerTurnAround::gmean 17.171400 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::stdev 2.885179 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::16-19 5428 97.21% 97.21% # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::20-23 84 1.50% 98.71% # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::24-27 28 0.50% 99.21% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::28-31 20 0.36% 99.57% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::32-35 9 0.16% 99.73% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::36-39 7 0.13% 99.86% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::40-43 2 0.04% 99.89% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::44-47 1 0.02% 99.91% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::48-51 2 0.04% 99.95% # Writes before turning the bus around for reads | 212system.physmem.rdPerTurnAround::total 5569 # Reads before turning the bus around for writes 213system.physmem.wrPerTurnAround::samples 5569 # Writes before turning the bus around for reads 214system.physmem.wrPerTurnAround::mean 17.333273 # Writes before turning the bus around for reads 215system.physmem.wrPerTurnAround::gmean 17.210704 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::stdev 3.188900 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::16-19 5418 97.29% 97.29% # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::20-23 79 1.42% 98.71% # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::24-27 23 0.41% 99.12% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::28-31 20 0.36% 99.48% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::32-35 9 0.16% 99.64% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::36-39 7 0.13% 99.77% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::40-43 5 0.09% 99.86% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::44-47 5 0.09% 99.95% # Writes before turning the bus around for reads |
| 226system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads | 225system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads |
| 227system.physmem.wrPerTurnAround::72-75 1 0.02% 99.98% # Writes before turning the bus around for reads | 226system.physmem.wrPerTurnAround::120-123 1 0.02% 99.98% # Writes before turning the bus around for reads |
| 228system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads | 227system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads |
| 229system.physmem.wrPerTurnAround::total 5584 # Writes before turning the bus around for reads 230system.physmem.totQLat 1580318000 # Total ticks spent queuing 231system.physmem.totMemAccLat 4280074250 # Total ticks spent from burst creation until serviced by the DRAM 232system.physmem.totBusLat 719935000 # Total ticks spent in databus transfers 233system.physmem.avgQLat 10975.42 # Average queueing delay per DRAM burst | 228system.physmem.wrPerTurnAround::total 5569 # Writes before turning the bus around for reads 229system.physmem.totQLat 1570268250 # Total ticks spent queuing 230system.physmem.totMemAccLat 4270868250 # Total ticks spent from burst creation until serviced by the DRAM 231system.physmem.totBusLat 720160000 # Total ticks spent in databus transfers 232system.physmem.avgQLat 10902.22 # Average queueing delay per DRAM burst |
| 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 233system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 235system.physmem.avgMemAccLat 29725.42 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 25.46 # Average DRAM read bandwidth in MiByte/s 237system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s 238system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s | 234system.physmem.avgMemAccLat 29652.22 # Average memory access latency per DRAM burst 235system.physmem.avgRdBW 25.23 # Average DRAM read bandwidth in MiByte/s 236system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s 237system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s 238system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s |
| 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 241system.physmem.busUtil 0.33 # Data bus utilization in percentage 242system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 244system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing | 239system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 240system.physmem.busUtil 0.33 # Data bus utilization in percentage 241system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 242system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 243system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| 245system.physmem.avgWrQLen 20.42 # Average write queue length when enqueuing 246system.physmem.readRowHits 111153 # Number of row buffer hits during reads 247system.physmem.writeRowHits 64649 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 66.98 # Row buffer hit rate for writes 250system.physmem.avgGap 1504001.60 # Average gap between requests 251system.physmem.pageHitRate 73.10 # Row buffer hit rate, read and write combined 252system.physmem.memoryStateTime::IDLE 254039828500 # Time in different power states 253system.physmem.memoryStateTime::REF 12083760000 # Time in different power states | 244system.physmem.avgWrQLen 19.86 # Average write queue length when enqueuing 245system.physmem.readRowHits 110988 # Number of row buffer hits during reads 246system.physmem.writeRowHits 64704 # Number of row buffer hits during writes 247system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads 248system.physmem.writeRowHitRate 67.02 # Row buffer hit rate for writes 249system.physmem.avgGap 1517942.39 # Average gap between requests 250system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined 251system.physmem.memoryStateTime::IDLE 256543365500 # Time in different power states 252system.physmem.memoryStateTime::REF 12199720000 # Time in different power states |
| 254system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 253system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 255system.physmem.memoryStateTime::ACT 95752175500 # Time in different power states | 254system.physmem.memoryStateTime::ACT 96603610750 # Time in different power states |
| 256system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 255system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 257system.physmem.actEnergy::0 246146040 # Energy for activate commands per rank (pJ) 258system.physmem.actEnergy::1 242562600 # Energy for activate commands per rank (pJ) 259system.physmem.preEnergy::0 134305875 # Energy for precharge commands per rank (pJ) 260system.physmem.preEnergy::1 132350625 # Energy for precharge commands per rank (pJ) 261system.physmem.readEnergy::0 560164800 # Energy for read commands per rank (pJ) 262system.physmem.readEnergy::1 562497000 # Energy for read commands per rank (pJ) 263system.physmem.writeEnergy::0 310469760 # Energy for write commands per rank (pJ) 264system.physmem.writeEnergy::1 314539200 # Energy for write commands per rank (pJ) 265system.physmem.refreshEnergy::0 23635834560 # Energy for refresh commands per rank (pJ) 266system.physmem.refreshEnergy::1 23635834560 # Energy for refresh commands per rank (pJ) 267system.physmem.actBackEnergy::0 46793455740 # Energy for active background per rank (pJ) 268system.physmem.actBackEnergy::1 46253268450 # Energy for active background per rank (pJ) 269system.physmem.preBackEnergy::0 176077509750 # Energy for precharge background per rank (pJ) 270system.physmem.preBackEnergy::1 176551358250 # Energy for precharge background per rank (pJ) 271system.physmem.totalEnergy::0 247757886525 # Total energy per rank (pJ) 272system.physmem.totalEnergy::1 247692410685 # Total energy per rank (pJ) 273system.physmem.averagePower::0 684.652353 # Core power per rank (mW) 274system.physmem.averagePower::1 684.471418 # Core power per rank (mW) 275system.membus.trans_dist::ReadReq 43225 # Transaction distribution 276system.membus.trans_dist::ReadResp 43225 # Transaction distribution 277system.membus.trans_dist::Writeback 96521 # Transaction distribution 278system.membus.trans_dist::ReadExReq 100866 # Transaction distribution 279system.membus.trans_dist::ReadExResp 100866 # Transaction distribution 280system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384703 # Packet count per connected master and slave (bytes) 281system.membus.pkt_count::total 384703 # Packet count per connected master and slave (bytes) 282system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15399168 # Cumulative packet size per connected master and slave (bytes) 283system.membus.pkt_size::total 15399168 # Cumulative packet size per connected master and slave (bytes) 284system.membus.snoops 0 # Total snoops (count) 285system.membus.snoop_fanout::samples 240612 # Request fanout histogram 286system.membus.snoop_fanout::mean 0 # Request fanout histogram 287system.membus.snoop_fanout::stdev 0 # Request fanout histogram 288system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 289system.membus.snoop_fanout::0 240612 100.00% 100.00% # Request fanout histogram 290system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 291system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 292system.membus.snoop_fanout::min_value 0 # Request fanout histogram 293system.membus.snoop_fanout::max_value 0 # Request fanout histogram 294system.membus.snoop_fanout::total 240612 # Request fanout histogram 295system.membus.reqLayer0.occupancy 1075136000 # Layer occupancy (ticks) 296system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 297system.membus.respLayer1.occupancy 1362650250 # Layer occupancy (ticks) 298system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 299system.cpu_clk_domain.clock 500 # Clock period in ticks 300system.cpu.branchPred.lookups 132262855 # Number of BP lookups 301system.cpu.branchPred.condPredicted 98270441 # Number of conditional branches predicted 302system.cpu.branchPred.condIncorrect 6551317 # Number of conditional branches incorrect 303system.cpu.branchPred.BTBLookups 68771118 # Number of BTB lookups 304system.cpu.branchPred.BTBHits 64694090 # Number of BTB hits | 256system.physmem.actEnergy::0 246584520 # Energy for activate commands per rank (pJ) 257system.physmem.actEnergy::1 243719280 # Energy for activate commands per rank (pJ) 258system.physmem.preEnergy::0 134545125 # Energy for precharge commands per rank (pJ) 259system.physmem.preEnergy::1 132981750 # Energy for precharge commands per rank (pJ) 260system.physmem.readEnergy::0 560422200 # Energy for read commands per rank (pJ) 261system.physmem.readEnergy::1 562972800 # Energy for read commands per rank (pJ) 262system.physmem.writeEnergy::0 310625280 # Energy for write commands per rank (pJ) 263system.physmem.writeEnergy::1 314778960 # Energy for write commands per rank (pJ) 264system.physmem.refreshEnergy::0 23862652320 # Energy for refresh commands per rank (pJ) 265system.physmem.refreshEnergy::1 23862652320 # Energy for refresh commands per rank (pJ) 266system.physmem.actBackEnergy::0 47112370740 # Energy for active background per rank (pJ) 267system.physmem.actBackEnergy::1 46678345380 # Energy for active background per rank (pJ) 268system.physmem.preBackEnergy::0 177881368500 # Energy for precharge background per rank (pJ) 269system.physmem.preBackEnergy::1 178262092500 # Energy for precharge background per rank (pJ) 270system.physmem.totalEnergy::0 250108568685 # Total energy per rank (pJ) 271system.physmem.totalEnergy::1 250057542990 # Total energy per rank (pJ) 272system.physmem.averagePower::0 684.578732 # Core power per rank (mW) 273system.physmem.averagePower::1 684.439068 # Core power per rank (mW) 274system.cpu.branchPred.lookups 132580026 # Number of BP lookups 275system.cpu.branchPred.condPredicted 98506360 # Number of conditional branches predicted 276system.cpu.branchPred.condIncorrect 6554090 # Number of conditional branches incorrect 277system.cpu.branchPred.BTBLookups 69003825 # Number of BTB lookups 278system.cpu.branchPred.BTBHits 64853184 # Number of BTB hits |
| 305system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 279system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 306system.cpu.branchPred.BTBHitPct 94.071598 # BTB Hit Percentage 307system.cpu.branchPred.usedRAS 9992883 # Number of times the RAS was used to get a target. 308system.cpu.branchPred.RASInCorrect 17801 # Number of incorrect RAS predictions. | 280system.cpu.branchPred.BTBHitPct 93.984912 # BTB Hit Percentage 281system.cpu.branchPred.usedRAS 10016062 # Number of times the RAS was used to get a target. 282system.cpu.branchPred.RASInCorrect 17737 # Number of incorrect RAS predictions. 283system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 309system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 310system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 311system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 312system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 313system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 314system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 315system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 316system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 386system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.itb.read_accesses 0 # DTB read accesses 388system.cpu.itb.write_accesses 0 # DTB write accesses 389system.cpu.itb.inst_accesses 0 # ITB inst accesses 390system.cpu.itb.hits 0 # DTB hits 391system.cpu.itb.misses 0 # DTB misses 392system.cpu.itb.accesses 0 # DTB accesses 393system.cpu.workload.num_syscalls 548 # Number of system calls | 284system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 285system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 286system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 287system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 288system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 289system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 290system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 291system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 361system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 362system.cpu.itb.read_accesses 0 # DTB read accesses 363system.cpu.itb.write_accesses 0 # DTB write accesses 364system.cpu.itb.inst_accesses 0 # ITB inst accesses 365system.cpu.itb.hits 0 # DTB hits 366system.cpu.itb.misses 0 # DTB misses 367system.cpu.itb.accesses 0 # DTB accesses 368system.cpu.workload.num_syscalls 548 # Number of system calls |
| 394system.cpu.numCycles 723761725 # number of cpu cycles simulated | 369system.cpu.numCycles 730695022 # number of cpu cycles simulated |
| 395system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 396system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 397system.cpu.committedInsts 506582155 # Number of instructions committed 398system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed | 370system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 371system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 372system.cpu.committedInsts 506582155 # Number of instructions committed 373system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed |
| 399system.cpu.discardedOps 14127209 # Number of ops (including micro ops) which were discarded before commit | 374system.cpu.discardedOps 13461717 # Number of ops (including micro ops) which were discarded before commit |
| 400system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 375system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 401system.cpu.cpi 1.428715 # CPI: cycles per instruction 402system.cpu.ipc 0.699929 # IPC: instructions per cycle 403system.cpu.tickCycles 687792337 # Number of cycles that the object actually ticked 404system.cpu.idleCycles 35969388 # Total number of cycles that the object has spent stopped 405system.cpu.icache.tags.replacements 17682 # number of replacements 406system.cpu.icache.tags.tagsinuse 1187.679119 # Cycle average of tags in use 407system.cpu.icache.tags.total_refs 200328523 # Total number of references to valid blocks. 408system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks. 409system.cpu.icache.tags.avg_refs 10245.411088 # Average number of references to valid blocks. | 376system.cpu.cpi 1.442402 # CPI: cycles per instruction 377system.cpu.ipc 0.693288 # IPC: instructions per cycle 378system.cpu.tickCycles 695775254 # Number of cycles that the object actually ticked 379system.cpu.idleCycles 34919768 # Total number of cycles that the object has spent stopped 380system.cpu.dcache.tags.replacements 1139848 # number of replacements 381system.cpu.dcache.tags.tagsinuse 4071.076883 # Cycle average of tags in use 382system.cpu.dcache.tags.total_refs 171283127 # Total number of references to valid blocks. 383system.cpu.dcache.tags.sampled_refs 1143944 # Sample count of references to valid blocks. 384system.cpu.dcache.tags.avg_refs 149.730343 # Average number of references to valid blocks. 385system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. 386system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.076883 # Average occupied blocks per requestor 387system.cpu.dcache.tags.occ_percent::cpu.inst 0.993915 # Average percentage of cache occupancy 388system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy 389system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 390system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 391system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id 392system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id 393system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id 394system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 395system.cpu.dcache.tags.tag_accesses 346820764 # Number of tag accesses 396system.cpu.dcache.tags.data_accesses 346820764 # Number of data accesses 397system.cpu.dcache.ReadReq_hits::cpu.inst 114767369 # number of ReadReq hits 398system.cpu.dcache.ReadReq_hits::total 114767369 # number of ReadReq hits 399system.cpu.dcache.WriteReq_hits::cpu.inst 53538676 # number of WriteReq hits 400system.cpu.dcache.WriteReq_hits::total 53538676 # number of WriteReq hits 401system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits 402system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 403system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits 404system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 405system.cpu.dcache.demand_hits::cpu.inst 168306045 # number of demand (read+write) hits 406system.cpu.dcache.demand_hits::total 168306045 # number of demand (read+write) hits 407system.cpu.dcache.overall_hits::cpu.inst 168306045 # number of overall hits 408system.cpu.dcache.overall_hits::total 168306045 # number of overall hits 409system.cpu.dcache.ReadReq_misses::cpu.inst 854653 # number of ReadReq misses 410system.cpu.dcache.ReadReq_misses::total 854653 # number of ReadReq misses 411system.cpu.dcache.WriteReq_misses::cpu.inst 700630 # number of WriteReq misses 412system.cpu.dcache.WriteReq_misses::total 700630 # number of WriteReq misses 413system.cpu.dcache.demand_misses::cpu.inst 1555283 # number of demand (read+write) misses 414system.cpu.dcache.demand_misses::total 1555283 # number of demand (read+write) misses 415system.cpu.dcache.overall_misses::cpu.inst 1555283 # number of overall misses 416system.cpu.dcache.overall_misses::total 1555283 # number of overall misses 417system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13708895232 # number of ReadReq miss cycles 418system.cpu.dcache.ReadReq_miss_latency::total 13708895232 # number of ReadReq miss cycles 419system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20586763000 # number of WriteReq miss cycles 420system.cpu.dcache.WriteReq_miss_latency::total 20586763000 # number of WriteReq miss cycles 421system.cpu.dcache.demand_miss_latency::cpu.inst 34295658232 # number of demand (read+write) miss cycles 422system.cpu.dcache.demand_miss_latency::total 34295658232 # number of demand (read+write) miss cycles 423system.cpu.dcache.overall_miss_latency::cpu.inst 34295658232 # number of overall miss cycles 424system.cpu.dcache.overall_miss_latency::total 34295658232 # number of overall miss cycles 425system.cpu.dcache.ReadReq_accesses::cpu.inst 115622022 # number of ReadReq accesses(hits+misses) 426system.cpu.dcache.ReadReq_accesses::total 115622022 # number of ReadReq accesses(hits+misses) 427system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) 428system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 429system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) 430system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 431system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) 432system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 433system.cpu.dcache.demand_accesses::cpu.inst 169861328 # number of demand (read+write) accesses 434system.cpu.dcache.demand_accesses::total 169861328 # number of demand (read+write) accesses 435system.cpu.dcache.overall_accesses::cpu.inst 169861328 # number of overall (read+write) accesses 436system.cpu.dcache.overall_accesses::total 169861328 # number of overall (read+write) accesses 437system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007392 # miss rate for ReadReq accesses 438system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses 439system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses 440system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses 441system.cpu.dcache.demand_miss_rate::cpu.inst 0.009156 # miss rate for demand accesses 442system.cpu.dcache.demand_miss_rate::total 0.009156 # miss rate for demand accesses 443system.cpu.dcache.overall_miss_rate::cpu.inst 0.009156 # miss rate for overall accesses 444system.cpu.dcache.overall_miss_rate::total 0.009156 # miss rate for overall accesses 445system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16040.305518 # average ReadReq miss latency 446system.cpu.dcache.ReadReq_avg_miss_latency::total 16040.305518 # average ReadReq miss latency 447system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29383.216534 # average WriteReq miss latency 448system.cpu.dcache.WriteReq_avg_miss_latency::total 29383.216534 # average WriteReq miss latency 449system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency 450system.cpu.dcache.demand_avg_miss_latency::total 22051.072526 # average overall miss latency 451system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency 452system.cpu.dcache.overall_avg_miss_latency::total 22051.072526 # average overall miss latency 453system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 454system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 455system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 456system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 457system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 458system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 459system.cpu.dcache.fast_writes 0 # number of fast writes performed 460system.cpu.dcache.cache_copies 0 # number of cache copies performed 461system.cpu.dcache.writebacks::writebacks 1068569 # number of writebacks 462system.cpu.dcache.writebacks::total 1068569 # number of writebacks 463system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66869 # number of ReadReq MSHR hits 464system.cpu.dcache.ReadReq_mshr_hits::total 66869 # number of ReadReq MSHR hits 465system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344470 # number of WriteReq MSHR hits 466system.cpu.dcache.WriteReq_mshr_hits::total 344470 # number of WriteReq MSHR hits 467system.cpu.dcache.demand_mshr_hits::cpu.inst 411339 # number of demand (read+write) MSHR hits 468system.cpu.dcache.demand_mshr_hits::total 411339 # number of demand (read+write) MSHR hits 469system.cpu.dcache.overall_mshr_hits::cpu.inst 411339 # number of overall MSHR hits 470system.cpu.dcache.overall_mshr_hits::total 411339 # number of overall MSHR hits 471system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787784 # number of ReadReq MSHR misses 472system.cpu.dcache.ReadReq_mshr_misses::total 787784 # number of ReadReq MSHR misses 473system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356160 # number of WriteReq MSHR misses 474system.cpu.dcache.WriteReq_mshr_misses::total 356160 # number of WriteReq MSHR misses 475system.cpu.dcache.demand_mshr_misses::cpu.inst 1143944 # number of demand (read+write) MSHR misses 476system.cpu.dcache.demand_mshr_misses::total 1143944 # number of demand (read+write) MSHR misses 477system.cpu.dcache.overall_mshr_misses::cpu.inst 1143944 # number of overall MSHR misses 478system.cpu.dcache.overall_mshr_misses::total 1143944 # number of overall MSHR misses 479system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11256226015 # number of ReadReq MSHR miss cycles 480system.cpu.dcache.ReadReq_mshr_miss_latency::total 11256226015 # number of ReadReq MSHR miss cycles 481system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10106063500 # number of WriteReq MSHR miss cycles 482system.cpu.dcache.WriteReq_mshr_miss_latency::total 10106063500 # number of WriteReq MSHR miss cycles 483system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21362289515 # number of demand (read+write) MSHR miss cycles 484system.cpu.dcache.demand_mshr_miss_latency::total 21362289515 # number of demand (read+write) MSHR miss cycles 485system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21362289515 # number of overall MSHR miss cycles 486system.cpu.dcache.overall_mshr_miss_latency::total 21362289515 # number of overall MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for ReadReq accesses 488system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses 489system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses 490system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses 491system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006735 # mshr miss rate for demand accesses 492system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses 493system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006735 # mshr miss rate for overall accesses 494system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses 495system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14288.467416 # average ReadReq mshr miss latency 496system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14288.467416 # average ReadReq mshr miss latency 497system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28375.065982 # average WriteReq mshr miss latency 498system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28375.065982 # average WriteReq mshr miss latency 499system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18674.244119 # average overall mshr miss latency 500system.cpu.dcache.demand_avg_mshr_miss_latency::total 18674.244119 # average overall mshr miss latency 501system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18674.244119 # average overall mshr miss latency 502system.cpu.dcache.overall_avg_mshr_miss_latency::total 18674.244119 # average overall mshr miss latency 503system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 504system.cpu.icache.tags.replacements 17642 # number of replacements 505system.cpu.icache.tags.tagsinuse 1190.521713 # Cycle average of tags in use 506system.cpu.icache.tags.total_refs 200940130 # Total number of references to valid blocks. 507system.cpu.icache.tags.sampled_refs 19514 # Sample count of references to valid blocks. 508system.cpu.icache.tags.avg_refs 10297.229169 # Average number of references to valid blocks. |
| 410system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 509system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 411system.cpu.icache.tags.occ_blocks::cpu.inst 1187.679119 # Average occupied blocks per requestor 412system.cpu.icache.tags.occ_percent::cpu.inst 0.579921 # Average percentage of cache occupancy 413system.cpu.icache.tags.occ_percent::total 0.579921 # Average percentage of cache occupancy 414system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id | 510system.cpu.icache.tags.occ_blocks::cpu.inst 1190.521713 # Average occupied blocks per requestor 511system.cpu.icache.tags.occ_percent::cpu.inst 0.581309 # Average percentage of cache occupancy 512system.cpu.icache.tags.occ_percent::total 0.581309 # Average percentage of cache occupancy 513system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id |
| 415system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 416system.cpu.icache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id | 514system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 515system.cpu.icache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id |
| 417system.cpu.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id 418system.cpu.icache.tags.age_task_id_blocks_1024::3 304 # Occupied blocks per task id 419system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id 420system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id 421system.cpu.icache.tags.tag_accesses 400715705 # Number of tag accesses 422system.cpu.icache.tags.data_accesses 400715705 # Number of data accesses 423system.cpu.icache.ReadReq_hits::cpu.inst 200328523 # number of ReadReq hits 424system.cpu.icache.ReadReq_hits::total 200328523 # number of ReadReq hits 425system.cpu.icache.demand_hits::cpu.inst 200328523 # number of demand (read+write) hits 426system.cpu.icache.demand_hits::total 200328523 # number of demand (read+write) hits 427system.cpu.icache.overall_hits::cpu.inst 200328523 # number of overall hits 428system.cpu.icache.overall_hits::total 200328523 # number of overall hits 429system.cpu.icache.ReadReq_misses::cpu.inst 19553 # number of ReadReq misses 430system.cpu.icache.ReadReq_misses::total 19553 # number of ReadReq misses 431system.cpu.icache.demand_misses::cpu.inst 19553 # number of demand (read+write) misses 432system.cpu.icache.demand_misses::total 19553 # number of demand (read+write) misses 433system.cpu.icache.overall_misses::cpu.inst 19553 # number of overall misses 434system.cpu.icache.overall_misses::total 19553 # number of overall misses 435system.cpu.icache.ReadReq_miss_latency::cpu.inst 468017498 # number of ReadReq miss cycles 436system.cpu.icache.ReadReq_miss_latency::total 468017498 # number of ReadReq miss cycles 437system.cpu.icache.demand_miss_latency::cpu.inst 468017498 # number of demand (read+write) miss cycles 438system.cpu.icache.demand_miss_latency::total 468017498 # number of demand (read+write) miss cycles 439system.cpu.icache.overall_miss_latency::cpu.inst 468017498 # number of overall miss cycles 440system.cpu.icache.overall_miss_latency::total 468017498 # number of overall miss cycles 441system.cpu.icache.ReadReq_accesses::cpu.inst 200348076 # number of ReadReq accesses(hits+misses) 442system.cpu.icache.ReadReq_accesses::total 200348076 # number of ReadReq accesses(hits+misses) 443system.cpu.icache.demand_accesses::cpu.inst 200348076 # number of demand (read+write) accesses 444system.cpu.icache.demand_accesses::total 200348076 # number of demand (read+write) accesses 445system.cpu.icache.overall_accesses::cpu.inst 200348076 # number of overall (read+write) accesses 446system.cpu.icache.overall_accesses::total 200348076 # number of overall (read+write) accesses 447system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses 448system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses 449system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses 450system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses 451system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses 452system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses 453system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23935.840945 # average ReadReq miss latency 454system.cpu.icache.ReadReq_avg_miss_latency::total 23935.840945 # average ReadReq miss latency 455system.cpu.icache.demand_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency 456system.cpu.icache.demand_avg_miss_latency::total 23935.840945 # average overall miss latency 457system.cpu.icache.overall_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency 458system.cpu.icache.overall_avg_miss_latency::total 23935.840945 # average overall miss latency | 516system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 517system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id 518system.cpu.icache.tags.age_task_id_blocks_1024::4 1411 # Occupied blocks per task id 519system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id 520system.cpu.icache.tags.tag_accesses 401938802 # Number of tag accesses 521system.cpu.icache.tags.data_accesses 401938802 # Number of data accesses 522system.cpu.icache.ReadReq_hits::cpu.inst 200940130 # number of ReadReq hits 523system.cpu.icache.ReadReq_hits::total 200940130 # number of ReadReq hits 524system.cpu.icache.demand_hits::cpu.inst 200940130 # number of demand (read+write) hits 525system.cpu.icache.demand_hits::total 200940130 # number of demand (read+write) hits 526system.cpu.icache.overall_hits::cpu.inst 200940130 # number of overall hits 527system.cpu.icache.overall_hits::total 200940130 # number of overall hits 528system.cpu.icache.ReadReq_misses::cpu.inst 19514 # number of ReadReq misses 529system.cpu.icache.ReadReq_misses::total 19514 # number of ReadReq misses 530system.cpu.icache.demand_misses::cpu.inst 19514 # number of demand (read+write) misses 531system.cpu.icache.demand_misses::total 19514 # number of demand (read+write) misses 532system.cpu.icache.overall_misses::cpu.inst 19514 # number of overall misses 533system.cpu.icache.overall_misses::total 19514 # number of overall misses 534system.cpu.icache.ReadReq_miss_latency::cpu.inst 467407495 # number of ReadReq miss cycles 535system.cpu.icache.ReadReq_miss_latency::total 467407495 # number of ReadReq miss cycles 536system.cpu.icache.demand_miss_latency::cpu.inst 467407495 # number of demand (read+write) miss cycles 537system.cpu.icache.demand_miss_latency::total 467407495 # number of demand (read+write) miss cycles 538system.cpu.icache.overall_miss_latency::cpu.inst 467407495 # number of overall miss cycles 539system.cpu.icache.overall_miss_latency::total 467407495 # number of overall miss cycles 540system.cpu.icache.ReadReq_accesses::cpu.inst 200959644 # number of ReadReq accesses(hits+misses) 541system.cpu.icache.ReadReq_accesses::total 200959644 # number of ReadReq accesses(hits+misses) 542system.cpu.icache.demand_accesses::cpu.inst 200959644 # number of demand (read+write) accesses 543system.cpu.icache.demand_accesses::total 200959644 # number of demand (read+write) accesses 544system.cpu.icache.overall_accesses::cpu.inst 200959644 # number of overall (read+write) accesses 545system.cpu.icache.overall_accesses::total 200959644 # number of overall (read+write) accesses 546system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses 547system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses 548system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses 549system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses 550system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses 551system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses 552system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23952.418520 # average ReadReq miss latency 553system.cpu.icache.ReadReq_avg_miss_latency::total 23952.418520 # average ReadReq miss latency 554system.cpu.icache.demand_avg_miss_latency::cpu.inst 23952.418520 # average overall miss latency 555system.cpu.icache.demand_avg_miss_latency::total 23952.418520 # average overall miss latency 556system.cpu.icache.overall_avg_miss_latency::cpu.inst 23952.418520 # average overall miss latency 557system.cpu.icache.overall_avg_miss_latency::total 23952.418520 # average overall miss latency |
| 459system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 460system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 461system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 462system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 463system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 464system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 465system.cpu.icache.fast_writes 0 # number of fast writes performed 466system.cpu.icache.cache_copies 0 # number of cache copies performed | 558system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 559system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 560system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 561system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 562system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 563system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 564system.cpu.icache.fast_writes 0 # number of fast writes performed 565system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 467system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19553 # number of ReadReq MSHR misses 468system.cpu.icache.ReadReq_mshr_misses::total 19553 # number of ReadReq MSHR misses 469system.cpu.icache.demand_mshr_misses::cpu.inst 19553 # number of demand (read+write) MSHR misses 470system.cpu.icache.demand_mshr_misses::total 19553 # number of demand (read+write) MSHR misses 471system.cpu.icache.overall_mshr_misses::cpu.inst 19553 # number of overall MSHR misses 472system.cpu.icache.overall_mshr_misses::total 19553 # number of overall MSHR misses 473system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 427542502 # number of ReadReq MSHR miss cycles 474system.cpu.icache.ReadReq_mshr_miss_latency::total 427542502 # number of ReadReq MSHR miss cycles 475system.cpu.icache.demand_mshr_miss_latency::cpu.inst 427542502 # number of demand (read+write) MSHR miss cycles 476system.cpu.icache.demand_mshr_miss_latency::total 427542502 # number of demand (read+write) MSHR miss cycles 477system.cpu.icache.overall_mshr_miss_latency::cpu.inst 427542502 # number of overall MSHR miss cycles 478system.cpu.icache.overall_mshr_miss_latency::total 427542502 # number of overall MSHR miss cycles 479system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses 480system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses 481system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses 482system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses 483system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses 484system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses 485system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21865.826318 # average ReadReq mshr miss latency 486system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21865.826318 # average ReadReq mshr miss latency 487system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21865.826318 # average overall mshr miss latency 488system.cpu.icache.demand_avg_mshr_miss_latency::total 21865.826318 # average overall mshr miss latency 489system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21865.826318 # average overall mshr miss latency 490system.cpu.icache.overall_avg_mshr_miss_latency::total 21865.826318 # average overall mshr miss latency | 566system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19514 # number of ReadReq MSHR misses 567system.cpu.icache.ReadReq_mshr_misses::total 19514 # number of ReadReq MSHR misses 568system.cpu.icache.demand_mshr_misses::cpu.inst 19514 # number of demand (read+write) MSHR misses 569system.cpu.icache.demand_mshr_misses::total 19514 # number of demand (read+write) MSHR misses 570system.cpu.icache.overall_mshr_misses::cpu.inst 19514 # number of overall MSHR misses 571system.cpu.icache.overall_mshr_misses::total 19514 # number of overall MSHR misses 572system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426999505 # number of ReadReq MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_latency::total 426999505 # number of ReadReq MSHR miss cycles 574system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426999505 # number of demand (read+write) MSHR miss cycles 575system.cpu.icache.demand_mshr_miss_latency::total 426999505 # number of demand (read+write) MSHR miss cycles 576system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426999505 # number of overall MSHR miss cycles 577system.cpu.icache.overall_mshr_miss_latency::total 426999505 # number of overall MSHR miss cycles 578system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses 579system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses 580system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses 581system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses 582system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses 583system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses 584system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21881.700574 # average ReadReq mshr miss latency 585system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21881.700574 # average ReadReq mshr miss latency 586system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21881.700574 # average overall mshr miss latency 587system.cpu.icache.demand_avg_mshr_miss_latency::total 21881.700574 # average overall mshr miss latency 588system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21881.700574 # average overall mshr miss latency 589system.cpu.icache.overall_avg_mshr_miss_latency::total 21881.700574 # average overall mshr miss latency |
| 491system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 590system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 492system.cpu.toL2Bus.trans_dist::ReadReq 806891 # Transaction distribution 493system.cpu.toL2Bus.trans_dist::ReadResp 806891 # Transaction distribution 494system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution 495system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution 496system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution 497system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39106 # Packet count per connected master and slave (bytes) 498system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355897 # Packet count per connected master and slave (bytes) 499system.cpu.toL2Bus.pkt_count::total 3395003 # Packet count per connected master and slave (bytes) 500system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes) 501system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141578176 # Cumulative packet size per connected master and slave (bytes) 502system.cpu.toL2Bus.pkt_size::total 142829568 # Cumulative packet size per connected master and slave (bytes) | 591system.cpu.l2cache.tags.replacements 111385 # number of replacements 592system.cpu.l2cache.tags.tagsinuse 27648.726753 # Cycle average of tags in use 593system.cpu.l2cache.tags.total_refs 1684688 # Total number of references to valid blocks. 594system.cpu.l2cache.tags.sampled_refs 142574 # Sample count of references to valid blocks. 595system.cpu.l2cache.tags.avg_refs 11.816236 # Average number of references to valid blocks. 596system.cpu.l2cache.tags.warmup_cycle 163201810500 # Cycle when the warmup percentage was hit. 597system.cpu.l2cache.tags.occ_blocks::writebacks 23524.085448 # Average occupied blocks per requestor 598system.cpu.l2cache.tags.occ_blocks::cpu.inst 4124.641306 # Average occupied blocks per requestor 599system.cpu.l2cache.tags.occ_percent::writebacks 0.717898 # Average percentage of cache occupancy 600system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125874 # Average percentage of cache occupancy 601system.cpu.l2cache.tags.occ_percent::total 0.843772 # Average percentage of cache occupancy 602system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id 603system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 604system.cpu.l2cache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id 605system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4940 # Occupied blocks per task id 606system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25859 # Occupied blocks per task id 607system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id 608system.cpu.l2cache.tags.tag_accesses 18355203 # Number of tag accesses 609system.cpu.l2cache.tags.data_accesses 18355203 # Number of data accesses 610system.cpu.l2cache.ReadReq_hits::cpu.inst 763758 # number of ReadReq hits 611system.cpu.l2cache.ReadReq_hits::total 763758 # number of ReadReq hits 612system.cpu.l2cache.Writeback_hits::writebacks 1068569 # number of Writeback hits 613system.cpu.l2cache.Writeback_hits::total 1068569 # number of Writeback hits 614system.cpu.l2cache.ReadExReq_hits::cpu.inst 255544 # number of ReadExReq hits 615system.cpu.l2cache.ReadExReq_hits::total 255544 # number of ReadExReq hits 616system.cpu.l2cache.demand_hits::cpu.inst 1019302 # number of demand (read+write) hits 617system.cpu.l2cache.demand_hits::total 1019302 # number of demand (read+write) hits 618system.cpu.l2cache.overall_hits::cpu.inst 1019302 # number of overall hits 619system.cpu.l2cache.overall_hits::total 1019302 # number of overall hits 620system.cpu.l2cache.ReadReq_misses::cpu.inst 43287 # number of ReadReq misses 621system.cpu.l2cache.ReadReq_misses::total 43287 # number of ReadReq misses 622system.cpu.l2cache.ReadExReq_misses::cpu.inst 100869 # number of ReadExReq misses 623system.cpu.l2cache.ReadExReq_misses::total 100869 # number of ReadExReq misses 624system.cpu.l2cache.demand_misses::cpu.inst 144156 # number of demand (read+write) misses 625system.cpu.l2cache.demand_misses::total 144156 # number of demand (read+write) misses 626system.cpu.l2cache.overall_misses::cpu.inst 144156 # number of overall misses 627system.cpu.l2cache.overall_misses::total 144156 # number of overall misses 628system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3231564500 # number of ReadReq miss cycles 629system.cpu.l2cache.ReadReq_miss_latency::total 3231564500 # number of ReadReq miss cycles 630system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7196834000 # number of ReadExReq miss cycles 631system.cpu.l2cache.ReadExReq_miss_latency::total 7196834000 # number of ReadExReq miss cycles 632system.cpu.l2cache.demand_miss_latency::cpu.inst 10428398500 # number of demand (read+write) miss cycles 633system.cpu.l2cache.demand_miss_latency::total 10428398500 # number of demand (read+write) miss cycles 634system.cpu.l2cache.overall_miss_latency::cpu.inst 10428398500 # number of overall miss cycles 635system.cpu.l2cache.overall_miss_latency::total 10428398500 # number of overall miss cycles 636system.cpu.l2cache.ReadReq_accesses::cpu.inst 807045 # number of ReadReq accesses(hits+misses) 637system.cpu.l2cache.ReadReq_accesses::total 807045 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.Writeback_accesses::writebacks 1068569 # number of Writeback accesses(hits+misses) 639system.cpu.l2cache.Writeback_accesses::total 1068569 # number of Writeback accesses(hits+misses) 640system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356413 # number of ReadExReq accesses(hits+misses) 641system.cpu.l2cache.ReadExReq_accesses::total 356413 # number of ReadExReq accesses(hits+misses) 642system.cpu.l2cache.demand_accesses::cpu.inst 1163458 # number of demand (read+write) accesses 643system.cpu.l2cache.demand_accesses::total 1163458 # number of demand (read+write) accesses 644system.cpu.l2cache.overall_accesses::cpu.inst 1163458 # number of overall (read+write) accesses 645system.cpu.l2cache.overall_accesses::total 1163458 # number of overall (read+write) accesses 646system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053636 # miss rate for ReadReq accesses 647system.cpu.l2cache.ReadReq_miss_rate::total 0.053636 # miss rate for ReadReq accesses 648system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283012 # miss rate for ReadExReq accesses 649system.cpu.l2cache.ReadExReq_miss_rate::total 0.283012 # miss rate for ReadExReq accesses 650system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123903 # miss rate for demand accesses 651system.cpu.l2cache.demand_miss_rate::total 0.123903 # miss rate for demand accesses 652system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123903 # miss rate for overall accesses 653system.cpu.l2cache.overall_miss_rate::total 0.123903 # miss rate for overall accesses 654system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74654.388153 # average ReadReq miss latency 655system.cpu.l2cache.ReadReq_avg_miss_latency::total 74654.388153 # average ReadReq miss latency 656system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71348.323072 # average ReadExReq miss latency 657system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71348.323072 # average ReadExReq miss latency 658system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72341.064541 # average overall miss latency 659system.cpu.l2cache.demand_avg_miss_latency::total 72341.064541 # average overall miss latency 660system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72341.064541 # average overall miss latency 661system.cpu.l2cache.overall_avg_miss_latency::total 72341.064541 # average overall miss latency 662system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 663system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 664system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 665system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 666system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 667system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 668system.cpu.l2cache.fast_writes 0 # number of fast writes performed 669system.cpu.l2cache.cache_copies 0 # number of cache copies performed 670system.cpu.l2cache.writebacks::writebacks 96547 # number of writebacks 671system.cpu.l2cache.writebacks::total 96547 # number of writebacks 672system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits 673system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 674system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits 675system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 676system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits 677system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 678system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43270 # number of ReadReq MSHR misses 679system.cpu.l2cache.ReadReq_mshr_misses::total 43270 # number of ReadReq MSHR misses 680system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100869 # number of ReadExReq MSHR misses 681system.cpu.l2cache.ReadExReq_mshr_misses::total 100869 # number of ReadExReq MSHR misses 682system.cpu.l2cache.demand_mshr_misses::cpu.inst 144139 # number of demand (read+write) MSHR misses 683system.cpu.l2cache.demand_mshr_misses::total 144139 # number of demand (read+write) MSHR misses 684system.cpu.l2cache.overall_mshr_misses::cpu.inst 144139 # number of overall MSHR misses 685system.cpu.l2cache.overall_mshr_misses::total 144139 # number of overall MSHR misses 686system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2682518500 # number of ReadReq MSHR miss cycles 687system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2682518500 # number of ReadReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5916082000 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5916082000 # number of ReadExReq MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8598600500 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::total 8598600500 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8598600500 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::total 8598600500 # number of overall MSHR miss cycles 694system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053615 # mshr miss rate for ReadReq accesses 695system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053615 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283012 # mshr miss rate for ReadExReq accesses 697system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283012 # mshr miss rate for ReadExReq accesses 698system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for demand accesses 699system.cpu.l2cache.demand_mshr_miss_rate::total 0.123888 # mshr miss rate for demand accesses 700system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for overall accesses 701system.cpu.l2cache.overall_mshr_miss_rate::total 0.123888 # mshr miss rate for overall accesses 702system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61994.880980 # average ReadReq mshr miss latency 703system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61994.880980 # average ReadReq mshr miss latency 704system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58651.141580 # average ReadExReq mshr miss latency 705system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58651.141580 # average ReadExReq mshr miss latency 706system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency 707system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency 708system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency 709system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency 710system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 711system.cpu.toL2Bus.trans_dist::ReadReq 807045 # Transaction distribution 712system.cpu.toL2Bus.trans_dist::ReadResp 807045 # Transaction distribution 713system.cpu.toL2Bus.trans_dist::Writeback 1068569 # Transaction distribution 714system.cpu.toL2Bus.trans_dist::ReadExReq 356413 # Transaction distribution 715system.cpu.toL2Bus.trans_dist::ReadExResp 356413 # Transaction distribution 716system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39028 # Packet count per connected master and slave (bytes) 717system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356457 # Packet count per connected master and slave (bytes) 718system.cpu.toL2Bus.pkt_count::total 3395485 # Packet count per connected master and slave (bytes) 719system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1248896 # Cumulative packet size per connected master and slave (bytes) 720system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141600832 # Cumulative packet size per connected master and slave (bytes) 721system.cpu.toL2Bus.pkt_size::total 142849728 # Cumulative packet size per connected master and slave (bytes) |
| 503system.cpu.toL2Bus.snoops 0 # Total snoops (count) | 722system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| 504system.cpu.toL2Bus.snoop_fanout::samples 2231712 # Request fanout histogram | 723system.cpu.toL2Bus.snoop_fanout::samples 2232027 # Request fanout histogram |
| 505system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 506system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 507system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 508system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 509system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 510system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 511system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 512system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 724system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 725system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 726system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 727system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 728system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 729system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 730system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 731system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 513system.cpu.toL2Bus.snoop_fanout::5 2231712 100.00% 100.00% # Request fanout histogram | 732system.cpu.toL2Bus.snoop_fanout::5 2232027 100.00% 100.00% # Request fanout histogram |
| 514system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 515system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 516system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 517system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram | 733system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 734system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 735system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 736system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram |
| 518system.cpu.toL2Bus.snoop_fanout::total 2231712 # Request fanout histogram 519system.cpu.toL2Bus.reqLayer0.occupancy 2184277000 # Layer occupancy (ticks) | 737system.cpu.toL2Bus.snoop_fanout::total 2232027 # Request fanout histogram 738system.cpu.toL2Bus.reqLayer0.occupancy 2184582500 # Layer occupancy (ticks) |
| 520system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) | 739system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 521system.cpu.toL2Bus.respLayer0.occupancy 30013998 # Layer occupancy (ticks) | 740system.cpu.toL2Bus.respLayer0.occupancy 29960995 # Layer occupancy (ticks) |
| 522system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 741system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 523system.cpu.toL2Bus.respLayer1.occupancy 1744433986 # Layer occupancy (ticks) | 742system.cpu.toL2Bus.respLayer1.occupancy 1744681985 # Layer occupancy (ticks) |
| 524system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) | 743system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) |
| 525system.cpu.l2cache.tags.replacements 111337 # number of replacements 526system.cpu.l2cache.tags.tagsinuse 27632.941712 # Cycle average of tags in use 527system.cpu.l2cache.tags.total_refs 1684357 # Total number of references to valid blocks. 528system.cpu.l2cache.tags.sampled_refs 142526 # Sample count of references to valid blocks. 529system.cpu.l2cache.tags.avg_refs 11.817893 # Average number of references to valid blocks. 530system.cpu.l2cache.tags.warmup_cycle 162521333500 # Cycle when the warmup percentage was hit. 531system.cpu.l2cache.tags.occ_blocks::writebacks 23524.774692 # Average occupied blocks per requestor 532system.cpu.l2cache.tags.occ_blocks::cpu.inst 4108.167019 # Average occupied blocks per requestor 533system.cpu.l2cache.tags.occ_percent::writebacks 0.717919 # Average percentage of cache occupancy 534system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125371 # Average percentage of cache occupancy 535system.cpu.l2cache.tags.occ_percent::total 0.843290 # Average percentage of cache occupancy 536system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id 537system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 538system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 539system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id 540system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4930 # Occupied blocks per task id 541system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25866 # Occupied blocks per task id 542system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id 543system.cpu.l2cache.tags.tag_accesses 18352622 # Number of tag accesses 544system.cpu.l2cache.tags.data_accesses 18352622 # Number of data accesses 545system.cpu.l2cache.ReadReq_hits::cpu.inst 763650 # number of ReadReq hits 546system.cpu.l2cache.ReadReq_hits::total 763650 # number of ReadReq hits 547system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits 548system.cpu.l2cache.Writeback_hits::total 1068421 # number of Writeback hits 549system.cpu.l2cache.ReadExReq_hits::cpu.inst 255534 # number of ReadExReq hits 550system.cpu.l2cache.ReadExReq_hits::total 255534 # number of ReadExReq hits 551system.cpu.l2cache.demand_hits::cpu.inst 1019184 # number of demand (read+write) hits 552system.cpu.l2cache.demand_hits::total 1019184 # number of demand (read+write) hits 553system.cpu.l2cache.overall_hits::cpu.inst 1019184 # number of overall hits 554system.cpu.l2cache.overall_hits::total 1019184 # number of overall hits 555system.cpu.l2cache.ReadReq_misses::cpu.inst 43241 # number of ReadReq misses 556system.cpu.l2cache.ReadReq_misses::total 43241 # number of ReadReq misses 557system.cpu.l2cache.ReadExReq_misses::cpu.inst 100866 # number of ReadExReq misses 558system.cpu.l2cache.ReadExReq_misses::total 100866 # number of ReadExReq misses 559system.cpu.l2cache.demand_misses::cpu.inst 144107 # number of demand (read+write) misses 560system.cpu.l2cache.demand_misses::total 144107 # number of demand (read+write) misses 561system.cpu.l2cache.overall_misses::cpu.inst 144107 # number of overall misses 562system.cpu.l2cache.overall_misses::total 144107 # number of overall misses 563system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3220591000 # number of ReadReq miss cycles 564system.cpu.l2cache.ReadReq_miss_latency::total 3220591000 # number of ReadReq miss cycles 565system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7211196000 # number of ReadExReq miss cycles 566system.cpu.l2cache.ReadExReq_miss_latency::total 7211196000 # number of ReadExReq miss cycles 567system.cpu.l2cache.demand_miss_latency::cpu.inst 10431787000 # number of demand (read+write) miss cycles 568system.cpu.l2cache.demand_miss_latency::total 10431787000 # number of demand (read+write) miss cycles 569system.cpu.l2cache.overall_miss_latency::cpu.inst 10431787000 # number of overall miss cycles 570system.cpu.l2cache.overall_miss_latency::total 10431787000 # number of overall miss cycles 571system.cpu.l2cache.ReadReq_accesses::cpu.inst 806891 # number of ReadReq accesses(hits+misses) 572system.cpu.l2cache.ReadReq_accesses::total 806891 # number of ReadReq accesses(hits+misses) 573system.cpu.l2cache.Writeback_accesses::writebacks 1068421 # number of Writeback accesses(hits+misses) 574system.cpu.l2cache.Writeback_accesses::total 1068421 # number of Writeback accesses(hits+misses) 575system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356400 # number of ReadExReq accesses(hits+misses) 576system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses) 577system.cpu.l2cache.demand_accesses::cpu.inst 1163291 # number of demand (read+write) accesses 578system.cpu.l2cache.demand_accesses::total 1163291 # number of demand (read+write) accesses 579system.cpu.l2cache.overall_accesses::cpu.inst 1163291 # number of overall (read+write) accesses 580system.cpu.l2cache.overall_accesses::total 1163291 # number of overall (read+write) accesses 581system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053590 # miss rate for ReadReq accesses 582system.cpu.l2cache.ReadReq_miss_rate::total 0.053590 # miss rate for ReadReq accesses 583system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283013 # miss rate for ReadExReq accesses 584system.cpu.l2cache.ReadExReq_miss_rate::total 0.283013 # miss rate for ReadExReq accesses 585system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123879 # miss rate for demand accesses 586system.cpu.l2cache.demand_miss_rate::total 0.123879 # miss rate for demand accesses 587system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123879 # miss rate for overall accesses 588system.cpu.l2cache.overall_miss_rate::total 0.123879 # miss rate for overall accesses 589system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74480.030527 # average ReadReq miss latency 590system.cpu.l2cache.ReadReq_avg_miss_latency::total 74480.030527 # average ReadReq miss latency 591system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71492.832074 # average ReadExReq miss latency 592system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71492.832074 # average ReadExReq miss latency 593system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency 594system.cpu.l2cache.demand_avg_miss_latency::total 72389.176098 # average overall miss latency 595system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency 596system.cpu.l2cache.overall_avg_miss_latency::total 72389.176098 # average overall miss latency 597system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 598system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 599system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 600system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 601system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 602system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 603system.cpu.l2cache.fast_writes 0 # number of fast writes performed 604system.cpu.l2cache.cache_copies 0 # number of cache copies performed 605system.cpu.l2cache.writebacks::writebacks 96521 # number of writebacks 606system.cpu.l2cache.writebacks::total 96521 # number of writebacks 607system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits 608system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits 609system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits 610system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 611system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits 612system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 613system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43225 # number of ReadReq MSHR misses 614system.cpu.l2cache.ReadReq_mshr_misses::total 43225 # number of ReadReq MSHR misses 615system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100866 # number of ReadExReq MSHR misses 616system.cpu.l2cache.ReadExReq_mshr_misses::total 100866 # number of ReadExReq MSHR misses 617system.cpu.l2cache.demand_mshr_misses::cpu.inst 144091 # number of demand (read+write) MSHR misses 618system.cpu.l2cache.demand_mshr_misses::total 144091 # number of demand (read+write) MSHR misses 619system.cpu.l2cache.overall_mshr_misses::cpu.inst 144091 # number of overall MSHR misses 620system.cpu.l2cache.overall_mshr_misses::total 144091 # number of overall MSHR misses 621system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2672436250 # number of ReadReq MSHR miss cycles 622system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2672436250 # number of ReadReq MSHR miss cycles 623system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5933940000 # number of ReadExReq MSHR miss cycles 624system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5933940000 # number of ReadExReq MSHR miss cycles 625system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8606376250 # number of demand (read+write) MSHR miss cycles 626system.cpu.l2cache.demand_mshr_miss_latency::total 8606376250 # number of demand (read+write) MSHR miss cycles 627system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8606376250 # number of overall MSHR miss cycles 628system.cpu.l2cache.overall_mshr_miss_latency::total 8606376250 # number of overall MSHR miss cycles 629system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053570 # mshr miss rate for ReadReq accesses 630system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053570 # mshr miss rate for ReadReq accesses 631system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283013 # mshr miss rate for ReadExReq accesses 632system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283013 # mshr miss rate for ReadExReq accesses 633system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for demand accesses 634system.cpu.l2cache.demand_mshr_miss_rate::total 0.123865 # mshr miss rate for demand accesses 635system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for overall accesses 636system.cpu.l2cache.overall_mshr_miss_rate::total 0.123865 # mshr miss rate for overall accesses 637system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.171197 # average ReadReq mshr miss latency 638system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.171197 # average ReadReq mshr miss latency 639system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58829.932782 # average ReadExReq mshr miss latency 640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58829.932782 # average ReadExReq mshr miss latency 641system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency 642system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency 643system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency 644system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency 645system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 646system.cpu.dcache.tags.replacements 1139642 # number of replacements 647system.cpu.dcache.tags.tagsinuse 4071.128930 # Cycle average of tags in use 648system.cpu.dcache.tags.total_refs 169306917 # Total number of references to valid blocks. 649system.cpu.dcache.tags.sampled_refs 1143738 # Sample count of references to valid blocks. 650system.cpu.dcache.tags.avg_refs 148.029459 # Average number of references to valid blocks. 651system.cpu.dcache.tags.warmup_cycle 4807181250 # Cycle when the warmup percentage was hit. 652system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.128930 # Average occupied blocks per requestor 653system.cpu.dcache.tags.occ_percent::cpu.inst 0.993928 # Average percentage of cache occupancy 654system.cpu.dcache.tags.occ_percent::total 0.993928 # Average percentage of cache occupancy 655system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 656system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 657system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 658system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id 659system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id 660system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 661system.cpu.dcache.tags.tag_accesses 342867294 # Number of tag accesses 662system.cpu.dcache.tags.data_accesses 342867294 # Number of data accesses 663system.cpu.dcache.ReadReq_hits::cpu.inst 112791129 # number of ReadReq hits 664system.cpu.dcache.ReadReq_hits::total 112791129 # number of ReadReq hits 665system.cpu.dcache.WriteReq_hits::cpu.inst 53538706 # number of WriteReq hits 666system.cpu.dcache.WriteReq_hits::total 53538706 # number of WriteReq hits 667system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits 668system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 669system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits 670system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 671system.cpu.dcache.demand_hits::cpu.inst 166329835 # number of demand (read+write) hits 672system.cpu.dcache.demand_hits::total 166329835 # number of demand (read+write) hits 673system.cpu.dcache.overall_hits::cpu.inst 166329835 # number of overall hits 674system.cpu.dcache.overall_hits::total 166329835 # number of overall hits 675system.cpu.dcache.ReadReq_misses::cpu.inst 854261 # number of ReadReq misses 676system.cpu.dcache.ReadReq_misses::total 854261 # number of ReadReq misses 677system.cpu.dcache.WriteReq_misses::cpu.inst 700600 # number of WriteReq misses 678system.cpu.dcache.WriteReq_misses::total 700600 # number of WriteReq misses 679system.cpu.dcache.demand_misses::cpu.inst 1554861 # number of demand (read+write) misses 680system.cpu.dcache.demand_misses::total 1554861 # number of demand (read+write) misses 681system.cpu.dcache.overall_misses::cpu.inst 1554861 # number of overall misses 682system.cpu.dcache.overall_misses::total 1554861 # number of overall misses 683system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13692452733 # number of ReadReq miss cycles 684system.cpu.dcache.ReadReq_miss_latency::total 13692452733 # number of ReadReq miss cycles 685system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20709081750 # number of WriteReq miss cycles 686system.cpu.dcache.WriteReq_miss_latency::total 20709081750 # number of WriteReq miss cycles 687system.cpu.dcache.demand_miss_latency::cpu.inst 34401534483 # number of demand (read+write) miss cycles 688system.cpu.dcache.demand_miss_latency::total 34401534483 # number of demand (read+write) miss cycles 689system.cpu.dcache.overall_miss_latency::cpu.inst 34401534483 # number of overall miss cycles 690system.cpu.dcache.overall_miss_latency::total 34401534483 # number of overall miss cycles 691system.cpu.dcache.ReadReq_accesses::cpu.inst 113645390 # number of ReadReq accesses(hits+misses) 692system.cpu.dcache.ReadReq_accesses::total 113645390 # number of ReadReq accesses(hits+misses) 693system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) 694system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 695system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) 696system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 697system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) 698system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 699system.cpu.dcache.demand_accesses::cpu.inst 167884696 # number of demand (read+write) accesses 700system.cpu.dcache.demand_accesses::total 167884696 # number of demand (read+write) accesses 701system.cpu.dcache.overall_accesses::cpu.inst 167884696 # number of overall (read+write) accesses 702system.cpu.dcache.overall_accesses::total 167884696 # number of overall (read+write) accesses 703system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007517 # miss rate for ReadReq accesses 704system.cpu.dcache.ReadReq_miss_rate::total 0.007517 # miss rate for ReadReq accesses 705system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses 706system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses 707system.cpu.dcache.demand_miss_rate::cpu.inst 0.009261 # miss rate for demand accesses 708system.cpu.dcache.demand_miss_rate::total 0.009261 # miss rate for demand accesses 709system.cpu.dcache.overall_miss_rate::cpu.inst 0.009261 # miss rate for overall accesses 710system.cpu.dcache.overall_miss_rate::total 0.009261 # miss rate for overall accesses 711system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16028.418403 # average ReadReq miss latency 712system.cpu.dcache.ReadReq_avg_miss_latency::total 16028.418403 # average ReadReq miss latency 713system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29559.066158 # average WriteReq miss latency 714system.cpu.dcache.WriteReq_avg_miss_latency::total 29559.066158 # average WriteReq miss latency 715system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency 716system.cpu.dcache.demand_avg_miss_latency::total 22125.151048 # average overall miss latency 717system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency 718system.cpu.dcache.overall_avg_miss_latency::total 22125.151048 # average overall miss latency 719system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 720system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 721system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 722system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 723system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 724system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 725system.cpu.dcache.fast_writes 0 # number of fast writes performed 726system.cpu.dcache.cache_copies 0 # number of cache copies performed 727system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks 728system.cpu.dcache.writebacks::total 1068421 # number of writebacks 729system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66670 # number of ReadReq MSHR hits 730system.cpu.dcache.ReadReq_mshr_hits::total 66670 # number of ReadReq MSHR hits 731system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344453 # number of WriteReq MSHR hits 732system.cpu.dcache.WriteReq_mshr_hits::total 344453 # number of WriteReq MSHR hits 733system.cpu.dcache.demand_mshr_hits::cpu.inst 411123 # number of demand (read+write) MSHR hits 734system.cpu.dcache.demand_mshr_hits::total 411123 # number of demand (read+write) MSHR hits 735system.cpu.dcache.overall_mshr_hits::cpu.inst 411123 # number of overall MSHR hits 736system.cpu.dcache.overall_mshr_hits::total 411123 # number of overall MSHR hits 737system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787591 # number of ReadReq MSHR misses 738system.cpu.dcache.ReadReq_mshr_misses::total 787591 # number of ReadReq MSHR misses 739system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356147 # number of WriteReq MSHR misses 740system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses 741system.cpu.dcache.demand_mshr_misses::cpu.inst 1143738 # number of demand (read+write) MSHR misses 742system.cpu.dcache.demand_mshr_misses::total 1143738 # number of demand (read+write) MSHR misses 743system.cpu.dcache.overall_mshr_misses::cpu.inst 1143738 # number of overall MSHR misses 744system.cpu.dcache.overall_mshr_misses::total 1143738 # number of overall MSHR misses 745system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11243518014 # number of ReadReq MSHR miss cycles 746system.cpu.dcache.ReadReq_mshr_miss_latency::total 11243518014 # number of ReadReq MSHR miss cycles 747system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10120311000 # number of WriteReq MSHR miss cycles 748system.cpu.dcache.WriteReq_mshr_miss_latency::total 10120311000 # number of WriteReq MSHR miss cycles 749system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21363829014 # number of demand (read+write) MSHR miss cycles 750system.cpu.dcache.demand_mshr_miss_latency::total 21363829014 # number of demand (read+write) MSHR miss cycles 751system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21363829014 # number of overall MSHR miss cycles 752system.cpu.dcache.overall_mshr_miss_latency::total 21363829014 # number of overall MSHR miss cycles 753system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses 754system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses 755system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses 756system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses 757system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for demand accesses 758system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses 759system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses 760system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses 761system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14275.833541 # average ReadReq mshr miss latency 762system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14275.833541 # average ReadReq mshr miss latency 763system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28416.106271 # average WriteReq mshr miss latency 764system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28416.106271 # average WriteReq mshr miss latency 765system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency 766system.cpu.dcache.demand_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency 767system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency 768system.cpu.dcache.overall_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency 769system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 744system.membus.trans_dist::ReadReq 43270 # Transaction distribution 745system.membus.trans_dist::ReadResp 43270 # Transaction distribution 746system.membus.trans_dist::Writeback 96547 # Transaction distribution 747system.membus.trans_dist::ReadExReq 100869 # Transaction distribution 748system.membus.trans_dist::ReadExResp 100869 # Transaction distribution 749system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384825 # Packet count per connected master and slave (bytes) 750system.membus.pkt_count::total 384825 # Packet count per connected master and slave (bytes) 751system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15403904 # Cumulative packet size per connected master and slave (bytes) 752system.membus.pkt_size::total 15403904 # Cumulative packet size per connected master and slave (bytes) 753system.membus.snoops 0 # Total snoops (count) 754system.membus.snoop_fanout::samples 240686 # Request fanout histogram 755system.membus.snoop_fanout::mean 0 # Request fanout histogram 756system.membus.snoop_fanout::stdev 0 # Request fanout histogram 757system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 758system.membus.snoop_fanout::0 240686 100.00% 100.00% # Request fanout histogram 759system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 760system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 761system.membus.snoop_fanout::min_value 0 # Request fanout histogram 762system.membus.snoop_fanout::max_value 0 # Request fanout histogram 763system.membus.snoop_fanout::total 240686 # Request fanout histogram 764system.membus.reqLayer0.occupancy 1081853000 # Layer occupancy (ticks) 765system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 766system.membus.respLayer1.occupancy 1366563500 # Layer occupancy (ticks) 767system.membus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 770 771---------- End Simulation Statistics ---------- | 768 769---------- End Simulation Statistics ---------- |