| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.361826 # Number of seconds simulated 4sim_ticks 361826015500 # Number of ticks simulated 5final_tick 361826015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.361881 # Number of seconds simulated 4sim_ticks 361880862500 # Number of ticks simulated 5final_tick 361880862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 231274 # Simulator instruction rate (inst/s) 8host_op_rate 250500 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 165186980 # Simulator tick rate (ticks/s) 10host_mem_usage 321304 # Number of bytes of host memory used 11host_seconds 2190.40 # Real time elapsed on the host | 7host_inst_rate 239591 # Simulator instruction rate (inst/s) 8host_op_rate 259509 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 171154005 # Simulator tick rate (ticks/s) 10host_mem_usage 311472 # Number of bytes of host memory used 11host_seconds 2114.36 # Real time elapsed on the host |
| 12sim_insts 506582155 # Number of instructions simulated 13sim_ops 548695378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 506582155 # Number of instructions simulated 13sim_ops 548695378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 9220736 # Number of bytes read from this memory 17system.physmem.bytes_read::total 9220736 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 6177024 # Number of bytes written to this memory 21system.physmem.bytes_written::total 6177024 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 144074 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 144074 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 96516 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 96516 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 25483894 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 25483894 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 612007 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 612007 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 17071807 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 17071807 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 17071807 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 25483894 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 42555702 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 144074 # Number of read requests accepted 36system.physmem.writeReqs 96516 # Number of write requests accepted 37system.physmem.readBursts 144074 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 96516 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 9213952 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue 41system.physmem.bytesWritten 6175488 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 9220736 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 6177024 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 9221824 # Number of bytes read from this memory 17system.physmem.bytes_read::total 9221824 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 6177344 # Number of bytes written to this memory 21system.physmem.bytes_written::total 6177344 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 144091 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 144091 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 96521 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 96521 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 25483039 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 25483039 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 612622 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 612622 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 17070104 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 17070104 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 17070104 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 25483039 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 42553143 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 144091 # Number of read requests accepted 36system.physmem.writeReqs 96521 # Number of write requests accepted 37system.physmem.readBursts 144091 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 96521 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 9215168 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue 41system.physmem.bytesWritten 6176128 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 9221824 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 6177344 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue |
| 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 47system.physmem.perBankRdBursts::0 9331 # Per bank write bursts 48system.physmem.perBankRdBursts::1 8974 # Per bank write bursts 49system.physmem.perBankRdBursts::2 8995 # Per bank write bursts 50system.physmem.perBankRdBursts::3 8704 # Per bank write bursts | 47system.physmem.perBankRdBursts::0 9338 # Per bank write bursts 48system.physmem.perBankRdBursts::1 8967 # Per bank write bursts 49system.physmem.perBankRdBursts::2 9003 # Per bank write bursts 50system.physmem.perBankRdBursts::3 8705 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::4 9445 # Per bank write bursts | 51system.physmem.perBankRdBursts::4 9445 # Per bank write bursts |
| 52system.physmem.perBankRdBursts::5 9338 # Per bank write bursts 53system.physmem.perBankRdBursts::6 8941 # Per bank write bursts 54system.physmem.perBankRdBursts::7 8096 # Per bank write bursts 55system.physmem.perBankRdBursts::8 8562 # Per bank write bursts 56system.physmem.perBankRdBursts::9 8674 # Per bank write bursts | 52system.physmem.perBankRdBursts::5 9343 # Per bank write bursts 53system.physmem.perBankRdBursts::6 8943 # Per bank write bursts 54system.physmem.perBankRdBursts::7 8100 # Per bank write bursts 55system.physmem.perBankRdBursts::8 8560 # Per bank write bursts 56system.physmem.perBankRdBursts::9 8672 # Per bank write bursts |
| 57system.physmem.perBankRdBursts::10 8773 # Per bank write bursts | 57system.physmem.perBankRdBursts::10 8773 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::11 9481 # Per bank write bursts 59system.physmem.perBankRdBursts::12 9368 # Per bank write bursts 60system.physmem.perBankRdBursts::13 9509 # Per bank write bursts 61system.physmem.perBankRdBursts::14 8709 # Per bank write bursts 62system.physmem.perBankRdBursts::15 9068 # Per bank write bursts 63system.physmem.perBankWrBursts::0 6188 # Per bank write bursts 64system.physmem.perBankWrBursts::1 6094 # Per bank write bursts 65system.physmem.perBankWrBursts::2 6004 # Per bank write bursts 66system.physmem.perBankWrBursts::3 5817 # Per bank write bursts 67system.physmem.perBankWrBursts::4 6158 # Per bank write bursts 68system.physmem.perBankWrBursts::5 6168 # Per bank write bursts 69system.physmem.perBankWrBursts::6 6012 # Per bank write bursts 70system.physmem.perBankWrBursts::7 5489 # Per bank write bursts 71system.physmem.perBankWrBursts::8 5725 # Per bank write bursts 72system.physmem.perBankWrBursts::9 5819 # Per bank write bursts | 58system.physmem.perBankRdBursts::11 9480 # Per bank write bursts 59system.physmem.perBankRdBursts::12 9371 # Per bank write bursts 60system.physmem.perBankRdBursts::13 9512 # Per bank write bursts 61system.physmem.perBankRdBursts::14 8706 # Per bank write bursts 62system.physmem.perBankRdBursts::15 9069 # Per bank write bursts 63system.physmem.perBankWrBursts::0 6189 # Per bank write bursts 64system.physmem.perBankWrBursts::1 6093 # Per bank write bursts 65system.physmem.perBankWrBursts::2 6008 # Per bank write bursts 66system.physmem.perBankWrBursts::3 5816 # Per bank write bursts 67system.physmem.perBankWrBursts::4 6159 # Per bank write bursts 68system.physmem.perBankWrBursts::5 6173 # Per bank write bursts 69system.physmem.perBankWrBursts::6 6014 # Per bank write bursts 70system.physmem.perBankWrBursts::7 5494 # Per bank write bursts 71system.physmem.perBankWrBursts::8 5724 # Per bank write bursts 72system.physmem.perBankWrBursts::9 5818 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::10 5961 # Per bank write bursts | 73system.physmem.perBankWrBursts::10 5961 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::11 6448 # Per bank write bursts 75system.physmem.perBankWrBursts::12 6304 # Per bank write bursts 76system.physmem.perBankWrBursts::13 6266 # Per bank write bursts 77system.physmem.perBankWrBursts::14 5996 # Per bank write bursts 78system.physmem.perBankWrBursts::15 6043 # Per bank write bursts | 74system.physmem.perBankWrBursts::11 6447 # Per bank write bursts 75system.physmem.perBankWrBursts::12 6306 # Per bank write bursts 76system.physmem.perBankWrBursts::13 6267 # Per bank write bursts 77system.physmem.perBankWrBursts::14 5992 # Per bank write bursts 78system.physmem.perBankWrBursts::15 6041 # Per bank write bursts |
| 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 81system.physmem.totGap 361825986500 # Total gap between requests | 81system.physmem.totGap 361880833500 # Total gap between requests |
| 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) | 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 88system.physmem.readPktSize::6 144074 # Read request sizes (log2) | 88system.physmem.readPktSize::6 144091 # Read request sizes (log2) |
| 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) | 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 95system.physmem.writePktSize::6 96516 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 143606 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see | 95system.physmem.writePktSize::6 96521 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 143620 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 348 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 143system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 3132 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 5676 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 5658 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 5671 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 5685 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 5655 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 5675 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 5648 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 5690 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 5726 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 5661 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 5632 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::15 2769 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 2939 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 5678 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 5669 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 5685 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 5687 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 5701 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 5699 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 5689 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 5716 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 5703 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 5641 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 5637 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see | 166system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see |
| 168system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see | 168system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see |
| 175system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 175system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 192system.physmem.bytesPerActivate::samples 64715 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 237.790435 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 157.392081 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 243.201287 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 24444 37.77% 37.77% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 18161 28.06% 65.83% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 6768 10.46% 76.29% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 7845 12.12% 88.42% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 2212 3.42% 91.83% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1114 1.72% 93.55% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 793 1.23% 94.78% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 596 0.92% 95.70% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 2782 4.30% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 64715 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 25.855065 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 382.360630 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 5564 99.93% 99.93% # Reads before turning the bus around for writes | 192system.physmem.bytesPerActivate::samples 64681 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 237.949073 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 157.463319 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 243.404639 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 24397 37.72% 37.72% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 18169 28.09% 65.81% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 6808 10.53% 76.33% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 7802 12.06% 88.40% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 2168 3.35% 91.75% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1166 1.80% 93.55% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 777 1.20% 94.75% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 613 0.95% 95.70% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 2781 4.30% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 64681 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 5584 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 25.784921 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 381.788967 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 5580 99.93% 99.93% # Reads before turning the bus around for writes |
| 210system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes | 210system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 212system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes 213system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads 214system.physmem.wrPerTurnAround::mean 17.329741 # Writes before turning the bus around for reads 215system.physmem.wrPerTurnAround::gmean 17.226111 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::stdev 2.490816 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::16-17 2624 47.13% 47.13% # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::18-19 2801 50.31% 97.43% # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::20-21 48 0.86% 98.29% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::22-23 25 0.45% 98.74% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::24-25 21 0.38% 99.12% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::26-27 12 0.22% 99.34% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::28-29 8 0.14% 99.48% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::30-31 6 0.11% 99.59% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::32-33 3 0.05% 99.64% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::34-35 4 0.07% 99.71% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::36-37 1 0.02% 99.73% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::38-39 5 0.09% 99.82% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::50-51 1 0.02% 99.87% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::52-53 1 0.02% 99.89% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-57 1 0.02% 99.91% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::58-59 1 0.02% 99.93% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::68-69 2 0.04% 99.96% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads 238system.physmem.totQLat 1536727500 # Total ticks spent queuing 239system.physmem.totMemAccLat 4236127500 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 719840000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst | 212system.physmem.rdPerTurnAround::total 5584 # Reads before turning the bus around for writes 213system.physmem.wrPerTurnAround::samples 5584 # Writes before turning the bus around for reads 214system.physmem.wrPerTurnAround::mean 17.281877 # Writes before turning the bus around for reads 215system.physmem.wrPerTurnAround::gmean 17.171400 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::stdev 2.885179 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::16-19 5428 97.21% 97.21% # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::20-23 84 1.50% 98.71% # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::24-27 28 0.50% 99.21% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::28-31 20 0.36% 99.57% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::32-35 9 0.16% 99.73% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::36-39 7 0.13% 99.86% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::40-43 2 0.04% 99.89% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::44-47 1 0.02% 99.91% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::48-51 2 0.04% 99.95% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::72-75 1 0.02% 99.98% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 5584 # Writes before turning the bus around for reads 230system.physmem.totQLat 1580318000 # Total ticks spent queuing 231system.physmem.totMemAccLat 4280074250 # Total ticks spent from burst creation until serviced by the DRAM 232system.physmem.totBusLat 719935000 # Total ticks spent in databus transfers 233system.physmem.avgQLat 10975.42 # Average queueing delay per DRAM burst |
| 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 243system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 25.47 # Average DRAM read bandwidth in MiByte/s | 235system.physmem.avgMemAccLat 29725.42 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 25.46 # Average DRAM read bandwidth in MiByte/s |
| 245system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 0.33 # Data bus utilization in percentage 250system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing | 237system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s 238system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 241system.physmem.busUtil 0.33 # Data bus utilization in percentage 242system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 244system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| 253system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing 254system.physmem.readRowHits 111270 # Number of row buffer hits during reads 255system.physmem.writeRowHits 64468 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 77.29 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes 258system.physmem.avgGap 1503911.16 # Average gap between requests 259system.physmem.pageHitRate 73.08 # Row buffer hit rate, read and write combined 260system.physmem.memoryStateTime::IDLE 254085865250 # Time in different power states 261system.physmem.memoryStateTime::REF 12081940000 # Time in different power states | 245system.physmem.avgWrQLen 20.42 # Average write queue length when enqueuing 246system.physmem.readRowHits 111153 # Number of row buffer hits during reads 247system.physmem.writeRowHits 64649 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 66.98 # Row buffer hit rate for writes 250system.physmem.avgGap 1504001.60 # Average gap between requests 251system.physmem.pageHitRate 73.10 # Row buffer hit rate, read and write combined 252system.physmem.memoryStateTime::IDLE 254039828500 # Time in different power states 253system.physmem.memoryStateTime::REF 12083760000 # Time in different power states |
| 262system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 254system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 263system.physmem.memoryStateTime::ACT 95653103250 # Time in different power states | 255system.physmem.memoryStateTime::ACT 95752175500 # Time in different power states |
| 264system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 256system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 265system.membus.throughput 42555702 # Throughput (bytes/s) 266system.membus.trans_dist::ReadReq 43212 # Transaction distribution 267system.membus.trans_dist::ReadResp 43212 # Transaction distribution 268system.membus.trans_dist::Writeback 96516 # Transaction distribution 269system.membus.trans_dist::ReadExReq 100862 # Transaction distribution 270system.membus.trans_dist::ReadExResp 100862 # Transaction distribution 271system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384664 # Packet count per connected master and slave (bytes) 272system.membus.pkt_count::total 384664 # Packet count per connected master and slave (bytes) 273system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15397760 # Cumulative packet size per connected master and slave (bytes) 274system.membus.tot_pkt_size::total 15397760 # Cumulative packet size per connected master and slave (bytes) 275system.membus.data_through_bus 15397760 # Total data (bytes) 276system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 277system.membus.reqLayer0.occupancy 1075054000 # Layer occupancy (ticks) | 257system.membus.trans_dist::ReadReq 43225 # Transaction distribution 258system.membus.trans_dist::ReadResp 43225 # Transaction distribution 259system.membus.trans_dist::Writeback 96521 # Transaction distribution 260system.membus.trans_dist::ReadExReq 100866 # Transaction distribution 261system.membus.trans_dist::ReadExResp 100866 # Transaction distribution 262system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384703 # Packet count per connected master and slave (bytes) 263system.membus.pkt_count::total 384703 # Packet count per connected master and slave (bytes) 264system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15399168 # Cumulative packet size per connected master and slave (bytes) 265system.membus.pkt_size::total 15399168 # Cumulative packet size per connected master and slave (bytes) 266system.membus.snoops 0 # Total snoops (count) 267system.membus.snoop_fanout::samples 240612 # Request fanout histogram 268system.membus.snoop_fanout::mean 0 # Request fanout histogram 269system.membus.snoop_fanout::stdev 0 # Request fanout histogram 270system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 271system.membus.snoop_fanout::0 240612 100.00% 100.00% # Request fanout histogram 272system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 273system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 274system.membus.snoop_fanout::min_value 0 # Request fanout histogram 275system.membus.snoop_fanout::max_value 0 # Request fanout histogram 276system.membus.snoop_fanout::total 240612 # Request fanout histogram 277system.membus.reqLayer0.occupancy 1075136000 # Layer occupancy (ticks) |
| 278system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) | 278system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) |
| 279system.membus.respLayer1.occupancy 1362559750 # Layer occupancy (ticks) | 279system.membus.respLayer1.occupancy 1362650250 # Layer occupancy (ticks) |
| 280system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 281system.cpu_clk_domain.clock 500 # Clock period in ticks | 280system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 281system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 282system.cpu.branchPred.lookups 132256489 # Number of BP lookups 283system.cpu.branchPred.condPredicted 98266035 # Number of conditional branches predicted 284system.cpu.branchPred.condIncorrect 6550672 # Number of conditional branches incorrect 285system.cpu.branchPred.BTBLookups 68852239 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 64692489 # Number of BTB hits | 282system.cpu.branchPred.lookups 132262855 # Number of BP lookups 283system.cpu.branchPred.condPredicted 98270441 # Number of conditional branches predicted 284system.cpu.branchPred.condIncorrect 6551317 # Number of conditional branches incorrect 285system.cpu.branchPred.BTBLookups 68771118 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 64694090 # Number of BTB hits |
| 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 288system.cpu.branchPred.BTBHitPct 93.958439 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 9992276 # Number of times the RAS was used to get a target. 290system.cpu.branchPred.RASInCorrect 17882 # Number of incorrect RAS predictions. | 288system.cpu.branchPred.BTBHitPct 94.071598 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 9992883 # Number of times the RAS was used to get a target. 290system.cpu.branchPred.RASInCorrect 17801 # Number of incorrect RAS predictions. |
| 291system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 292system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 293system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 294system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 295system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 296system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 297system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 298system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 368system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.itb.read_accesses 0 # DTB read accesses 370system.cpu.itb.write_accesses 0 # DTB write accesses 371system.cpu.itb.inst_accesses 0 # ITB inst accesses 372system.cpu.itb.hits 0 # DTB hits 373system.cpu.itb.misses 0 # DTB misses 374system.cpu.itb.accesses 0 # DTB accesses 375system.cpu.workload.num_syscalls 548 # Number of system calls | 291system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 292system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 293system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 294system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 295system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 296system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 297system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 298system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 368system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.itb.read_accesses 0 # DTB read accesses 370system.cpu.itb.write_accesses 0 # DTB write accesses 371system.cpu.itb.inst_accesses 0 # ITB inst accesses 372system.cpu.itb.hits 0 # DTB hits 373system.cpu.itb.misses 0 # DTB misses 374system.cpu.itb.accesses 0 # DTB accesses 375system.cpu.workload.num_syscalls 548 # Number of system calls |
| 376system.cpu.numCycles 723652031 # number of cpu cycles simulated | 376system.cpu.numCycles 723761725 # number of cpu cycles simulated |
| 377system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 378system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 379system.cpu.committedInsts 506582155 # Number of instructions committed 380system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed | 377system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 378system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 379system.cpu.committedInsts 506582155 # Number of instructions committed 380system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed |
| 381system.cpu.discardedOps 14122871 # Number of ops (including micro ops) which were discarded before commit | 381system.cpu.discardedOps 14127209 # Number of ops (including micro ops) which were discarded before commit |
| 382system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 382system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 383system.cpu.cpi 1.428499 # CPI: cycles per instruction 384system.cpu.ipc 0.700036 # IPC: instructions per cycle 385system.cpu.tickCycles 687771211 # Number of cycles that the object actually ticked 386system.cpu.idleCycles 35880820 # Total number of cycles that the object has spent stopped 387system.cpu.icache.tags.replacements 17660 # number of replacements 388system.cpu.icache.tags.tagsinuse 1187.686040 # Cycle average of tags in use 389system.cpu.icache.tags.total_refs 200323378 # Total number of references to valid blocks. 390system.cpu.icache.tags.sampled_refs 19531 # Sample count of references to valid blocks. 391system.cpu.icache.tags.avg_refs 10256.688239 # Average number of references to valid blocks. | 383system.cpu.cpi 1.428715 # CPI: cycles per instruction 384system.cpu.ipc 0.699929 # IPC: instructions per cycle 385system.cpu.tickCycles 687792337 # Number of cycles that the object actually ticked 386system.cpu.idleCycles 35969388 # Total number of cycles that the object has spent stopped 387system.cpu.icache.tags.replacements 17682 # number of replacements 388system.cpu.icache.tags.tagsinuse 1187.679119 # Cycle average of tags in use 389system.cpu.icache.tags.total_refs 200328523 # Total number of references to valid blocks. 390system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks. 391system.cpu.icache.tags.avg_refs 10245.411088 # Average number of references to valid blocks. |
| 392system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 392system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 393system.cpu.icache.tags.occ_blocks::cpu.inst 1187.686040 # Average occupied blocks per requestor 394system.cpu.icache.tags.occ_percent::cpu.inst 0.579925 # Average percentage of cache occupancy 395system.cpu.icache.tags.occ_percent::total 0.579925 # Average percentage of cache occupancy | 393system.cpu.icache.tags.occ_blocks::cpu.inst 1187.679119 # Average occupied blocks per requestor 394system.cpu.icache.tags.occ_percent::cpu.inst 0.579921 # Average percentage of cache occupancy 395system.cpu.icache.tags.occ_percent::total 0.579921 # Average percentage of cache occupancy |
| 396system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id 397system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id | 396system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id 397system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id |
| 398system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 399system.cpu.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id 400system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id 401system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id | 398system.cpu.icache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id 399system.cpu.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id 400system.cpu.icache.tags.age_task_id_blocks_1024::3 304 # Occupied blocks per task id 401system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id |
| 402system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id | 402system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id |
| 403system.cpu.icache.tags.tag_accesses 400705349 # Number of tag accesses 404system.cpu.icache.tags.data_accesses 400705349 # Number of data accesses 405system.cpu.icache.ReadReq_hits::cpu.inst 200323378 # number of ReadReq hits 406system.cpu.icache.ReadReq_hits::total 200323378 # number of ReadReq hits 407system.cpu.icache.demand_hits::cpu.inst 200323378 # number of demand (read+write) hits 408system.cpu.icache.demand_hits::total 200323378 # number of demand (read+write) hits 409system.cpu.icache.overall_hits::cpu.inst 200323378 # number of overall hits 410system.cpu.icache.overall_hits::total 200323378 # number of overall hits 411system.cpu.icache.ReadReq_misses::cpu.inst 19531 # number of ReadReq misses 412system.cpu.icache.ReadReq_misses::total 19531 # number of ReadReq misses 413system.cpu.icache.demand_misses::cpu.inst 19531 # number of demand (read+write) misses 414system.cpu.icache.demand_misses::total 19531 # number of demand (read+write) misses 415system.cpu.icache.overall_misses::cpu.inst 19531 # number of overall misses 416system.cpu.icache.overall_misses::total 19531 # number of overall misses 417system.cpu.icache.ReadReq_miss_latency::cpu.inst 466485747 # number of ReadReq miss cycles 418system.cpu.icache.ReadReq_miss_latency::total 466485747 # number of ReadReq miss cycles 419system.cpu.icache.demand_miss_latency::cpu.inst 466485747 # number of demand (read+write) miss cycles 420system.cpu.icache.demand_miss_latency::total 466485747 # number of demand (read+write) miss cycles 421system.cpu.icache.overall_miss_latency::cpu.inst 466485747 # number of overall miss cycles 422system.cpu.icache.overall_miss_latency::total 466485747 # number of overall miss cycles 423system.cpu.icache.ReadReq_accesses::cpu.inst 200342909 # number of ReadReq accesses(hits+misses) 424system.cpu.icache.ReadReq_accesses::total 200342909 # number of ReadReq accesses(hits+misses) 425system.cpu.icache.demand_accesses::cpu.inst 200342909 # number of demand (read+write) accesses 426system.cpu.icache.demand_accesses::total 200342909 # number of demand (read+write) accesses 427system.cpu.icache.overall_accesses::cpu.inst 200342909 # number of overall (read+write) accesses 428system.cpu.icache.overall_accesses::total 200342909 # number of overall (read+write) accesses 429system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses 430system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses 431system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses 432system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses 433system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses 434system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses 435system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966 # average ReadReq miss latency 436system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966 # average ReadReq miss latency 437system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency 438system.cpu.icache.demand_avg_miss_latency::total 23884.375966 # average overall miss latency 439system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency 440system.cpu.icache.overall_avg_miss_latency::total 23884.375966 # average overall miss latency | 403system.cpu.icache.tags.tag_accesses 400715705 # Number of tag accesses 404system.cpu.icache.tags.data_accesses 400715705 # Number of data accesses 405system.cpu.icache.ReadReq_hits::cpu.inst 200328523 # number of ReadReq hits 406system.cpu.icache.ReadReq_hits::total 200328523 # number of ReadReq hits 407system.cpu.icache.demand_hits::cpu.inst 200328523 # number of demand (read+write) hits 408system.cpu.icache.demand_hits::total 200328523 # number of demand (read+write) hits 409system.cpu.icache.overall_hits::cpu.inst 200328523 # number of overall hits 410system.cpu.icache.overall_hits::total 200328523 # number of overall hits 411system.cpu.icache.ReadReq_misses::cpu.inst 19553 # number of ReadReq misses 412system.cpu.icache.ReadReq_misses::total 19553 # number of ReadReq misses 413system.cpu.icache.demand_misses::cpu.inst 19553 # number of demand (read+write) misses 414system.cpu.icache.demand_misses::total 19553 # number of demand (read+write) misses 415system.cpu.icache.overall_misses::cpu.inst 19553 # number of overall misses 416system.cpu.icache.overall_misses::total 19553 # number of overall misses 417system.cpu.icache.ReadReq_miss_latency::cpu.inst 468017498 # number of ReadReq miss cycles 418system.cpu.icache.ReadReq_miss_latency::total 468017498 # number of ReadReq miss cycles 419system.cpu.icache.demand_miss_latency::cpu.inst 468017498 # number of demand (read+write) miss cycles 420system.cpu.icache.demand_miss_latency::total 468017498 # number of demand (read+write) miss cycles 421system.cpu.icache.overall_miss_latency::cpu.inst 468017498 # number of overall miss cycles 422system.cpu.icache.overall_miss_latency::total 468017498 # number of overall miss cycles 423system.cpu.icache.ReadReq_accesses::cpu.inst 200348076 # number of ReadReq accesses(hits+misses) 424system.cpu.icache.ReadReq_accesses::total 200348076 # number of ReadReq accesses(hits+misses) 425system.cpu.icache.demand_accesses::cpu.inst 200348076 # number of demand (read+write) accesses 426system.cpu.icache.demand_accesses::total 200348076 # number of demand (read+write) accesses 427system.cpu.icache.overall_accesses::cpu.inst 200348076 # number of overall (read+write) accesses 428system.cpu.icache.overall_accesses::total 200348076 # number of overall (read+write) accesses 429system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses 430system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses 431system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses 432system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses 433system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses 434system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses 435system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23935.840945 # average ReadReq miss latency 436system.cpu.icache.ReadReq_avg_miss_latency::total 23935.840945 # average ReadReq miss latency 437system.cpu.icache.demand_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency 438system.cpu.icache.demand_avg_miss_latency::total 23935.840945 # average overall miss latency 439system.cpu.icache.overall_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency 440system.cpu.icache.overall_avg_miss_latency::total 23935.840945 # average overall miss latency |
| 441system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 442system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 443system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 444system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 445system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 446system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 447system.cpu.icache.fast_writes 0 # number of fast writes performed 448system.cpu.icache.cache_copies 0 # number of cache copies performed | 441system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 442system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 443system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 444system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 445system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 446system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 447system.cpu.icache.fast_writes 0 # number of fast writes performed 448system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 449system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19531 # number of ReadReq MSHR misses 450system.cpu.icache.ReadReq_mshr_misses::total 19531 # number of ReadReq MSHR misses 451system.cpu.icache.demand_mshr_misses::cpu.inst 19531 # number of demand (read+write) MSHR misses 452system.cpu.icache.demand_mshr_misses::total 19531 # number of demand (read+write) MSHR misses 453system.cpu.icache.overall_mshr_misses::cpu.inst 19531 # number of overall MSHR misses 454system.cpu.icache.overall_mshr_misses::total 19531 # number of overall MSHR misses 455system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426041253 # number of ReadReq MSHR miss cycles 456system.cpu.icache.ReadReq_mshr_miss_latency::total 426041253 # number of ReadReq MSHR miss cycles 457system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426041253 # number of demand (read+write) MSHR miss cycles 458system.cpu.icache.demand_mshr_miss_latency::total 426041253 # number of demand (read+write) MSHR miss cycles 459system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426041253 # number of overall MSHR miss cycles 460system.cpu.icache.overall_mshr_miss_latency::total 426041253 # number of overall MSHR miss cycles 461system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses 462system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses 463system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses 464system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses 465system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses 466system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses 467system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21813.591368 # average ReadReq mshr miss latency 468system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21813.591368 # average ReadReq mshr miss latency 469system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency 470system.cpu.icache.demand_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency 471system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency 472system.cpu.icache.overall_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency | 449system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19553 # number of ReadReq MSHR misses 450system.cpu.icache.ReadReq_mshr_misses::total 19553 # number of ReadReq MSHR misses 451system.cpu.icache.demand_mshr_misses::cpu.inst 19553 # number of demand (read+write) MSHR misses 452system.cpu.icache.demand_mshr_misses::total 19553 # number of demand (read+write) MSHR misses 453system.cpu.icache.overall_mshr_misses::cpu.inst 19553 # number of overall MSHR misses 454system.cpu.icache.overall_mshr_misses::total 19553 # number of overall MSHR misses 455system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 427542502 # number of ReadReq MSHR miss cycles 456system.cpu.icache.ReadReq_mshr_miss_latency::total 427542502 # number of ReadReq MSHR miss cycles 457system.cpu.icache.demand_mshr_miss_latency::cpu.inst 427542502 # number of demand (read+write) MSHR miss cycles 458system.cpu.icache.demand_mshr_miss_latency::total 427542502 # number of demand (read+write) MSHR miss cycles 459system.cpu.icache.overall_mshr_miss_latency::cpu.inst 427542502 # number of overall MSHR miss cycles 460system.cpu.icache.overall_mshr_miss_latency::total 427542502 # number of overall MSHR miss cycles 461system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses 462system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses 463system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses 464system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses 465system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses 466system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses 467system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21865.826318 # average ReadReq mshr miss latency 468system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21865.826318 # average ReadReq mshr miss latency 469system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21865.826318 # average overall mshr miss latency 470system.cpu.icache.demand_avg_mshr_miss_latency::total 21865.826318 # average overall mshr miss latency 471system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21865.826318 # average overall mshr miss latency 472system.cpu.icache.overall_avg_mshr_miss_latency::total 21865.826318 # average overall mshr miss latency |
| 473system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 473system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 474system.cpu.toL2Bus.throughput 394741942 # Throughput (bytes/s) 475system.cpu.toL2Bus.trans_dist::ReadReq 806872 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::ReadResp 806872 # Transaction distribution | 474system.cpu.toL2Bus.trans_dist::ReadReq 806891 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::ReadResp 806891 # Transaction distribution |
| 477system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution | 476system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution |
| 478system.cpu.toL2Bus.trans_dist::ReadExReq 356393 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::ReadExResp 356393 # Transaction distribution 480system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39062 # Packet count per connected master and slave (bytes) 481system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355889 # Packet count per connected master and slave (bytes) 482system.cpu.toL2Bus.pkt_count::total 3394951 # Packet count per connected master and slave (bytes) 483system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1249984 # Cumulative packet size per connected master and slave (bytes) 484system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141577920 # Cumulative packet size per connected master and slave (bytes) 485system.cpu.toL2Bus.tot_pkt_size::total 142827904 # Cumulative packet size per connected master and slave (bytes) 486system.cpu.toL2Bus.data_through_bus 142827904 # Total data (bytes) 487system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 488system.cpu.toL2Bus.reqLayer0.occupancy 2184264000 # Layer occupancy (ticks) | 477system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution 479system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39106 # Packet count per connected master and slave (bytes) 480system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355897 # Packet count per connected master and slave (bytes) 481system.cpu.toL2Bus.pkt_count::total 3395003 # Packet count per connected master and slave (bytes) 482system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes) 483system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141578176 # Cumulative packet size per connected master and slave (bytes) 484system.cpu.toL2Bus.pkt_size::total 142829568 # Cumulative packet size per connected master and slave (bytes) 485system.cpu.toL2Bus.snoops 0 # Total snoops (count) 486system.cpu.toL2Bus.snoop_fanout::samples 2231712 # Request fanout histogram 487system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 488system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 490system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 491system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 492system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::5 2231712 100.00% 100.00% # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 497system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 498system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 499system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 500system.cpu.toL2Bus.snoop_fanout::total 2231712 # Request fanout histogram 501system.cpu.toL2Bus.reqLayer0.occupancy 2184277000 # Layer occupancy (ticks) |
| 489system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) | 502system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 490system.cpu.toL2Bus.respLayer0.occupancy 29987747 # Layer occupancy (ticks) | 503system.cpu.toL2Bus.respLayer0.occupancy 30013998 # Layer occupancy (ticks) |
| 491system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 504system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 492system.cpu.toL2Bus.respLayer1.occupancy 1744465986 # Layer occupancy (ticks) | 505system.cpu.toL2Bus.respLayer1.occupancy 1744433986 # Layer occupancy (ticks) |
| 493system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) | 506system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) |
| 494system.cpu.l2cache.tags.replacements 111319 # number of replacements 495system.cpu.l2cache.tags.tagsinuse 27632.304905 # Cycle average of tags in use 496system.cpu.l2cache.tags.total_refs 1684536 # Total number of references to valid blocks. 497system.cpu.l2cache.tags.sampled_refs 142508 # Sample count of references to valid blocks. 498system.cpu.l2cache.tags.avg_refs 11.820642 # Average number of references to valid blocks. 499system.cpu.l2cache.tags.warmup_cycle 162493519500 # Cycle when the warmup percentage was hit. 500system.cpu.l2cache.tags.occ_blocks::writebacks 23524.678269 # Average occupied blocks per requestor 501system.cpu.l2cache.tags.occ_blocks::cpu.inst 4107.626636 # Average occupied blocks per requestor 502system.cpu.l2cache.tags.occ_percent::writebacks 0.717916 # Average percentage of cache occupancy 503system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125355 # Average percentage of cache occupancy 504system.cpu.l2cache.tags.occ_percent::total 0.843271 # Average percentage of cache occupancy | 507system.cpu.l2cache.tags.replacements 111337 # number of replacements 508system.cpu.l2cache.tags.tagsinuse 27632.941712 # Cycle average of tags in use 509system.cpu.l2cache.tags.total_refs 1684357 # Total number of references to valid blocks. 510system.cpu.l2cache.tags.sampled_refs 142526 # Sample count of references to valid blocks. 511system.cpu.l2cache.tags.avg_refs 11.817893 # Average number of references to valid blocks. 512system.cpu.l2cache.tags.warmup_cycle 162521333500 # Cycle when the warmup percentage was hit. 513system.cpu.l2cache.tags.occ_blocks::writebacks 23524.774692 # Average occupied blocks per requestor 514system.cpu.l2cache.tags.occ_blocks::cpu.inst 4108.167019 # Average occupied blocks per requestor 515system.cpu.l2cache.tags.occ_percent::writebacks 0.717919 # Average percentage of cache occupancy 516system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125371 # Average percentage of cache occupancy 517system.cpu.l2cache.tags.occ_percent::total 0.843290 # Average percentage of cache occupancy |
| 505system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id | 518system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id |
| 506system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 507system.cpu.l2cache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id 508system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4925 # Occupied blocks per task id 509system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25872 # Occupied blocks per task id | 519system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 520system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 521system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id 522system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4930 # Occupied blocks per task id 523system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25866 # Occupied blocks per task id |
| 510system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id | 524system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id |
| 511system.cpu.l2cache.tags.tag_accesses 18352389 # Number of tag accesses 512system.cpu.l2cache.tags.data_accesses 18352389 # Number of data accesses 513system.cpu.l2cache.ReadReq_hits::cpu.inst 763644 # number of ReadReq hits 514system.cpu.l2cache.ReadReq_hits::total 763644 # number of ReadReq hits | 525system.cpu.l2cache.tags.tag_accesses 18352622 # Number of tag accesses 526system.cpu.l2cache.tags.data_accesses 18352622 # Number of data accesses 527system.cpu.l2cache.ReadReq_hits::cpu.inst 763650 # number of ReadReq hits 528system.cpu.l2cache.ReadReq_hits::total 763650 # number of ReadReq hits |
| 515system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits 516system.cpu.l2cache.Writeback_hits::total 1068421 # number of Writeback hits | 529system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits 530system.cpu.l2cache.Writeback_hits::total 1068421 # number of Writeback hits |
| 517system.cpu.l2cache.ReadExReq_hits::cpu.inst 255531 # number of ReadExReq hits 518system.cpu.l2cache.ReadExReq_hits::total 255531 # number of ReadExReq hits 519system.cpu.l2cache.demand_hits::cpu.inst 1019175 # number of demand (read+write) hits 520system.cpu.l2cache.demand_hits::total 1019175 # number of demand (read+write) hits 521system.cpu.l2cache.overall_hits::cpu.inst 1019175 # number of overall hits 522system.cpu.l2cache.overall_hits::total 1019175 # number of overall hits 523system.cpu.l2cache.ReadReq_misses::cpu.inst 43228 # number of ReadReq misses 524system.cpu.l2cache.ReadReq_misses::total 43228 # number of ReadReq misses 525system.cpu.l2cache.ReadExReq_misses::cpu.inst 100862 # number of ReadExReq misses 526system.cpu.l2cache.ReadExReq_misses::total 100862 # number of ReadExReq misses 527system.cpu.l2cache.demand_misses::cpu.inst 144090 # number of demand (read+write) misses 528system.cpu.l2cache.demand_misses::total 144090 # number of demand (read+write) misses 529system.cpu.l2cache.overall_misses::cpu.inst 144090 # number of overall misses 530system.cpu.l2cache.overall_misses::total 144090 # number of overall misses 531system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3220977500 # number of ReadReq miss cycles 532system.cpu.l2cache.ReadReq_miss_latency::total 3220977500 # number of ReadReq miss cycles 533system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7166346750 # number of ReadExReq miss cycles 534system.cpu.l2cache.ReadExReq_miss_latency::total 7166346750 # number of ReadExReq miss cycles 535system.cpu.l2cache.demand_miss_latency::cpu.inst 10387324250 # number of demand (read+write) miss cycles 536system.cpu.l2cache.demand_miss_latency::total 10387324250 # number of demand (read+write) miss cycles 537system.cpu.l2cache.overall_miss_latency::cpu.inst 10387324250 # number of overall miss cycles 538system.cpu.l2cache.overall_miss_latency::total 10387324250 # number of overall miss cycles 539system.cpu.l2cache.ReadReq_accesses::cpu.inst 806872 # number of ReadReq accesses(hits+misses) 540system.cpu.l2cache.ReadReq_accesses::total 806872 # number of ReadReq accesses(hits+misses) | 531system.cpu.l2cache.ReadExReq_hits::cpu.inst 255534 # number of ReadExReq hits 532system.cpu.l2cache.ReadExReq_hits::total 255534 # number of ReadExReq hits 533system.cpu.l2cache.demand_hits::cpu.inst 1019184 # number of demand (read+write) hits 534system.cpu.l2cache.demand_hits::total 1019184 # number of demand (read+write) hits 535system.cpu.l2cache.overall_hits::cpu.inst 1019184 # number of overall hits 536system.cpu.l2cache.overall_hits::total 1019184 # number of overall hits 537system.cpu.l2cache.ReadReq_misses::cpu.inst 43241 # number of ReadReq misses 538system.cpu.l2cache.ReadReq_misses::total 43241 # number of ReadReq misses 539system.cpu.l2cache.ReadExReq_misses::cpu.inst 100866 # number of ReadExReq misses 540system.cpu.l2cache.ReadExReq_misses::total 100866 # number of ReadExReq misses 541system.cpu.l2cache.demand_misses::cpu.inst 144107 # number of demand (read+write) misses 542system.cpu.l2cache.demand_misses::total 144107 # number of demand (read+write) misses 543system.cpu.l2cache.overall_misses::cpu.inst 144107 # number of overall misses 544system.cpu.l2cache.overall_misses::total 144107 # number of overall misses 545system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3220591000 # number of ReadReq miss cycles 546system.cpu.l2cache.ReadReq_miss_latency::total 3220591000 # number of ReadReq miss cycles 547system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7211196000 # number of ReadExReq miss cycles 548system.cpu.l2cache.ReadExReq_miss_latency::total 7211196000 # number of ReadExReq miss cycles 549system.cpu.l2cache.demand_miss_latency::cpu.inst 10431787000 # number of demand (read+write) miss cycles 550system.cpu.l2cache.demand_miss_latency::total 10431787000 # number of demand (read+write) miss cycles 551system.cpu.l2cache.overall_miss_latency::cpu.inst 10431787000 # number of overall miss cycles 552system.cpu.l2cache.overall_miss_latency::total 10431787000 # number of overall miss cycles 553system.cpu.l2cache.ReadReq_accesses::cpu.inst 806891 # number of ReadReq accesses(hits+misses) 554system.cpu.l2cache.ReadReq_accesses::total 806891 # number of ReadReq accesses(hits+misses) |
| 541system.cpu.l2cache.Writeback_accesses::writebacks 1068421 # number of Writeback accesses(hits+misses) 542system.cpu.l2cache.Writeback_accesses::total 1068421 # number of Writeback accesses(hits+misses) | 555system.cpu.l2cache.Writeback_accesses::writebacks 1068421 # number of Writeback accesses(hits+misses) 556system.cpu.l2cache.Writeback_accesses::total 1068421 # number of Writeback accesses(hits+misses) |
| 543system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356393 # number of ReadExReq accesses(hits+misses) 544system.cpu.l2cache.ReadExReq_accesses::total 356393 # number of ReadExReq accesses(hits+misses) 545system.cpu.l2cache.demand_accesses::cpu.inst 1163265 # number of demand (read+write) accesses 546system.cpu.l2cache.demand_accesses::total 1163265 # number of demand (read+write) accesses 547system.cpu.l2cache.overall_accesses::cpu.inst 1163265 # number of overall (read+write) accesses 548system.cpu.l2cache.overall_accesses::total 1163265 # number of overall (read+write) accesses 549system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053575 # miss rate for ReadReq accesses 550system.cpu.l2cache.ReadReq_miss_rate::total 0.053575 # miss rate for ReadReq accesses 551system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283008 # miss rate for ReadExReq accesses 552system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses 553system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123867 # miss rate for demand accesses 554system.cpu.l2cache.demand_miss_rate::total 0.123867 # miss rate for demand accesses 555system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123867 # miss rate for overall accesses 556system.cpu.l2cache.overall_miss_rate::total 0.123867 # miss rate for overall accesses 557system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74511.369945 # average ReadReq miss latency 558system.cpu.l2cache.ReadReq_avg_miss_latency::total 74511.369945 # average ReadReq miss latency 559system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71051.007813 # average ReadExReq miss latency 560system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71051.007813 # average ReadExReq miss latency 561system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency 562system.cpu.l2cache.demand_avg_miss_latency::total 72089.140468 # average overall miss latency 563system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency 564system.cpu.l2cache.overall_avg_miss_latency::total 72089.140468 # average overall miss latency | 557system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356400 # number of ReadExReq accesses(hits+misses) 558system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses) 559system.cpu.l2cache.demand_accesses::cpu.inst 1163291 # number of demand (read+write) accesses 560system.cpu.l2cache.demand_accesses::total 1163291 # number of demand (read+write) accesses 561system.cpu.l2cache.overall_accesses::cpu.inst 1163291 # number of overall (read+write) accesses 562system.cpu.l2cache.overall_accesses::total 1163291 # number of overall (read+write) accesses 563system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053590 # miss rate for ReadReq accesses 564system.cpu.l2cache.ReadReq_miss_rate::total 0.053590 # miss rate for ReadReq accesses 565system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283013 # miss rate for ReadExReq accesses 566system.cpu.l2cache.ReadExReq_miss_rate::total 0.283013 # miss rate for ReadExReq accesses 567system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123879 # miss rate for demand accesses 568system.cpu.l2cache.demand_miss_rate::total 0.123879 # miss rate for demand accesses 569system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123879 # miss rate for overall accesses 570system.cpu.l2cache.overall_miss_rate::total 0.123879 # miss rate for overall accesses 571system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74480.030527 # average ReadReq miss latency 572system.cpu.l2cache.ReadReq_avg_miss_latency::total 74480.030527 # average ReadReq miss latency 573system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71492.832074 # average ReadExReq miss latency 574system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71492.832074 # average ReadExReq miss latency 575system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency 576system.cpu.l2cache.demand_avg_miss_latency::total 72389.176098 # average overall miss latency 577system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::total 72389.176098 # average overall miss latency |
| 565system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 566system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 567system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 568system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 569system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 570system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 571system.cpu.l2cache.fast_writes 0 # number of fast writes performed 572system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 579system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 580system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 583system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 584system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 585system.cpu.l2cache.fast_writes 0 # number of fast writes performed 586system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 573system.cpu.l2cache.writebacks::writebacks 96516 # number of writebacks 574system.cpu.l2cache.writebacks::total 96516 # number of writebacks | 587system.cpu.l2cache.writebacks::writebacks 96521 # number of writebacks 588system.cpu.l2cache.writebacks::total 96521 # number of writebacks |
| 575system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits 576system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits 577system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits 578system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 579system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits 580system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits | 589system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits 590system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits 591system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits 592system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 593system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits 594system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits |
| 581system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43212 # number of ReadReq MSHR misses 582system.cpu.l2cache.ReadReq_mshr_misses::total 43212 # number of ReadReq MSHR misses 583system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100862 # number of ReadExReq MSHR misses 584system.cpu.l2cache.ReadExReq_mshr_misses::total 100862 # number of ReadExReq MSHR misses 585system.cpu.l2cache.demand_mshr_misses::cpu.inst 144074 # number of demand (read+write) MSHR misses 586system.cpu.l2cache.demand_mshr_misses::total 144074 # number of demand (read+write) MSHR misses 587system.cpu.l2cache.overall_mshr_misses::cpu.inst 144074 # number of overall MSHR misses 588system.cpu.l2cache.overall_mshr_misses::total 144074 # number of overall MSHR misses 589system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2672872000 # number of ReadReq MSHR miss cycles 590system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2672872000 # number of ReadReq MSHR miss cycles 591system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5889125250 # number of ReadExReq MSHR miss cycles 592system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5889125250 # number of ReadExReq MSHR miss cycles 593system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8561997250 # number of demand (read+write) MSHR miss cycles 594system.cpu.l2cache.demand_mshr_miss_latency::total 8561997250 # number of demand (read+write) MSHR miss cycles 595system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8561997250 # number of overall MSHR miss cycles 596system.cpu.l2cache.overall_mshr_miss_latency::total 8561997250 # number of overall MSHR miss cycles 597system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053555 # mshr miss rate for ReadReq accesses 598system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053555 # mshr miss rate for ReadReq accesses 599system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283008 # mshr miss rate for ReadExReq accesses 600system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses 601system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for demand accesses 602system.cpu.l2cache.demand_mshr_miss_rate::total 0.123853 # mshr miss rate for demand accesses 603system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for overall accesses 604system.cpu.l2cache.overall_mshr_miss_rate::total 0.123853 # mshr miss rate for overall accesses 605system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61854.855133 # average ReadReq mshr miss latency 606system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61854.855133 # average ReadReq mshr miss latency 607system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58387.948385 # average ReadExReq mshr miss latency 608system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58387.948385 # average ReadExReq mshr miss latency 609system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59427.774963 # average overall mshr miss latency 610system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59427.774963 # average overall mshr miss latency 611system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59427.774963 # average overall mshr miss latency 612system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59427.774963 # average overall mshr miss latency | 595system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43225 # number of ReadReq MSHR misses 596system.cpu.l2cache.ReadReq_mshr_misses::total 43225 # number of ReadReq MSHR misses 597system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100866 # number of ReadExReq MSHR misses 598system.cpu.l2cache.ReadExReq_mshr_misses::total 100866 # number of ReadExReq MSHR misses 599system.cpu.l2cache.demand_mshr_misses::cpu.inst 144091 # number of demand (read+write) MSHR misses 600system.cpu.l2cache.demand_mshr_misses::total 144091 # number of demand (read+write) MSHR misses 601system.cpu.l2cache.overall_mshr_misses::cpu.inst 144091 # number of overall MSHR misses 602system.cpu.l2cache.overall_mshr_misses::total 144091 # number of overall MSHR misses 603system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2672436250 # number of ReadReq MSHR miss cycles 604system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2672436250 # number of ReadReq MSHR miss cycles 605system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5933940000 # number of ReadExReq MSHR miss cycles 606system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5933940000 # number of ReadExReq MSHR miss cycles 607system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8606376250 # number of demand (read+write) MSHR miss cycles 608system.cpu.l2cache.demand_mshr_miss_latency::total 8606376250 # number of demand (read+write) MSHR miss cycles 609system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8606376250 # number of overall MSHR miss cycles 610system.cpu.l2cache.overall_mshr_miss_latency::total 8606376250 # number of overall MSHR miss cycles 611system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053570 # mshr miss rate for ReadReq accesses 612system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053570 # mshr miss rate for ReadReq accesses 613system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283013 # mshr miss rate for ReadExReq accesses 614system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283013 # mshr miss rate for ReadExReq accesses 615system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for demand accesses 616system.cpu.l2cache.demand_mshr_miss_rate::total 0.123865 # mshr miss rate for demand accesses 617system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for overall accesses 618system.cpu.l2cache.overall_mshr_miss_rate::total 0.123865 # mshr miss rate for overall accesses 619system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.171197 # average ReadReq mshr miss latency 620system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.171197 # average ReadReq mshr miss latency 621system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58829.932782 # average ReadExReq mshr miss latency 622system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58829.932782 # average ReadExReq mshr miss latency 623system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency 624system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency 625system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency 626system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency |
| 613system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 627system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 614system.cpu.dcache.tags.replacements 1139638 # number of replacements 615system.cpu.dcache.tags.tagsinuse 4071.125159 # Cycle average of tags in use 616system.cpu.dcache.tags.total_refs 169305637 # Total number of references to valid blocks. 617system.cpu.dcache.tags.sampled_refs 1143734 # Sample count of references to valid blocks. 618system.cpu.dcache.tags.avg_refs 148.028857 # Average number of references to valid blocks. | 628system.cpu.dcache.tags.replacements 1139642 # number of replacements 629system.cpu.dcache.tags.tagsinuse 4071.128930 # Cycle average of tags in use 630system.cpu.dcache.tags.total_refs 169306917 # Total number of references to valid blocks. 631system.cpu.dcache.tags.sampled_refs 1143738 # Sample count of references to valid blocks. 632system.cpu.dcache.tags.avg_refs 148.029459 # Average number of references to valid blocks. |
| 619system.cpu.dcache.tags.warmup_cycle 4807181250 # Cycle when the warmup percentage was hit. | 633system.cpu.dcache.tags.warmup_cycle 4807181250 # Cycle when the warmup percentage was hit. |
| 620system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.125159 # Average occupied blocks per requestor 621system.cpu.dcache.tags.occ_percent::cpu.inst 0.993927 # Average percentage of cache occupancy 622system.cpu.dcache.tags.occ_percent::total 0.993927 # Average percentage of cache occupancy | 634system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.128930 # Average occupied blocks per requestor 635system.cpu.dcache.tags.occ_percent::cpu.inst 0.993928 # Average percentage of cache occupancy 636system.cpu.dcache.tags.occ_percent::total 0.993928 # Average percentage of cache occupancy |
| 623system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 624system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id | 637system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 638system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id |
| 625system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 626system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id 627system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id | 639system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 640system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id 641system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id |
| 628system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 642system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 629system.cpu.dcache.tags.tag_accesses 342864800 # Number of tag accesses 630system.cpu.dcache.tags.data_accesses 342864800 # Number of data accesses 631system.cpu.dcache.ReadReq_hits::cpu.inst 112789835 # number of ReadReq hits 632system.cpu.dcache.ReadReq_hits::total 112789835 # number of ReadReq hits 633system.cpu.dcache.WriteReq_hits::cpu.inst 53538720 # number of WriteReq hits 634system.cpu.dcache.WriteReq_hits::total 53538720 # number of WriteReq hits | 643system.cpu.dcache.tags.tag_accesses 342867294 # Number of tag accesses 644system.cpu.dcache.tags.data_accesses 342867294 # Number of data accesses 645system.cpu.dcache.ReadReq_hits::cpu.inst 112791129 # number of ReadReq hits 646system.cpu.dcache.ReadReq_hits::total 112791129 # number of ReadReq hits 647system.cpu.dcache.WriteReq_hits::cpu.inst 53538706 # number of WriteReq hits 648system.cpu.dcache.WriteReq_hits::total 53538706 # number of WriteReq hits |
| 635system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits 636system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 637system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits 638system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits | 649system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits 650system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 651system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits 652system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits |
| 639system.cpu.dcache.demand_hits::cpu.inst 166328555 # number of demand (read+write) hits 640system.cpu.dcache.demand_hits::total 166328555 # number of demand (read+write) hits 641system.cpu.dcache.overall_hits::cpu.inst 166328555 # number of overall hits 642system.cpu.dcache.overall_hits::total 166328555 # number of overall hits 643system.cpu.dcache.ReadReq_misses::cpu.inst 854310 # number of ReadReq misses 644system.cpu.dcache.ReadReq_misses::total 854310 # number of ReadReq misses 645system.cpu.dcache.WriteReq_misses::cpu.inst 700586 # number of WriteReq misses 646system.cpu.dcache.WriteReq_misses::total 700586 # number of WriteReq misses 647system.cpu.dcache.demand_misses::cpu.inst 1554896 # number of demand (read+write) misses 648system.cpu.dcache.demand_misses::total 1554896 # number of demand (read+write) misses 649system.cpu.dcache.overall_misses::cpu.inst 1554896 # number of overall misses 650system.cpu.dcache.overall_misses::total 1554896 # number of overall misses 651system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13696134233 # number of ReadReq miss cycles 652system.cpu.dcache.ReadReq_miss_latency::total 13696134233 # number of ReadReq miss cycles 653system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20619900500 # number of WriteReq miss cycles 654system.cpu.dcache.WriteReq_miss_latency::total 20619900500 # number of WriteReq miss cycles 655system.cpu.dcache.demand_miss_latency::cpu.inst 34316034733 # number of demand (read+write) miss cycles 656system.cpu.dcache.demand_miss_latency::total 34316034733 # number of demand (read+write) miss cycles 657system.cpu.dcache.overall_miss_latency::cpu.inst 34316034733 # number of overall miss cycles 658system.cpu.dcache.overall_miss_latency::total 34316034733 # number of overall miss cycles 659system.cpu.dcache.ReadReq_accesses::cpu.inst 113644145 # number of ReadReq accesses(hits+misses) 660system.cpu.dcache.ReadReq_accesses::total 113644145 # number of ReadReq accesses(hits+misses) | 653system.cpu.dcache.demand_hits::cpu.inst 166329835 # number of demand (read+write) hits 654system.cpu.dcache.demand_hits::total 166329835 # number of demand (read+write) hits 655system.cpu.dcache.overall_hits::cpu.inst 166329835 # number of overall hits 656system.cpu.dcache.overall_hits::total 166329835 # number of overall hits 657system.cpu.dcache.ReadReq_misses::cpu.inst 854261 # number of ReadReq misses 658system.cpu.dcache.ReadReq_misses::total 854261 # number of ReadReq misses 659system.cpu.dcache.WriteReq_misses::cpu.inst 700600 # number of WriteReq misses 660system.cpu.dcache.WriteReq_misses::total 700600 # number of WriteReq misses 661system.cpu.dcache.demand_misses::cpu.inst 1554861 # number of demand (read+write) misses 662system.cpu.dcache.demand_misses::total 1554861 # number of demand (read+write) misses 663system.cpu.dcache.overall_misses::cpu.inst 1554861 # number of overall misses 664system.cpu.dcache.overall_misses::total 1554861 # number of overall misses 665system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13692452733 # number of ReadReq miss cycles 666system.cpu.dcache.ReadReq_miss_latency::total 13692452733 # number of ReadReq miss cycles 667system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20709081750 # number of WriteReq miss cycles 668system.cpu.dcache.WriteReq_miss_latency::total 20709081750 # number of WriteReq miss cycles 669system.cpu.dcache.demand_miss_latency::cpu.inst 34401534483 # number of demand (read+write) miss cycles 670system.cpu.dcache.demand_miss_latency::total 34401534483 # number of demand (read+write) miss cycles 671system.cpu.dcache.overall_miss_latency::cpu.inst 34401534483 # number of overall miss cycles 672system.cpu.dcache.overall_miss_latency::total 34401534483 # number of overall miss cycles 673system.cpu.dcache.ReadReq_accesses::cpu.inst 113645390 # number of ReadReq accesses(hits+misses) 674system.cpu.dcache.ReadReq_accesses::total 113645390 # number of ReadReq accesses(hits+misses) |
| 661system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) 662system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 663system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) 664system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 665system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) 666system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) | 675system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) 676system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 677system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) 678system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 679system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) 680system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) |
| 667system.cpu.dcache.demand_accesses::cpu.inst 167883451 # number of demand (read+write) accesses 668system.cpu.dcache.demand_accesses::total 167883451 # number of demand (read+write) accesses 669system.cpu.dcache.overall_accesses::cpu.inst 167883451 # number of overall (read+write) accesses 670system.cpu.dcache.overall_accesses::total 167883451 # number of overall (read+write) accesses | 681system.cpu.dcache.demand_accesses::cpu.inst 167884696 # number of demand (read+write) accesses 682system.cpu.dcache.demand_accesses::total 167884696 # number of demand (read+write) accesses 683system.cpu.dcache.overall_accesses::cpu.inst 167884696 # number of overall (read+write) accesses 684system.cpu.dcache.overall_accesses::total 167884696 # number of overall (read+write) accesses |
| 671system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007517 # miss rate for ReadReq accesses 672system.cpu.dcache.ReadReq_miss_rate::total 0.007517 # miss rate for ReadReq accesses 673system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses 674system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses | 685system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007517 # miss rate for ReadReq accesses 686system.cpu.dcache.ReadReq_miss_rate::total 0.007517 # miss rate for ReadReq accesses 687system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses 688system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses |
| 675system.cpu.dcache.demand_miss_rate::cpu.inst 0.009262 # miss rate for demand accesses 676system.cpu.dcache.demand_miss_rate::total 0.009262 # miss rate for demand accesses 677system.cpu.dcache.overall_miss_rate::cpu.inst 0.009262 # miss rate for overall accesses 678system.cpu.dcache.overall_miss_rate::total 0.009262 # miss rate for overall accesses 679system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16031.808399 # average ReadReq miss latency 680system.cpu.dcache.ReadReq_avg_miss_latency::total 16031.808399 # average ReadReq miss latency 681system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29432.361623 # average WriteReq miss latency 682system.cpu.dcache.WriteReq_avg_miss_latency::total 29432.361623 # average WriteReq miss latency 683system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency 684system.cpu.dcache.demand_avg_miss_latency::total 22069.665581 # average overall miss latency 685system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency 686system.cpu.dcache.overall_avg_miss_latency::total 22069.665581 # average overall miss latency | 689system.cpu.dcache.demand_miss_rate::cpu.inst 0.009261 # miss rate for demand accesses 690system.cpu.dcache.demand_miss_rate::total 0.009261 # miss rate for demand accesses 691system.cpu.dcache.overall_miss_rate::cpu.inst 0.009261 # miss rate for overall accesses 692system.cpu.dcache.overall_miss_rate::total 0.009261 # miss rate for overall accesses 693system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16028.418403 # average ReadReq miss latency 694system.cpu.dcache.ReadReq_avg_miss_latency::total 16028.418403 # average ReadReq miss latency 695system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29559.066158 # average WriteReq miss latency 696system.cpu.dcache.WriteReq_avg_miss_latency::total 29559.066158 # average WriteReq miss latency 697system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency 698system.cpu.dcache.demand_avg_miss_latency::total 22125.151048 # average overall miss latency 699system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency 700system.cpu.dcache.overall_avg_miss_latency::total 22125.151048 # average overall miss latency |
| 687system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 688system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 690system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 692system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 693system.cpu.dcache.fast_writes 0 # number of fast writes performed 694system.cpu.dcache.cache_copies 0 # number of cache copies performed 695system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks 696system.cpu.dcache.writebacks::total 1068421 # number of writebacks | 701system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 702system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 703system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 704system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 705system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 706system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 707system.cpu.dcache.fast_writes 0 # number of fast writes performed 708system.cpu.dcache.cache_copies 0 # number of cache copies performed 709system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks 710system.cpu.dcache.writebacks::total 1068421 # number of writebacks |
| 697system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66718 # number of ReadReq MSHR hits 698system.cpu.dcache.ReadReq_mshr_hits::total 66718 # number of ReadReq MSHR hits 699system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344444 # number of WriteReq MSHR hits 700system.cpu.dcache.WriteReq_mshr_hits::total 344444 # number of WriteReq MSHR hits 701system.cpu.dcache.demand_mshr_hits::cpu.inst 411162 # number of demand (read+write) MSHR hits 702system.cpu.dcache.demand_mshr_hits::total 411162 # number of demand (read+write) MSHR hits 703system.cpu.dcache.overall_mshr_hits::cpu.inst 411162 # number of overall MSHR hits 704system.cpu.dcache.overall_mshr_hits::total 411162 # number of overall MSHR hits 705system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787592 # number of ReadReq MSHR misses 706system.cpu.dcache.ReadReq_mshr_misses::total 787592 # number of ReadReq MSHR misses 707system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356142 # number of WriteReq MSHR misses 708system.cpu.dcache.WriteReq_mshr_misses::total 356142 # number of WriteReq MSHR misses 709system.cpu.dcache.demand_mshr_misses::cpu.inst 1143734 # number of demand (read+write) MSHR misses 710system.cpu.dcache.demand_mshr_misses::total 1143734 # number of demand (read+write) MSHR misses 711system.cpu.dcache.overall_mshr_misses::cpu.inst 1143734 # number of overall MSHR misses 712system.cpu.dcache.overall_mshr_misses::total 1143734 # number of overall MSHR misses 713system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11245323264 # number of ReadReq MSHR miss cycles 714system.cpu.dcache.ReadReq_mshr_miss_latency::total 11245323264 # number of ReadReq MSHR miss cycles 715system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10075452250 # number of WriteReq MSHR miss cycles 716system.cpu.dcache.WriteReq_mshr_miss_latency::total 10075452250 # number of WriteReq MSHR miss cycles 717system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21320775514 # number of demand (read+write) MSHR miss cycles 718system.cpu.dcache.demand_mshr_miss_latency::total 21320775514 # number of demand (read+write) MSHR miss cycles 719system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21320775514 # number of overall MSHR miss cycles 720system.cpu.dcache.overall_mshr_miss_latency::total 21320775514 # number of overall MSHR miss cycles | 711system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66670 # number of ReadReq MSHR hits 712system.cpu.dcache.ReadReq_mshr_hits::total 66670 # number of ReadReq MSHR hits 713system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344453 # number of WriteReq MSHR hits 714system.cpu.dcache.WriteReq_mshr_hits::total 344453 # number of WriteReq MSHR hits 715system.cpu.dcache.demand_mshr_hits::cpu.inst 411123 # number of demand (read+write) MSHR hits 716system.cpu.dcache.demand_mshr_hits::total 411123 # number of demand (read+write) MSHR hits 717system.cpu.dcache.overall_mshr_hits::cpu.inst 411123 # number of overall MSHR hits 718system.cpu.dcache.overall_mshr_hits::total 411123 # number of overall MSHR hits 719system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787591 # number of ReadReq MSHR misses 720system.cpu.dcache.ReadReq_mshr_misses::total 787591 # number of ReadReq MSHR misses 721system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356147 # number of WriteReq MSHR misses 722system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses 723system.cpu.dcache.demand_mshr_misses::cpu.inst 1143738 # number of demand (read+write) MSHR misses 724system.cpu.dcache.demand_mshr_misses::total 1143738 # number of demand (read+write) MSHR misses 725system.cpu.dcache.overall_mshr_misses::cpu.inst 1143738 # number of overall MSHR misses 726system.cpu.dcache.overall_mshr_misses::total 1143738 # number of overall MSHR misses 727system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11243518014 # number of ReadReq MSHR miss cycles 728system.cpu.dcache.ReadReq_mshr_miss_latency::total 11243518014 # number of ReadReq MSHR miss cycles 729system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10120311000 # number of WriteReq MSHR miss cycles 730system.cpu.dcache.WriteReq_mshr_miss_latency::total 10120311000 # number of WriteReq MSHR miss cycles 731system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21363829014 # number of demand (read+write) MSHR miss cycles 732system.cpu.dcache.demand_mshr_miss_latency::total 21363829014 # number of demand (read+write) MSHR miss cycles 733system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21363829014 # number of overall MSHR miss cycles 734system.cpu.dcache.overall_mshr_miss_latency::total 21363829014 # number of overall MSHR miss cycles |
| 721system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses 722system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses 723system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses 724system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses 725system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for demand accesses 726system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses 727system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses 728system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses | 735system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses 736system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses 737system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses 738system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses 739system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for demand accesses 740system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses 741system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses 742system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses |
| 729system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.107528 # average ReadReq mshr miss latency 730system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.107528 # average ReadReq mshr miss latency 731system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28290.547731 # average WriteReq mshr miss latency 732system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28290.547731 # average WriteReq mshr miss latency 733system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency 734system.cpu.dcache.demand_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency 735system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency 736system.cpu.dcache.overall_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency | 743system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14275.833541 # average ReadReq mshr miss latency 744system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14275.833541 # average ReadReq mshr miss latency 745system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28416.106271 # average WriteReq mshr miss latency 746system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28416.106271 # average WriteReq mshr miss latency 747system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency 748system.cpu.dcache.demand_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency 749system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency 750system.cpu.dcache.overall_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency |
| 737system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 738 739---------- End Simulation Statistics ---------- | 751system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 752 753---------- End Simulation Statistics ---------- |