| stats.txt (10260:384d554cea8c) | stats.txt (10352:5f1f92bf76ee) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3final_tick 377848323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 4host_inst_rate 209721 # Simulator instruction rate (inst/s) 5host_mem_usage 298084 # Number of bytes of host memory used 6host_op_rate 236376 # Simulator op (including micro ops) rate (op/s) 7host_seconds 2415.51 # Real time elapsed on the host 8host_tick_rate 156426000 # Simulator tick rate (ticks/s) | 3sim_seconds 0.361826 # Number of seconds simulated 4sim_ticks 361826015500 # Number of ticks simulated 5final_tick 361826015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 9sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 231274 # Simulator instruction rate (inst/s) 8host_op_rate 250500 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 165186980 # Simulator tick rate (ticks/s) 10host_mem_usage 321304 # Number of bytes of host memory used 11host_seconds 2190.40 # Real time elapsed on the host |
|
| 10sim_insts 506582155 # Number of instructions simulated | 12sim_insts 506582155 # Number of instructions simulated |
| 11sim_ops 570968717 # Number of ops (including micro ops) simulated 12sim_seconds 0.377848 # Number of seconds simulated 13sim_ticks 377848323500 # Number of ticks simulated | 13sim_ops 548695378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts |
| 14system.clk_domain.clock 1000 # Clock period in ticks | 15system.clk_domain.clock 1000 # Clock period in ticks |
| 15system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 16system.cpu.branchPred.BTBHitPct 88.099044 # BTB Hit Percentage 17system.cpu.branchPred.BTBHits 66115419 # Number of BTB hits 18system.cpu.branchPred.BTBLookups 75046693 # Number of BTB lookups 19system.cpu.branchPred.RASInCorrect 20332 # Number of incorrect RAS predictions. 20system.cpu.branchPred.condIncorrect 6724593 # Number of conditional branches incorrect 21system.cpu.branchPred.condPredicted 104577278 # Number of conditional branches predicted 22system.cpu.branchPred.lookups 137186083 # Number of BP lookups 23system.cpu.branchPred.usedRAS 8950727 # Number of times the RAS was used to get a target. 24system.cpu.committedInsts 506582155 # Number of instructions committed 25system.cpu.committedOps 570968717 # Number of ops (including micro ops) committed 26system.cpu.cpi 1.491755 # CPI: cycles per instruction 27system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) 28system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 29system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits 30system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 31system.cpu.dcache.ReadReq_accesses::cpu.inst 123498792 # number of ReadReq accesses(hits+misses) 32system.cpu.dcache.ReadReq_accesses::total 123498792 # number of ReadReq accesses(hits+misses) 33system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16388.035885 # average ReadReq miss latency 34system.cpu.dcache.ReadReq_avg_miss_latency::total 16388.035885 # average ReadReq miss latency 35system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.902943 # average ReadReq mshr miss latency 36system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.902943 # average ReadReq mshr miss latency 37system.cpu.dcache.ReadReq_hits::cpu.inst 122622654 # number of ReadReq hits 38system.cpu.dcache.ReadReq_hits::total 122622654 # number of ReadReq hits 39system.cpu.dcache.ReadReq_miss_latency::cpu.inst 14358180984 # number of ReadReq miss cycles 40system.cpu.dcache.ReadReq_miss_latency::total 14358180984 # number of ReadReq miss cycles 41system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007094 # miss rate for ReadReq accesses 42system.cpu.dcache.ReadReq_miss_rate::total 0.007094 # miss rate for ReadReq accesses 43system.cpu.dcache.ReadReq_misses::cpu.inst 876138 # number of ReadReq misses 44system.cpu.dcache.ReadReq_misses::total 876138 # number of ReadReq misses 45system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 88069 # number of ReadReq MSHR hits 46system.cpu.dcache.ReadReq_mshr_hits::total 88069 # number of ReadReq MSHR hits 47system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11252760763 # number of ReadReq MSHR miss cycles 48system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252760763 # number of ReadReq MSHR miss cycles 49system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006381 # mshr miss rate for ReadReq accesses 50system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006381 # mshr miss rate for ReadReq accesses 51system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 788069 # number of ReadReq MSHR misses 52system.cpu.dcache.ReadReq_mshr_misses::total 788069 # number of ReadReq MSHR misses 53system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) 54system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 55system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits 56system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 57system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) 58system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 59system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29400.581233 # average WriteReq miss latency 60system.cpu.dcache.WriteReq_avg_miss_latency::total 29400.581233 # average WriteReq miss latency 61system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28261.554772 # average WriteReq mshr miss latency 62system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28261.554772 # average WriteReq mshr miss latency 63system.cpu.dcache.WriteReq_hits::cpu.inst 53538382 # number of WriteReq hits 64system.cpu.dcache.WriteReq_hits::total 53538382 # number of WriteReq hits 65system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20607573000 # number of WriteReq miss cycles 66system.cpu.dcache.WriteReq_miss_latency::total 20607573000 # number of WriteReq miss cycles 67system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012923 # miss rate for WriteReq accesses 68system.cpu.dcache.WriteReq_miss_rate::total 0.012923 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses::cpu.inst 700924 # number of WriteReq misses 70system.cpu.dcache.WriteReq_misses::total 700924 # number of WriteReq misses 71system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344621 # number of WriteReq MSHR hits 72system.cpu.dcache.WriteReq_mshr_hits::total 344621 # number of WriteReq MSHR hits 73system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10069676750 # number of WriteReq MSHR miss cycles 74system.cpu.dcache.WriteReq_mshr_miss_latency::total 10069676750 # number of WriteReq MSHR miss cycles 75system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006569 # mshr miss rate for WriteReq accesses 76system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses 77system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356303 # number of WriteReq MSHR misses 78system.cpu.dcache.WriteReq_mshr_misses::total 356303 # number of WriteReq MSHR misses 79system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 82system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 83system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 84system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85system.cpu.dcache.cache_copies 0 # number of cache copies performed 86system.cpu.dcache.demand_accesses::cpu.inst 177738098 # number of demand (read+write) accesses 87system.cpu.dcache.demand_accesses::total 177738098 # number of demand (read+write) accesses 88system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22171.451715 # average overall miss latency 89system.cpu.dcache.demand_avg_miss_latency::total 22171.451715 # average overall miss latency 90system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18632.435531 # average overall mshr miss latency 91system.cpu.dcache.demand_avg_mshr_miss_latency::total 18632.435531 # average overall mshr miss latency 92system.cpu.dcache.demand_hits::cpu.inst 176161036 # number of demand (read+write) hits 93system.cpu.dcache.demand_hits::total 176161036 # number of demand (read+write) hits 94system.cpu.dcache.demand_miss_latency::cpu.inst 34965753984 # number of demand (read+write) miss cycles 95system.cpu.dcache.demand_miss_latency::total 34965753984 # number of demand (read+write) miss cycles 96system.cpu.dcache.demand_miss_rate::cpu.inst 0.008873 # miss rate for demand accesses 97system.cpu.dcache.demand_miss_rate::total 0.008873 # miss rate for demand accesses 98system.cpu.dcache.demand_misses::cpu.inst 1577062 # number of demand (read+write) misses 99system.cpu.dcache.demand_misses::total 1577062 # number of demand (read+write) misses 100system.cpu.dcache.demand_mshr_hits::cpu.inst 432690 # number of demand (read+write) MSHR hits 101system.cpu.dcache.demand_mshr_hits::total 432690 # number of demand (read+write) MSHR hits 102system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21322437513 # number of demand (read+write) MSHR miss cycles 103system.cpu.dcache.demand_mshr_miss_latency::total 21322437513 # number of demand (read+write) MSHR miss cycles 104system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006439 # mshr miss rate for demand accesses 105system.cpu.dcache.demand_mshr_miss_rate::total 0.006439 # mshr miss rate for demand accesses 106system.cpu.dcache.demand_mshr_misses::cpu.inst 1144372 # number of demand (read+write) MSHR misses 107system.cpu.dcache.demand_mshr_misses::total 1144372 # number of demand (read+write) MSHR misses 108system.cpu.dcache.fast_writes 0 # number of fast writes performed 109system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 110system.cpu.dcache.overall_accesses::cpu.inst 177738098 # number of overall (read+write) accesses 111system.cpu.dcache.overall_accesses::total 177738098 # number of overall (read+write) accesses 112system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22171.451715 # average overall miss latency 113system.cpu.dcache.overall_avg_miss_latency::total 22171.451715 # average overall miss latency 114system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18632.435531 # average overall mshr miss latency 115system.cpu.dcache.overall_avg_mshr_miss_latency::total 18632.435531 # average overall mshr miss latency 116system.cpu.dcache.overall_hits::cpu.inst 176161036 # number of overall hits 117system.cpu.dcache.overall_hits::total 176161036 # number of overall hits 118system.cpu.dcache.overall_miss_latency::cpu.inst 34965753984 # number of overall miss cycles 119system.cpu.dcache.overall_miss_latency::total 34965753984 # number of overall miss cycles 120system.cpu.dcache.overall_miss_rate::cpu.inst 0.008873 # miss rate for overall accesses 121system.cpu.dcache.overall_miss_rate::total 0.008873 # miss rate for overall accesses 122system.cpu.dcache.overall_misses::cpu.inst 1577062 # number of overall misses 123system.cpu.dcache.overall_misses::total 1577062 # number of overall misses 124system.cpu.dcache.overall_mshr_hits::cpu.inst 432690 # number of overall MSHR hits 125system.cpu.dcache.overall_mshr_hits::total 432690 # number of overall MSHR hits 126system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21322437513 # number of overall MSHR miss cycles 127system.cpu.dcache.overall_mshr_miss_latency::total 21322437513 # number of overall MSHR miss cycles 128system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006439 # mshr miss rate for overall accesses 129system.cpu.dcache.overall_mshr_miss_rate::total 0.006439 # mshr miss rate for overall accesses 130system.cpu.dcache.overall_mshr_misses::cpu.inst 1144372 # number of overall MSHR misses 131system.cpu.dcache.overall_mshr_misses::total 1144372 # number of overall MSHR misses 132system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 133system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 134system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id 135system.cpu.dcache.tags.age_task_id_blocks_1024::3 3508 # Occupied blocks per task id 136system.cpu.dcache.tags.avg_refs 156.538362 # Average number of references to valid blocks. 137system.cpu.dcache.tags.data_accesses 362574732 # Number of data accesses 138system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.496497 # Average occupied blocks per requestor 139system.cpu.dcache.tags.occ_percent::cpu.inst 0.994018 # Average percentage of cache occupancy 140system.cpu.dcache.tags.occ_percent::total 0.994018 # Average percentage of cache occupancy 141system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 142system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 143system.cpu.dcache.tags.replacements 1140276 # number of replacements 144system.cpu.dcache.tags.sampled_refs 1144372 # Sample count of references to valid blocks. 145system.cpu.dcache.tags.tag_accesses 362574732 # Number of tag accesses 146system.cpu.dcache.tags.tagsinuse 4071.496497 # Cycle average of tags in use 147system.cpu.dcache.tags.total_refs 179138118 # Total number of references to valid blocks. 148system.cpu.dcache.tags.warmup_cycle 4941909250 # Cycle when the warmup percentage was hit. 149system.cpu.dcache.writebacks::writebacks 1068741 # number of writebacks 150system.cpu.dcache.writebacks::total 1068741 # number of writebacks 151system.cpu.discardedOps 18127434 # Number of ops (including micro ops) which were discarded before commit 152system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 153system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 154system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 155system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 156system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 157system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 158system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 159system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 160system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 161system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 162system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 163system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 164system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 165system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 166system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 167system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 168system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 169system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 170system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 171system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 172system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 173system.cpu.dtb.accesses 0 # DTB accesses 174system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 175system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 176system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 177system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 178system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 179system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 180system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 181system.cpu.dtb.hits 0 # DTB hits 182system.cpu.dtb.inst_accesses 0 # ITB inst accesses 183system.cpu.dtb.inst_hits 0 # ITB inst hits 184system.cpu.dtb.inst_misses 0 # ITB inst misses 185system.cpu.dtb.misses 0 # DTB misses 186system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 187system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 188system.cpu.dtb.read_accesses 0 # DTB read accesses 189system.cpu.dtb.read_hits 0 # DTB read hits 190system.cpu.dtb.read_misses 0 # DTB read misses 191system.cpu.dtb.write_accesses 0 # DTB write accesses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.icache.ReadReq_accesses::cpu.inst 204480200 # number of ReadReq accesses(hits+misses) 195system.cpu.icache.ReadReq_accesses::total 204480200 # number of ReadReq accesses(hits+misses) 196system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23608.753898 # average ReadReq miss latency 197system.cpu.icache.ReadReq_avg_miss_latency::total 23608.753898 # average ReadReq miss latency 198system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.715773 # average ReadReq mshr miss latency 199system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.715773 # average ReadReq mshr miss latency 200system.cpu.icache.ReadReq_hits::cpu.inst 204459741 # number of ReadReq hits 201system.cpu.icache.ReadReq_hits::total 204459741 # number of ReadReq hits 202system.cpu.icache.ReadReq_miss_latency::cpu.inst 483011496 # number of ReadReq miss cycles 203system.cpu.icache.ReadReq_miss_latency::total 483011496 # number of ReadReq miss cycles 204system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses 205system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses 206system.cpu.icache.ReadReq_misses::cpu.inst 20459 # number of ReadReq misses 207system.cpu.icache.ReadReq_misses::total 20459 # number of ReadReq misses 208system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440701504 # number of ReadReq MSHR miss cycles 209system.cpu.icache.ReadReq_mshr_miss_latency::total 440701504 # number of ReadReq MSHR miss cycles 210system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for ReadReq accesses 211system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000100 # mshr miss rate for ReadReq accesses 212system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20459 # number of ReadReq MSHR misses 213system.cpu.icache.ReadReq_mshr_misses::total 20459 # number of ReadReq MSHR misses 214system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 215system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 216system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 217system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 218system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 219system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 220system.cpu.icache.cache_copies 0 # number of cache copies performed 221system.cpu.icache.demand_accesses::cpu.inst 204480200 # number of demand (read+write) accesses 222system.cpu.icache.demand_accesses::total 204480200 # number of demand (read+write) accesses 223system.cpu.icache.demand_avg_miss_latency::cpu.inst 23608.753898 # average overall miss latency 224system.cpu.icache.demand_avg_miss_latency::total 23608.753898 # average overall miss latency 225system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.715773 # average overall mshr miss latency 226system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.715773 # average overall mshr miss latency 227system.cpu.icache.demand_hits::cpu.inst 204459741 # number of demand (read+write) hits 228system.cpu.icache.demand_hits::total 204459741 # number of demand (read+write) hits 229system.cpu.icache.demand_miss_latency::cpu.inst 483011496 # number of demand (read+write) miss cycles 230system.cpu.icache.demand_miss_latency::total 483011496 # number of demand (read+write) miss cycles 231system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses 232system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses 233system.cpu.icache.demand_misses::cpu.inst 20459 # number of demand (read+write) misses 234system.cpu.icache.demand_misses::total 20459 # number of demand (read+write) misses 235system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440701504 # number of demand (read+write) MSHR miss cycles 236system.cpu.icache.demand_mshr_miss_latency::total 440701504 # number of demand (read+write) MSHR miss cycles 237system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for demand accesses 238system.cpu.icache.demand_mshr_miss_rate::total 0.000100 # mshr miss rate for demand accesses 239system.cpu.icache.demand_mshr_misses::cpu.inst 20459 # number of demand (read+write) MSHR misses 240system.cpu.icache.demand_mshr_misses::total 20459 # number of demand (read+write) MSHR misses 241system.cpu.icache.fast_writes 0 # number of fast writes performed 242system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 243system.cpu.icache.overall_accesses::cpu.inst 204480200 # number of overall (read+write) accesses 244system.cpu.icache.overall_accesses::total 204480200 # number of overall (read+write) accesses 245system.cpu.icache.overall_avg_miss_latency::cpu.inst 23608.753898 # average overall miss latency 246system.cpu.icache.overall_avg_miss_latency::total 23608.753898 # average overall miss latency 247system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.715773 # average overall mshr miss latency 248system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.715773 # average overall mshr miss latency 249system.cpu.icache.overall_hits::cpu.inst 204459741 # number of overall hits 250system.cpu.icache.overall_hits::total 204459741 # number of overall hits 251system.cpu.icache.overall_miss_latency::cpu.inst 483011496 # number of overall miss cycles 252system.cpu.icache.overall_miss_latency::total 483011496 # number of overall miss cycles 253system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses 254system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses 255system.cpu.icache.overall_misses::cpu.inst 20459 # number of overall misses 256system.cpu.icache.overall_misses::total 20459 # number of overall misses 257system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440701504 # number of overall MSHR miss cycles 258system.cpu.icache.overall_mshr_miss_latency::total 440701504 # number of overall MSHR miss cycles 259system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for overall accesses 260system.cpu.icache.overall_mshr_miss_rate::total 0.000100 # mshr miss rate for overall accesses 261system.cpu.icache.overall_mshr_misses::cpu.inst 20459 # number of overall MSHR misses 262system.cpu.icache.overall_mshr_misses::total 20459 # number of overall MSHR misses 263system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 264system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id 265system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 266system.cpu.icache.tags.age_task_id_blocks_1024::3 315 # Occupied blocks per task id 267system.cpu.icache.tags.age_task_id_blocks_1024::4 1399 # Occupied blocks per task id 268system.cpu.icache.tags.avg_refs 9993.633169 # Average number of references to valid blocks. 269system.cpu.icache.tags.data_accesses 408980859 # Number of data accesses 270system.cpu.icache.tags.occ_blocks::cpu.inst 1204.301311 # Average occupied blocks per requestor 271system.cpu.icache.tags.occ_percent::cpu.inst 0.588038 # Average percentage of cache occupancy 272system.cpu.icache.tags.occ_percent::total 0.588038 # Average percentage of cache occupancy 273system.cpu.icache.tags.occ_task_id_blocks::1024 1881 # Occupied blocks per task id 274system.cpu.icache.tags.occ_task_id_percent::1024 0.918457 # Percentage of cache occupancy per task id 275system.cpu.icache.tags.replacements 18578 # number of replacements 276system.cpu.icache.tags.sampled_refs 20459 # Sample count of references to valid blocks. 277system.cpu.icache.tags.tag_accesses 408980859 # Number of tag accesses 278system.cpu.icache.tags.tagsinuse 1204.301311 # Cycle average of tags in use 279system.cpu.icache.tags.total_refs 204459741 # Total number of references to valid blocks. 280system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 281system.cpu.idleCycles 36857312 # Total number of cycles that the CPU has spent unscheduled due to idling 282system.cpu.ipc 0.670351 # IPC: instructions per cycle 283system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 284system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 285system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 286system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 287system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 288system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 289system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 290system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 291system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 292system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 294system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 295system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 296system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 298system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 299system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 300system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 301system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 302system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 303system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 304system.cpu.itb.accesses 0 # DTB accesses 305system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 306system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 307system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 308system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 309system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 310system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 311system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 312system.cpu.itb.hits 0 # DTB hits 313system.cpu.itb.inst_accesses 0 # ITB inst accesses 314system.cpu.itb.inst_hits 0 # ITB inst hits 315system.cpu.itb.inst_misses 0 # ITB inst misses 316system.cpu.itb.misses 0 # DTB misses 317system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 318system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 319system.cpu.itb.read_accesses 0 # DTB read accesses 320system.cpu.itb.read_hits 0 # DTB read hits 321system.cpu.itb.read_misses 0 # DTB read misses 322system.cpu.itb.write_accesses 0 # DTB write accesses 323system.cpu.itb.write_hits 0 # DTB write hits 324system.cpu.itb.write_misses 0 # DTB write misses 325system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356556 # number of ReadExReq accesses(hits+misses) 326system.cpu.l2cache.ReadExReq_accesses::total 356556 # number of ReadExReq accesses(hits+misses) 327system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70944.376455 # average ReadExReq miss latency 328system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70944.376455 # average ReadExReq miss latency 329system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58283.052569 # average ReadExReq mshr miss latency 330system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58283.052569 # average ReadExReq mshr miss latency 331system.cpu.l2cache.ReadExReq_hits::cpu.inst 255641 # number of ReadExReq hits 332system.cpu.l2cache.ReadExReq_hits::total 255641 # number of ReadExReq hits 333system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7159351750 # number of ReadExReq miss cycles 334system.cpu.l2cache.ReadExReq_miss_latency::total 7159351750 # number of ReadExReq miss cycles 335system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283027 # miss rate for ReadExReq accesses 336system.cpu.l2cache.ReadExReq_miss_rate::total 0.283027 # miss rate for ReadExReq accesses 337system.cpu.l2cache.ReadExReq_misses::cpu.inst 100915 # number of ReadExReq misses 338system.cpu.l2cache.ReadExReq_misses::total 100915 # number of ReadExReq misses 339system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5881634250 # number of ReadExReq MSHR miss cycles 340system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5881634250 # number of ReadExReq MSHR miss cycles 341system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283027 # mshr miss rate for ReadExReq accesses 342system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283027 # mshr miss rate for ReadExReq accesses 343system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100915 # number of ReadExReq MSHR misses 344system.cpu.l2cache.ReadExReq_mshr_misses::total 100915 # number of ReadExReq MSHR misses 345system.cpu.l2cache.ReadReq_accesses::cpu.inst 808275 # number of ReadReq accesses(hits+misses) 346system.cpu.l2cache.ReadReq_accesses::total 808275 # number of ReadReq accesses(hits+misses) 347system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74397.741148 # average ReadReq miss latency 348system.cpu.l2cache.ReadReq_avg_miss_latency::total 74397.741148 # average ReadReq miss latency 349system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61739.381683 # average ReadReq mshr miss latency 350system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61739.381683 # average ReadReq mshr miss latency 351system.cpu.l2cache.ReadReq_hits::cpu.inst 764868 # number of ReadReq hits 352system.cpu.l2cache.ReadReq_hits::total 764868 # number of ReadReq hits 353system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3229382750 # number of ReadReq miss cycles 354system.cpu.l2cache.ReadReq_miss_latency::total 3229382750 # number of ReadReq miss cycles 355system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053703 # miss rate for ReadReq accesses 356system.cpu.l2cache.ReadReq_miss_rate::total 0.053703 # miss rate for ReadReq accesses 357system.cpu.l2cache.ReadReq_misses::cpu.inst 43407 # number of ReadReq misses 358system.cpu.l2cache.ReadReq_misses::total 43407 # number of ReadReq misses 359system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits 360system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits 361system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2678995250 # number of ReadReq MSHR miss cycles 362system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2678995250 # number of ReadReq MSHR miss cycles 363system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053685 # mshr miss rate for ReadReq accesses 364system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053685 # mshr miss rate for ReadReq accesses 365system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43392 # number of ReadReq MSHR misses 366system.cpu.l2cache.ReadReq_mshr_misses::total 43392 # number of ReadReq MSHR misses 367system.cpu.l2cache.Writeback_accesses::writebacks 1068741 # number of Writeback accesses(hits+misses) 368system.cpu.l2cache.Writeback_accesses::total 1068741 # number of Writeback accesses(hits+misses) 369system.cpu.l2cache.Writeback_hits::writebacks 1068741 # number of Writeback hits 370system.cpu.l2cache.Writeback_hits::total 1068741 # number of Writeback hits 371system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 372system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 373system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 375system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 376system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 377system.cpu.l2cache.cache_copies 0 # number of cache copies performed 378system.cpu.l2cache.demand_accesses::cpu.inst 1164831 # number of demand (read+write) accesses 379system.cpu.l2cache.demand_accesses::total 1164831 # number of demand (read+write) accesses 380system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71983.027536 # average overall miss latency 381system.cpu.l2cache.demand_avg_miss_latency::total 71983.027536 # average overall miss latency 382system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59322.344030 # average overall mshr miss latency 383system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59322.344030 # average overall mshr miss latency 384system.cpu.l2cache.demand_hits::cpu.inst 1020509 # number of demand (read+write) hits 385system.cpu.l2cache.demand_hits::total 1020509 # number of demand (read+write) hits 386system.cpu.l2cache.demand_miss_latency::cpu.inst 10388734500 # number of demand (read+write) miss cycles 387system.cpu.l2cache.demand_miss_latency::total 10388734500 # number of demand (read+write) miss cycles 388system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123900 # miss rate for demand accesses 389system.cpu.l2cache.demand_miss_rate::total 0.123900 # miss rate for demand accesses 390system.cpu.l2cache.demand_misses::cpu.inst 144322 # number of demand (read+write) misses 391system.cpu.l2cache.demand_misses::total 144322 # number of demand (read+write) misses 392system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits 393system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 394system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8560629500 # number of demand (read+write) MSHR miss cycles 395system.cpu.l2cache.demand_mshr_miss_latency::total 8560629500 # number of demand (read+write) MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123887 # mshr miss rate for demand accesses 397system.cpu.l2cache.demand_mshr_miss_rate::total 0.123887 # mshr miss rate for demand accesses 398system.cpu.l2cache.demand_mshr_misses::cpu.inst 144307 # number of demand (read+write) MSHR misses 399system.cpu.l2cache.demand_mshr_misses::total 144307 # number of demand (read+write) MSHR misses 400system.cpu.l2cache.fast_writes 0 # number of fast writes performed 401system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 402system.cpu.l2cache.overall_accesses::cpu.inst 1164831 # number of overall (read+write) accesses 403system.cpu.l2cache.overall_accesses::total 1164831 # number of overall (read+write) accesses 404system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71983.027536 # average overall miss latency 405system.cpu.l2cache.overall_avg_miss_latency::total 71983.027536 # average overall miss latency 406system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59322.344030 # average overall mshr miss latency 407system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59322.344030 # average overall mshr miss latency 408system.cpu.l2cache.overall_hits::cpu.inst 1020509 # number of overall hits 409system.cpu.l2cache.overall_hits::total 1020509 # number of overall hits 410system.cpu.l2cache.overall_miss_latency::cpu.inst 10388734500 # number of overall miss cycles 411system.cpu.l2cache.overall_miss_latency::total 10388734500 # number of overall miss cycles 412system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123900 # miss rate for overall accesses 413system.cpu.l2cache.overall_miss_rate::total 0.123900 # miss rate for overall accesses 414system.cpu.l2cache.overall_misses::cpu.inst 144322 # number of overall misses 415system.cpu.l2cache.overall_misses::total 144322 # number of overall misses 416system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits 417system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits 418system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8560629500 # number of overall MSHR miss cycles 419system.cpu.l2cache.overall_mshr_miss_latency::total 8560629500 # number of overall MSHR miss cycles 420system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123887 # mshr miss rate for overall accesses 421system.cpu.l2cache.overall_mshr_miss_rate::total 0.123887 # mshr miss rate for overall accesses 422system.cpu.l2cache.overall_mshr_misses::cpu.inst 144307 # number of overall MSHR misses 423system.cpu.l2cache.overall_mshr_misses::total 144307 # number of overall MSHR misses 424system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 425system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id 426system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4944 # Occupied blocks per task id 427system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id 428system.cpu.l2cache.tags.avg_refs 11.811039 # Average number of references to valid blocks. 429system.cpu.l2cache.tags.data_accesses 18367876 # Number of data accesses 430system.cpu.l2cache.tags.occ_blocks::writebacks 23534.473696 # Average occupied blocks per requestor 431system.cpu.l2cache.tags.occ_blocks::cpu.inst 4154.581244 # Average occupied blocks per requestor 432system.cpu.l2cache.tags.occ_percent::writebacks 0.718215 # Average percentage of cache occupancy 433system.cpu.l2cache.tags.occ_percent::cpu.inst 0.126788 # Average percentage of cache occupancy 434system.cpu.l2cache.tags.occ_percent::total 0.845003 # Average percentage of cache occupancy 435system.cpu.l2cache.tags.occ_task_id_blocks::1024 31193 # Occupied blocks per task id 436system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951935 # Percentage of cache occupancy per task id 437system.cpu.l2cache.tags.replacements 111551 # number of replacements 438system.cpu.l2cache.tags.sampled_refs 142744 # Sample count of references to valid blocks. 439system.cpu.l2cache.tags.tag_accesses 18367876 # Number of tag accesses 440system.cpu.l2cache.tags.tagsinuse 27689.054939 # Cycle average of tags in use 441system.cpu.l2cache.tags.total_refs 1685955 # Total number of references to valid blocks. 442system.cpu.l2cache.tags.warmup_cycle 168523988500 # Cycle when the warmup percentage was hit. 443system.cpu.l2cache.writebacks::writebacks 96655 # number of writebacks 444system.cpu.l2cache.writebacks::total 96655 # number of writebacks 445system.cpu.numCycles 755696647 # number of cpu cycles simulated 446system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 447system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 448system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 449system.cpu.tickCycles 718839335 # Number of cycles that the CPU actually ticked 450system.cpu.toL2Bus.data_through_bus 142948608 # Total data (bytes) 451system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40918 # Packet count per connected master and slave (bytes) 452system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3357485 # Packet count per connected master and slave (bytes) 453system.cpu.toL2Bus.pkt_count::total 3398403 # Packet count per connected master and slave (bytes) 454system.cpu.toL2Bus.reqLayer0.occupancy 2185527000 # Layer occupancy (ticks) 455system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 456system.cpu.toL2Bus.respLayer0.occupancy 31384496 # Layer occupancy (ticks) 457system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 458system.cpu.toL2Bus.respLayer1.occupancy 1745291987 # Layer occupancy (ticks) 459system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 460system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 461system.cpu.toL2Bus.throughput 378322727 # Throughput (bytes/s) 462system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1309376 # Cumulative packet size per connected master and slave (bytes) 463system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141639232 # Cumulative packet size per connected master and slave (bytes) 464system.cpu.toL2Bus.tot_pkt_size::total 142948608 # Cumulative packet size per connected master and slave (bytes) 465system.cpu.toL2Bus.trans_dist::ReadReq 808275 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadResp 808275 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::Writeback 1068741 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExReq 356556 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadExResp 356556 # Transaction distribution 470system.cpu.workload.num_syscalls 548 # Number of system calls 471system.cpu_clk_domain.clock 500 # Clock period in ticks 472system.membus.data_through_bus 15421568 # Total data (bytes) 473system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 385269 # Packet count per connected master and slave (bytes) 474system.membus.pkt_count::total 385269 # Packet count per connected master and slave (bytes) 475system.membus.reqLayer0.occupancy 1076098500 # Layer occupancy (ticks) 476system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 477system.membus.respLayer1.occupancy 1364495500 # Layer occupancy (ticks) 478system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 479system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 480system.membus.throughput 40814176 # Throughput (bytes/s) 481system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15421568 # Cumulative packet size per connected master and slave (bytes) 482system.membus.tot_pkt_size::total 15421568 # Cumulative packet size per connected master and slave (bytes) 483system.membus.trans_dist::ReadReq 43392 # Transaction distribution 484system.membus.trans_dist::ReadResp 43392 # Transaction distribution 485system.membus.trans_dist::Writeback 96655 # Transaction distribution 486system.membus.trans_dist::ReadExReq 100915 # Transaction distribution 487system.membus.trans_dist::ReadExResp 100915 # Transaction distribution 488system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 489system.physmem.avgGap 1568082.50 # Average gap between requests 490system.physmem.avgMemAccLat 29316.89 # Average memory access latency per DRAM burst 491system.physmem.avgQLat 10566.89 # Average queueing delay per DRAM burst 492system.physmem.avgRdBW 24.43 # Average DRAM read bandwidth in MiByte/s 493system.physmem.avgRdBWSys 24.44 # Average system read bandwidth in MiByte/s 494system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 495system.physmem.avgWrBW 16.37 # Average achieved write bandwidth in MiByte/s 496system.physmem.avgWrBWSys 16.37 # Average system write bandwidth in MiByte/s 497system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing 498system.physmem.busUtil 0.32 # Data bus utilization in percentage 499system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads 500system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 501system.physmem.bw_inst_read::cpu.inst 599436 # Instruction read bandwidth from this memory (bytes/s) 502system.physmem.bw_inst_read::total 599436 # Instruction read bandwidth from this memory (bytes/s) 503system.physmem.bw_read::cpu.inst 24442739 # Total read bandwidth from this memory (bytes/s) 504system.physmem.bw_read::total 24442739 # Total read bandwidth from this memory (bytes/s) 505system.physmem.bw_total::writebacks 16371437 # Total bandwidth to/from this memory (bytes/s) 506system.physmem.bw_total::cpu.inst 24442739 # Total bandwidth to/from this memory (bytes/s) 507system.physmem.bw_total::total 40814176 # Total bandwidth to/from this memory (bytes/s) 508system.physmem.bw_write::writebacks 16371437 # Write bandwidth from this memory (bytes/s) 509system.physmem.bw_write::total 16371437 # Write bandwidth from this memory (bytes/s) 510system.physmem.bytesPerActivate::samples 65344 # Bytes accessed per row activation 511system.physmem.bytesPerActivate::mean 235.879530 # Bytes accessed per row activation 512system.physmem.bytesPerActivate::gmean 156.532408 # Bytes accessed per row activation 513system.physmem.bytesPerActivate::stdev 241.691059 # Bytes accessed per row activation 514system.physmem.bytesPerActivate::0-127 24749 37.87% 37.87% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::128-255 18254 27.94% 65.81% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::256-383 7150 10.94% 76.75% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::384-511 7883 12.06% 88.82% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::512-639 2042 3.12% 91.94% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::640-767 1102 1.69% 93.63% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::768-895 756 1.16% 94.78% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::896-1023 612 0.94% 95.72% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::1024-1151 2796 4.28% 100.00% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::total 65344 # Bytes accessed per row activation 524system.physmem.bytesReadDRAM 9229248 # Total number of bytes read from DRAM 525system.physmem.bytesReadSys 9235648 # Total read bytes from the system interface side 526system.physmem.bytesReadWrQ 6400 # Total number of bytes read from write queue 527system.physmem.bytesWritten 6184768 # Total number of bytes written to DRAM 528system.physmem.bytesWrittenSys 6185920 # Total written bytes from the system interface side 529system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory 530system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory 531system.physmem.bytes_read::cpu.inst 9235648 # Number of bytes read from this memory 532system.physmem.bytes_read::total 9235648 # Number of bytes read from this memory 533system.physmem.bytes_written::writebacks 6185920 # Number of bytes written to this memory 534system.physmem.bytes_written::total 6185920 # Number of bytes written to this memory 535system.physmem.memoryStateTime::IDLE 265986637250 # Time in different power states 536system.physmem.memoryStateTime::REF 12617020000 # Time in different power states 537system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 538system.physmem.memoryStateTime::ACT 99239970250 # Time in different power states 539system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 16system.physmem.bytes_read::cpu.inst 9220736 # Number of bytes read from this memory 17system.physmem.bytes_read::total 9220736 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 6177024 # Number of bytes written to this memory 21system.physmem.bytes_written::total 6177024 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 144074 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 144074 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 96516 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 96516 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 25483894 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 25483894 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 612007 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 612007 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 17071807 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 17071807 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 17071807 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 25483894 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 42555702 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 144074 # Number of read requests accepted 36system.physmem.writeReqs 96516 # Number of write requests accepted 37system.physmem.readBursts 144074 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 96516 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 9213952 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue 41system.physmem.bytesWritten 6175488 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 9220736 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 6177024 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue |
| 540system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 541system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 47system.physmem.perBankRdBursts::0 9331 # Per bank write bursts 48system.physmem.perBankRdBursts::1 8974 # Per bank write bursts 49system.physmem.perBankRdBursts::2 8995 # Per bank write bursts 50system.physmem.perBankRdBursts::3 8704 # Per bank write bursts 51system.physmem.perBankRdBursts::4 9445 # Per bank write bursts 52system.physmem.perBankRdBursts::5 9338 # Per bank write bursts 53system.physmem.perBankRdBursts::6 8941 # Per bank write bursts 54system.physmem.perBankRdBursts::7 8096 # Per bank write bursts 55system.physmem.perBankRdBursts::8 8562 # Per bank write bursts 56system.physmem.perBankRdBursts::9 8674 # Per bank write bursts 57system.physmem.perBankRdBursts::10 8773 # Per bank write bursts 58system.physmem.perBankRdBursts::11 9481 # Per bank write bursts 59system.physmem.perBankRdBursts::12 9368 # Per bank write bursts 60system.physmem.perBankRdBursts::13 9509 # Per bank write bursts 61system.physmem.perBankRdBursts::14 8709 # Per bank write bursts 62system.physmem.perBankRdBursts::15 9068 # Per bank write bursts 63system.physmem.perBankWrBursts::0 6188 # Per bank write bursts 64system.physmem.perBankWrBursts::1 6094 # Per bank write bursts 65system.physmem.perBankWrBursts::2 6004 # Per bank write bursts 66system.physmem.perBankWrBursts::3 5817 # Per bank write bursts 67system.physmem.perBankWrBursts::4 6158 # Per bank write bursts 68system.physmem.perBankWrBursts::5 6168 # Per bank write bursts 69system.physmem.perBankWrBursts::6 6012 # Per bank write bursts 70system.physmem.perBankWrBursts::7 5489 # Per bank write bursts 71system.physmem.perBankWrBursts::8 5725 # Per bank write bursts 72system.physmem.perBankWrBursts::9 5819 # Per bank write bursts 73system.physmem.perBankWrBursts::10 5961 # Per bank write bursts 74system.physmem.perBankWrBursts::11 6448 # Per bank write bursts 75system.physmem.perBankWrBursts::12 6304 # Per bank write bursts 76system.physmem.perBankWrBursts::13 6266 # Per bank write bursts 77system.physmem.perBankWrBursts::14 5996 # Per bank write bursts 78system.physmem.perBankWrBursts::15 6043 # Per bank write bursts |
|
| 542system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 543system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 544system.physmem.num_reads::cpu.inst 144307 # Number of read requests responded to by this memory 545system.physmem.num_reads::total 144307 # Number of read requests responded to by this memory 546system.physmem.num_writes::writebacks 96655 # Number of write requests responded to by this memory 547system.physmem.num_writes::total 96655 # Number of write requests responded to by this memory 548system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined 549system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 550system.physmem.perBankRdBursts::0 9328 # Per bank write bursts 551system.physmem.perBankRdBursts::1 8986 # Per bank write bursts 552system.physmem.perBankRdBursts::2 9010 # Per bank write bursts 553system.physmem.perBankRdBursts::3 8718 # Per bank write bursts 554system.physmem.perBankRdBursts::4 9475 # Per bank write bursts 555system.physmem.perBankRdBursts::5 9358 # Per bank write bursts 556system.physmem.perBankRdBursts::6 8951 # Per bank write bursts 557system.physmem.perBankRdBursts::7 8100 # Per bank write bursts 558system.physmem.perBankRdBursts::8 8572 # Per bank write bursts 559system.physmem.perBankRdBursts::9 8669 # Per bank write bursts 560system.physmem.perBankRdBursts::10 8784 # Per bank write bursts 561system.physmem.perBankRdBursts::11 9499 # Per bank write bursts 562system.physmem.perBankRdBursts::12 9376 # Per bank write bursts 563system.physmem.perBankRdBursts::13 9538 # Per bank write bursts 564system.physmem.perBankRdBursts::14 8741 # Per bank write bursts 565system.physmem.perBankRdBursts::15 9102 # Per bank write bursts 566system.physmem.perBankWrBursts::0 6202 # Per bank write bursts 567system.physmem.perBankWrBursts::1 6099 # Per bank write bursts 568system.physmem.perBankWrBursts::2 6021 # Per bank write bursts 569system.physmem.perBankWrBursts::3 5821 # Per bank write bursts 570system.physmem.perBankWrBursts::4 6172 # Per bank write bursts 571system.physmem.perBankWrBursts::5 6184 # Per bank write bursts 572system.physmem.perBankWrBursts::6 6018 # Per bank write bursts 573system.physmem.perBankWrBursts::7 5493 # Per bank write bursts 574system.physmem.perBankWrBursts::8 5732 # Per bank write bursts 575system.physmem.perBankWrBursts::9 5815 # Per bank write bursts 576system.physmem.perBankWrBursts::10 5965 # Per bank write bursts 577system.physmem.perBankWrBursts::11 6456 # Per bank write bursts 578system.physmem.perBankWrBursts::12 6307 # Per bank write bursts 579system.physmem.perBankWrBursts::13 6282 # Per bank write bursts 580system.physmem.perBankWrBursts::14 6014 # Per bank write bursts 581system.physmem.perBankWrBursts::15 6056 # Per bank write bursts 582system.physmem.rdPerTurnAround::samples 5563 # Reads before turning the bus around for writes 583system.physmem.rdPerTurnAround::mean 25.922344 # Reads before turning the bus around for writes 584system.physmem.rdPerTurnAround::stdev 382.692234 # Reads before turning the bus around for writes 585system.physmem.rdPerTurnAround::0-1023 5559 99.93% 99.93% # Reads before turning the bus around for writes 586system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes 587system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 588system.physmem.rdPerTurnAround::total 5563 # Reads before turning the bus around for writes 589system.physmem.rdQLenPdf::0 143841 # What read queue length does an incoming req see 590system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see 591system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see | 81system.physmem.totGap 361825986500 # Total gap between requests 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) 88system.physmem.readPktSize::6 144074 # Read request sizes (log2) 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) 95system.physmem.writePktSize::6 96516 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 143606 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see |
| 592system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 593system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 594system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 595system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 596system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 597system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 598system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 599system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 613system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 614system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 615system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 616system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 617system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 618system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 619system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 620system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 621system.physmem.readBursts 144307 # Number of DRAM read bursts, including those serviced by the write queue 622system.physmem.readPktSize::0 0 # Read request sizes (log2) 623system.physmem.readPktSize::1 0 # Read request sizes (log2) 624system.physmem.readPktSize::2 0 # Read request sizes (log2) 625system.physmem.readPktSize::3 0 # Read request sizes (log2) 626system.physmem.readPktSize::4 0 # Read request sizes (log2) 627system.physmem.readPktSize::5 0 # Read request sizes (log2) 628system.physmem.readPktSize::6 144307 # Read request sizes (log2) 629system.physmem.readReqs 144307 # Number of read requests accepted 630system.physmem.readRowHitRate 76.88 # Row buffer hit rate for reads 631system.physmem.readRowHits 110862 # Number of row buffer hits during reads 632system.physmem.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue 633system.physmem.totBusLat 721035000 # Total ticks spent in databus transfers 634system.physmem.totGap 377848294500 # Total gap between requests 635system.physmem.totMemAccLat 4227701250 # Total ticks spent from burst creation until serviced by the DRAM 636system.physmem.totQLat 1523820000 # Total ticks spent queuing 637system.physmem.wrPerTurnAround::samples 5563 # Writes before turning the bus around for reads 638system.physmem.wrPerTurnAround::mean 17.371382 # Writes before turning the bus around for reads 639system.physmem.wrPerTurnAround::gmean 17.273622 # Writes before turning the bus around for reads 640system.physmem.wrPerTurnAround::stdev 2.337365 # Writes before turning the bus around for reads 641system.physmem.wrPerTurnAround::16-17 2499 44.92% 44.92% # Writes before turning the bus around for reads 642system.physmem.wrPerTurnAround::18-19 2925 52.58% 97.50% # Writes before turning the bus around for reads 643system.physmem.wrPerTurnAround::20-21 45 0.81% 98.31% # Writes before turning the bus around for reads 644system.physmem.wrPerTurnAround::22-23 18 0.32% 98.63% # Writes before turning the bus around for reads 645system.physmem.wrPerTurnAround::24-25 19 0.34% 98.98% # Writes before turning the bus around for reads 646system.physmem.wrPerTurnAround::26-27 16 0.29% 99.26% # Writes before turning the bus around for reads 647system.physmem.wrPerTurnAround::28-29 12 0.22% 99.48% # Writes before turning the bus around for reads 648system.physmem.wrPerTurnAround::30-31 7 0.13% 99.60% # Writes before turning the bus around for reads 649system.physmem.wrPerTurnAround::32-33 2 0.04% 99.64% # Writes before turning the bus around for reads 650system.physmem.wrPerTurnAround::34-35 3 0.05% 99.69% # Writes before turning the bus around for reads 651system.physmem.wrPerTurnAround::36-37 1 0.02% 99.71% # Writes before turning the bus around for reads 652system.physmem.wrPerTurnAround::38-39 4 0.07% 99.78% # Writes before turning the bus around for reads 653system.physmem.wrPerTurnAround::40-41 4 0.07% 99.86% # Writes before turning the bus around for reads 654system.physmem.wrPerTurnAround::42-43 2 0.04% 99.89% # Writes before turning the bus around for reads 655system.physmem.wrPerTurnAround::46-47 1 0.02% 99.91% # Writes before turning the bus around for reads 656system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads 657system.physmem.wrPerTurnAround::52-53 1 0.02% 99.95% # Writes before turning the bus around for reads 658system.physmem.wrPerTurnAround::70-71 2 0.04% 99.98% # Writes before turning the bus around for reads 659system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads 660system.physmem.wrPerTurnAround::total 5563 # Writes before turning the bus around for reads | |
| 661system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 662system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 663system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 664system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 665system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 666system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 667system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 668system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 669system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 670system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 671system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 672system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 673system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 674system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 675system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 128system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 676system.physmem.wrQLenPdf::15 3052 # What write queue length does an incoming req see 677system.physmem.wrQLenPdf::16 3240 # What write queue length does an incoming req see 678system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see 679system.physmem.wrQLenPdf::18 5663 # What write queue length does an incoming req see 680system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see 681system.physmem.wrQLenPdf::20 5657 # What write queue length does an incoming req see 682system.physmem.wrQLenPdf::21 5657 # What write queue length does an incoming req see 683system.physmem.wrQLenPdf::22 5655 # What write queue length does an incoming req see 684system.physmem.wrQLenPdf::23 5664 # What write queue length does an incoming req see 685system.physmem.wrQLenPdf::24 5680 # What write queue length does an incoming req see 686system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see 687system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see 688system.physmem.wrQLenPdf::27 5707 # What write queue length does an incoming req see 689system.physmem.wrQLenPdf::28 5632 # What write queue length does an incoming req see 690system.physmem.wrQLenPdf::29 5620 # What write queue length does an incoming req see 691system.physmem.wrQLenPdf::30 5645 # What write queue length does an incoming req see 692system.physmem.wrQLenPdf::31 5589 # What write queue length does an incoming req see 693system.physmem.wrQLenPdf::32 5570 # What write queue length does an incoming req see 694system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see 695system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see 696system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see 697system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 3132 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 5676 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 5658 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 5671 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 5685 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 5655 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 5675 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 5648 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 5690 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 5726 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 5661 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 5632 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see |
| 698system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see | 165system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see |
| 699system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see 700system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see | 166system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see |
| 701system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 702system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see | 168system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see |
| 703system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see | 170system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see |
| 704system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see | 171system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see |
| 705system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see | 172system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see |
| 706system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 707system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 708system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 709system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 710system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 711system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 712system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 713system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 714system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 715system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 716system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 717system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 718system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 719system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 720system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 721system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 722system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 723system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 724system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 173system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 725system.physmem.writeBursts 96655 # Number of DRAM write bursts, including those merged in the write queue 726system.physmem.writePktSize::0 0 # Write request sizes (log2) 727system.physmem.writePktSize::1 0 # Write request sizes (log2) 728system.physmem.writePktSize::2 0 # Write request sizes (log2) 729system.physmem.writePktSize::3 0 # Write request sizes (log2) 730system.physmem.writePktSize::4 0 # Write request sizes (log2) 731system.physmem.writePktSize::5 0 # Write request sizes (log2) 732system.physmem.writePktSize::6 96655 # Write request sizes (log2) 733system.physmem.writeReqs 96655 # Number of write requests accepted 734system.physmem.writeRowHitRate 66.87 # Row buffer hit rate for writes 735system.physmem.writeRowHits 64630 # Number of row buffer hits during writes 736system.voltage_domain.voltage 1 # Voltage in Volts | 192system.physmem.bytesPerActivate::samples 64715 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 237.790435 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 157.392081 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 243.201287 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 24444 37.77% 37.77% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 18161 28.06% 65.83% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 6768 10.46% 76.29% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 7845 12.12% 88.42% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 2212 3.42% 91.83% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1114 1.72% 93.55% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 793 1.23% 94.78% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 596 0.92% 95.70% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 2782 4.30% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 64715 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 25.855065 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 382.360630 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 5564 99.93% 99.93% # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes 213system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads 214system.physmem.wrPerTurnAround::mean 17.329741 # Writes before turning the bus around for reads 215system.physmem.wrPerTurnAround::gmean 17.226111 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::stdev 2.490816 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::16-17 2624 47.13% 47.13% # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::18-19 2801 50.31% 97.43% # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::20-21 48 0.86% 98.29% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::22-23 25 0.45% 98.74% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::24-25 21 0.38% 99.12% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::26-27 12 0.22% 99.34% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::28-29 8 0.14% 99.48% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::30-31 6 0.11% 99.59% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::32-33 3 0.05% 99.64% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::34-35 4 0.07% 99.71% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::36-37 1 0.02% 99.73% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::38-39 5 0.09% 99.82% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::50-51 1 0.02% 99.87% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::52-53 1 0.02% 99.89% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-57 1 0.02% 99.91% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::58-59 1 0.02% 99.93% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::68-69 2 0.04% 99.96% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads 238system.physmem.totQLat 1536727500 # Total ticks spent queuing 239system.physmem.totMemAccLat 4236127500 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 719840000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 243system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 25.47 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 0.33 # Data bus utilization in percentage 250system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing 254system.physmem.readRowHits 111270 # Number of row buffer hits during reads 255system.physmem.writeRowHits 64468 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 77.29 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes 258system.physmem.avgGap 1503911.16 # Average gap between requests 259system.physmem.pageHitRate 73.08 # Row buffer hit rate, read and write combined 260system.physmem.memoryStateTime::IDLE 254085865250 # Time in different power states 261system.physmem.memoryStateTime::REF 12081940000 # Time in different power states 262system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 263system.physmem.memoryStateTime::ACT 95653103250 # Time in different power states 264system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 265system.membus.throughput 42555702 # Throughput (bytes/s) 266system.membus.trans_dist::ReadReq 43212 # Transaction distribution 267system.membus.trans_dist::ReadResp 43212 # Transaction distribution 268system.membus.trans_dist::Writeback 96516 # Transaction distribution 269system.membus.trans_dist::ReadExReq 100862 # Transaction distribution 270system.membus.trans_dist::ReadExResp 100862 # Transaction distribution 271system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384664 # Packet count per connected master and slave (bytes) 272system.membus.pkt_count::total 384664 # Packet count per connected master and slave (bytes) 273system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15397760 # Cumulative packet size per connected master and slave (bytes) 274system.membus.tot_pkt_size::total 15397760 # Cumulative packet size per connected master and slave (bytes) 275system.membus.data_through_bus 15397760 # Total data (bytes) 276system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 277system.membus.reqLayer0.occupancy 1075054000 # Layer occupancy (ticks) 278system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 279system.membus.respLayer1.occupancy 1362559750 # Layer occupancy (ticks) 280system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 281system.cpu_clk_domain.clock 500 # Clock period in ticks 282system.cpu.branchPred.lookups 132256489 # Number of BP lookups 283system.cpu.branchPred.condPredicted 98266035 # Number of conditional branches predicted 284system.cpu.branchPred.condIncorrect 6550672 # Number of conditional branches incorrect 285system.cpu.branchPred.BTBLookups 68852239 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 64692489 # Number of BTB hits 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 288system.cpu.branchPred.BTBHitPct 93.958439 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 9992276 # Number of times the RAS was used to get a target. 290system.cpu.branchPred.RASInCorrect 17882 # Number of incorrect RAS predictions. 291system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 292system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 293system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 294system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 295system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 296system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 297system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 298system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 299system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 300system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 301system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 302system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 303system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 304system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 305system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 306system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 307system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 308system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 309system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 310system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 311system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 312system.cpu.dtb.inst_hits 0 # ITB inst hits 313system.cpu.dtb.inst_misses 0 # ITB inst misses 314system.cpu.dtb.read_hits 0 # DTB read hits 315system.cpu.dtb.read_misses 0 # DTB read misses 316system.cpu.dtb.write_hits 0 # DTB write hits 317system.cpu.dtb.write_misses 0 # DTB write misses 318system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 319system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 320system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 321system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 322system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 323system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 324system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 325system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dtb.read_accesses 0 # DTB read accesses 328system.cpu.dtb.write_accesses 0 # DTB write accesses 329system.cpu.dtb.inst_accesses 0 # ITB inst accesses 330system.cpu.dtb.hits 0 # DTB hits 331system.cpu.dtb.misses 0 # DTB misses 332system.cpu.dtb.accesses 0 # DTB accesses 333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 354system.cpu.itb.inst_hits 0 # ITB inst hits 355system.cpu.itb.inst_misses 0 # ITB inst misses 356system.cpu.itb.read_hits 0 # DTB read hits 357system.cpu.itb.read_misses 0 # DTB read misses 358system.cpu.itb.write_hits 0 # DTB write hits 359system.cpu.itb.write_misses 0 # DTB write misses 360system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 361system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 362system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 363system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 364system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 365system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 366system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 367system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.itb.read_accesses 0 # DTB read accesses 370system.cpu.itb.write_accesses 0 # DTB write accesses 371system.cpu.itb.inst_accesses 0 # ITB inst accesses 372system.cpu.itb.hits 0 # DTB hits 373system.cpu.itb.misses 0 # DTB misses 374system.cpu.itb.accesses 0 # DTB accesses 375system.cpu.workload.num_syscalls 548 # Number of system calls 376system.cpu.numCycles 723652031 # number of cpu cycles simulated 377system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 378system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 379system.cpu.committedInsts 506582155 # Number of instructions committed 380system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed 381system.cpu.discardedOps 14122871 # Number of ops (including micro ops) which were discarded before commit 382system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 383system.cpu.cpi 1.428499 # CPI: cycles per instruction 384system.cpu.ipc 0.700036 # IPC: instructions per cycle 385system.cpu.tickCycles 687771211 # Number of cycles that the object actually ticked 386system.cpu.idleCycles 35880820 # Total number of cycles that the object has spent stopped 387system.cpu.icache.tags.replacements 17660 # number of replacements 388system.cpu.icache.tags.tagsinuse 1187.686040 # Cycle average of tags in use 389system.cpu.icache.tags.total_refs 200323378 # Total number of references to valid blocks. 390system.cpu.icache.tags.sampled_refs 19531 # Sample count of references to valid blocks. 391system.cpu.icache.tags.avg_refs 10256.688239 # Average number of references to valid blocks. 392system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 393system.cpu.icache.tags.occ_blocks::cpu.inst 1187.686040 # Average occupied blocks per requestor 394system.cpu.icache.tags.occ_percent::cpu.inst 0.579925 # Average percentage of cache occupancy 395system.cpu.icache.tags.occ_percent::total 0.579925 # Average percentage of cache occupancy 396system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id 397system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 398system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 399system.cpu.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id 400system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id 401system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id 402system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id 403system.cpu.icache.tags.tag_accesses 400705349 # Number of tag accesses 404system.cpu.icache.tags.data_accesses 400705349 # Number of data accesses 405system.cpu.icache.ReadReq_hits::cpu.inst 200323378 # number of ReadReq hits 406system.cpu.icache.ReadReq_hits::total 200323378 # number of ReadReq hits 407system.cpu.icache.demand_hits::cpu.inst 200323378 # number of demand (read+write) hits 408system.cpu.icache.demand_hits::total 200323378 # number of demand (read+write) hits 409system.cpu.icache.overall_hits::cpu.inst 200323378 # number of overall hits 410system.cpu.icache.overall_hits::total 200323378 # number of overall hits 411system.cpu.icache.ReadReq_misses::cpu.inst 19531 # number of ReadReq misses 412system.cpu.icache.ReadReq_misses::total 19531 # number of ReadReq misses 413system.cpu.icache.demand_misses::cpu.inst 19531 # number of demand (read+write) misses 414system.cpu.icache.demand_misses::total 19531 # number of demand (read+write) misses 415system.cpu.icache.overall_misses::cpu.inst 19531 # number of overall misses 416system.cpu.icache.overall_misses::total 19531 # number of overall misses 417system.cpu.icache.ReadReq_miss_latency::cpu.inst 466485747 # number of ReadReq miss cycles 418system.cpu.icache.ReadReq_miss_latency::total 466485747 # number of ReadReq miss cycles 419system.cpu.icache.demand_miss_latency::cpu.inst 466485747 # number of demand (read+write) miss cycles 420system.cpu.icache.demand_miss_latency::total 466485747 # number of demand (read+write) miss cycles 421system.cpu.icache.overall_miss_latency::cpu.inst 466485747 # number of overall miss cycles 422system.cpu.icache.overall_miss_latency::total 466485747 # number of overall miss cycles 423system.cpu.icache.ReadReq_accesses::cpu.inst 200342909 # number of ReadReq accesses(hits+misses) 424system.cpu.icache.ReadReq_accesses::total 200342909 # number of ReadReq accesses(hits+misses) 425system.cpu.icache.demand_accesses::cpu.inst 200342909 # number of demand (read+write) accesses 426system.cpu.icache.demand_accesses::total 200342909 # number of demand (read+write) accesses 427system.cpu.icache.overall_accesses::cpu.inst 200342909 # number of overall (read+write) accesses 428system.cpu.icache.overall_accesses::total 200342909 # number of overall (read+write) accesses 429system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses 430system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses 431system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses 432system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses 433system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses 434system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses 435system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966 # average ReadReq miss latency 436system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966 # average ReadReq miss latency 437system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency 438system.cpu.icache.demand_avg_miss_latency::total 23884.375966 # average overall miss latency 439system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency 440system.cpu.icache.overall_avg_miss_latency::total 23884.375966 # average overall miss latency 441system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 442system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 443system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 444system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 445system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 446system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 447system.cpu.icache.fast_writes 0 # number of fast writes performed 448system.cpu.icache.cache_copies 0 # number of cache copies performed 449system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19531 # number of ReadReq MSHR misses 450system.cpu.icache.ReadReq_mshr_misses::total 19531 # number of ReadReq MSHR misses 451system.cpu.icache.demand_mshr_misses::cpu.inst 19531 # number of demand (read+write) MSHR misses 452system.cpu.icache.demand_mshr_misses::total 19531 # number of demand (read+write) MSHR misses 453system.cpu.icache.overall_mshr_misses::cpu.inst 19531 # number of overall MSHR misses 454system.cpu.icache.overall_mshr_misses::total 19531 # number of overall MSHR misses 455system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426041253 # number of ReadReq MSHR miss cycles 456system.cpu.icache.ReadReq_mshr_miss_latency::total 426041253 # number of ReadReq MSHR miss cycles 457system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426041253 # number of demand (read+write) MSHR miss cycles 458system.cpu.icache.demand_mshr_miss_latency::total 426041253 # number of demand (read+write) MSHR miss cycles 459system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426041253 # number of overall MSHR miss cycles 460system.cpu.icache.overall_mshr_miss_latency::total 426041253 # number of overall MSHR miss cycles 461system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses 462system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses 463system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses 464system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses 465system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses 466system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses 467system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21813.591368 # average ReadReq mshr miss latency 468system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21813.591368 # average ReadReq mshr miss latency 469system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency 470system.cpu.icache.demand_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency 471system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency 472system.cpu.icache.overall_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency 473system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 474system.cpu.toL2Bus.throughput 394741942 # Throughput (bytes/s) 475system.cpu.toL2Bus.trans_dist::ReadReq 806872 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::ReadResp 806872 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::ReadExReq 356393 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::ReadExResp 356393 # Transaction distribution 480system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39062 # Packet count per connected master and slave (bytes) 481system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355889 # Packet count per connected master and slave (bytes) 482system.cpu.toL2Bus.pkt_count::total 3394951 # Packet count per connected master and slave (bytes) 483system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1249984 # Cumulative packet size per connected master and slave (bytes) 484system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141577920 # Cumulative packet size per connected master and slave (bytes) 485system.cpu.toL2Bus.tot_pkt_size::total 142827904 # Cumulative packet size per connected master and slave (bytes) 486system.cpu.toL2Bus.data_through_bus 142827904 # Total data (bytes) 487system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 488system.cpu.toL2Bus.reqLayer0.occupancy 2184264000 # Layer occupancy (ticks) 489system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 490system.cpu.toL2Bus.respLayer0.occupancy 29987747 # Layer occupancy (ticks) 491system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 492system.cpu.toL2Bus.respLayer1.occupancy 1744465986 # Layer occupancy (ticks) 493system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 494system.cpu.l2cache.tags.replacements 111319 # number of replacements 495system.cpu.l2cache.tags.tagsinuse 27632.304905 # Cycle average of tags in use 496system.cpu.l2cache.tags.total_refs 1684536 # Total number of references to valid blocks. 497system.cpu.l2cache.tags.sampled_refs 142508 # Sample count of references to valid blocks. 498system.cpu.l2cache.tags.avg_refs 11.820642 # Average number of references to valid blocks. 499system.cpu.l2cache.tags.warmup_cycle 162493519500 # Cycle when the warmup percentage was hit. 500system.cpu.l2cache.tags.occ_blocks::writebacks 23524.678269 # Average occupied blocks per requestor 501system.cpu.l2cache.tags.occ_blocks::cpu.inst 4107.626636 # Average occupied blocks per requestor 502system.cpu.l2cache.tags.occ_percent::writebacks 0.717916 # Average percentage of cache occupancy 503system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125355 # Average percentage of cache occupancy 504system.cpu.l2cache.tags.occ_percent::total 0.843271 # Average percentage of cache occupancy 505system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id 506system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 507system.cpu.l2cache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id 508system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4925 # Occupied blocks per task id 509system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25872 # Occupied blocks per task id 510system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id 511system.cpu.l2cache.tags.tag_accesses 18352389 # Number of tag accesses 512system.cpu.l2cache.tags.data_accesses 18352389 # Number of data accesses 513system.cpu.l2cache.ReadReq_hits::cpu.inst 763644 # number of ReadReq hits 514system.cpu.l2cache.ReadReq_hits::total 763644 # number of ReadReq hits 515system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits 516system.cpu.l2cache.Writeback_hits::total 1068421 # number of Writeback hits 517system.cpu.l2cache.ReadExReq_hits::cpu.inst 255531 # number of ReadExReq hits 518system.cpu.l2cache.ReadExReq_hits::total 255531 # number of ReadExReq hits 519system.cpu.l2cache.demand_hits::cpu.inst 1019175 # number of demand (read+write) hits 520system.cpu.l2cache.demand_hits::total 1019175 # number of demand (read+write) hits 521system.cpu.l2cache.overall_hits::cpu.inst 1019175 # number of overall hits 522system.cpu.l2cache.overall_hits::total 1019175 # number of overall hits 523system.cpu.l2cache.ReadReq_misses::cpu.inst 43228 # number of ReadReq misses 524system.cpu.l2cache.ReadReq_misses::total 43228 # number of ReadReq misses 525system.cpu.l2cache.ReadExReq_misses::cpu.inst 100862 # number of ReadExReq misses 526system.cpu.l2cache.ReadExReq_misses::total 100862 # number of ReadExReq misses 527system.cpu.l2cache.demand_misses::cpu.inst 144090 # number of demand (read+write) misses 528system.cpu.l2cache.demand_misses::total 144090 # number of demand (read+write) misses 529system.cpu.l2cache.overall_misses::cpu.inst 144090 # number of overall misses 530system.cpu.l2cache.overall_misses::total 144090 # number of overall misses 531system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3220977500 # number of ReadReq miss cycles 532system.cpu.l2cache.ReadReq_miss_latency::total 3220977500 # number of ReadReq miss cycles 533system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7166346750 # number of ReadExReq miss cycles 534system.cpu.l2cache.ReadExReq_miss_latency::total 7166346750 # number of ReadExReq miss cycles 535system.cpu.l2cache.demand_miss_latency::cpu.inst 10387324250 # number of demand (read+write) miss cycles 536system.cpu.l2cache.demand_miss_latency::total 10387324250 # number of demand (read+write) miss cycles 537system.cpu.l2cache.overall_miss_latency::cpu.inst 10387324250 # number of overall miss cycles 538system.cpu.l2cache.overall_miss_latency::total 10387324250 # number of overall miss cycles 539system.cpu.l2cache.ReadReq_accesses::cpu.inst 806872 # number of ReadReq accesses(hits+misses) 540system.cpu.l2cache.ReadReq_accesses::total 806872 # number of ReadReq accesses(hits+misses) 541system.cpu.l2cache.Writeback_accesses::writebacks 1068421 # number of Writeback accesses(hits+misses) 542system.cpu.l2cache.Writeback_accesses::total 1068421 # number of Writeback accesses(hits+misses) 543system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356393 # number of ReadExReq accesses(hits+misses) 544system.cpu.l2cache.ReadExReq_accesses::total 356393 # number of ReadExReq accesses(hits+misses) 545system.cpu.l2cache.demand_accesses::cpu.inst 1163265 # number of demand (read+write) accesses 546system.cpu.l2cache.demand_accesses::total 1163265 # number of demand (read+write) accesses 547system.cpu.l2cache.overall_accesses::cpu.inst 1163265 # number of overall (read+write) accesses 548system.cpu.l2cache.overall_accesses::total 1163265 # number of overall (read+write) accesses 549system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053575 # miss rate for ReadReq accesses 550system.cpu.l2cache.ReadReq_miss_rate::total 0.053575 # miss rate for ReadReq accesses 551system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283008 # miss rate for ReadExReq accesses 552system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses 553system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123867 # miss rate for demand accesses 554system.cpu.l2cache.demand_miss_rate::total 0.123867 # miss rate for demand accesses 555system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123867 # miss rate for overall accesses 556system.cpu.l2cache.overall_miss_rate::total 0.123867 # miss rate for overall accesses 557system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74511.369945 # average ReadReq miss latency 558system.cpu.l2cache.ReadReq_avg_miss_latency::total 74511.369945 # average ReadReq miss latency 559system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71051.007813 # average ReadExReq miss latency 560system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71051.007813 # average ReadExReq miss latency 561system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency 562system.cpu.l2cache.demand_avg_miss_latency::total 72089.140468 # average overall miss latency 563system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency 564system.cpu.l2cache.overall_avg_miss_latency::total 72089.140468 # average overall miss latency 565system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 566system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 567system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 568system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 569system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 570system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 571system.cpu.l2cache.fast_writes 0 # number of fast writes performed 572system.cpu.l2cache.cache_copies 0 # number of cache copies performed 573system.cpu.l2cache.writebacks::writebacks 96516 # number of writebacks 574system.cpu.l2cache.writebacks::total 96516 # number of writebacks 575system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits 576system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits 577system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits 578system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 579system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits 580system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 581system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43212 # number of ReadReq MSHR misses 582system.cpu.l2cache.ReadReq_mshr_misses::total 43212 # number of ReadReq MSHR misses 583system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100862 # number of ReadExReq MSHR misses 584system.cpu.l2cache.ReadExReq_mshr_misses::total 100862 # number of ReadExReq MSHR misses 585system.cpu.l2cache.demand_mshr_misses::cpu.inst 144074 # number of demand (read+write) MSHR misses 586system.cpu.l2cache.demand_mshr_misses::total 144074 # number of demand (read+write) MSHR misses 587system.cpu.l2cache.overall_mshr_misses::cpu.inst 144074 # number of overall MSHR misses 588system.cpu.l2cache.overall_mshr_misses::total 144074 # number of overall MSHR misses 589system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2672872000 # number of ReadReq MSHR miss cycles 590system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2672872000 # number of ReadReq MSHR miss cycles 591system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5889125250 # number of ReadExReq MSHR miss cycles 592system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5889125250 # number of ReadExReq MSHR miss cycles 593system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8561997250 # number of demand (read+write) MSHR miss cycles 594system.cpu.l2cache.demand_mshr_miss_latency::total 8561997250 # number of demand (read+write) MSHR miss cycles 595system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8561997250 # number of overall MSHR miss cycles 596system.cpu.l2cache.overall_mshr_miss_latency::total 8561997250 # number of overall MSHR miss cycles 597system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053555 # mshr miss rate for ReadReq accesses 598system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053555 # mshr miss rate for ReadReq accesses 599system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283008 # mshr miss rate for ReadExReq accesses 600system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses 601system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for demand accesses 602system.cpu.l2cache.demand_mshr_miss_rate::total 0.123853 # mshr miss rate for demand accesses 603system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for overall accesses 604system.cpu.l2cache.overall_mshr_miss_rate::total 0.123853 # mshr miss rate for overall accesses 605system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61854.855133 # average ReadReq mshr miss latency 606system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61854.855133 # average ReadReq mshr miss latency 607system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58387.948385 # average ReadExReq mshr miss latency 608system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58387.948385 # average ReadExReq mshr miss latency 609system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59427.774963 # average overall mshr miss latency 610system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59427.774963 # average overall mshr miss latency 611system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59427.774963 # average overall mshr miss latency 612system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59427.774963 # average overall mshr miss latency 613system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 614system.cpu.dcache.tags.replacements 1139638 # number of replacements 615system.cpu.dcache.tags.tagsinuse 4071.125159 # Cycle average of tags in use 616system.cpu.dcache.tags.total_refs 169305637 # Total number of references to valid blocks. 617system.cpu.dcache.tags.sampled_refs 1143734 # Sample count of references to valid blocks. 618system.cpu.dcache.tags.avg_refs 148.028857 # Average number of references to valid blocks. 619system.cpu.dcache.tags.warmup_cycle 4807181250 # Cycle when the warmup percentage was hit. 620system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.125159 # Average occupied blocks per requestor 621system.cpu.dcache.tags.occ_percent::cpu.inst 0.993927 # Average percentage of cache occupancy 622system.cpu.dcache.tags.occ_percent::total 0.993927 # Average percentage of cache occupancy 623system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 624system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 625system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 626system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id 627system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id 628system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 629system.cpu.dcache.tags.tag_accesses 342864800 # Number of tag accesses 630system.cpu.dcache.tags.data_accesses 342864800 # Number of data accesses 631system.cpu.dcache.ReadReq_hits::cpu.inst 112789835 # number of ReadReq hits 632system.cpu.dcache.ReadReq_hits::total 112789835 # number of ReadReq hits 633system.cpu.dcache.WriteReq_hits::cpu.inst 53538720 # number of WriteReq hits 634system.cpu.dcache.WriteReq_hits::total 53538720 # number of WriteReq hits 635system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits 636system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 637system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits 638system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 639system.cpu.dcache.demand_hits::cpu.inst 166328555 # number of demand (read+write) hits 640system.cpu.dcache.demand_hits::total 166328555 # number of demand (read+write) hits 641system.cpu.dcache.overall_hits::cpu.inst 166328555 # number of overall hits 642system.cpu.dcache.overall_hits::total 166328555 # number of overall hits 643system.cpu.dcache.ReadReq_misses::cpu.inst 854310 # number of ReadReq misses 644system.cpu.dcache.ReadReq_misses::total 854310 # number of ReadReq misses 645system.cpu.dcache.WriteReq_misses::cpu.inst 700586 # number of WriteReq misses 646system.cpu.dcache.WriteReq_misses::total 700586 # number of WriteReq misses 647system.cpu.dcache.demand_misses::cpu.inst 1554896 # number of demand (read+write) misses 648system.cpu.dcache.demand_misses::total 1554896 # number of demand (read+write) misses 649system.cpu.dcache.overall_misses::cpu.inst 1554896 # number of overall misses 650system.cpu.dcache.overall_misses::total 1554896 # number of overall misses 651system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13696134233 # number of ReadReq miss cycles 652system.cpu.dcache.ReadReq_miss_latency::total 13696134233 # number of ReadReq miss cycles 653system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20619900500 # number of WriteReq miss cycles 654system.cpu.dcache.WriteReq_miss_latency::total 20619900500 # number of WriteReq miss cycles 655system.cpu.dcache.demand_miss_latency::cpu.inst 34316034733 # number of demand (read+write) miss cycles 656system.cpu.dcache.demand_miss_latency::total 34316034733 # number of demand (read+write) miss cycles 657system.cpu.dcache.overall_miss_latency::cpu.inst 34316034733 # number of overall miss cycles 658system.cpu.dcache.overall_miss_latency::total 34316034733 # number of overall miss cycles 659system.cpu.dcache.ReadReq_accesses::cpu.inst 113644145 # number of ReadReq accesses(hits+misses) 660system.cpu.dcache.ReadReq_accesses::total 113644145 # number of ReadReq accesses(hits+misses) 661system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) 662system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 663system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) 664system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 665system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) 666system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 667system.cpu.dcache.demand_accesses::cpu.inst 167883451 # number of demand (read+write) accesses 668system.cpu.dcache.demand_accesses::total 167883451 # number of demand (read+write) accesses 669system.cpu.dcache.overall_accesses::cpu.inst 167883451 # number of overall (read+write) accesses 670system.cpu.dcache.overall_accesses::total 167883451 # number of overall (read+write) accesses 671system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007517 # miss rate for ReadReq accesses 672system.cpu.dcache.ReadReq_miss_rate::total 0.007517 # miss rate for ReadReq accesses 673system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses 674system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses 675system.cpu.dcache.demand_miss_rate::cpu.inst 0.009262 # miss rate for demand accesses 676system.cpu.dcache.demand_miss_rate::total 0.009262 # miss rate for demand accesses 677system.cpu.dcache.overall_miss_rate::cpu.inst 0.009262 # miss rate for overall accesses 678system.cpu.dcache.overall_miss_rate::total 0.009262 # miss rate for overall accesses 679system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16031.808399 # average ReadReq miss latency 680system.cpu.dcache.ReadReq_avg_miss_latency::total 16031.808399 # average ReadReq miss latency 681system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29432.361623 # average WriteReq miss latency 682system.cpu.dcache.WriteReq_avg_miss_latency::total 29432.361623 # average WriteReq miss latency 683system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency 684system.cpu.dcache.demand_avg_miss_latency::total 22069.665581 # average overall miss latency 685system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency 686system.cpu.dcache.overall_avg_miss_latency::total 22069.665581 # average overall miss latency 687system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 688system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 690system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 692system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 693system.cpu.dcache.fast_writes 0 # number of fast writes performed 694system.cpu.dcache.cache_copies 0 # number of cache copies performed 695system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks 696system.cpu.dcache.writebacks::total 1068421 # number of writebacks 697system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66718 # number of ReadReq MSHR hits 698system.cpu.dcache.ReadReq_mshr_hits::total 66718 # number of ReadReq MSHR hits 699system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344444 # number of WriteReq MSHR hits 700system.cpu.dcache.WriteReq_mshr_hits::total 344444 # number of WriteReq MSHR hits 701system.cpu.dcache.demand_mshr_hits::cpu.inst 411162 # number of demand (read+write) MSHR hits 702system.cpu.dcache.demand_mshr_hits::total 411162 # number of demand (read+write) MSHR hits 703system.cpu.dcache.overall_mshr_hits::cpu.inst 411162 # number of overall MSHR hits 704system.cpu.dcache.overall_mshr_hits::total 411162 # number of overall MSHR hits 705system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787592 # number of ReadReq MSHR misses 706system.cpu.dcache.ReadReq_mshr_misses::total 787592 # number of ReadReq MSHR misses 707system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356142 # number of WriteReq MSHR misses 708system.cpu.dcache.WriteReq_mshr_misses::total 356142 # number of WriteReq MSHR misses 709system.cpu.dcache.demand_mshr_misses::cpu.inst 1143734 # number of demand (read+write) MSHR misses 710system.cpu.dcache.demand_mshr_misses::total 1143734 # number of demand (read+write) MSHR misses 711system.cpu.dcache.overall_mshr_misses::cpu.inst 1143734 # number of overall MSHR misses 712system.cpu.dcache.overall_mshr_misses::total 1143734 # number of overall MSHR misses 713system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11245323264 # number of ReadReq MSHR miss cycles 714system.cpu.dcache.ReadReq_mshr_miss_latency::total 11245323264 # number of ReadReq MSHR miss cycles 715system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10075452250 # number of WriteReq MSHR miss cycles 716system.cpu.dcache.WriteReq_mshr_miss_latency::total 10075452250 # number of WriteReq MSHR miss cycles 717system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21320775514 # number of demand (read+write) MSHR miss cycles 718system.cpu.dcache.demand_mshr_miss_latency::total 21320775514 # number of demand (read+write) MSHR miss cycles 719system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21320775514 # number of overall MSHR miss cycles 720system.cpu.dcache.overall_mshr_miss_latency::total 21320775514 # number of overall MSHR miss cycles 721system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses 722system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses 723system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses 724system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses 725system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for demand accesses 726system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses 727system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses 728system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses 729system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.107528 # average ReadReq mshr miss latency 730system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.107528 # average ReadReq mshr miss latency 731system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28290.547731 # average WriteReq mshr miss latency 732system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28290.547731 # average WriteReq mshr miss latency 733system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency 734system.cpu.dcache.demand_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency 735system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency 736system.cpu.dcache.overall_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency 737system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 737 738---------- End Simulation Statistics ---------- | 738 739---------- End Simulation Statistics ---------- |