1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 0.365348 # Number of seconds simulated 4sim_ticks 365347511000 # Number of ticks simulated 5final_tick 365347511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 224796 # Simulator instruction rate (inst/s) 8host_op_rate 243484 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 162123009 # Simulator tick rate (ticks/s) 10host_mem_usage 256924 # Number of bytes of host memory used 11host_seconds 2253.52 # Real time elapsed on the host |
12sim_insts 506582155 # Number of instructions simulated 13sim_ops 548695378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
16system.physmem.bytes_read::cpu.inst 9224896 # Number of bytes read from this memory 17system.physmem.bytes_read::total 9224896 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 221312 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 221312 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 6179008 # Number of bytes written to this memory 21system.physmem.bytes_written::total 6179008 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 144139 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 144139 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 96547 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 96547 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 25249648 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 25249648 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 605758 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 605758 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 16912687 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 16912687 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 16912687 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 25249648 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 42162335 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 144139 # Number of read requests accepted 36system.physmem.writeReqs 96547 # Number of write requests accepted 37system.physmem.readBursts 144139 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 96547 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 9218048 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue 41system.physmem.bytesWritten 6177856 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 9224896 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 6179008 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue |
45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
47system.physmem.perBankRdBursts::0 9344 # Per bank write bursts 48system.physmem.perBankRdBursts::1 8969 # Per bank write bursts 49system.physmem.perBankRdBursts::2 8998 # Per bank write bursts 50system.physmem.perBankRdBursts::3 8704 # Per bank write bursts 51system.physmem.perBankRdBursts::4 9453 # Per bank write bursts 52system.physmem.perBankRdBursts::5 9341 # Per bank write bursts 53system.physmem.perBankRdBursts::6 8940 # Per bank write bursts 54system.physmem.perBankRdBursts::7 8101 # Per bank write bursts 55system.physmem.perBankRdBursts::8 8571 # Per bank write bursts 56system.physmem.perBankRdBursts::9 8677 # Per bank write bursts 57system.physmem.perBankRdBursts::10 8772 # Per bank write bursts 58system.physmem.perBankRdBursts::11 9476 # Per bank write bursts 59system.physmem.perBankRdBursts::12 9379 # Per bank write bursts 60system.physmem.perBankRdBursts::13 9523 # Per bank write bursts 61system.physmem.perBankRdBursts::14 8710 # Per bank write bursts 62system.physmem.perBankRdBursts::15 9074 # Per bank write bursts 63system.physmem.perBankWrBursts::0 6191 # Per bank write bursts |
64system.physmem.perBankWrBursts::1 6093 # Per bank write bursts |
65system.physmem.perBankWrBursts::2 6006 # Per bank write bursts 66system.physmem.perBankWrBursts::3 5817 # Per bank write bursts 67system.physmem.perBankWrBursts::4 6161 # Per bank write bursts 68system.physmem.perBankWrBursts::5 6171 # Per bank write bursts 69system.physmem.perBankWrBursts::6 6013 # Per bank write bursts |
70system.physmem.perBankWrBursts::7 5494 # Per bank write bursts |
71system.physmem.perBankWrBursts::8 5728 # Per bank write bursts 72system.physmem.perBankWrBursts::9 5821 # Per bank write bursts |
73system.physmem.perBankWrBursts::10 5961 # Per bank write bursts |
74system.physmem.perBankWrBursts::11 6446 # Per bank write bursts 75system.physmem.perBankWrBursts::12 6308 # Per bank write bursts 76system.physmem.perBankWrBursts::13 6280 # Per bank write bursts 77system.physmem.perBankWrBursts::14 5994 # Per bank write bursts 78system.physmem.perBankWrBursts::15 6045 # Per bank write bursts |
79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
81system.physmem.totGap 365347483000 # Total gap between requests |
82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) |
88system.physmem.readPktSize::6 144139 # Read request sizes (log2) |
89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) |
95system.physmem.writePktSize::6 96547 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see |
99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
143system.physmem.wrQLenPdf::15 2861 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 3022 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 5536 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 5697 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 5670 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 5682 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 5668 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 5678 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 5702 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 5698 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 5672 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 5626 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 5701 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 5628 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 5584 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see |
172system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see |
173system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see |
175system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
192system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 237.344433 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 157.101707 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 243.291878 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 24488 37.75% 37.75% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 18300 28.21% 65.96% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 6859 10.57% 76.54% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 7791 12.01% 88.55% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 2064 3.18% 91.73% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1161 1.79% 93.52% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 764 1.18% 94.70% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 681 1.05% 95.75% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 2758 4.25% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 5569 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 25.862992 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 382.285392 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 5565 99.93% 99.93% # Reads before turning the bus around for writes |
210system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes |
212system.physmem.rdPerTurnAround::total 5569 # Reads before turning the bus around for writes 213system.physmem.wrPerTurnAround::samples 5569 # Writes before turning the bus around for reads 214system.physmem.wrPerTurnAround::mean 17.333273 # Writes before turning the bus around for reads 215system.physmem.wrPerTurnAround::gmean 17.210704 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::stdev 3.188900 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::16-19 5418 97.29% 97.29% # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::20-23 79 1.42% 98.71% # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::24-27 23 0.41% 99.12% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::28-31 20 0.36% 99.48% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::32-35 9 0.16% 99.64% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::36-39 7 0.13% 99.77% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::40-43 5 0.09% 99.86% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::44-47 5 0.09% 99.95% # Writes before turning the bus around for reads |
225system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads |
226system.physmem.wrPerTurnAround::120-123 1 0.02% 99.98% # Writes before turning the bus around for reads |
227system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads |
228system.physmem.wrPerTurnAround::total 5569 # Writes before turning the bus around for reads 229system.physmem.totQLat 1570268250 # Total ticks spent queuing 230system.physmem.totMemAccLat 4270868250 # Total ticks spent from burst creation until serviced by the DRAM 231system.physmem.totBusLat 720160000 # Total ticks spent in databus transfers 232system.physmem.avgQLat 10902.22 # Average queueing delay per DRAM burst |
233system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
234system.physmem.avgMemAccLat 29652.22 # Average memory access latency per DRAM burst 235system.physmem.avgRdBW 25.23 # Average DRAM read bandwidth in MiByte/s 236system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s 237system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s 238system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s |
239system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 240system.physmem.busUtil 0.33 # Data bus utilization in percentage 241system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 242system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 243system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
244system.physmem.avgWrQLen 19.86 # Average write queue length when enqueuing 245system.physmem.readRowHits 110988 # Number of row buffer hits during reads 246system.physmem.writeRowHits 64704 # Number of row buffer hits during writes 247system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads 248system.physmem.writeRowHitRate 67.02 # Row buffer hit rate for writes 249system.physmem.avgGap 1517942.39 # Average gap between requests 250system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined 251system.physmem.memoryStateTime::IDLE 256543365500 # Time in different power states 252system.physmem.memoryStateTime::REF 12199720000 # Time in different power states |
253system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
254system.physmem.memoryStateTime::ACT 96603610750 # Time in different power states |
255system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
256system.physmem.actEnergy::0 246584520 # Energy for activate commands per rank (pJ) 257system.physmem.actEnergy::1 243719280 # Energy for activate commands per rank (pJ) 258system.physmem.preEnergy::0 134545125 # Energy for precharge commands per rank (pJ) 259system.physmem.preEnergy::1 132981750 # Energy for precharge commands per rank (pJ) 260system.physmem.readEnergy::0 560422200 # Energy for read commands per rank (pJ) 261system.physmem.readEnergy::1 562972800 # Energy for read commands per rank (pJ) 262system.physmem.writeEnergy::0 310625280 # Energy for write commands per rank (pJ) 263system.physmem.writeEnergy::1 314778960 # Energy for write commands per rank (pJ) 264system.physmem.refreshEnergy::0 23862652320 # Energy for refresh commands per rank (pJ) 265system.physmem.refreshEnergy::1 23862652320 # Energy for refresh commands per rank (pJ) 266system.physmem.actBackEnergy::0 47112370740 # Energy for active background per rank (pJ) 267system.physmem.actBackEnergy::1 46678345380 # Energy for active background per rank (pJ) 268system.physmem.preBackEnergy::0 177881368500 # Energy for precharge background per rank (pJ) 269system.physmem.preBackEnergy::1 178262092500 # Energy for precharge background per rank (pJ) 270system.physmem.totalEnergy::0 250108568685 # Total energy per rank (pJ) 271system.physmem.totalEnergy::1 250057542990 # Total energy per rank (pJ) 272system.physmem.averagePower::0 684.578732 # Core power per rank (mW) 273system.physmem.averagePower::1 684.439068 # Core power per rank (mW) 274system.cpu.branchPred.lookups 132580026 # Number of BP lookups 275system.cpu.branchPred.condPredicted 98506360 # Number of conditional branches predicted 276system.cpu.branchPred.condIncorrect 6554090 # Number of conditional branches incorrect 277system.cpu.branchPred.BTBLookups 69003825 # Number of BTB lookups 278system.cpu.branchPred.BTBHits 64853184 # Number of BTB hits |
279system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
280system.cpu.branchPred.BTBHitPct 93.984912 # BTB Hit Percentage 281system.cpu.branchPred.usedRAS 10016062 # Number of times the RAS was used to get a target. 282system.cpu.branchPred.RASInCorrect 17737 # Number of incorrect RAS predictions. 283system.cpu_clk_domain.clock 500 # Clock period in ticks |
284system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 285system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 286system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 287system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 288system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 289system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 290system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 291system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 361system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 362system.cpu.itb.read_accesses 0 # DTB read accesses 363system.cpu.itb.write_accesses 0 # DTB write accesses 364system.cpu.itb.inst_accesses 0 # ITB inst accesses 365system.cpu.itb.hits 0 # DTB hits 366system.cpu.itb.misses 0 # DTB misses 367system.cpu.itb.accesses 0 # DTB accesses 368system.cpu.workload.num_syscalls 548 # Number of system calls |
369system.cpu.numCycles 730695022 # number of cpu cycles simulated |
370system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 371system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 372system.cpu.committedInsts 506582155 # Number of instructions committed 373system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed |
374system.cpu.discardedOps 13461717 # Number of ops (including micro ops) which were discarded before commit |
375system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
376system.cpu.cpi 1.442402 # CPI: cycles per instruction 377system.cpu.ipc 0.693288 # IPC: instructions per cycle 378system.cpu.tickCycles 695775254 # Number of cycles that the object actually ticked 379system.cpu.idleCycles 34919768 # Total number of cycles that the object has spent stopped 380system.cpu.dcache.tags.replacements 1139848 # number of replacements 381system.cpu.dcache.tags.tagsinuse 4071.076883 # Cycle average of tags in use 382system.cpu.dcache.tags.total_refs 171283127 # Total number of references to valid blocks. 383system.cpu.dcache.tags.sampled_refs 1143944 # Sample count of references to valid blocks. 384system.cpu.dcache.tags.avg_refs 149.730343 # Average number of references to valid blocks. 385system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. 386system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.076883 # Average occupied blocks per requestor 387system.cpu.dcache.tags.occ_percent::cpu.inst 0.993915 # Average percentage of cache occupancy 388system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy 389system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 390system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 391system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id 392system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id 393system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id 394system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 395system.cpu.dcache.tags.tag_accesses 346820764 # Number of tag accesses 396system.cpu.dcache.tags.data_accesses 346820764 # Number of data accesses 397system.cpu.dcache.ReadReq_hits::cpu.inst 114767369 # number of ReadReq hits 398system.cpu.dcache.ReadReq_hits::total 114767369 # number of ReadReq hits 399system.cpu.dcache.WriteReq_hits::cpu.inst 53538676 # number of WriteReq hits 400system.cpu.dcache.WriteReq_hits::total 53538676 # number of WriteReq hits 401system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits 402system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 403system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits 404system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 405system.cpu.dcache.demand_hits::cpu.inst 168306045 # number of demand (read+write) hits 406system.cpu.dcache.demand_hits::total 168306045 # number of demand (read+write) hits 407system.cpu.dcache.overall_hits::cpu.inst 168306045 # number of overall hits 408system.cpu.dcache.overall_hits::total 168306045 # number of overall hits 409system.cpu.dcache.ReadReq_misses::cpu.inst 854653 # number of ReadReq misses 410system.cpu.dcache.ReadReq_misses::total 854653 # number of ReadReq misses 411system.cpu.dcache.WriteReq_misses::cpu.inst 700630 # number of WriteReq misses 412system.cpu.dcache.WriteReq_misses::total 700630 # number of WriteReq misses 413system.cpu.dcache.demand_misses::cpu.inst 1555283 # number of demand (read+write) misses 414system.cpu.dcache.demand_misses::total 1555283 # number of demand (read+write) misses 415system.cpu.dcache.overall_misses::cpu.inst 1555283 # number of overall misses 416system.cpu.dcache.overall_misses::total 1555283 # number of overall misses 417system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13708895232 # number of ReadReq miss cycles 418system.cpu.dcache.ReadReq_miss_latency::total 13708895232 # number of ReadReq miss cycles 419system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20586763000 # number of WriteReq miss cycles 420system.cpu.dcache.WriteReq_miss_latency::total 20586763000 # number of WriteReq miss cycles 421system.cpu.dcache.demand_miss_latency::cpu.inst 34295658232 # number of demand (read+write) miss cycles 422system.cpu.dcache.demand_miss_latency::total 34295658232 # number of demand (read+write) miss cycles 423system.cpu.dcache.overall_miss_latency::cpu.inst 34295658232 # number of overall miss cycles 424system.cpu.dcache.overall_miss_latency::total 34295658232 # number of overall miss cycles 425system.cpu.dcache.ReadReq_accesses::cpu.inst 115622022 # number of ReadReq accesses(hits+misses) 426system.cpu.dcache.ReadReq_accesses::total 115622022 # number of ReadReq accesses(hits+misses) 427system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) 428system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 429system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) 430system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 431system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) 432system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 433system.cpu.dcache.demand_accesses::cpu.inst 169861328 # number of demand (read+write) accesses 434system.cpu.dcache.demand_accesses::total 169861328 # number of demand (read+write) accesses 435system.cpu.dcache.overall_accesses::cpu.inst 169861328 # number of overall (read+write) accesses 436system.cpu.dcache.overall_accesses::total 169861328 # number of overall (read+write) accesses 437system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007392 # miss rate for ReadReq accesses 438system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses 439system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses 440system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses 441system.cpu.dcache.demand_miss_rate::cpu.inst 0.009156 # miss rate for demand accesses 442system.cpu.dcache.demand_miss_rate::total 0.009156 # miss rate for demand accesses 443system.cpu.dcache.overall_miss_rate::cpu.inst 0.009156 # miss rate for overall accesses 444system.cpu.dcache.overall_miss_rate::total 0.009156 # miss rate for overall accesses 445system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16040.305518 # average ReadReq miss latency 446system.cpu.dcache.ReadReq_avg_miss_latency::total 16040.305518 # average ReadReq miss latency 447system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29383.216534 # average WriteReq miss latency 448system.cpu.dcache.WriteReq_avg_miss_latency::total 29383.216534 # average WriteReq miss latency 449system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency 450system.cpu.dcache.demand_avg_miss_latency::total 22051.072526 # average overall miss latency 451system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency 452system.cpu.dcache.overall_avg_miss_latency::total 22051.072526 # average overall miss latency 453system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 454system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 455system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 456system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 457system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 458system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 459system.cpu.dcache.fast_writes 0 # number of fast writes performed 460system.cpu.dcache.cache_copies 0 # number of cache copies performed 461system.cpu.dcache.writebacks::writebacks 1068569 # number of writebacks 462system.cpu.dcache.writebacks::total 1068569 # number of writebacks 463system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66869 # number of ReadReq MSHR hits 464system.cpu.dcache.ReadReq_mshr_hits::total 66869 # number of ReadReq MSHR hits 465system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344470 # number of WriteReq MSHR hits 466system.cpu.dcache.WriteReq_mshr_hits::total 344470 # number of WriteReq MSHR hits 467system.cpu.dcache.demand_mshr_hits::cpu.inst 411339 # number of demand (read+write) MSHR hits 468system.cpu.dcache.demand_mshr_hits::total 411339 # number of demand (read+write) MSHR hits 469system.cpu.dcache.overall_mshr_hits::cpu.inst 411339 # number of overall MSHR hits 470system.cpu.dcache.overall_mshr_hits::total 411339 # number of overall MSHR hits 471system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787784 # number of ReadReq MSHR misses 472system.cpu.dcache.ReadReq_mshr_misses::total 787784 # number of ReadReq MSHR misses 473system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356160 # number of WriteReq MSHR misses 474system.cpu.dcache.WriteReq_mshr_misses::total 356160 # number of WriteReq MSHR misses 475system.cpu.dcache.demand_mshr_misses::cpu.inst 1143944 # number of demand (read+write) MSHR misses 476system.cpu.dcache.demand_mshr_misses::total 1143944 # number of demand (read+write) MSHR misses 477system.cpu.dcache.overall_mshr_misses::cpu.inst 1143944 # number of overall MSHR misses 478system.cpu.dcache.overall_mshr_misses::total 1143944 # number of overall MSHR misses 479system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11256226015 # number of ReadReq MSHR miss cycles 480system.cpu.dcache.ReadReq_mshr_miss_latency::total 11256226015 # number of ReadReq MSHR miss cycles 481system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10106063500 # number of WriteReq MSHR miss cycles 482system.cpu.dcache.WriteReq_mshr_miss_latency::total 10106063500 # number of WriteReq MSHR miss cycles 483system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21362289515 # number of demand (read+write) MSHR miss cycles 484system.cpu.dcache.demand_mshr_miss_latency::total 21362289515 # number of demand (read+write) MSHR miss cycles 485system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21362289515 # number of overall MSHR miss cycles 486system.cpu.dcache.overall_mshr_miss_latency::total 21362289515 # number of overall MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for ReadReq accesses 488system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses 489system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses 490system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses 491system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006735 # mshr miss rate for demand accesses 492system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses 493system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006735 # mshr miss rate for overall accesses 494system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses 495system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14288.467416 # average ReadReq mshr miss latency 496system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14288.467416 # average ReadReq mshr miss latency 497system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28375.065982 # average WriteReq mshr miss latency 498system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28375.065982 # average WriteReq mshr miss latency 499system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18674.244119 # average overall mshr miss latency 500system.cpu.dcache.demand_avg_mshr_miss_latency::total 18674.244119 # average overall mshr miss latency 501system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18674.244119 # average overall mshr miss latency 502system.cpu.dcache.overall_avg_mshr_miss_latency::total 18674.244119 # average overall mshr miss latency 503system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 504system.cpu.icache.tags.replacements 17642 # number of replacements 505system.cpu.icache.tags.tagsinuse 1190.521713 # Cycle average of tags in use 506system.cpu.icache.tags.total_refs 200940130 # Total number of references to valid blocks. 507system.cpu.icache.tags.sampled_refs 19514 # Sample count of references to valid blocks. 508system.cpu.icache.tags.avg_refs 10297.229169 # Average number of references to valid blocks. |
509system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
510system.cpu.icache.tags.occ_blocks::cpu.inst 1190.521713 # Average occupied blocks per requestor 511system.cpu.icache.tags.occ_percent::cpu.inst 0.581309 # Average percentage of cache occupancy 512system.cpu.icache.tags.occ_percent::total 0.581309 # Average percentage of cache occupancy 513system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id |
514system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 515system.cpu.icache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id |
516system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 517system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id 518system.cpu.icache.tags.age_task_id_blocks_1024::4 1411 # Occupied blocks per task id 519system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id 520system.cpu.icache.tags.tag_accesses 401938802 # Number of tag accesses 521system.cpu.icache.tags.data_accesses 401938802 # Number of data accesses 522system.cpu.icache.ReadReq_hits::cpu.inst 200940130 # number of ReadReq hits 523system.cpu.icache.ReadReq_hits::total 200940130 # number of ReadReq hits 524system.cpu.icache.demand_hits::cpu.inst 200940130 # number of demand (read+write) hits 525system.cpu.icache.demand_hits::total 200940130 # number of demand (read+write) hits 526system.cpu.icache.overall_hits::cpu.inst 200940130 # number of overall hits 527system.cpu.icache.overall_hits::total 200940130 # number of overall hits 528system.cpu.icache.ReadReq_misses::cpu.inst 19514 # number of ReadReq misses 529system.cpu.icache.ReadReq_misses::total 19514 # number of ReadReq misses 530system.cpu.icache.demand_misses::cpu.inst 19514 # number of demand (read+write) misses 531system.cpu.icache.demand_misses::total 19514 # number of demand (read+write) misses 532system.cpu.icache.overall_misses::cpu.inst 19514 # number of overall misses 533system.cpu.icache.overall_misses::total 19514 # number of overall misses 534system.cpu.icache.ReadReq_miss_latency::cpu.inst 467407495 # number of ReadReq miss cycles 535system.cpu.icache.ReadReq_miss_latency::total 467407495 # number of ReadReq miss cycles 536system.cpu.icache.demand_miss_latency::cpu.inst 467407495 # number of demand (read+write) miss cycles 537system.cpu.icache.demand_miss_latency::total 467407495 # number of demand (read+write) miss cycles 538system.cpu.icache.overall_miss_latency::cpu.inst 467407495 # number of overall miss cycles 539system.cpu.icache.overall_miss_latency::total 467407495 # number of overall miss cycles 540system.cpu.icache.ReadReq_accesses::cpu.inst 200959644 # number of ReadReq accesses(hits+misses) 541system.cpu.icache.ReadReq_accesses::total 200959644 # number of ReadReq accesses(hits+misses) 542system.cpu.icache.demand_accesses::cpu.inst 200959644 # number of demand (read+write) accesses 543system.cpu.icache.demand_accesses::total 200959644 # number of demand (read+write) accesses 544system.cpu.icache.overall_accesses::cpu.inst 200959644 # number of overall (read+write) accesses 545system.cpu.icache.overall_accesses::total 200959644 # number of overall (read+write) accesses 546system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses 547system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses 548system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses 549system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses 550system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses 551system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses 552system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23952.418520 # average ReadReq miss latency 553system.cpu.icache.ReadReq_avg_miss_latency::total 23952.418520 # average ReadReq miss latency 554system.cpu.icache.demand_avg_miss_latency::cpu.inst 23952.418520 # average overall miss latency 555system.cpu.icache.demand_avg_miss_latency::total 23952.418520 # average overall miss latency 556system.cpu.icache.overall_avg_miss_latency::cpu.inst 23952.418520 # average overall miss latency 557system.cpu.icache.overall_avg_miss_latency::total 23952.418520 # average overall miss latency |
558system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 559system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 560system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 561system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 562system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 563system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 564system.cpu.icache.fast_writes 0 # number of fast writes performed 565system.cpu.icache.cache_copies 0 # number of cache copies performed |
566system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19514 # number of ReadReq MSHR misses 567system.cpu.icache.ReadReq_mshr_misses::total 19514 # number of ReadReq MSHR misses 568system.cpu.icache.demand_mshr_misses::cpu.inst 19514 # number of demand (read+write) MSHR misses 569system.cpu.icache.demand_mshr_misses::total 19514 # number of demand (read+write) MSHR misses 570system.cpu.icache.overall_mshr_misses::cpu.inst 19514 # number of overall MSHR misses 571system.cpu.icache.overall_mshr_misses::total 19514 # number of overall MSHR misses 572system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426999505 # number of ReadReq MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_latency::total 426999505 # number of ReadReq MSHR miss cycles 574system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426999505 # number of demand (read+write) MSHR miss cycles 575system.cpu.icache.demand_mshr_miss_latency::total 426999505 # number of demand (read+write) MSHR miss cycles 576system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426999505 # number of overall MSHR miss cycles 577system.cpu.icache.overall_mshr_miss_latency::total 426999505 # number of overall MSHR miss cycles 578system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses 579system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses 580system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses 581system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses 582system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses 583system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses 584system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21881.700574 # average ReadReq mshr miss latency 585system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21881.700574 # average ReadReq mshr miss latency 586system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21881.700574 # average overall mshr miss latency 587system.cpu.icache.demand_avg_mshr_miss_latency::total 21881.700574 # average overall mshr miss latency 588system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21881.700574 # average overall mshr miss latency 589system.cpu.icache.overall_avg_mshr_miss_latency::total 21881.700574 # average overall mshr miss latency |
590system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
591system.cpu.l2cache.tags.replacements 111385 # number of replacements 592system.cpu.l2cache.tags.tagsinuse 27648.726753 # Cycle average of tags in use 593system.cpu.l2cache.tags.total_refs 1684688 # Total number of references to valid blocks. 594system.cpu.l2cache.tags.sampled_refs 142574 # Sample count of references to valid blocks. 595system.cpu.l2cache.tags.avg_refs 11.816236 # Average number of references to valid blocks. 596system.cpu.l2cache.tags.warmup_cycle 163201810500 # Cycle when the warmup percentage was hit. 597system.cpu.l2cache.tags.occ_blocks::writebacks 23524.085448 # Average occupied blocks per requestor 598system.cpu.l2cache.tags.occ_blocks::cpu.inst 4124.641306 # Average occupied blocks per requestor 599system.cpu.l2cache.tags.occ_percent::writebacks 0.717898 # Average percentage of cache occupancy 600system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125874 # Average percentage of cache occupancy 601system.cpu.l2cache.tags.occ_percent::total 0.843772 # Average percentage of cache occupancy 602system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id 603system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 604system.cpu.l2cache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id 605system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4940 # Occupied blocks per task id 606system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25859 # Occupied blocks per task id 607system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id 608system.cpu.l2cache.tags.tag_accesses 18355203 # Number of tag accesses 609system.cpu.l2cache.tags.data_accesses 18355203 # Number of data accesses 610system.cpu.l2cache.ReadReq_hits::cpu.inst 763758 # number of ReadReq hits 611system.cpu.l2cache.ReadReq_hits::total 763758 # number of ReadReq hits 612system.cpu.l2cache.Writeback_hits::writebacks 1068569 # number of Writeback hits 613system.cpu.l2cache.Writeback_hits::total 1068569 # number of Writeback hits 614system.cpu.l2cache.ReadExReq_hits::cpu.inst 255544 # number of ReadExReq hits 615system.cpu.l2cache.ReadExReq_hits::total 255544 # number of ReadExReq hits 616system.cpu.l2cache.demand_hits::cpu.inst 1019302 # number of demand (read+write) hits 617system.cpu.l2cache.demand_hits::total 1019302 # number of demand (read+write) hits 618system.cpu.l2cache.overall_hits::cpu.inst 1019302 # number of overall hits 619system.cpu.l2cache.overall_hits::total 1019302 # number of overall hits 620system.cpu.l2cache.ReadReq_misses::cpu.inst 43287 # number of ReadReq misses 621system.cpu.l2cache.ReadReq_misses::total 43287 # number of ReadReq misses 622system.cpu.l2cache.ReadExReq_misses::cpu.inst 100869 # number of ReadExReq misses 623system.cpu.l2cache.ReadExReq_misses::total 100869 # number of ReadExReq misses 624system.cpu.l2cache.demand_misses::cpu.inst 144156 # number of demand (read+write) misses 625system.cpu.l2cache.demand_misses::total 144156 # number of demand (read+write) misses 626system.cpu.l2cache.overall_misses::cpu.inst 144156 # number of overall misses 627system.cpu.l2cache.overall_misses::total 144156 # number of overall misses 628system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3231564500 # number of ReadReq miss cycles 629system.cpu.l2cache.ReadReq_miss_latency::total 3231564500 # number of ReadReq miss cycles 630system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7196834000 # number of ReadExReq miss cycles 631system.cpu.l2cache.ReadExReq_miss_latency::total 7196834000 # number of ReadExReq miss cycles 632system.cpu.l2cache.demand_miss_latency::cpu.inst 10428398500 # number of demand (read+write) miss cycles 633system.cpu.l2cache.demand_miss_latency::total 10428398500 # number of demand (read+write) miss cycles 634system.cpu.l2cache.overall_miss_latency::cpu.inst 10428398500 # number of overall miss cycles 635system.cpu.l2cache.overall_miss_latency::total 10428398500 # number of overall miss cycles 636system.cpu.l2cache.ReadReq_accesses::cpu.inst 807045 # number of ReadReq accesses(hits+misses) 637system.cpu.l2cache.ReadReq_accesses::total 807045 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.Writeback_accesses::writebacks 1068569 # number of Writeback accesses(hits+misses) 639system.cpu.l2cache.Writeback_accesses::total 1068569 # number of Writeback accesses(hits+misses) 640system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356413 # number of ReadExReq accesses(hits+misses) 641system.cpu.l2cache.ReadExReq_accesses::total 356413 # number of ReadExReq accesses(hits+misses) 642system.cpu.l2cache.demand_accesses::cpu.inst 1163458 # number of demand (read+write) accesses 643system.cpu.l2cache.demand_accesses::total 1163458 # number of demand (read+write) accesses 644system.cpu.l2cache.overall_accesses::cpu.inst 1163458 # number of overall (read+write) accesses 645system.cpu.l2cache.overall_accesses::total 1163458 # number of overall (read+write) accesses 646system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053636 # miss rate for ReadReq accesses 647system.cpu.l2cache.ReadReq_miss_rate::total 0.053636 # miss rate for ReadReq accesses 648system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283012 # miss rate for ReadExReq accesses 649system.cpu.l2cache.ReadExReq_miss_rate::total 0.283012 # miss rate for ReadExReq accesses 650system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123903 # miss rate for demand accesses 651system.cpu.l2cache.demand_miss_rate::total 0.123903 # miss rate for demand accesses 652system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123903 # miss rate for overall accesses 653system.cpu.l2cache.overall_miss_rate::total 0.123903 # miss rate for overall accesses 654system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74654.388153 # average ReadReq miss latency 655system.cpu.l2cache.ReadReq_avg_miss_latency::total 74654.388153 # average ReadReq miss latency 656system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71348.323072 # average ReadExReq miss latency 657system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71348.323072 # average ReadExReq miss latency 658system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72341.064541 # average overall miss latency 659system.cpu.l2cache.demand_avg_miss_latency::total 72341.064541 # average overall miss latency 660system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72341.064541 # average overall miss latency 661system.cpu.l2cache.overall_avg_miss_latency::total 72341.064541 # average overall miss latency 662system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 663system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 664system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 665system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 666system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 667system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 668system.cpu.l2cache.fast_writes 0 # number of fast writes performed 669system.cpu.l2cache.cache_copies 0 # number of cache copies performed 670system.cpu.l2cache.writebacks::writebacks 96547 # number of writebacks 671system.cpu.l2cache.writebacks::total 96547 # number of writebacks 672system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits 673system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 674system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits 675system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 676system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits 677system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 678system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43270 # number of ReadReq MSHR misses 679system.cpu.l2cache.ReadReq_mshr_misses::total 43270 # number of ReadReq MSHR misses 680system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100869 # number of ReadExReq MSHR misses 681system.cpu.l2cache.ReadExReq_mshr_misses::total 100869 # number of ReadExReq MSHR misses 682system.cpu.l2cache.demand_mshr_misses::cpu.inst 144139 # number of demand (read+write) MSHR misses 683system.cpu.l2cache.demand_mshr_misses::total 144139 # number of demand (read+write) MSHR misses 684system.cpu.l2cache.overall_mshr_misses::cpu.inst 144139 # number of overall MSHR misses 685system.cpu.l2cache.overall_mshr_misses::total 144139 # number of overall MSHR misses 686system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2682518500 # number of ReadReq MSHR miss cycles 687system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2682518500 # number of ReadReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5916082000 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5916082000 # number of ReadExReq MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8598600500 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::total 8598600500 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8598600500 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::total 8598600500 # number of overall MSHR miss cycles 694system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053615 # mshr miss rate for ReadReq accesses 695system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053615 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283012 # mshr miss rate for ReadExReq accesses 697system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283012 # mshr miss rate for ReadExReq accesses 698system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for demand accesses 699system.cpu.l2cache.demand_mshr_miss_rate::total 0.123888 # mshr miss rate for demand accesses 700system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for overall accesses 701system.cpu.l2cache.overall_mshr_miss_rate::total 0.123888 # mshr miss rate for overall accesses 702system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61994.880980 # average ReadReq mshr miss latency 703system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61994.880980 # average ReadReq mshr miss latency 704system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58651.141580 # average ReadExReq mshr miss latency 705system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58651.141580 # average ReadExReq mshr miss latency 706system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency 707system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency 708system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency 709system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency 710system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 711system.cpu.toL2Bus.trans_dist::ReadReq 807045 # Transaction distribution 712system.cpu.toL2Bus.trans_dist::ReadResp 807045 # Transaction distribution 713system.cpu.toL2Bus.trans_dist::Writeback 1068569 # Transaction distribution 714system.cpu.toL2Bus.trans_dist::ReadExReq 356413 # Transaction distribution 715system.cpu.toL2Bus.trans_dist::ReadExResp 356413 # Transaction distribution 716system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39028 # Packet count per connected master and slave (bytes) 717system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356457 # Packet count per connected master and slave (bytes) 718system.cpu.toL2Bus.pkt_count::total 3395485 # Packet count per connected master and slave (bytes) 719system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1248896 # Cumulative packet size per connected master and slave (bytes) 720system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141600832 # Cumulative packet size per connected master and slave (bytes) 721system.cpu.toL2Bus.pkt_size::total 142849728 # Cumulative packet size per connected master and slave (bytes) |
722system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
723system.cpu.toL2Bus.snoop_fanout::samples 2232027 # Request fanout histogram |
724system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 725system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 726system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 727system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 728system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 729system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 730system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 731system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
732system.cpu.toL2Bus.snoop_fanout::5 2232027 100.00% 100.00% # Request fanout histogram |
733system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 734system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 735system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 736system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram |
737system.cpu.toL2Bus.snoop_fanout::total 2232027 # Request fanout histogram 738system.cpu.toL2Bus.reqLayer0.occupancy 2184582500 # Layer occupancy (ticks) |
739system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) |
740system.cpu.toL2Bus.respLayer0.occupancy 29960995 # Layer occupancy (ticks) |
741system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
742system.cpu.toL2Bus.respLayer1.occupancy 1744681985 # Layer occupancy (ticks) |
743system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) |
744system.membus.trans_dist::ReadReq 43270 # Transaction distribution 745system.membus.trans_dist::ReadResp 43270 # Transaction distribution 746system.membus.trans_dist::Writeback 96547 # Transaction distribution 747system.membus.trans_dist::ReadExReq 100869 # Transaction distribution 748system.membus.trans_dist::ReadExResp 100869 # Transaction distribution 749system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384825 # Packet count per connected master and slave (bytes) 750system.membus.pkt_count::total 384825 # Packet count per connected master and slave (bytes) 751system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15403904 # Cumulative packet size per connected master and slave (bytes) 752system.membus.pkt_size::total 15403904 # Cumulative packet size per connected master and slave (bytes) 753system.membus.snoops 0 # Total snoops (count) 754system.membus.snoop_fanout::samples 240686 # Request fanout histogram 755system.membus.snoop_fanout::mean 0 # Request fanout histogram 756system.membus.snoop_fanout::stdev 0 # Request fanout histogram 757system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 758system.membus.snoop_fanout::0 240686 100.00% 100.00% # Request fanout histogram 759system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 760system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 761system.membus.snoop_fanout::min_value 0 # Request fanout histogram 762system.membus.snoop_fanout::max_value 0 # Request fanout histogram 763system.membus.snoop_fanout::total 240686 # Request fanout histogram 764system.membus.reqLayer0.occupancy 1081853000 # Layer occupancy (ticks) 765system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 766system.membus.respLayer1.occupancy 1366563500 # Layer occupancy (ticks) 767system.membus.respLayer1.utilization 0.4 # Layer utilization (%) |
768 769---------- End Simulation Statistics ---------- |