4,5c4,5
< sim_ticks 368600034500 # Number of ticks simulated
< final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 368600047500 # Number of ticks simulated
> final_tick 368600047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 368828 # Simulator instruction rate (inst/s)
< host_op_rate 399489 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 268368313 # Simulator tick rate (ticks/s)
< host_mem_usage 276836 # Number of bytes of host memory used
< host_seconds 1373.49 # Real time elapsed on the host
---
> host_inst_rate 377886 # Simulator instruction rate (inst/s)
> host_op_rate 409300 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 274959159 # Simulator tick rate (ticks/s)
> host_mem_usage 276756 # Number of bytes of host memory used
> host_seconds 1340.56 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
30,31c30,31
< system.physmem.bw_read::cpu.data 24561517 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 25049417 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 24561516 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 25049416 # Total read bandwidth from this memory (bytes/s)
38,39c38,39
< system.physmem.bw_total::cpu.data 24561517 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 41983197 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 24561516 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 41983196 # Total bandwidth to/from this memory (bytes/s)
86c86
< system.physmem.totGap 368600009000 # Total gap between requests
---
> system.physmem.totGap 368600022000 # Total gap between requests
231,232c231,232
< system.physmem.totQLat 3577413000 # Total ticks spent queuing
< system.physmem.totMemAccLat 6280300500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3577410500 # Total ticks spent queuing
> system.physmem.totMemAccLat 6280298000 # Total ticks spent from burst creation until serviced by the DRAM
234c234
< system.physmem.avgQLat 24816.61 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 24816.59 # Average queueing delay per DRAM burst
236c236
< system.physmem.avgMemAccLat 43566.61 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 43566.59 # Average memory access latency per DRAM burst
251c251
< system.physmem.avgGap 1524419.28 # Average gap between requests
---
> system.physmem.avgGap 1524419.34 # Average gap between requests
258,265c258,265
< system.physmem_0.actBackEnergy 3985238790 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 353652480 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 24742370760 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 8329193280 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 68838779610 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 115080424995 # Total energy per rank (pJ)
< system.physmem_0.averagePower 312.209476 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 358934915250 # Total Idle time Per DRAM Rank
---
> system.physmem_0.actBackEnergy 3985232520 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 353635200 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 24742392420 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 8329190880 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 68838786810 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 115080429525 # Total energy per rank (pJ)
> system.physmem_0.averagePower 312.209478 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 358934929250 # Total Idle time Per DRAM Rank
268,271c268,271
< system.physmem_0.memoryStateTime::SREF 282985145000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 21690770000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 5858999750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 54259446500 # Time in different power states
---
> system.physmem_0.memoryStateTime::SREF 282985158000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 21690772000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 5858998750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 54259445500 # Time in different power states
277,284c277,284
< system.physmem_1.actBackEnergy 3990658350 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 342745440 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 24389253480 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 8128930080 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 69135041760 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 114698280525 # Total energy per rank (pJ)
< system.physmem_1.averagePower 311.172732 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 358951286500 # Total Idle time Per DRAM Rank
---
> system.physmem_1.actBackEnergy 3990680010 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 342748800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 24389261460 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 8128903200 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 69135043560 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 114698287785 # Total energy per rank (pJ)
> system.physmem_1.averagePower 311.172742 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 358951299500 # Total Idle time Per DRAM Rank
287c287
< system.physmem_1.memoryStateTime::SREF 284296674500 # Time in different power states
---
> system.physmem_1.memoryStateTime::SREF 284296687500 # Time in different power states
291c291
< system.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
306c306
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
336c336
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
366c366
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
396c396
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
427,428c427,428
< system.cpu.pwrStateResidencyTicks::ON 368600034500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 737200069 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 368600047500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 737200095 # number of cpu cycles simulated
476,478c476,478
< system.cpu.tickCycles 694074439 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 43125630 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 694074449 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 43125646 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
480,481c480,481
< system.cpu.dcache.tags.tagsinuse 4070.214597 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 171083824 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4070.214598 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 171083823 # Total number of references to valid blocks.
485c485
< system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214597 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214598 # Average occupied blocks per requestor
494,498c494,498
< system.cpu.dcache.tags.tag_accesses 346338045 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 346338045 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 114566013 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 114566013 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 346338043 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 346338043 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 114566012 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 114566012 # number of ReadReq hits
507,510c507,510
< system.cpu.dcache.demand_hits::cpu.data 168103948 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168103948 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168106742 # number of overall hits
< system.cpu.dcache.overall_hits::total 168106742 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 168103947 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168103947 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168106741 # number of overall hits
> system.cpu.dcache.overall_hits::total 168106741 # number of overall hits
521,530c521,530
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511838000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 14511838000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015669000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 24015669000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 38527507000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 38527507000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 38527507000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 38527507000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 115377366 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 115377366 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511839000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 14511839000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015670000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 24015670000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 38527509000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 38527509000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 38527509000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 38527509000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 115377365 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 115377365 # number of ReadReq accesses(hits+misses)
539,542c539,542
< system.cpu.dcache.demand_accesses::cpu.data 169616415 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 169616415 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 169619224 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 169619224 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 169616414 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 169616414 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 169619223 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 169619223 # number of overall (read+write) accesses
553,560c553,560
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 25473.287682 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 25473.035051 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 25473.289004 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 25473.036373 # average overall miss latency
587,590c587,590
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416891000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416891000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416892000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416892000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191500 # number of WriteReq MSHR miss cycles
593,596c593,596
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613082000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 25613082000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617379000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 25617379000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613083500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 25613083500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617380500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 25617380500 # number of overall MSHR miss cycles
607,610c607,610
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116 # average WriteReq mshr miss latency
613,617c613,617
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
619,620c619,620
< system.cpu.icache.tags.tagsinuse 1186.508914 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 199149017 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1186.508929 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 199149019 # Total number of references to valid blocks.
622c622
< system.cpu.icache.tags.avg_refs 9932.619302 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 9932.619401 # Average number of references to valid blocks.
624c624
< system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508914 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508929 # Average occupied blocks per requestor
634,642c634,642
< system.cpu.icache.tags.tag_accesses 398358184 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 398358184 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 199149017 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 199149017 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 199149017 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 199149017 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 199149017 # number of overall hits
< system.cpu.icache.overall_hits::total 199149017 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 398358188 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 398358188 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 199149019 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 199149019 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 199149019 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 199149019 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 199149019 # number of overall hits
> system.cpu.icache.overall_hits::total 199149019 # number of overall hits
649,660c649,660
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 544281000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 544281000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 544281000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 544281000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 544281000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 544281000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 199169067 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 199169067 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 199169067 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 199169067 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 199169067 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 199169067 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 544279500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 544279500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 544279500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 544279500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 544279500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 544279500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 199169069 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 199169069 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 199169069 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 199169069 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 199169069 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 199169069 # number of overall (read+write) accesses
667,672c667,672
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 27146.184539 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 27146.184539 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.109726 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 27146.109726 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 27146.109726 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 27146.109726 # average overall miss latency
687,692c687,692
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524231000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 524231000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524231000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 524231000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524231000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 524231000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524229500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 524229500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524229500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 524229500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524229500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 524229500 # number of overall MSHR miss cycles
699,705c699,705
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.109726 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.109726 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
707c707
< system.cpu.l2cache.tags.tagsinuse 29076.847904 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 29076.848035 # Cycle average of tags in use
712,714c712,714
< system.cpu.l2cache.tags.occ_blocks::writebacks 133.889042 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541070 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 133.889045 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541066 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417923 # Average occupied blocks per requestor
727c727
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
756,763c756,763
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8979653000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312477500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 312477500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360667500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360667500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 312477500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13340320500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8979653500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312476000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 312476000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360668500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360668500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 312476000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13340322000 # number of demand (read+write) miss cycles
765,766c765,766
< system.cpu.l2cache.overall_miss_latency::cpu.inst 312477500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13340320500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 312476000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13340322000 # number of overall miss cycles
796,803c796,803
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.830597 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.830597 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111161.864105 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111161.864105 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.780758 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.780758 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency
805,806c805,806
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency
838,845c838,845
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284302500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284302500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953965500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953965500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284302500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923838500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284301000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284301000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953966500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953966500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284301000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923840000 # number of demand (read+write) MSHR miss cycles
847,848c847,848
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284302500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923838500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284301000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923840000 # number of overall MSHR miss cycles
862,869c862,869
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.830597 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.830597 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101174.733096 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101174.733096 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.625133 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.625133 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency
871,872c871,872
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency
880c880
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
920c920
< system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
943c943
< system.membus.reqLayer0.occupancy 685124000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 685127000 # Layer occupancy (ticks)
945c945
< system.membus.respLayer1.occupancy 765885250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 765884750 # Layer occupancy (ticks)
< sim_ticks 368600034500 # Number of ticks simulated
< final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 368600047500 # Number of ticks simulated
> final_tick 368600047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 368828 # Simulator instruction rate (inst/s)
< host_op_rate 399489 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 268368313 # Simulator tick rate (ticks/s)
< host_mem_usage 276836 # Number of bytes of host memory used
< host_seconds 1373.49 # Real time elapsed on the host
---
> host_inst_rate 377886 # Simulator instruction rate (inst/s)
> host_op_rate 409300 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 274959159 # Simulator tick rate (ticks/s)
> host_mem_usage 276756 # Number of bytes of host memory used
> host_seconds 1340.56 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
30,31c30,31
< system.physmem.bw_read::cpu.data 24561517 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 25049417 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 24561516 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 25049416 # Total read bandwidth from this memory (bytes/s)
38,39c38,39
< system.physmem.bw_total::cpu.data 24561517 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 41983197 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 24561516 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 41983196 # Total bandwidth to/from this memory (bytes/s)
86c86
< system.physmem.totGap 368600009000 # Total gap between requests
---
> system.physmem.totGap 368600022000 # Total gap between requests
231,232c231,232
< system.physmem.totQLat 3577413000 # Total ticks spent queuing
< system.physmem.totMemAccLat 6280300500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3577410500 # Total ticks spent queuing
> system.physmem.totMemAccLat 6280298000 # Total ticks spent from burst creation until serviced by the DRAM
234c234
< system.physmem.avgQLat 24816.61 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 24816.59 # Average queueing delay per DRAM burst
236c236
< system.physmem.avgMemAccLat 43566.61 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 43566.59 # Average memory access latency per DRAM burst
251c251
< system.physmem.avgGap 1524419.28 # Average gap between requests
---
> system.physmem.avgGap 1524419.34 # Average gap between requests
258,265c258,265
< system.physmem_0.actBackEnergy 3985238790 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 353652480 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 24742370760 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 8329193280 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 68838779610 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 115080424995 # Total energy per rank (pJ)
< system.physmem_0.averagePower 312.209476 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 358934915250 # Total Idle time Per DRAM Rank
---
> system.physmem_0.actBackEnergy 3985232520 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 353635200 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 24742392420 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 8329190880 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 68838786810 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 115080429525 # Total energy per rank (pJ)
> system.physmem_0.averagePower 312.209478 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 358934929250 # Total Idle time Per DRAM Rank
268,271c268,271
< system.physmem_0.memoryStateTime::SREF 282985145000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 21690770000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 5858999750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 54259446500 # Time in different power states
---
> system.physmem_0.memoryStateTime::SREF 282985158000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 21690772000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 5858998750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 54259445500 # Time in different power states
277,284c277,284
< system.physmem_1.actBackEnergy 3990658350 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 342745440 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 24389253480 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 8128930080 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 69135041760 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 114698280525 # Total energy per rank (pJ)
< system.physmem_1.averagePower 311.172732 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 358951286500 # Total Idle time Per DRAM Rank
---
> system.physmem_1.actBackEnergy 3990680010 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 342748800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 24389261460 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 8128903200 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 69135043560 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 114698287785 # Total energy per rank (pJ)
> system.physmem_1.averagePower 311.172742 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 358951299500 # Total Idle time Per DRAM Rank
287c287
< system.physmem_1.memoryStateTime::SREF 284296674500 # Time in different power states
---
> system.physmem_1.memoryStateTime::SREF 284296687500 # Time in different power states
291c291
< system.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
306c306
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
336c336
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
366c366
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
396c396
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
427,428c427,428
< system.cpu.pwrStateResidencyTicks::ON 368600034500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 737200069 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 368600047500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 737200095 # number of cpu cycles simulated
476,478c476,478
< system.cpu.tickCycles 694074439 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 43125630 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 694074449 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 43125646 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
480,481c480,481
< system.cpu.dcache.tags.tagsinuse 4070.214597 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 171083824 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4070.214598 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 171083823 # Total number of references to valid blocks.
485c485
< system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214597 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214598 # Average occupied blocks per requestor
494,498c494,498
< system.cpu.dcache.tags.tag_accesses 346338045 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 346338045 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 114566013 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 114566013 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 346338043 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 346338043 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 114566012 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 114566012 # number of ReadReq hits
507,510c507,510
< system.cpu.dcache.demand_hits::cpu.data 168103948 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168103948 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168106742 # number of overall hits
< system.cpu.dcache.overall_hits::total 168106742 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 168103947 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168103947 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168106741 # number of overall hits
> system.cpu.dcache.overall_hits::total 168106741 # number of overall hits
521,530c521,530
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511838000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 14511838000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015669000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 24015669000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 38527507000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 38527507000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 38527507000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 38527507000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 115377366 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 115377366 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511839000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 14511839000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015670000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 24015670000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 38527509000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 38527509000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 38527509000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 38527509000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 115377365 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 115377365 # number of ReadReq accesses(hits+misses)
539,542c539,542
< system.cpu.dcache.demand_accesses::cpu.data 169616415 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 169616415 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 169619224 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 169619224 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 169616414 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 169616414 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 169619223 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 169619223 # number of overall (read+write) accesses
553,560c553,560
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 25473.287682 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 25473.035051 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 25473.289004 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 25473.036373 # average overall miss latency
587,590c587,590
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416891000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416891000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416892000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416892000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191500 # number of WriteReq MSHR miss cycles
593,596c593,596
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613082000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 25613082000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617379000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 25617379000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613083500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 25613083500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617380500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 25617380500 # number of overall MSHR miss cycles
607,610c607,610
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116 # average WriteReq mshr miss latency
613,617c613,617
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
619,620c619,620
< system.cpu.icache.tags.tagsinuse 1186.508914 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 199149017 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1186.508929 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 199149019 # Total number of references to valid blocks.
622c622
< system.cpu.icache.tags.avg_refs 9932.619302 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 9932.619401 # Average number of references to valid blocks.
624c624
< system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508914 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508929 # Average occupied blocks per requestor
634,642c634,642
< system.cpu.icache.tags.tag_accesses 398358184 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 398358184 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 199149017 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 199149017 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 199149017 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 199149017 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 199149017 # number of overall hits
< system.cpu.icache.overall_hits::total 199149017 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 398358188 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 398358188 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 199149019 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 199149019 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 199149019 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 199149019 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 199149019 # number of overall hits
> system.cpu.icache.overall_hits::total 199149019 # number of overall hits
649,660c649,660
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 544281000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 544281000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 544281000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 544281000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 544281000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 544281000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 199169067 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 199169067 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 199169067 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 199169067 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 199169067 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 199169067 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 544279500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 544279500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 544279500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 544279500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 544279500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 544279500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 199169069 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 199169069 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 199169069 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 199169069 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 199169069 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 199169069 # number of overall (read+write) accesses
667,672c667,672
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 27146.184539 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 27146.184539 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.109726 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 27146.109726 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 27146.109726 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 27146.109726 # average overall miss latency
687,692c687,692
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524231000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 524231000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524231000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 524231000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524231000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 524231000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524229500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 524229500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524229500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 524229500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524229500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 524229500 # number of overall MSHR miss cycles
699,705c699,705
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.109726 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.109726 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
707c707
< system.cpu.l2cache.tags.tagsinuse 29076.847904 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 29076.848035 # Cycle average of tags in use
712,714c712,714
< system.cpu.l2cache.tags.occ_blocks::writebacks 133.889042 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541070 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 133.889045 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541066 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417923 # Average occupied blocks per requestor
727c727
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
756,763c756,763
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8979653000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312477500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 312477500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360667500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360667500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 312477500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13340320500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8979653500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312476000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 312476000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360668500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360668500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 312476000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13340322000 # number of demand (read+write) miss cycles
765,766c765,766
< system.cpu.l2cache.overall_miss_latency::cpu.inst 312477500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13340320500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 312476000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13340322000 # number of overall miss cycles
796,803c796,803
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.830597 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.830597 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111161.864105 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111161.864105 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.780758 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.780758 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency
805,806c805,806
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency
838,845c838,845
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284302500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284302500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953965500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953965500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284302500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923838500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284301000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284301000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953966500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953966500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284301000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923840000 # number of demand (read+write) MSHR miss cycles
847,848c847,848
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284302500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923838500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284301000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923840000 # number of overall MSHR miss cycles
862,869c862,869
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.830597 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.830597 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101174.733096 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101174.733096 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.625133 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.625133 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency
871,872c871,872
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency
880c880
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
920c920
< system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
943c943
< system.membus.reqLayer0.occupancy 685124000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 685127000 # Layer occupancy (ticks)
945c945
< system.membus.respLayer1.occupancy 765885250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 765884750 # Layer occupancy (ticks)