3,5c3,5
< sim_seconds 0.366632 # Number of seconds simulated
< sim_ticks 366631719500 # Number of ticks simulated
< final_tick 366631719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.368600 # Number of seconds simulated
> sim_ticks 368600034500 # Number of ticks simulated
> final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 211005 # Simulator instruction rate (inst/s)
< host_op_rate 228546 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 152712719 # Simulator tick rate (ticks/s)
< host_mem_usage 277288 # Number of bytes of host memory used
< host_seconds 2400.79 # Real time elapsed on the host
---
> host_inst_rate 189198 # Simulator instruction rate (inst/s)
> host_op_rate 204927 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 137665575 # Simulator tick rate (ticks/s)
> host_mem_usage 274600 # Number of bytes of host memory used
> host_seconds 2677.50 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
29,39c29,39
< system.physmem.bw_read::cpu.inst 490519 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 24693379 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 25183898 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 490519 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 490519 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 17024692 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 17024692 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 17024692 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 490519 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 24693379 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 42208590 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 24561517 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 25049417 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 24561517 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 41983197 # Total bandwidth to/from this memory (bytes/s)
44,46c44,46
< system.physmem.bytesReadDRAM 9226688 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6240064 # Total number of bytes written to DRAM
---
> system.physmem.bytesReadDRAM 9225856 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6240448 # Total number of bytes written to DRAM
49c49
< system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue
52c52
< system.physmem.perBankRdBursts::0 9376 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 9372 # Per bank write bursts
54,57c54,57
< system.physmem.perBankRdBursts::2 8964 # Per bank write bursts
< system.physmem.perBankRdBursts::3 8666 # Per bank write bursts
< system.physmem.perBankRdBursts::4 9423 # Per bank write bursts
< system.physmem.perBankRdBursts::5 9371 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 8963 # Per bank write bursts
> system.physmem.perBankRdBursts::3 8667 # Per bank write bursts
> system.physmem.perBankRdBursts::4 9424 # Per bank write bursts
> system.physmem.perBankRdBursts::5 9372 # Per bank write bursts
59,60c59,60
< system.physmem.perBankRdBursts::7 8126 # Per bank write bursts
< system.physmem.perBankRdBursts::8 8634 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 8127 # Per bank write bursts
> system.physmem.perBankRdBursts::8 8635 # Per bank write bursts
62,68c62,68
< system.physmem.perBankRdBursts::10 8760 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9487 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9347 # Per bank write bursts
< system.physmem.perBankRdBursts::13 9550 # Per bank write bursts
< system.physmem.perBankRdBursts::14 8728 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9135 # Per bank write bursts
< system.physmem.perBankWrBursts::0 6252 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 8761 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9485 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9346 # Per bank write bursts
> system.physmem.perBankRdBursts::13 9545 # Per bank write bursts
> system.physmem.perBankRdBursts::14 8729 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9128 # Per bank write bursts
> system.physmem.perBankWrBursts::0 6253 # Per bank write bursts
75,76c75,76
< system.physmem.perBankWrBursts::7 5534 # Per bank write bursts
< system.physmem.perBankWrBursts::8 5815 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 5535 # Per bank write bursts
> system.physmem.perBankWrBursts::8 5819 # Per bank write bursts
86c86
< system.physmem.totGap 366631694000 # Total gap between requests
---
> system.physmem.totGap 368600009000 # Total gap between requests
101,103c101,103
< system.physmem.rdQLenPdf::0 143840 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 311 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 143801 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 333 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
148,173c148,173
< system.physmem.wrQLenPdf::15 2842 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2979 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5670 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5725 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5731 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5730 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5730 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5734 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 5731 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5736 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5741 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5739 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5754 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5737 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5732 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5729 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5727 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2730 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5739 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5742 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5743 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5744 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5746 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5749 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5745 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5752 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5747 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
197,215c197,214
< system.physmem.bytesPerActivate::samples 63306 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 244.314283 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 163.017060 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 244.594379 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 22538 35.60% 35.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17961 28.37% 63.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 7327 11.57% 75.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7996 12.63% 88.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2051 3.24% 91.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1180 1.86% 93.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 835 1.32% 94.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 660 1.04% 95.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 2758 4.36% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63306 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5727 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 25.172342 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 18.597400 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 376.088417 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 5724 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 63970 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 241.763327 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 162.115864 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 241.210402 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22774 35.60% 35.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 18302 28.61% 64.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 7461 11.66% 75.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 8049 12.58% 88.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2117 3.31% 91.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1180 1.84% 93.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 776 1.21% 94.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 623 0.97% 95.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 2688 4.20% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63970 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5740 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 25.113240 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 375.658190 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 5737 99.95% 99.95% # Reads before turning the bus around for writes
218,234c217,234
< system.physmem.rdPerTurnAround::total 5727 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5727 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.024795 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.995243 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.004050 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 2743 47.90% 47.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 142 2.48% 50.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 2814 49.14% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 20 0.35% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 6 0.10% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5727 # Writes before turning the bus around for reads
< system.physmem.totQLat 1581653750 # Total ticks spent queuing
< system.physmem.totMemAccLat 4284785000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 720835000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10970.98 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5740 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5740 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.987282 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.957535 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.009458 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 2852 49.69% 49.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 159 2.77% 52.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 2701 47.06% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 19 0.33% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 6 0.10% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads
> system.physmem.totQLat 3577413000 # Total ticks spent queuing
> system.physmem.totMemAccLat 6280300500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 720770000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 24816.61 # Average queueing delay per DRAM burst
236,240c236,240
< system.physmem.avgMemAccLat 29720.98 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 43566.61 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 16.93 # Average system write bandwidth in MiByte/s
246,283c246,293
< system.physmem.avgWrQLen 20.20 # Average write queue length when enqueuing
< system.physmem.readRowHits 110439 # Number of row buffer hits during reads
< system.physmem.writeRowHits 67921 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 76.60 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes
< system.physmem.avgGap 1516278.92 # Average gap between requests
< system.physmem.pageHitRate 73.80 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 239652000 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 130762500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 560266200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 313968960 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 47282173740 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 178503263250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 250976651370 # Total energy per rank (pJ)
< system.physmem_0.averagePower 684.547573 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 296644648000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 12242620000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 57744168750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 238941360 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 130374750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 564213000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 317837520 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 47121480765 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 178644216000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 250963628115 # Total energy per rank (pJ)
< system.physmem_1.averagePower 684.512070 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 296880094250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 12242620000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 57508713250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 132103795 # Number of BP lookups
< system.cpu.branchPred.condPredicted 98193288 # Number of conditional branches predicted
---
> system.physmem.avgWrQLen 20.06 # Average write queue length when enqueuing
> system.physmem.readRowHits 110541 # Number of row buffer hits during reads
> system.physmem.writeRowHits 67141 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes
> system.physmem.avgGap 1524419.28 # Average gap between requests
> system.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 3985238790 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 353652480 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 24742370760 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 8329193280 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 68838779610 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 115080424995 # Total energy per rank (pJ)
> system.physmem_0.averagePower 312.209476 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 358934915250 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 282985145000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 21690770000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 5858999750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 54259446500 # Time in different power states
> system.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 3990658350 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 342745440 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 24389253480 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 8128930080 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 69135041760 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 114698280525 # Total energy per rank (pJ)
> system.physmem_1.averagePower 311.172732 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 358951286500 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 284296674500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 132103819 # Number of BP lookups
> system.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted
285,286c295,296
< system.cpu.branchPred.BTBLookups 68601542 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 60590460 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 68601561 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 60590477 # Number of BTB hits
288,289c298,299
< system.cpu.branchPred.BTBHitPct 88.322300 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 88.322301 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 10017121 # Number of times the RAS was used to get a target.
291,292c301,302
< system.cpu.branchPred.indirectLookups 3891574 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits.
---
> system.cpu.branchPred.indirectLookups 3891575 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 3883028 # Number of indirect target hits.
296c306
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
326c336
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
356c366
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
386c396
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
417,418c427,428
< system.cpu.pwrStateResidencyTicks::ON 366631719500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 733263439 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 368600034500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 737200069 # number of cpu cycles simulated
423c433
< system.cpu.discardedOps 12939754 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 12939783 # Number of ops (including micro ops) which were discarded before commit
425,426c435,436
< system.cpu.cpi 1.447480 # CPI: cycles per instruction
< system.cpu.ipc 0.690856 # IPC: instructions per cycle
---
> system.cpu.cpi 1.455251 # CPI: cycles per instruction
> system.cpu.ipc 0.687167 # IPC: instructions per cycle
462,464c472,474
< system.cpu.tickCycles 694072576 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 39190863 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 694074439 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 43125630 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
466,467c476,477
< system.cpu.dcache.tags.tagsinuse 4070.301946 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 171083822 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4070.214597 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 171083824 # Total number of references to valid blocks.
469,473c479,483
< system.cpu.dcache.tags.avg_refs 149.361702 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 5036525500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4070.301946 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.993726 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.993726 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214597 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy
475,478c485,488
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id
480,486c490,496
< system.cpu.dcache.tags.tag_accesses 346338109 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 346338109 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 114566017 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 114566017 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 346338045 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 346338045 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 114566013 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 114566013 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits
493,500c503,510
< system.cpu.dcache.demand_hits::cpu.data 168103946 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168103946 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168106740 # number of overall hits
< system.cpu.dcache.overall_hits::total 168106740 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 701120 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 168103948 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168103948 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168106742 # number of overall hits
> system.cpu.dcache.overall_hits::total 168106742 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 701114 # number of WriteReq misses
503,516c513,526
< system.cpu.dcache.demand_misses::cpu.data 1512501 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses
< system.cpu.dcache.overall_misses::total 1512516 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 13515584500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 13515584500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 22200332500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 22200332500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 35715917000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 35715917000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 35715917000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 35715917000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 115377398 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 115377398 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 1512467 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses
> system.cpu.dcache.overall_misses::total 1512482 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511838000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 14511838000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015669000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 24015669000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 38527507000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 38527507000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 38527507000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 38527507000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 115377366 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 115377366 # number of ReadReq accesses(hits+misses)
525,528c535,538
< system.cpu.dcache.demand_accesses::cpu.data 169616447 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 169616447 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 169619256 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 169619256 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 169616415 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 169616415 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 169619224 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 169619224 # number of overall (read+write) accesses
539,546c549,556
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 23613.813809 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 23613.579625 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 25473.287682 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 25473.035051 # average overall miss latency
555,562c565,572
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 344732 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 367080 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 367080 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 367080 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 367080 # number of overall MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22320 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 22320 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344726 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 344726 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 367046 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 367046 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 367046 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 367046 # number of overall MSHR hits
573,582c583,592
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12423186500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 12423186500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11274063500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11274063500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 942500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 942500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23697250000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23697250000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23698192500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23698192500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416891000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416891000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613082000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 25613082000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617379000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 25617379000 # number of overall MSHR miss cycles
593,608c603,618
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 18175 # number of replacements
< system.cpu.icache.tags.tagsinuse 1187.102530 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 199148962 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 9934.102958 # Average number of references to valid blocks.
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 18178 # number of replacements
> system.cpu.icache.tags.tagsinuse 1186.508914 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 199149017 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 20050 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 9932.619302 # Average number of references to valid blocks.
610,612c620,622
< system.cpu.icache.tags.occ_blocks::cpu.inst 1187.102530 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.579640 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.579640 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508914 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy
620,646c630,656
< system.cpu.icache.tags.tag_accesses 398358065 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 398358065 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 199148962 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 199148962 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 199148962 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 199148962 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 199148962 # number of overall hits
< system.cpu.icache.overall_hits::total 199148962 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 20047 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 20047 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 20047 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 20047 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 20047 # number of overall misses
< system.cpu.icache.overall_misses::total 20047 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 467837000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 467837000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 467837000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 467837000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 467837000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 467837000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 199169009 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 199169009 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 199169009 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 199169009 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 199169009 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 199169009 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 398358184 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 398358184 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 199149017 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 199149017 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 199149017 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 199149017 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 199149017 # number of overall hits
> system.cpu.icache.overall_hits::total 199149017 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 20050 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 20050 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 20050 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 20050 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 20050 # number of overall misses
> system.cpu.icache.overall_misses::total 20050 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 544281000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 544281000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 544281000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 544281000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 544281000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 544281000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 199169067 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 199169067 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 199169067 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 199169067 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 199169067 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 199169067 # number of overall (read+write) accesses
653,658c663,668
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23337.008031 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 23337.008031 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 23337.008031 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 23337.008031 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 27146.184539 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 27146.184539 # average overall miss latency
665,678c675,688
< system.cpu.icache.writebacks::writebacks 18175 # number of writebacks
< system.cpu.icache.writebacks::total 18175 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20047 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 20047 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 20047 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 447790000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 447790000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 447790000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 447790000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 447790000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 447790000 # number of overall MSHR miss cycles
---
> system.cpu.icache.writebacks::writebacks 18178 # number of writebacks
> system.cpu.icache.writebacks::total 18178 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20050 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 20050 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 20050 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 20050 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 20050 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 20050 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524231000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 524231000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524231000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 524231000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524231000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 524231000 # number of overall MSHR miss cycles
685,691c695,701
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
693,694c703,704
< system.cpu.l2cache.tags.tagsinuse 29068.883602 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2174452 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 29076.847904 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2174458 # Total number of references to valid blocks.
696,704c706,714
< system.cpu.l2cache.tags.avg_refs 14.941709 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 101788000000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 134.067060 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.855024 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.004091 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009395 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.873626 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.887112 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.avg_refs 14.941750 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 102118428000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 133.889042 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541070 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.004086 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009385 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.873884 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.887355 # Average percentage of cache occupancy
711,713c721,723
< system.cpu.l2cache.tags.tag_accesses 18705497 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 18705497 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.tag_accesses 18705537 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 18705537 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
716,717c726,727
< system.cpu.l2cache.WritebackClean_hits::writebacks 17938 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 17938 # number of WritebackClean hits
---
> system.cpu.l2cache.WritebackClean_hits::writebacks 17940 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 17940 # number of WritebackClean hits
720,721c730,731
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17235 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 17235 # number of ReadCleanReq hits
---
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17239 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 17239 # number of ReadCleanReq hits
724c734
< system.cpu.l2cache.demand_hits::cpu.inst 17235 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 17239 # number of demand (read+write) hits
726,727c736,737
< system.cpu.l2cache.demand_hits::total 1021196 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 17235 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 1021200 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 17239 # number of overall hits
729c739
< system.cpu.l2cache.overall_hits::total 1021196 # number of overall hits
---
> system.cpu.l2cache.overall_hits::total 1021200 # number of overall hits
732,733c742,743
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2812 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 2812 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses
736c746
< system.cpu.l2cache.demand_misses::cpu.inst 2812 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 2811 # number of demand (read+write) misses
738,739c748,749
< system.cpu.l2cache.demand_misses::total 144284 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2812 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 144283 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses
741,753c751,763
< system.cpu.l2cache.overall_misses::total 144284 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8057525500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8057525500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236084500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 236084500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3363607000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 3363607000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 236084500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11421132500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11657217000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 236084500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11421132500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11657217000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::total 144283 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8979653000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312477500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 312477500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360667500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360667500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 312477500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13340320500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 13652798000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 312477500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13340320500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 13652798000 # number of overall miss cycles
756,757c766,767
< system.cpu.l2cache.WritebackClean_accesses::writebacks 17938 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 17938 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.WritebackClean_accesses::writebacks 17940 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 17940 # number of WritebackClean accesses(hits+misses)
760,761c770,771
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20047 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 20047 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20050 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 20050 # number of ReadCleanReq accesses(hits+misses)
764c774
< system.cpu.l2cache.demand_accesses::cpu.inst 20047 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 20050 # number of demand (read+write) accesses
766,767c776,777
< system.cpu.l2cache.demand_accesses::total 1165480 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 20047 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 1165483 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 20050 # number of overall (read+write) accesses
769c779
< system.cpu.l2cache.overall_accesses::total 1165480 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 1165483 # number of overall (read+write) accesses
772,773c782,783
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140270 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140270 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140200 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140200 # miss rate for ReadCleanReq accesses
776c786
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140270 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140200 # miss rate for demand accesses
778,779c788,789
< system.cpu.l2cache.demand_miss_rate::total 0.123798 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140270 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.123797 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140200 # miss rate for overall accesses
781,793c791,803
< system.cpu.l2cache.overall_miss_rate::total 0.123798 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79794.861257 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79794.861257 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83956.081081 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83956.081081 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83064.330518 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83064.330518 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 80793.552993 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 80793.552993 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.123797 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552 # average overall miss latency
802,803c812,813
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
---
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
806c816
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
808,809c818,819
< system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
811c821
< system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits
---
> system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
824,835c834,845
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7047745500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7047745500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207624000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207624000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2957433000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2957433000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207624000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10005178500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10212802500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207624000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10005178500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 10212802500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284302500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284302500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953965500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953965500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284302500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923838500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 12208141000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284302500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923838500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 12208141000 # number of overall MSHR miss cycles
838,839c848,849
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140171 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140150 # mshr miss rate for ReadCleanReq accesses
842c852
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for demand accesses
845c855
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for overall accesses
848,862c858,872
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.861257 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.861257 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73887.544484 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 2324998 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159585 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
866,867c876,877
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution
869c879
< system.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution
873c883
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 20050 # Transaction distribution
875c885
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58269 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58278 # Packet count per connected master and slave (bytes)
877,878c887,888
< system.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 3490481 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446592 # Cumulative packet size per connected master and slave (bytes)
880c890
< system.cpu.toL2Bus.pkt_size::total 144166208 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 144166592 # Cumulative packet size per connected master and slave (bytes)
883,885c893,895
< system.cpu.toL2Bus.snoop_fanout::samples 1278241 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.006014 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.077345 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 1278244 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.006015 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.077350 # Request fanout histogram
887,888c897,898
< system.cpu.toL2Bus.snoop_fanout::0 1270557 99.40% 99.40% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 7681 0.60% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1270559 99.40% 99.40% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 7682 0.60% 100.00% # Request fanout histogram
893,894c903,904
< system.cpu.toL2Bus.snoop_fanout::total 1278241 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2249613000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1278244 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2249619000 # Layer occupancy (ticks)
896c906
< system.cpu.toL2Bus.respLayer0.occupancy 30094452 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 30098453 # Layer occupancy (ticks)
906c916
< system.membus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
929c939
< system.membus.reqLayer0.occupancy 685129000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 685124000 # Layer occupancy (ticks)
931c941
< system.membus.respLayer1.occupancy 765930250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 765885250 # Layer occupancy (ticks)