Cross Reference: /gem5/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

Deleted Added

sdiff udiff text old ( 11570:4aac82f10951 ) new ( 11606:6b749761c398 )

full compact

3,5c3,5
< sim_seconds 0.366439 # Number of seconds simulated
< sim_ticks 366439129500 # Number of ticks simulated
< final_tick 366439129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.366632 # Number of seconds simulated
> sim_ticks 366631719500 # Number of ticks simulated
> final_tick 366631719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 188596 # Simulator instruction rate (inst/s)
< host_op_rate 204275 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 136422977 # Simulator tick rate (ticks/s)
< host_mem_usage 271112 # Number of bytes of host memory used
< host_seconds 2686.05 # Real time elapsed on the host
---
> host_inst_rate 211005 # Simulator instruction rate (inst/s)
> host_op_rate 228546 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 152712719 # Simulator tick rate (ticks/s)
> host_mem_usage 277288 # Number of bytes of host memory used
> host_seconds 2400.79 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 9028544 # Number of bytes read from this memory
< system.physmem.bytes_read::total 9208384 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory
> system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory
22,23c22,23
< system.physmem.bytes_written::writebacks 6219648 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6219648 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory
25,49c25,49
< system.physmem.num_reads::cpu.data 141071 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 143881 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 97182 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 97182 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 490777 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 24638591 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 25129369 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 490777 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 490777 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 16973209 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 16973209 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 16973209 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 490777 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 24638591 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 42102578 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 143881 # Number of read requests accepted
< system.physmem.writeReqs 97182 # Number of write requests accepted
< system.physmem.readBursts 143881 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 97182 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 9201344 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6217600 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 9208384 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 6219648 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 490519 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 24693379 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 25183898 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 490519 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 490519 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 17024692 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 17024692 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 17024692 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 490519 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 24693379 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 42208590 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 144269 # Number of read requests accepted
> system.physmem.writeReqs 97528 # Number of write requests accepted
> system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 9226688 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6240064 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue
52,83c52,83
< system.physmem.perBankRdBursts::0 9364 # Per bank write bursts
< system.physmem.perBankRdBursts::1 8912 # Per bank write bursts
< system.physmem.perBankRdBursts::2 8949 # Per bank write bursts
< system.physmem.perBankRdBursts::3 8655 # Per bank write bursts
< system.physmem.perBankRdBursts::4 9392 # Per bank write bursts
< system.physmem.perBankRdBursts::5 9355 # Per bank write bursts
< system.physmem.perBankRdBursts::6 8959 # Per bank write bursts
< system.physmem.perBankRdBursts::7 8100 # Per bank write bursts
< system.physmem.perBankRdBursts::8 8596 # Per bank write bursts
< system.physmem.perBankRdBursts::9 8629 # Per bank write bursts
< system.physmem.perBankRdBursts::10 8739 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9451 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9334 # Per bank write bursts
< system.physmem.perBankRdBursts::13 9512 # Per bank write bursts
< system.physmem.perBankRdBursts::14 8707 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9117 # Per bank write bursts
< system.physmem.perBankWrBursts::0 6231 # Per bank write bursts
< system.physmem.perBankWrBursts::1 6102 # Per bank write bursts
< system.physmem.perBankWrBursts::2 6028 # Per bank write bursts
< system.physmem.perBankWrBursts::3 5879 # Per bank write bursts
< system.physmem.perBankWrBursts::4 6243 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6239 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6050 # Per bank write bursts
< system.physmem.perBankWrBursts::7 5507 # Per bank write bursts
< system.physmem.perBankWrBursts::8 5786 # Per bank write bursts
< system.physmem.perBankWrBursts::9 5859 # Per bank write bursts
< system.physmem.perBankWrBursts::10 5978 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6493 # Per bank write bursts
< system.physmem.perBankWrBursts::12 6351 # Per bank write bursts
< system.physmem.perBankWrBursts::13 6319 # Per bank write bursts
< system.physmem.perBankWrBursts::14 5995 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6090 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 9376 # Per bank write bursts
> system.physmem.perBankRdBursts::1 8929 # Per bank write bursts
> system.physmem.perBankRdBursts::2 8964 # Per bank write bursts
> system.physmem.perBankRdBursts::3 8666 # Per bank write bursts
> system.physmem.perBankRdBursts::4 9423 # Per bank write bursts
> system.physmem.perBankRdBursts::5 9371 # Per bank write bursts
> system.physmem.perBankRdBursts::6 8974 # Per bank write bursts
> system.physmem.perBankRdBursts::7 8126 # Per bank write bursts
> system.physmem.perBankRdBursts::8 8634 # Per bank write bursts
> system.physmem.perBankRdBursts::9 8697 # Per bank write bursts
> system.physmem.perBankRdBursts::10 8760 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9487 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9347 # Per bank write bursts
> system.physmem.perBankRdBursts::13 9550 # Per bank write bursts
> system.physmem.perBankRdBursts::14 8728 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9135 # Per bank write bursts
> system.physmem.perBankWrBursts::0 6252 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6118 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6042 # Per bank write bursts
> system.physmem.perBankWrBursts::3 5901 # Per bank write bursts
> system.physmem.perBankWrBursts::4 6273 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6263 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6069 # Per bank write bursts
> system.physmem.perBankWrBursts::7 5534 # Per bank write bursts
> system.physmem.perBankWrBursts::8 5815 # Per bank write bursts
> system.physmem.perBankWrBursts::9 5920 # Per bank write bursts
> system.physmem.perBankWrBursts::10 5985 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6510 # Per bank write bursts
> system.physmem.perBankWrBursts::12 6360 # Per bank write bursts
> system.physmem.perBankWrBursts::13 6344 # Per bank write bursts
> system.physmem.perBankWrBursts::14 6013 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6102 # Per bank write bursts
86c86
< system.physmem.totGap 366439104000 # Total gap between requests
---
> system.physmem.totGap 366631694000 # Total gap between requests
93c93
< system.physmem.readPktSize::6 143881 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 144269 # Read request sizes (log2)
100,103c100,103
< system.physmem.writePktSize::6 97182 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 143447 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 307 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 97528 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 143840 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 311 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see
148,175c148,175
< system.physmem.wrQLenPdf::15 2945 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5546 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5695 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5698 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5688 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5708 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 5734 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5737 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5721 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5718 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5715 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5728 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5685 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5691 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5629 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5618 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2842 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2979 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5670 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5725 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5731 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5730 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5730 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5734 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5731 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5736 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5739 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5754 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5737 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5732 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5729 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5727 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
197,215c197,216
< system.physmem.bytesPerActivate::samples 65604 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 235.015914 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 156.088937 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 241.071665 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 24900 37.96% 37.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 18453 28.13% 66.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 7121 10.85% 76.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7867 11.99% 88.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 1977 3.01% 91.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1093 1.67% 93.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 809 1.23% 94.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 630 0.96% 95.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 2754 4.20% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 65604 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 25.620745 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 380.610137 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 63306 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 244.314283 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 163.017060 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 244.594379 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22538 35.60% 35.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17961 28.37% 63.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 7327 11.57% 75.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7996 12.63% 88.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2051 3.24% 91.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1180 1.86% 93.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 835 1.32% 94.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 660 1.04% 95.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 2758 4.36% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63306 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5727 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 25.172342 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 18.597400 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 376.088417 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 5724 99.95% 99.95% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes
217,246c218,234
< system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.314204 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.219748 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 2.335766 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-17 2654 47.30% 47.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18-19 2805 49.99% 97.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-21 62 1.10% 98.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-25 17 0.30% 99.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-29 10 0.18% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::30-31 10 0.18% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-33 2 0.04% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::34-35 4 0.07% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-37 2 0.04% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-45 1 0.02% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::50-51 1 0.02% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-53 2 0.04% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::62-63 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads
< system.physmem.totQLat 1554447250 # Total ticks spent queuing
< system.physmem.totMemAccLat 4250153500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 718855000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10811.97 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5727 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5727 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.024795 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.995243 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.004050 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 2743 47.90% 47.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 142 2.48% 50.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 2814 49.14% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 20 0.35% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 6 0.10% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5727 # Writes before turning the bus around for reads
> system.physmem.totQLat 1581653750 # Total ticks spent queuing
> system.physmem.totMemAccLat 4284785000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 720835000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10970.98 # Average queueing delay per DRAM burst
248,252c236,240
< system.physmem.avgMemAccLat 29561.97 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 25.11 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 16.97 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 25.13 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 16.97 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 29720.98 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s
258,275c246,263
< system.physmem.avgWrQLen 19.60 # Average write queue length when enqueuing
< system.physmem.readRowHits 110522 # Number of row buffer hits during reads
< system.physmem.writeRowHits 64789 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 76.87 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes
< system.physmem.avgGap 1520096.84 # Average gap between requests
< system.physmem.pageHitRate 72.76 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 249842880 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 136323000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 559080600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 312783120 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 47987220420 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 177768013500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 250947114240 # Total energy per rank (pJ)
< system.physmem_0.averagePower 684.830589 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 295423376000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 12236120000 # Time in different power states
---
> system.physmem.avgWrQLen 20.20 # Average write queue length when enqueuing
> system.physmem.readRowHits 110439 # Number of row buffer hits during reads
> system.physmem.writeRowHits 67921 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 76.60 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes
> system.physmem.avgGap 1516278.92 # Average gap between requests
> system.physmem.pageHitRate 73.80 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 239652000 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 130762500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 560266200 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 313968960 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 47282173740 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 178503263250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 250976651370 # Total energy per rank (pJ)
> system.physmem_0.averagePower 684.547573 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 296644648000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 12242620000 # Time in different power states
277c265
< system.physmem_0.memoryStateTime::ACT 58777294250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 57744168750 # Time in different power states
279,289c267,277
< system.physmem_1.actEnergy 246017520 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 134235750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 562114800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 316645200 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 47395195335 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 178287321750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 250875381075 # Total energy per rank (pJ)
< system.physmem_1.averagePower 684.634868 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 296291389000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 12236120000 # Time in different power states
---
> system.physmem_1.actEnergy 238941360 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 130374750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 564213000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 317837520 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 47121480765 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 178644216000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 250963628115 # Total energy per rank (pJ)
> system.physmem_1.averagePower 684.512070 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 296880094250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 12242620000 # Time in different power states
291c279
< system.physmem_1.memoryStateTime::ACT 57909758500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 57508713250 # Time in different power states
293,298c281,286
< system.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 132103761 # Number of BP lookups
< system.cpu.branchPred.condPredicted 98193255 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 5910050 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 68601566 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 60590451 # Number of BTB hits
---
> system.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 132103795 # Number of BP lookups
> system.cpu.branchPred.condPredicted 98193288 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 68601542 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 60590460 # Number of BTB hits
300c288
< system.cpu.branchPred.BTBHitPct 88.322256 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 88.322300 # BTB Hit Percentage
303c291
< system.cpu.branchPred.indirectLookups 3891572 # Number of indirect predictor lookups.
---
> system.cpu.branchPred.indirectLookups 3891574 # Number of indirect predictor lookups.
305c293
< system.cpu.branchPred.indirectMisses 8545 # Number of indirect misses.
---
> system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses.
308c296
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
338c326
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
368c356
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
398c386
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
429,430c417,418
< system.cpu.pwrStateResidencyTicks::ON 366439129500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 732878259 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 366631719500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 733263439 # number of cpu cycles simulated
435c423
< system.cpu.discardedOps 12939743 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 12939754 # Number of ops (including micro ops) which were discarded before commit
437,438c425,426
< system.cpu.cpi 1.446720 # CPI: cycles per instruction
< system.cpu.ipc 0.691219 # IPC: instructions per cycle
---
> system.cpu.cpi 1.447480 # CPI: cycles per instruction
> system.cpu.ipc 0.690856 # IPC: instructions per cycle
474,476c462,464
< system.cpu.tickCycles 694071941 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 38806318 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 694072576 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 39190863 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
478,479c466,467
< system.cpu.dcache.tags.tagsinuse 4070.313641 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 171083825 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4070.301946 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 171083822 # Total number of references to valid blocks.
481,485c469,473
< system.cpu.dcache.tags.avg_refs 149.361704 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 5033914500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4070.313641 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.993729 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.993729 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.avg_refs 149.361702 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 5036525500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4070.301946 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.993726 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.993726 # Average percentage of cache occupancy
492,496c480,484
< system.cpu.dcache.tags.tag_accesses 346338115 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 346338115 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 114566020 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 114566020 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 346338109 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 346338109 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 114566017 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 114566017 # number of ReadReq hits
505,508c493,496
< system.cpu.dcache.demand_hits::cpu.data 168103949 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168103949 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168106743 # number of overall hits
< system.cpu.dcache.overall_hits::total 168106743 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 168103946 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168103946 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168106740 # number of overall hits
> system.cpu.dcache.overall_hits::total 168106740 # number of overall hits
519,528c507,516
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 13462011000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 13462011000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 21943272000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 21943272000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 35405283000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 35405283000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 35405283000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 35405283000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 115377401 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 115377401 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 13515584500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 13515584500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 22200332500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 22200332500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 35715917000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 35715917000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 35715917000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 35715917000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 115377398 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 115377398 # number of ReadReq accesses(hits+misses)
537,540c525,528
< system.cpu.dcache.demand_accesses::cpu.data 169616450 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 169616450 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 169619259 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 169619259 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 169616447 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 169616447 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 169619256 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 169619256 # number of overall (read+write) accesses
551,558c539,546
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16591.479219 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16591.479219 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31297.455500 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 31297.455500 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 23408.436094 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 23408.436094 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 23408.203946 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 23408.203946 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 23613.813809 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 23613.579625 # average overall miss latency
565,566c553,554
< system.cpu.dcache.writebacks::writebacks 1069267 # number of writebacks
< system.cpu.dcache.writebacks::total 1069267 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks
> system.cpu.dcache.writebacks::total 1068942 # number of writebacks
585,594c573,582
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12369658000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 12369658000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11145800500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11145800500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1093500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1093500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23515458500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23515458500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23516552000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23516552000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12423186500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 12423186500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11274063500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11274063500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 942500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 942500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23697250000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23697250000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23698192500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23698192500 # number of overall MSHR miss cycles
605,615c593,603
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15676.984359 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15676.984359 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31274.342851 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31274.342851 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 91125 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 91125 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.969767 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.969767 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20530.709347 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 20530.709347 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
617,618c605,606
< system.cpu.icache.tags.tagsinuse 1187.153068 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 199148908 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 1187.102530 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 199148962 # Total number of references to valid blocks.
620c608
< system.cpu.icache.tags.avg_refs 9934.100264 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 9934.102958 # Average number of references to valid blocks.
622,624c610,612
< system.cpu.icache.tags.occ_blocks::cpu.inst 1187.153068 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.579665 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.579665 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1187.102530 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.579640 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.579640 # Average percentage of cache occupancy
632,640c620,628
< system.cpu.icache.tags.tag_accesses 398357957 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 398357957 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 199148908 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 199148908 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 199148908 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 199148908 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 199148908 # number of overall hits
< system.cpu.icache.overall_hits::total 199148908 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 398358065 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 398358065 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 199148962 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 199148962 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 199148962 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 199148962 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 199148962 # number of overall hits
> system.cpu.icache.overall_hits::total 199148962 # number of overall hits
647,658c635,646
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 455856500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 455856500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 455856500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 455856500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 455856500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 455856500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 199168955 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 199168955 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 199168955 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 199168955 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 199168955 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 199168955 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 467837000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 467837000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 467837000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 467837000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 467837000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 467837000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 199169009 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 199169009 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 199169009 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 199169009 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 199169009 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 199169009 # number of overall (read+write) accesses
665,670c653,658
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.387440 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 22739.387440 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 22739.387440 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 22739.387440 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23337.008031 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 23337.008031 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 23337.008031 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 23337.008031 # average overall miss latency
685,690c673,678
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435809500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 435809500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435809500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 435809500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435809500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 435809500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 447790000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 447790000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 447790000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 447790000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 447790000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 447790000 # number of overall MSHR miss cycles
697,727c685,715
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.387440 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.387440 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 112318 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 27616.037174 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1771878 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 143528 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 12.345173 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 165163715500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 23489.264935 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.326790 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3818.445449 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.716835 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009409 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.116530 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.842775 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 31210 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4934 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952454 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 19060134 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 19060134 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 1069267 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 1069267 # number of WritebackDirty hits
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 112761 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 29068.883602 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2174452 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 14.941709 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 101788000000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 134.067060 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.855024 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.004091 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009395 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.873626 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.887112 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 18705497 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 18705497 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits
730,767c718,755
< system.cpu.l2cache.ReadExReq_hits::cpu.data 255711 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 255711 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17236 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 17236 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748638 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 748638 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 17236 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1004349 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1021585 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 17236 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1004349 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1021585 # number of overall hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 100927 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 100927 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40157 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 40157 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 2811 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 141084 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 143895 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 141084 # number of overall misses
< system.cpu.l2cache.overall_misses::total 143895 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7928727500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7928727500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 224093000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 224093000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3306674000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 3306674000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 224093000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11235401500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11459494500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 224093000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11235401500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11459494500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 1069267 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 1069267 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 255660 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 255660 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17235 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 17235 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748301 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 748301 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 17235 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1003961 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1021196 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 17235 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1003961 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1021196 # number of overall hits
> system.cpu.l2cache.ReadExReq_misses::cpu.data 100978 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 100978 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2812 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 2812 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40494 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 40494 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 2812 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 141472 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 144284 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2812 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses
> system.cpu.l2cache.overall_misses::total 144284 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8057525500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8057525500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236084500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 236084500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3363607000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 3363607000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 236084500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11421132500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11657217000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 236084500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11421132500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11657217000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses)
782,805c770,793
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282996 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.282996 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140220 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140220 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050909 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050909 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140220 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.123171 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.123464 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140220 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.123171 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.123464 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78559.032766 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78559.032766 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79720.028460 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79720.028460 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82343.651169 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82343.651169 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 79637.892213 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 79637.892213 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140270 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140270 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140270 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.123798 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140270 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.123798 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79794.861257 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79794.861257 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83956.081081 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83956.081081 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83064.330518 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83064.330518 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 80793.552993 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 80793.552993 # average overall miss latency
812,815c800,803
< system.cpu.l2cache.writebacks::writebacks 97182 # number of writebacks
< system.cpu.l2cache.writebacks::total 97182 # number of writebacks
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks
> system.cpu.l2cache.writebacks::total 97528 # number of writebacks
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
818c806
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
820,821c808,809
< system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
823,825c811,813
< system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100927 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 100927 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses
828,829c816,817
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40144 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40144 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses
831,832c819,820
< system.cpu.l2cache.demand_mshr_misses::cpu.data 141071 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 143881 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses
834,849c822,837
< system.cpu.l2cache.overall_mshr_misses::cpu.data 141071 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 143881 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6919457500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6919457500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195753000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195753000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2904162000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2904162000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195753000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9823619500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10019372500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195753000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9823619500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 10019372500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282996 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282996 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7047745500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7047745500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207624000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207624000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2957433000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2957433000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207624000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10005178500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10212802500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207624000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10005178500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 10212802500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses
852,853c840,841
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050893 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050893 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses
855,856c843,844
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.123452 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses
858,871c846,859
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.123452 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68559.032766 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68559.032766 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69662.989324 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69662.989324 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72343.612993 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72343.612993 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.861257 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.861257 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73887.544484 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency
875,876c863,864
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2610 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2607 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
878c866
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
880c868
< system.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution
882c870
< system.cpu.toL2Bus.trans_dist::CleanEvict 87206 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution
891,897c879,885
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141740800 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 144187008 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 112318 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 6219648 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 1277798 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.006010 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.077318 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 144166208 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 112761 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 1278241 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.006014 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.077345 # Request fanout histogram
899,900c887,888
< system.cpu.toL2Bus.snoop_fanout::0 1270122 99.40% 99.40% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 7673 0.60% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1270557 99.40% 99.40% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 7681 0.60% 100.00% # Request fanout histogram
905,906c893,894
< system.cpu.toL2Bus.snoop_fanout::total 1277798 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2249938000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1278241 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2249613000 # Layer occupancy (ticks)
908c896
< system.cpu.toL2Bus.respLayer0.occupancy 30093953 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 30094452 # Layer occupancy (ticks)
910c898
< system.cpu.toL2Bus.respLayer1.occupancy 1718157484 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks)
912,922c900,916
< system.membus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 42954 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 97182 # Transaction distribution
< system.membus.trans_dist::CleanEvict 12526 # Transaction distribution
< system.membus.trans_dist::ReadExReq 100927 # Transaction distribution
< system.membus.trans_dist::ReadExResp 100927 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 42954 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397470 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 397470 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15428032 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 15428032 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 43291 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution
> system.membus.trans_dist::CleanEvict 12615 # Transaction distribution
> system.membus.trans_dist::ReadExReq 100978 # Transaction distribution
> system.membus.trans_dist::ReadExResp 100978 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes)
925c919
< system.membus.snoop_fanout::samples 253589 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 144269 # Request fanout histogram
929c923
< system.membus.snoop_fanout::0 253589 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram
934,935c928,929
< system.membus.snoop_fanout::total 253589 # Request fanout histogram
< system.membus.reqLayer0.occupancy 685523500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 144269 # Request fanout histogram
> system.membus.reqLayer0.occupancy 685129000 # Layer occupancy (ticks)
937c931
< system.membus.respLayer1.occupancy 763755750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 765930250 # Layer occupancy (ticks)