3,5c3,5
< sim_seconds 0.363605 # Number of seconds simulated
< sim_ticks 363605295500 # Number of ticks simulated
< final_tick 363605295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.363600 # Number of seconds simulated
> sim_ticks 363599502500 # Number of ticks simulated
> final_tick 363599502500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 163495 # Simulator instruction rate (inst/s)
< host_op_rate 177087 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 117350463 # Simulator tick rate (ticks/s)
< host_mem_usage 312624 # Number of bytes of host memory used
< host_seconds 3098.46 # Real time elapsed on the host
---
> host_inst_rate 226144 # Simulator instruction rate (inst/s)
> host_op_rate 244944 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 162315109 # Simulator tick rate (ticks/s)
> host_mem_usage 321124 # Number of bytes of host memory used
> host_seconds 2240.08 # Real time elapsed on the host
16c16
< system.physmem.bytes_read::cpu.inst 219264 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 219456 # Number of bytes read from this memory
18,23c18,23
< system.physmem.bytes_read::total 9223744 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 219264 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 219264 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6189056 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6189056 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 3426 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 9223936 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 219456 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 219456 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6189376 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6189376 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3429 # Number of read requests responded to by this memory
25,48c25,48
< system.physmem.num_reads::total 144121 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 96704 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 96704 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 603028 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 24764436 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 25367463 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 603028 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 603028 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 17021358 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 17021358 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 17021358 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 603028 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 24764436 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 42388822 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 144121 # Number of read requests accepted
< system.physmem.writeReqs 96704 # Number of write requests accepted
< system.physmem.readBursts 144121 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 96704 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 9217792 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6187328 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 9223744 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 6189056 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::total 144124 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 96709 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 96709 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 603565 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 24764830 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 25368396 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 603565 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 603565 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 17022510 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 17022510 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 17022510 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 603565 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 24764830 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 42390905 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 144124 # Number of read requests accepted
> system.physmem.writeReqs 96709 # Number of write requests accepted
> system.physmem.readBursts 144124 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 96709 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 9217920 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6188224 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 9223936 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6189376 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue
51c51
< system.physmem.perBankRdBursts::0 9327 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 9331 # Per bank write bursts
53c53
< system.physmem.perBankRdBursts::2 9002 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 9003 # Per bank write bursts
55c55
< system.physmem.perBankRdBursts::4 9455 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 9453 # Per bank write bursts
57c57
< system.physmem.perBankRdBursts::6 8946 # Per bank write bursts
---
> system.physmem.perBankRdBursts::6 8945 # Per bank write bursts
60c60
< system.physmem.perBankRdBursts::9 8671 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 8674 # Per bank write bursts
62,67c62,67
< system.physmem.perBankRdBursts::11 9475 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9349 # Per bank write bursts
< system.physmem.perBankRdBursts::13 9515 # Per bank write bursts
< system.physmem.perBankRdBursts::14 8723 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9120 # Per bank write bursts
< system.physmem.perBankWrBursts::0 6189 # Per bank write bursts
---
> system.physmem.perBankRdBursts::11 9476 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9348 # Per bank write bursts
> system.physmem.perBankRdBursts::13 9513 # Per bank write bursts
> system.physmem.perBankRdBursts::14 8719 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9123 # Per bank write bursts
> system.physmem.perBankWrBursts::0 6195 # Per bank write bursts
69c69
< system.physmem.perBankWrBursts::2 6010 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 6011 # Per bank write bursts
71,72c71,72
< system.physmem.perBankWrBursts::4 6183 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6186 # Per bank write bursts
---
> system.physmem.perBankWrBursts::4 6181 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6188 # Per bank write bursts
74,76c74,76
< system.physmem.perBankWrBursts::7 5498 # Per bank write bursts
< system.physmem.perBankWrBursts::8 5738 # Per bank write bursts
< system.physmem.perBankWrBursts::9 5829 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 5499 # Per bank write bursts
> system.physmem.perBankWrBursts::8 5743 # Per bank write bursts
> system.physmem.perBankWrBursts::9 5830 # Per bank write bursts
79c79
< system.physmem.perBankWrBursts::12 6313 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 6312 # Per bank write bursts
81,82c81,82
< system.physmem.perBankWrBursts::14 6005 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6083 # Per bank write bursts
---
> system.physmem.perBankWrBursts::14 6003 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6086 # Per bank write bursts
85c85
< system.physmem.totGap 363605269500 # Total gap between requests
---
> system.physmem.totGap 363599476500 # Total gap between requests
92c92
< system.physmem.readPktSize::6 144121 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 144124 # Read request sizes (log2)
99,102c99,102
< system.physmem.writePktSize::6 96704 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 143663 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 343 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 96709 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 349 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
147,149c147,149
< system.physmem.wrQLenPdf::15 2949 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3103 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5548 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see
151,158c151,158
< system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5668 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5673 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 5682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5670 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5674 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5686 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5666 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5668 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5670 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5680 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5666 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see
160,165c160,165
< system.physmem.wrQLenPdf::28 5716 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5669 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5677 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5614 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::28 5712 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5670 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5613 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see
167c167
< system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see
169,172c169,172
< system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
174c174
< system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
196,213c196,213
< system.physmem.bytesPerActivate::samples 65251 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 236.074482 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 156.620272 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 241.651300 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 24697 37.85% 37.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 18374 28.16% 66.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6917 10.60% 76.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7938 12.17% 88.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2038 3.12% 91.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1147 1.76% 93.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 769 1.18% 94.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 621 0.95% 95.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 2750 4.21% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 65251 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5585 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 25.786571 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 381.841879 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 5581 99.93% 99.93% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 65302 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 235.912652 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 156.372535 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 241.914583 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 24788 37.96% 37.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 18406 28.19% 66.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6849 10.49% 76.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7905 12.11% 88.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2084 3.19% 91.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1111 1.70% 93.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 761 1.17% 94.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 643 0.98% 95.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 2755 4.22% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 65302 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5583 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 25.797421 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 381.883100 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 5579 99.93% 99.93% # Reads before turning the bus around for writes
216,242c216,244
< system.physmem.rdPerTurnAround::total 5585 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5585 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.310116 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.217866 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 2.213646 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 2534 45.37% 45.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 92 1.65% 47.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 2660 47.63% 94.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 156 2.79% 97.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 36 0.64% 98.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 18 0.32% 98.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 16 0.29% 98.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 9 0.16% 98.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 7 0.13% 98.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 10 0.18% 99.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 4 0.07% 99.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::27 4 0.07% 99.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28 4 0.07% 99.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::29 6 0.11% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::30 2 0.04% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::31 4 0.07% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32 3 0.05% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::33 4 0.07% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::35 2 0.04% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::37 2 0.04% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::39 1 0.02% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40 1 0.02% 99.82% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5583 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5583 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.318825 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.224966 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 2.238810 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 2516 45.07% 45.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 99 1.77% 46.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 2663 47.70% 94.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 163 2.92% 97.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 38 0.68% 98.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 18 0.32% 98.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 14 0.25% 98.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 8 0.14% 98.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 6 0.11% 98.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 9 0.16% 99.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 5 0.09% 99.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::27 4 0.07% 99.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28 4 0.07% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::29 6 0.11% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::30 2 0.04% 99.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::31 3 0.05% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32 2 0.04% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::33 4 0.07% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::34 2 0.04% 99.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::35 2 0.04% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::37 2 0.04% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::39 1 0.02% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40 1 0.02% 99.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::41 1 0.02% 99.82% # Writes before turning the bus around for reads
252,256c254,258
< system.physmem.wrPerTurnAround::total 5585 # Writes before turning the bus around for reads
< system.physmem.totQLat 1541292750 # Total ticks spent queuing
< system.physmem.totMemAccLat 4241817750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 720140000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10701.34 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 5583 # Writes before turning the bus around for reads
> system.physmem.totQLat 1538433000 # Total ticks spent queuing
> system.physmem.totMemAccLat 4238995500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 720150000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10681.34 # Average queueing delay per DRAM burst
258c260
< system.physmem.avgMemAccLat 29451.34 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 29431.34 # Average memory access latency per DRAM burst
268,270c270,272
< system.physmem.avgWrQLen 19.51 # Average write queue length when enqueuing
< system.physmem.readRowHits 110876 # Number of row buffer hits during reads
< system.physmem.writeRowHits 64571 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 19.80 # Average write queue length when enqueuing
> system.physmem.readRowHits 110870 # Number of row buffer hits during reads
> system.physmem.writeRowHits 64542 # Number of row buffer hits during writes
272,285c274,287
< system.physmem.writeRowHitRate 66.77 # Row buffer hit rate for writes
< system.physmem.avgGap 1509831.91 # Average gap between requests
< system.physmem.pageHitRate 72.88 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 248028480 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 135333000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 560164800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 310884480 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 47382783300 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 176597692500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 248983621440 # Total energy per rank (pJ)
< system.physmem_0.averagePower 684.768610 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 293478926000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states
---
> system.physmem.writeRowHitRate 66.74 # Row buffer hit rate for writes
> system.physmem.avgGap 1509757.70 # Average gap between requests
> system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 248293080 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 135477375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 560086800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 310832640 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 47486002320 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 176502477750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 248991396285 # Total energy per rank (pJ)
> system.physmem_0.averagePower 684.804658 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 293320694250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 12141220000 # Time in different power states
287c289
< system.physmem_0.memoryStateTime::ACT 57982170250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 58133810750 # Time in different power states
289,299c291,301
< system.physmem_1.actEnergy 245080080 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 133724250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 563004000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 315375120 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 46983341835 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 176948079750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 248937339915 # Total energy per rank (pJ)
< system.physmem_1.averagePower 684.641324 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 294063578500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states
---
> system.physmem_1.actEnergy 245148120 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 133761375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 562957200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 315401040 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 46957937220 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 176965692750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 248929124025 # Total energy per rank (pJ)
> system.physmem_1.averagePower 684.633389 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 294092512000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 12141220000 # Time in different power states
301c303
< system.physmem_1.memoryStateTime::ACT 57397836750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 57361058000 # Time in different power states
303,307c305,309
< system.cpu.branchPred.lookups 131896308 # Number of BP lookups
< system.cpu.branchPred.condPredicted 98031712 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 6139352 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 68410049 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 64397752 # Number of BTB hits
---
> system.cpu.branchPred.lookups 131895360 # Number of BP lookups
> system.cpu.branchPred.condPredicted 98029927 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 6139026 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 68388068 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 64396789 # Number of BTB hits
309,311c311,313
< system.cpu.branchPred.BTBHitPct 94.134930 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 9981293 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 18014 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 94.163779 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 9981632 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 18119 # Number of incorrect RAS predictions.
430c432
< system.cpu.numCycles 727210591 # number of cpu cycles simulated
---
> system.cpu.numCycles 727199005 # number of cpu cycles simulated
435c437
< system.cpu.discardedOps 13199856 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 13199573 # Number of ops (including micro ops) which were discarded before commit
437,445c439,447
< system.cpu.cpi 1.435524 # CPI: cycles per instruction
< system.cpu.ipc 0.696610 # IPC: instructions per cycle
< system.cpu.tickCycles 690727435 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 36483156 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 1139971 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4070.789837 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 171168979 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1144067 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 149.614471 # Average number of references to valid blocks.
---
> system.cpu.cpi 1.435501 # CPI: cycles per instruction
> system.cpu.ipc 0.696621 # IPC: instructions per cycle
> system.cpu.tickCycles 690715590 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 36483415 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 1139984 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4070.789434 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 171168644 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1144080 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 149.612478 # Average number of references to valid blocks.
447c449
< system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789837 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789434 # Average occupied blocks per requestor
452c454
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
454c456
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id
456,463c458,465
< system.cpu.dcache.tags.tag_accesses 346593001 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 346593001 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 114650515 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 114650515 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 53538628 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 53538628 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 2754 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 2754 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 346592332 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 346592332 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 114650184 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 114650184 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 53538625 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 53538625 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 2753 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 2753 # number of SoftPFReq hits
468,491c470,493
< system.cpu.dcache.demand_hits::cpu.data 168189143 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168189143 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168191897 # number of overall hits
< system.cpu.dcache.overall_hits::total 168191897 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 854793 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 854793 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 700678 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 700678 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 17 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 17 # number of SoftPFReq misses
< system.cpu.dcache.demand_misses::cpu.data 1555471 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1555471 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1555488 # number of overall misses
< system.cpu.dcache.overall_misses::total 1555488 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024452000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 14024452000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 21892214000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 21892214000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 35916666000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 35916666000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 35916666000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 35916666000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 115505308 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 115505308 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 168188809 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168188809 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168191562 # number of overall hits
> system.cpu.dcache.overall_hits::total 168191562 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 854786 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 854786 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 700681 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 700681 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 1555467 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1555467 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1555482 # number of overall misses
> system.cpu.dcache.overall_misses::total 1555482 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024022500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 14024022500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 21893600500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 21893600500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 35917623000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 35917623000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 35917623000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 35917623000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 115504970 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 115504970 # number of ReadReq accesses(hits+misses)
494,495c496,497
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 2771 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 2771 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2768 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2768 # number of SoftPFReq accesses(hits+misses)
500,503c502,505
< system.cpu.dcache.demand_accesses::cpu.data 169744614 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 169744614 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 169747385 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 169747385 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 169744276 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 169744276 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 169747044 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 169747044 # number of overall (read+write) accesses
508,509c510,511
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.006135 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.006135 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005419 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.005419 # miss rate for SoftPFReq accesses
514,521c516,523
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.840019 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.840019 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31244.329064 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 31244.329064 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 23090.540422 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 23090.540422 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.288064 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 23090.288064 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.471912 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.471912 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31246.174079 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31246.174079 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 23091.215050 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 23091.215050 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.992374 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 23090.992374 # average overall miss latency
530,559c532,561
< system.cpu.dcache.writebacks::writebacks 1068574 # number of writebacks
< system.cpu.dcache.writebacks::total 1068574 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66907 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 66907 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344511 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 344511 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 411418 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 411418 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 411418 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 411418 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787886 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 787886 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356167 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 356167 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 14 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 14 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1144053 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1144053 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1144067 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1144067 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337562000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337562000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11120015500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11120015500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1028000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1028000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23457577500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23457577500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23458605500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23458605500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.writebacks::writebacks 1068583 # number of writebacks
> system.cpu.dcache.writebacks::total 1068583 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66886 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 66886 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344513 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 344513 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 411399 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 411399 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 411399 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 411399 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787900 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 787900 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356168 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 356168 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1144068 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1144068 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1144080 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1144080 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337991000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337991000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11121217500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11121217500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 946000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 946000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23459208500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23459208500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23460154500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23460154500 # number of overall MSHR miss cycles
564,565c566,567
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005052 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005052 # mshr miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004335 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004335 # mshr miss rate for SoftPFReq accesses
570,579c572,581
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.069967 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.069967 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31221.352624 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31221.352624 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73428.571429 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73428.571429 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20503.925517 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 20503.925517 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20504.573159 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 20504.573159 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.336210 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.336210 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31224.639777 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31224.639777 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78833.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78833.333333 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20505.082303 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 20505.082303 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20505.694095 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 20505.694095 # average overall mshr miss latency
581,585c583,587
< system.cpu.icache.tags.replacements 17719 # number of replacements
< system.cpu.icache.tags.tagsinuse 1188.326281 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 199317838 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 19591 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 10173.949160 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 17702 # number of replacements
> system.cpu.icache.tags.tagsinuse 1188.317648 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 199314883 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 19574 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 10182.634260 # Average number of references to valid blocks.
587,589c589,591
< system.cpu.icache.tags.occ_blocks::cpu.inst 1188.326281 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.580237 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.580237 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1188.317648 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.580233 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.580233 # Average percentage of cache occupancy
592,595c594,597
< system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1407 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 306 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id
597,622c599,624
< system.cpu.icache.tags.tag_accesses 398694449 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 398694449 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 199317838 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 199317838 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 199317838 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 199317838 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 199317838 # number of overall hits
< system.cpu.icache.overall_hits::total 199317838 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 19591 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 19591 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 19591 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 19591 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 19591 # number of overall misses
< system.cpu.icache.overall_misses::total 19591 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 490899000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 490899000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 490899000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 490899000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 490899000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 490899000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 199337429 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 199337429 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 199337429 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 199337429 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 199337429 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 199337429 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 398688488 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 398688488 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 199314883 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 199314883 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 199314883 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 199314883 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 199314883 # number of overall hits
> system.cpu.icache.overall_hits::total 199314883 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 19574 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 19574 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 19574 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 19574 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 19574 # number of overall misses
> system.cpu.icache.overall_misses::total 19574 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 491333500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 491333500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 491333500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 491333500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 491333500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 491333500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 199334457 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 199334457 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 199334457 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 199334457 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 199334457 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 199334457 # number of overall (read+write) accesses
629,634c631,636
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25057.373284 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 25057.373284 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 25057.373284 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 25057.373284 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 25057.373284 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 25057.373284 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25101.333401 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 25101.333401 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 25101.333401 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 25101.333401 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 25101.333401 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 25101.333401 # average overall miss latency
643,654c645,656
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19591 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 19591 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 19591 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 19591 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 19591 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 19591 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 471308000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 471308000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 471308000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 471308000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 471308000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 471308000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19574 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 19574 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 19574 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 19574 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 19574 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 19574 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 471759500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 471759500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 471759500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 471759500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 471759500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 471759500 # number of overall MSHR miss cycles
661,666c663,668
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24057.373284 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24057.373284 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24057.373284 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 24057.373284 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24057.373284 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 24057.373284 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24101.333401 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24101.333401 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24101.333401 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 24101.333401 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24101.333401 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 24101.333401 # average overall mshr miss latency
668,682c670,684
< system.cpu.l2cache.tags.replacements 111367 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 27634.082837 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1767150 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 142553 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 12.396442 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 163253470000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 23457.963317 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.755870 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3786.363650 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.715880 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011894 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.115551 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.843325 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.replacements 111370 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 27634.033642 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1767249 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 142558 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 12.396702 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 163253473000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 23457.713364 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.652620 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3786.667658 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.715873 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011891 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.115560 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.843324 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
684,702c686,704
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4935 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25860 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 19030386 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 19030386 # Number of data accesses
< system.cpu.l2cache.Writeback_hits::writebacks 1068574 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1068574 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 255588 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 255588 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16163 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 16163 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747770 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 747770 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 16163 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1003358 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1019521 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 16163 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1003358 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1019521 # number of overall hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25857 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 19030322 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 19030322 # Number of data accesses
> system.cpu.l2cache.Writeback_hits::writebacks 1068583 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1068583 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 255591 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 255591 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16143 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 16143 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747780 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 747780 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 16143 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1003371 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1019514 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 16143 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1003371 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1019514 # number of overall hits
705,706c707,708
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3428 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 3428 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3431 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 3431 # number of ReadCleanReq misses
709c711
< system.cpu.l2cache.demand_misses::cpu.inst 3428 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 3431 # number of demand (read+write) misses
711,712c713,714
< system.cpu.l2cache.demand_misses::total 144137 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3428 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 144140 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3431 # number of overall misses
714,764c716,766
< system.cpu.l2cache.overall_misses::total 144137 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7904552500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7904552500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 272166000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 272166000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3286207500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 3286207500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 272166000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11190760000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11462926000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 272166000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11190760000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11462926000 # number of overall miss cycles
< system.cpu.l2cache.Writeback_accesses::writebacks 1068574 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1068574 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 356417 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 356417 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19591 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 19591 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 787650 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 787650 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 19591 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1144067 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1163658 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 19591 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1144067 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1163658 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282896 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.282896 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.174978 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.174978 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050632 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050632 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.174978 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.122990 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.123865 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.174978 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.122990 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.123865 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78395.625267 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78395.625267 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79394.982497 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79394.982497 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82402.394684 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82402.394684 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79394.982497 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79531.231122 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 79527.990731 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79394.982497 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79531.231122 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 79527.990731 # average overall miss latency
---
> system.cpu.l2cache.overall_misses::total 144140 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7905743000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7905743000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 272299500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 272299500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3282195500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 3282195500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 272299500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11187938500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11460238000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 272299500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11187938500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11460238000 # number of overall miss cycles
> system.cpu.l2cache.Writeback_accesses::writebacks 1068583 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1068583 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 356420 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 356420 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19574 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 19574 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 787660 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 787660 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 19574 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1144080 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1163654 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 19574 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1144080 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1163654 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282894 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.282894 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.175284 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.175284 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050631 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050631 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175284 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.122989 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.123868 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175284 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.122989 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.123868 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78407.432386 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78407.432386 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79364.471000 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79364.471000 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82301.792879 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82301.792879 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79364.471000 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79511.179100 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 79507.686971 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79364.471000 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79511.179100 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 79507.686971 # average overall miss latency
773,774c775,776
< system.cpu.l2cache.writebacks::writebacks 96704 # number of writebacks
< system.cpu.l2cache.writebacks::total 96704 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 96709 # number of writebacks
> system.cpu.l2cache.writebacks::total 96709 # number of writebacks
785,786c787,788
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1193 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 1193 # number of CleanEvict MSHR misses
---
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1197 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 1197 # number of CleanEvict MSHR misses
789,790c791,792
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3426 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3426 # number of ReadCleanReq MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3429 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3429 # number of ReadCleanReq MSHR misses
793c795
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3426 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3429 # number of demand (read+write) MSHR misses
795,796c797,798
< system.cpu.l2cache.demand_mshr_misses::total 144121 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3426 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 144124 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3429 # number of overall MSHR misses
798,810c800,812
< system.cpu.l2cache.overall_mshr_misses::total 144121 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6896262500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6896262500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 237598000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 237598000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2886048500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2886048500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 237598000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9782311000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10019909000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 237598000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9782311000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 10019909000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::total 144124 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6897453000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6897453000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 237701500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 237701500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2882229000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2882229000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 237701500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9779682000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10017383500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 237701500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9779682000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 10017383500 # number of overall MSHR miss cycles
813,836c815,838
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282896 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282896 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.174876 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050614 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050614 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.123852 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.123852 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68395.625267 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68395.625267 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69351.430239 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69351.430239 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72393.731501 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72393.731501 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282894 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282894 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.175181 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050613 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050613 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.123855 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.175181 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.123855 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68407.432386 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68407.432386 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69320.939049 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69320.939049 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72297.923042 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72297.923042 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69320.939049 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69509.804897 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69505.311399 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69320.939049 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69509.804897 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69505.311399 # average overall mshr miss latency
838,854c840,862
< system.cpu.toL2Bus.trans_dist::ReadResp 807241 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 1165278 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 98858 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 19591 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 787650 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56664 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423421 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 3480085 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253824 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141609024 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 142862848 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 111367 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 2432715 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.045779 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.209005 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 2321340 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157756 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4922 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2616 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2613 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.trans_dist::ReadResp 807234 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 1165292 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 98842 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 356420 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 356420 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 19574 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 787660 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56613 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423459 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 3480072 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252736 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141610432 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 142863168 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 111370 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 2432710 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.005152 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.071609 # Request fanout histogram
856,858c864,866
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 2321348 95.42% 95.42% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 111367 4.58% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2420180 99.48% 99.48% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 12527 0.51% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram
860c868
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
862,863c870,871
< system.cpu.toL2Bus.snoop_fanout::total 2432715 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2229248000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2432710 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2229253000 # Layer occupancy (ticks)
865c873
< system.cpu.toL2Bus.respLayer0.occupancy 29387997 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 29379463 # Layer occupancy (ticks)
867c875
< system.cpu.toL2Bus.respLayer1.occupancy 1716107486 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1716126986 # Layer occupancy (ticks)
869,871c877,879
< system.membus.trans_dist::ReadResp 43292 # Transaction distribution
< system.membus.trans_dist::Writeback 96704 # Transaction distribution
< system.membus.trans_dist::CleanEvict 13244 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 43295 # Transaction distribution
> system.membus.trans_dist::Writeback 96709 # Transaction distribution
> system.membus.trans_dist::CleanEvict 13242 # Transaction distribution
874,878c882,886
< system.membus.trans_dist::ReadSharedReq 43292 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398190 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 398190 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15412800 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 15412800 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 43295 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398199 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 398199 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15413312 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 15413312 # Cumulative packet size per connected master and slave (bytes)
880c888
< system.membus.snoop_fanout::samples 254069 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 254075 # Request fanout histogram
884c892
< system.membus.snoop_fanout::0 254069 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 254075 100.00% 100.00% # Request fanout histogram
889,890c897,898
< system.membus.snoop_fanout::total 254069 # Request fanout histogram
< system.membus.reqLayer0.occupancy 683631500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 254075 # Request fanout histogram
> system.membus.reqLayer0.occupancy 683661500 # Layer occupancy (ticks)
892c900
< system.membus.respLayer1.occupancy 765040250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 765035500 # Layer occupancy (ticks)