3,5c3,5
< sim_seconds 0.365317 # Number of seconds simulated
< sim_ticks 365317233000 # Number of ticks simulated
< final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.366359 # Number of seconds simulated
> sim_ticks 366358704500 # Number of ticks simulated
> final_tick 366358704500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 157262 # Simulator instruction rate (inst/s)
< host_op_rate 170335 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 113407877 # Simulator tick rate (ticks/s)
< host_mem_usage 304680 # Number of bytes of host memory used
< host_seconds 3221.27 # Real time elapsed on the host
---
> host_inst_rate 242855 # Simulator instruction rate (inst/s)
> host_op_rate 263044 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 175631724 # Simulator tick rate (ticks/s)
> host_mem_usage 316616 # Number of bytes of host memory used
> host_seconds 2085.95 # Real time elapsed on the host
16,48c16,48
< system.physmem.bytes_read::cpu.inst 222144 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9003904 # Number of bytes read from this memory
< system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory
< system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 3471 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 140686 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 608085 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 24646809 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 608085 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 24646809 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 144157 # Number of read requests accepted
< system.physmem.writeReqs 96561 # Number of write requests accepted
< system.physmem.readBursts 144157 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 96561 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 9219904 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6178688 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 9226048 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 6179904 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9006016 # Number of bytes read from this memory
> system.physmem.bytes_read::total 9227712 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6179648 # Number of bytes written to this memory
> system.physmem.bytes_written::total 6179648 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 140719 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 144183 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 96557 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 96557 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 605134 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 24582509 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 25187642 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 605134 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 605134 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 16867753 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 16867753 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 16867753 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 605134 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 24582509 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 42055395 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 144183 # Number of read requests accepted
> system.physmem.writeReqs 96557 # Number of write requests accepted
> system.physmem.readBursts 144183 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 96557 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6178496 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 9227712 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6179648 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue
52,54c52,54
< system.physmem.perBankRdBursts::1 8970 # Per bank write bursts
< system.physmem.perBankRdBursts::2 8998 # Per bank write bursts
< system.physmem.perBankRdBursts::3 8695 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 9007 # Per bank write bursts
> system.physmem.perBankRdBursts::2 8992 # Per bank write bursts
> system.physmem.perBankRdBursts::3 8698 # Per bank write bursts
57,59c57,59
< system.physmem.perBankRdBursts::6 8947 # Per bank write bursts
< system.physmem.perBankRdBursts::7 8101 # Per bank write bursts
< system.physmem.perBankRdBursts::8 8578 # Per bank write bursts
---
> system.physmem.perBankRdBursts::6 8946 # Per bank write bursts
> system.physmem.perBankRdBursts::7 8102 # Per bank write bursts
> system.physmem.perBankRdBursts::8 8570 # Per bank write bursts
61,62c61,62
< system.physmem.perBankRdBursts::10 8774 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9477 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 8773 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9476 # Per bank write bursts
64c64
< system.physmem.perBankRdBursts::13 9525 # Per bank write bursts
---
> system.physmem.perBankRdBursts::13 9521 # Per bank write bursts
66,70c66,70
< system.physmem.perBankRdBursts::15 9087 # Per bank write bursts
< system.physmem.perBankWrBursts::0 6196 # Per bank write bursts
< system.physmem.perBankWrBursts::1 6092 # Per bank write bursts
< system.physmem.perBankWrBursts::2 6006 # Per bank write bursts
< system.physmem.perBankWrBursts::3 5813 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 9073 # Per bank write bursts
> system.physmem.perBankWrBursts::0 6191 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6098 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6005 # Per bank write bursts
> system.physmem.perBankWrBursts::3 5815 # Per bank write bursts
72c72
< system.physmem.perBankWrBursts::5 6172 # Per bank write bursts
---
> system.physmem.perBankWrBursts::5 6174 # Per bank write bursts
74,77c74,77
< system.physmem.perBankWrBursts::7 5493 # Per bank write bursts
< system.physmem.perBankWrBursts::8 5728 # Per bank write bursts
< system.physmem.perBankWrBursts::9 5823 # Per bank write bursts
< system.physmem.perBankWrBursts::10 5962 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 5494 # Per bank write bursts
> system.physmem.perBankWrBursts::8 5727 # Per bank write bursts
> system.physmem.perBankWrBursts::9 5822 # Per bank write bursts
> system.physmem.perBankWrBursts::10 5961 # Per bank write bursts
80,82c80,82
< system.physmem.perBankWrBursts::13 6282 # Per bank write bursts
< system.physmem.perBankWrBursts::14 5997 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6048 # Per bank write bursts
---
> system.physmem.perBankWrBursts::13 6277 # Per bank write bursts
> system.physmem.perBankWrBursts::14 5998 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6047 # Per bank write bursts
85c85
< system.physmem.totGap 365317203500 # Total gap between requests
---
> system.physmem.totGap 366358675500 # Total gap between requests
92c92
< system.physmem.readPktSize::6 144157 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 144183 # Read request sizes (log2)
99,102c99,102
< system.physmem.writePktSize::6 96561 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 96557 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 143693 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
147c147
< system.physmem.wrQLenPdf::15 2939 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see
149,177c149,177
< system.physmem.wrQLenPdf::17 5543 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5664 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5672 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5680 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5680 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 5691 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5692 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 5666 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 5669 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5692 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 5677 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5643 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5596 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::17 5533 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5680 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5677 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5673 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5679 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5677 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5676 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5696 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5690 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5657 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5648 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5587 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5575 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
196,213c196,213
< system.physmem.bytesPerActivate::samples 65080 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 236.601352 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 156.588709 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 242.751381 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 24737 38.01% 38.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 18138 27.87% 65.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6930 10.65% 76.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7871 12.09% 88.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2125 3.27% 91.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1134 1.74% 93.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 708 1.09% 94.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 644 0.99% 95.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 2793 4.29% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 65080 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 25.854092 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 382.114973 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 65205 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 236.159558 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 156.546491 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 241.906067 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 24752 37.96% 37.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 18185 27.89% 65.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 7019 10.76% 76.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7903 12.12% 88.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2061 3.16% 91.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1167 1.79% 93.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 745 1.14% 94.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 604 0.93% 95.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 2769 4.25% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 65205 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 25.873563 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 382.195910 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 5565 99.95% 99.95% # Reads before turning the bus around for writes
216,238c216,240
< system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.326274 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.230410 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 2.286782 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-17 2628 47.16% 47.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18-19 2789 50.05% 97.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-21 53 0.95% 98.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22-23 30 0.54% 98.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-25 23 0.41% 99.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26-27 9 0.16% 99.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-29 9 0.16% 99.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::30-31 6 0.11% 99.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-33 7 0.13% 99.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::34-35 3 0.05% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-37 1 0.02% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::38-39 4 0.07% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::42-43 2 0.04% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-45 2 0.04% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::46-47 2 0.04% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::54-55 1 0.02% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.338182 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.234627 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 2.449204 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-17 2631 47.25% 47.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18-19 2778 49.89% 97.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-21 61 1.10% 98.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22-23 29 0.52% 98.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-25 20 0.36% 99.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::30-31 7 0.13% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-33 5 0.09% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::34-35 2 0.04% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-37 5 0.09% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::38-39 2 0.04% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-41 2 0.04% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::42-43 2 0.04% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::46-47 1 0.02% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-53 2 0.04% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-57 1 0.02% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-61 1 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads
240,244c242,246
< system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads
< system.physmem.totQLat 1534207250 # Total ticks spent queuing
< system.physmem.totMemAccLat 4235351000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 720305000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10649.71 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads
> system.physmem.totQLat 1536843000 # Total ticks spent queuing
> system.physmem.totMemAccLat 4238099250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10667.56 # Average queueing delay per DRAM burst
246,250c248,252
< system.physmem.avgMemAccLat 29399.71 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 25.24 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 16.92 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 29417.56 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 16.86 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s
255,273c257,275
< system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 20.29 # Average write queue length when enqueuing
< system.physmem.readRowHits 111019 # Number of row buffer hits during reads
< system.physmem.writeRowHits 64498 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes
< system.physmem.avgGap 1517614.82 # Average gap between requests
< system.physmem.pageHitRate 72.94 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 247892400 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 135258750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 560445600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 47138982615 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 177839337750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 250093102155 # Total energy per rank (pJ)
< system.physmem_0.averagePower 684.594758 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 295545266000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 12198680000 # Time in different power states
---
> system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 20.79 # Average write queue length when enqueuing
> system.physmem.readRowHits 110982 # Number of row buffer hits during reads
> system.physmem.writeRowHits 64419 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 66.72 # Row buffer hit rate for writes
> system.physmem.avgGap 1521802.26 # Average gap between requests
> system.physmem.pageHitRate 72.89 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 248111640 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 135378375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 560734200 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 310741920 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 47516601060 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 178134108000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 250834440315 # Total energy per rank (pJ)
> system.physmem_0.averagePower 684.668623 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 296034178750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 12233260000 # Time in different power states
275c277
< system.physmem_0.memoryStateTime::ACT 57571800000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 58091210000 # Time in different power states
277,287c279,289
< system.physmem_1.actEnergy 244014120 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 133142625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 563058600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 314817840 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 46734210225 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 178194401250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 250044262740 # Total energy per rank (pJ)
< system.physmem_1.averagePower 684.461067 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 296138902500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 12198680000 # Time in different power states
---
> system.physmem_1.actEnergy 244838160 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 133592250 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 562988400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 314830800 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 46994125095 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 178592423250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 250771563075 # Total energy per rank (pJ)
> system.physmem_1.averagePower 684.496987 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 296797282750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 12233260000 # Time in different power states
289c291
< system.physmem_1.memoryStateTime::ACT 56977968750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 57328110000 # Time in different power states
291,295c293,297
< system.cpu.branchPred.lookups 132578917 # Number of BP lookups
< system.cpu.branchPred.condPredicted 98507789 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 6555100 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 69037584 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 64855119 # Number of BTB hits
---
> system.cpu.branchPred.lookups 132587783 # Number of BP lookups
> system.cpu.branchPred.condPredicted 98513206 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 6558220 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 68845364 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 64852055 # Number of BTB hits
297,299c299,301
< system.cpu.branchPred.BTBHitPct 93.941756 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 10014942 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 17500 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 94.199596 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 10016928 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 17846 # Number of incorrect RAS predictions.
418c420
< system.cpu.numCycles 730634466 # number of cpu cycles simulated
---
> system.cpu.numCycles 732717409 # number of cpu cycles simulated
423c425
< system.cpu.discardedOps 13461155 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 13466110 # Number of ops (including micro ops) which were discarded before commit
425,437c427,439
< system.cpu.cpi 1.442282 # CPI: cycles per instruction
< system.cpu.ipc 0.693346 # IPC: instructions per cycle
< system.cpu.tickCycles 695780172 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 34854294 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 1139812 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4071.074819 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 171281876 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4071.074819 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.993915 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy
---
> system.cpu.cpi 1.446394 # CPI: cycles per instruction
> system.cpu.ipc 0.691375 # IPC: instructions per cycle
> system.cpu.tickCycles 695820940 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 36896469 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 1139887 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4070.954708 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 171283476 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1143983 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 149.725543 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954708 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy
440c442
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
442c444
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id
444,449c446,451
< system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 114766084 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 53538710 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 346821767 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 346821767 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 114767712 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 114767712 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 53538682 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 53538682 # number of WriteReq hits
454,475c456,477
< system.cpu.dcache.demand_hits::cpu.data 168304794 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 168304794 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 168304794 # number of overall hits
< system.cpu.dcache.overall_hits::total 168304794 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 854755 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 854755 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 700596 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 700596 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1555351 # number of overall misses
< system.cpu.dcache.overall_misses::total 1555351 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 13707430482 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 13707430482 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 20521575250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 20521575250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34229005732 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34229005732 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34229005732 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34229005732 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 115620839 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 115620839 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 168306394 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 168306394 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 168306394 # number of overall hits
> system.cpu.dcache.overall_hits::total 168306394 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 854792 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 854792 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 700624 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 700624 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 1555416 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1555416 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1555416 # number of overall misses
> system.cpu.dcache.overall_misses::total 1555416 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024046732 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 14024046732 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 22031424000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 22031424000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 36055470732 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 36055470732 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 36055470732 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 36055470732 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 115622504 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 115622504 # number of ReadReq accesses(hits+misses)
482,485c484,487
< system.cpu.dcache.demand_accesses::cpu.data 169860145 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 169860145 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 169860145 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 169860145 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 169861810 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 169861810 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 169861810 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 169861810 # number of overall (read+write) accesses
494,501c496,503
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16036.677740 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29291.596369 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 22007.254782 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.385100 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.385100 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31445.431501 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31445.431501 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 23180.596530 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 23180.596530 # average overall miss latency
510,537c512,539
< system.cpu.dcache.writebacks::writebacks 1068525 # number of writebacks
< system.cpu.dcache.writebacks::total 1068525 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66991 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 66991 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344452 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 344452 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 411443 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 411443 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 411443 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 411443 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787764 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 787764 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356144 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 356144 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1143908 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1143908 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1143908 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1143908 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11252029015 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252029015 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10073374750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10073374750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21325403765 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 21325403765 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21325403765 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 21325403765 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.writebacks::writebacks 1068568 # number of writebacks
> system.cpu.dcache.writebacks::total 1068568 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66956 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 66956 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344477 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 344477 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 411433 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 411433 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 411433 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 411433 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787836 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 787836 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356147 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1143983 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1143983 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1143983 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1143983 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930645015 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930645015 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10967643750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10967643750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22898288765 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 22898288765 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22898288765 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 22898288765 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006814 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006814 # mshr miss rate for ReadReq accesses
540,551c542,553
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14283.502439 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14283.502439 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28284.555545 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28284.555545 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15143.564162 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15143.564162 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30795.272037 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30795.272037 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency
553,557c555,559
< system.cpu.icache.tags.replacements 17690 # number of replacements
< system.cpu.icache.tags.tagsinuse 1190.635807 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 200942292 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 19563 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 10271.547922 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 17670 # number of replacements
> system.cpu.icache.tags.tagsinuse 1190.214047 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 200949213 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 19542 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 10282.939975 # Average number of references to valid blocks.
559,562c561,564
< system.cpu.icache.tags.occ_blocks::cpu.inst 1190.635807 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.581365 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.581365 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1873 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1190.214047 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.581159 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.581159 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id
565,594c567,596
< system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1406 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.914551 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 401943273 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 401943273 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 200942292 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 200942292 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 200942292 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 200942292 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 200942292 # number of overall hits
< system.cpu.icache.overall_hits::total 200942292 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 19563 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 19563 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 19563 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 19563 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 19563 # number of overall misses
< system.cpu.icache.overall_misses::total 19563 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 469537995 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 469537995 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 469537995 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 469537995 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 469537995 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 469537995 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 200961855 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 200961855 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 200961855 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 200961855 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 200961855 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 200961855 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 401957052 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 401957052 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 200949213 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 200949213 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 200949213 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 200949213 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 200949213 # number of overall hits
> system.cpu.icache.overall_hits::total 200949213 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 19542 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 19542 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 19542 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 19542 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 19542 # number of overall misses
> system.cpu.icache.overall_misses::total 19542 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 494400997 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 494400997 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 494400997 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 494400997 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 494400997 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 494400997 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 200968755 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 200968755 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 200968755 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 200968755 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 200968755 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 200968755 # number of overall (read+write) accesses
601,606c603,608
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24001.328784 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 24001.328784 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 24001.328784 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 24001.328784 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 24001.328784 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 24001.328784 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25299.406253 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 25299.406253 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 25299.406253 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 25299.406253 # average overall miss latency
615,626c617,628
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19563 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 19563 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 19563 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 19563 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 19563 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 19563 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429024005 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 429024005 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429024005 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 429024005 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429024005 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 429024005 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19542 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 19542 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 19542 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 19542 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 19542 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 19542 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 463701003 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 463701003 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 463701003 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 463701003 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 463701003 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 463701003 # number of overall MSHR miss cycles
633,638c635,640
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21930.379032 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21930.379032 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21930.379032 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 21930.379032 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21930.379032 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 21930.379032 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23728.431225 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23728.431225 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23728.431225 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 23728.431225 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23728.431225 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 23728.431225 # average overall mshr miss latency
640,653c642,655
< system.cpu.l2cache.tags.replacements 111403 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 27648.458293 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1684717 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 142590 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 11.815113 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 163177408500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 23523.224801 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.561382 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 3735.672111 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.717872 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011888 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.114004 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.843764 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 31187 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.replacements 111429 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 27648.762381 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1684764 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 142617 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 11.813206 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 163811788500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 23520.899956 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.576322 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 3737.286102 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.717801 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.114053 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.843773 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
655,730c657,732
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4940 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25856 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951752 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 18354956 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 18354956 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 16090 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 747677 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 763767 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1068525 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1068525 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 255530 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 255530 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 16090 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1003207 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1019297 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 16090 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1003207 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1019297 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 3473 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 39833 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 43306 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 100868 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 100868 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 3473 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 140701 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 144174 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 3473 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 140701 # number of overall misses
< system.cpu.l2cache.overall_misses::total 144174 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 248520000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2980751000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 3229271000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7164307250 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7164307250 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 248520000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10145058250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10393578250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 248520000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10145058250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10393578250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 19563 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 787510 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 807073 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1068525 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1068525 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 356398 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 356398 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 19563 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1143908 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1163471 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 19563 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1143908 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1163471 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177529 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050581 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.053658 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283021 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.283021 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177529 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.123000 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.123917 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177529 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.123000 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.123917 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71557.731068 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74831.195240 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74568.674087 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71026.561942 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71026.561942 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71557.731068 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72103.668417 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72090.517361 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71557.731068 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72103.668417 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72090.517361 # average overall miss latency
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4941 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 18355761 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 18355761 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 16076 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 747713 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 763789 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1068568 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1068568 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 255536 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 255536 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 16076 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1003249 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1019325 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 16076 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1003249 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1019325 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 3466 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 39870 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 43336 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 100864 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 100864 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 3466 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 140734 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 144200 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 3466 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 140734 # number of overall misses
> system.cpu.l2cache.overall_misses::total 144200 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 275297000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3285022000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 3560319000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7930866750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7930866750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 275297000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11215888750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11491185750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 275297000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11215888750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11491185750 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 19542 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 787583 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 807125 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1068568 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1068568 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 356400 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 19542 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1143983 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1163525 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 19542 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1143983 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1163525 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177362 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050623 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.053692 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283008 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177362 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.123021 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.123934 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177362 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.123021 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.123934 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79427.870744 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82393.328317 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 82156.151929 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78629.310259 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78629.310259 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79427.870744 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79695.658121 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 79689.221567 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79427.870744 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79695.658121 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 79689.221567 # average overall miss latency
739,740c741,742
< system.cpu.l2cache.writebacks::writebacks 96561 # number of writebacks
< system.cpu.l2cache.writebacks::total 96561 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 96557 # number of writebacks
> system.cpu.l2cache.writebacks::total 96557 # number of writebacks
750,793c752,795
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3471 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39818 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 43289 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100868 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 100868 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 3471 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 140686 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 144157 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 3471 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 140686 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 144157 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 204743500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2475547000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2680290500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5883442250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5883442250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204743500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8358989250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 8563732750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204743500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8358989250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 8563732750 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050562 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053637 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283021 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283021 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.123903 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.123903 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58986.891386 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62171.555578 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58328.134294 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3464 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39855 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 43319 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100864 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 100864 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 3464 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 140719 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 144183 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 3464 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 140719 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 144183 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 231582500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2784547250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3016129750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6669444250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6669444250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 231582500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9453991500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9685574000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 231582500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9453991500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9685574000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050604 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053671 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283008 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123008 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123008 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66854.070439 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69866.948940 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69626.024377 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66123.138583 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66123.138583 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency
795,805c797,807
< system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 807073 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 1068525 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 356398 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 356398 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39126 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356341 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 3395467 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252032 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141595712 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 142847744 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadReq 807125 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 807125 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 1068568 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39084 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356534 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 3395618 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250688 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141603264 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 142853952 # Cumulative packet size per connected master and slave (bytes)
807,808c809,810
< system.cpu.toL2Bus.snoop_fanout::samples 2231996 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 2232093 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
814,817c816,817
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 2231996 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 2232093 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
819,822c819,822
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 2231996 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2184523000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 2232093 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2184614500 # Layer occupancy (ticks)
824c824
< system.cpu.toL2Bus.respLayer0.occupancy 30038495 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 30006497 # Layer occupancy (ticks)
826c826
< system.cpu.toL2Bus.respLayer1.occupancy 1744651235 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1744748235 # Layer occupancy (ticks)
828,836c828,836
< system.membus.trans_dist::ReadReq 43289 # Transaction distribution
< system.membus.trans_dist::ReadResp 43289 # Transaction distribution
< system.membus.trans_dist::Writeback 96561 # Transaction distribution
< system.membus.trans_dist::ReadExReq 100868 # Transaction distribution
< system.membus.trans_dist::ReadExResp 100868 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384875 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 384875 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15405952 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 15405952 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadReq 43319 # Transaction distribution
> system.membus.trans_dist::ReadResp 43319 # Transaction distribution
> system.membus.trans_dist::Writeback 96557 # Transaction distribution
> system.membus.trans_dist::ReadExReq 100864 # Transaction distribution
> system.membus.trans_dist::ReadExResp 100864 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384923 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 384923 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407360 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 15407360 # Cumulative packet size per connected master and slave (bytes)
838c838
< system.membus.snoop_fanout::samples 240718 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 240740 # Request fanout histogram
842c842
< system.membus.snoop_fanout::0 240718 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 240740 100.00% 100.00% # Request fanout histogram
847,851c847,851
< system.membus.snoop_fanout::total 240718 # Request fanout histogram
< system.membus.reqLayer0.occupancy 1081999000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
< system.membus.respLayer1.occupancy 1366864750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
---
> system.membus.snoop_fanout::total 240740 # Request fanout histogram
> system.membus.reqLayer0.occupancy 679202000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
> system.membus.respLayer1.occupancy 765364000 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.2 # Layer utilization (%)