Cross Reference: /gem5/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.368600 # Number of seconds simulated

4sim_ticks 368600034500 # Number of ticks simulated
5final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 368600047500 # Number of ticks simulated
5final_tick 368600047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 368828 # Simulator instruction rate (inst/s)
8host_op_rate 399489 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 268368313 # Simulator tick rate (ticks/s)
10host_mem_usage 276836 # Number of bytes of host memory used
11host_seconds 1373.49 # Real time elapsed on the host

7host_inst_rate 377886 # Simulator instruction rate (inst/s)
8host_op_rate 409300 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 274959159 # Simulator tick rate (ticks/s)
10host_mem_usage 276756 # Number of bytes of host memory used
11host_seconds 1340.56 # Real time elapsed on the host

12sim_insts 506579366 # Number of instructions simulated
13sim_ops 548692589 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory
19system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory
23system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory
29system.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s)

30system.physmem.bw_read::cpu.data 24561517 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 25049417 # Total read bandwidth from this memory (bytes/s)

30system.physmem.bw_read::cpu.data 24561516 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 25049416 # Total read bandwidth from this memory (bytes/s)

32system.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s)

38system.physmem.bw_total::cpu.data 24561517 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 41983197 # Total bandwidth to/from this memory (bytes/s)

38system.physmem.bw_total::cpu.data 24561516 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 41983196 # Total bandwidth to/from this memory (bytes/s)

40system.physmem.readReqs 144269 # Number of read requests accepted
41system.physmem.writeReqs 97528 # Number of write requests accepted
42system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue
43system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue
44system.physmem.bytesReadDRAM 9225856 # Total number of bytes read from DRAM
45system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue
46system.physmem.bytesWritten 6240448 # Total number of bytes written to DRAM
47system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side
48system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side
49system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue
50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
52system.physmem.perBankRdBursts::0 9372 # Per bank write bursts
53system.physmem.perBankRdBursts::1 8929 # Per bank write bursts
54system.physmem.perBankRdBursts::2 8963 # Per bank write bursts
55system.physmem.perBankRdBursts::3 8667 # Per bank write bursts
56system.physmem.perBankRdBursts::4 9424 # Per bank write bursts
57system.physmem.perBankRdBursts::5 9372 # Per bank write bursts
58system.physmem.perBankRdBursts::6 8974 # Per bank write bursts
59system.physmem.perBankRdBursts::7 8127 # Per bank write bursts
60system.physmem.perBankRdBursts::8 8635 # Per bank write bursts
61system.physmem.perBankRdBursts::9 8697 # Per bank write bursts
62system.physmem.perBankRdBursts::10 8761 # Per bank write bursts
63system.physmem.perBankRdBursts::11 9485 # Per bank write bursts
64system.physmem.perBankRdBursts::12 9346 # Per bank write bursts
65system.physmem.perBankRdBursts::13 9545 # Per bank write bursts
66system.physmem.perBankRdBursts::14 8729 # Per bank write bursts
67system.physmem.perBankRdBursts::15 9128 # Per bank write bursts
68system.physmem.perBankWrBursts::0 6253 # Per bank write bursts
69system.physmem.perBankWrBursts::1 6118 # Per bank write bursts
70system.physmem.perBankWrBursts::2 6042 # Per bank write bursts
71system.physmem.perBankWrBursts::3 5901 # Per bank write bursts
72system.physmem.perBankWrBursts::4 6273 # Per bank write bursts
73system.physmem.perBankWrBursts::5 6263 # Per bank write bursts
74system.physmem.perBankWrBursts::6 6069 # Per bank write bursts
75system.physmem.perBankWrBursts::7 5535 # Per bank write bursts
76system.physmem.perBankWrBursts::8 5819 # Per bank write bursts
77system.physmem.perBankWrBursts::9 5920 # Per bank write bursts
78system.physmem.perBankWrBursts::10 5985 # Per bank write bursts
79system.physmem.perBankWrBursts::11 6510 # Per bank write bursts
80system.physmem.perBankWrBursts::12 6360 # Per bank write bursts
81system.physmem.perBankWrBursts::13 6344 # Per bank write bursts
82system.physmem.perBankWrBursts::14 6013 # Per bank write bursts
83system.physmem.perBankWrBursts::15 6102 # Per bank write bursts
84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

86system.physmem.totGap 368600009000 # Total gap between requests

86system.physmem.totGap 368600022000 # Total gap between requests

87system.physmem.readPktSize::0 0 # Read request sizes (log2)
88system.physmem.readPktSize::1 0 # Read request sizes (log2)
89system.physmem.readPktSize::2 0 # Read request sizes (log2)
90system.physmem.readPktSize::3 0 # Read request sizes (log2)
91system.physmem.readPktSize::4 0 # Read request sizes (log2)
92system.physmem.readPktSize::5 0 # Read request sizes (log2)
93system.physmem.readPktSize::6 144269 # Read request sizes (log2)
94system.physmem.writePktSize::0 0 # Write request sizes (log2)
95system.physmem.writePktSize::1 0 # Write request sizes (log2)
96system.physmem.writePktSize::2 0 # Write request sizes (log2)
97system.physmem.writePktSize::3 0 # Write request sizes (log2)
98system.physmem.writePktSize::4 0 # Write request sizes (log2)
99system.physmem.writePktSize::5 0 # Write request sizes (log2)
100system.physmem.writePktSize::6 97528 # Write request sizes (log2)
101system.physmem.rdQLenPdf::0 143801 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 333 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
133system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::15 2730 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::17 5701 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::18 5739 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::19 5742 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::20 5743 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::21 5741 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::22 5741 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::23 5741 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::24 5744 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::25 5746 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::26 5749 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::28 5745 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::30 5752 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::31 5747 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::32 5741 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
197system.physmem.bytesPerActivate::samples 63970 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::mean 241.763327 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::gmean 162.115864 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::stdev 241.210402 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::0-127 22774 35.60% 35.60% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::128-255 18302 28.61% 64.21% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::256-383 7461 11.66% 75.87% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::384-511 8049 12.58% 88.46% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::512-639 2117 3.31% 91.77% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::640-767 1180 1.84% 93.61% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::768-895 776 1.21% 94.82% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::896-1023 623 0.97% 95.80% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::1024-1151 2688 4.20% 100.00% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::total 63970 # Bytes accessed per row activation
211system.physmem.rdPerTurnAround::samples 5740 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::mean 25.113240 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::stdev 375.658190 # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::0-1023 5737 99.95% 99.95% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::total 5740 # Reads before turning the bus around for writes
218system.physmem.wrPerTurnAround::samples 5740 # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::mean 16.987282 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::gmean 16.957535 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::stdev 1.009458 # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::16 2852 49.69% 49.69% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::17 159 2.77% 52.46% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::18 2701 47.06% 99.51% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::19 19 0.33% 99.84% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::20 6 0.10% 99.95% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads

231system.physmem.totQLat 3577413000 # Total ticks spent queuing
232system.physmem.totMemAccLat 6280300500 # Total ticks spent from burst creation until serviced by the DRAM

231system.physmem.totQLat 3577410500 # Total ticks spent queuing
232system.physmem.totMemAccLat 6280298000 # Total ticks spent from burst creation until serviced by the DRAM

233system.physmem.totBusLat 720770000 # Total ticks spent in databus transfers

234system.physmem.avgQLat 24816.61 # Average queueing delay per DRAM burst

234system.physmem.avgQLat 24816.59 # Average queueing delay per DRAM burst

235system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

236system.physmem.avgMemAccLat 43566.61 # Average memory access latency per DRAM burst

236system.physmem.avgMemAccLat 43566.59 # Average memory access latency per DRAM burst

237system.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s
238system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s
239system.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s
240system.physmem.avgWrBWSys 16.93 # Average system write bandwidth in MiByte/s
241system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
242system.physmem.busUtil 0.33 # Data bus utilization in percentage
243system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
244system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
245system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
246system.physmem.avgWrQLen 20.06 # Average write queue length when enqueuing
247system.physmem.readRowHits 110541 # Number of row buffer hits during reads
248system.physmem.writeRowHits 67141 # Number of row buffer hits during writes
249system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads
250system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes

251system.physmem.avgGap 1524419.28 # Average gap between requests

251system.physmem.avgGap 1524419.34 # Average gap between requests

252system.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined
253system.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ)
254system.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ)
255system.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ)
256system.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ)
257system.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ)

258system.physmem_0.actBackEnergy 3985238790 # Energy for active background per rank (pJ)
259system.physmem_0.preBackEnergy 353652480 # Energy for precharge background per rank (pJ)
260system.physmem_0.actPowerDownEnergy 24742370760 # Energy for active power-down per rank (pJ)
261system.physmem_0.prePowerDownEnergy 8329193280 # Energy for precharge power-down per rank (pJ)
262system.physmem_0.selfRefreshEnergy 68838779610 # Energy for self refresh per rank (pJ)
263system.physmem_0.totalEnergy 115080424995 # Total energy per rank (pJ)
264system.physmem_0.averagePower 312.209476 # Core power per rank (mW)
265system.physmem_0.totalIdleTime 358934915250 # Total Idle time Per DRAM Rank

258system.physmem_0.actBackEnergy 3985232520 # Energy for active background per rank (pJ)
259system.physmem_0.preBackEnergy 353635200 # Energy for precharge background per rank (pJ)
260system.physmem_0.actPowerDownEnergy 24742392420 # Energy for active power-down per rank (pJ)
261system.physmem_0.prePowerDownEnergy 8329190880 # Energy for precharge power-down per rank (pJ)
262system.physmem_0.selfRefreshEnergy 68838786810 # Energy for self refresh per rank (pJ)
263system.physmem_0.totalEnergy 115080429525 # Total energy per rank (pJ)
264system.physmem_0.averagePower 312.209478 # Core power per rank (mW)
265system.physmem_0.totalIdleTime 358934929250 # Total Idle time Per DRAM Rank

266system.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states
267system.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states

268system.physmem_0.memoryStateTime::SREF 282985145000 # Time in different power states
269system.physmem_0.memoryStateTime::PRE_PDN 21690770000 # Time in different power states
270system.physmem_0.memoryStateTime::ACT 5858999750 # Time in different power states
271system.physmem_0.memoryStateTime::ACT_PDN 54259446500 # Time in different power states

268system.physmem_0.memoryStateTime::SREF 282985158000 # Time in different power states
269system.physmem_0.memoryStateTime::PRE_PDN 21690772000 # Time in different power states
270system.physmem_0.memoryStateTime::ACT 5858998750 # Time in different power states
271system.physmem_0.memoryStateTime::ACT_PDN 54259445500 # Time in different power states

272system.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ)
273system.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ)
274system.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ)
275system.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ)
276system.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ)

277system.physmem_1.actBackEnergy 3990658350 # Energy for active background per rank (pJ)
278system.physmem_1.preBackEnergy 342745440 # Energy for precharge background per rank (pJ)
279system.physmem_1.actPowerDownEnergy 24389253480 # Energy for active power-down per rank (pJ)
280system.physmem_1.prePowerDownEnergy 8128930080 # Energy for precharge power-down per rank (pJ)
281system.physmem_1.selfRefreshEnergy 69135041760 # Energy for self refresh per rank (pJ)
282system.physmem_1.totalEnergy 114698280525 # Total energy per rank (pJ)
283system.physmem_1.averagePower 311.172732 # Core power per rank (mW)
284system.physmem_1.totalIdleTime 358951286500 # Total Idle time Per DRAM Rank

277system.physmem_1.actBackEnergy 3990680010 # Energy for active background per rank (pJ)
278system.physmem_1.preBackEnergy 342748800 # Energy for precharge background per rank (pJ)
279system.physmem_1.actPowerDownEnergy 24389261460 # Energy for active power-down per rank (pJ)
280system.physmem_1.prePowerDownEnergy 8128903200 # Energy for precharge power-down per rank (pJ)
281system.physmem_1.selfRefreshEnergy 69135043560 # Energy for self refresh per rank (pJ)
282system.physmem_1.totalEnergy 114698287785 # Total energy per rank (pJ)
283system.physmem_1.averagePower 311.172742 # Core power per rank (mW)
284system.physmem_1.totalIdleTime 358951299500 # Total Idle time Per DRAM Rank

285system.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states
286system.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states

287system.physmem_1.memoryStateTime::SREF 284296674500 # Time in different power states

287system.physmem_1.memoryStateTime::SREF 284296687500 # Time in different power states

288system.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states
289system.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states
290system.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states

291system.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

291system.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

292system.cpu.branchPred.lookups 132103819 # Number of BP lookups
293system.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted
294system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect
295system.cpu.branchPred.BTBLookups 68601561 # Number of BTB lookups
296system.cpu.branchPred.BTBHits 60590477 # Number of BTB hits
297system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
298system.cpu.branchPred.BTBHitPct 88.322301 # BTB Hit Percentage
299system.cpu.branchPred.usedRAS 10017121 # Number of times the RAS was used to get a target.
300system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions.
301system.cpu.branchPred.indirectLookups 3891575 # Number of indirect predictor lookups.
302system.cpu.branchPred.indirectHits 3883028 # Number of indirect target hits.
303system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses.
304system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches.
305system.cpu_clk_domain.clock 500 # Clock period in ticks

306system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

306system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

307system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
315system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
316system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
317system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
318system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
319system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
320system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
322system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
323system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
324system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
325system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
326system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
327system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
328system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
329system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
330system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
331system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
332system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
333system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
334system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
335system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

336system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

336system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

337system.cpu.dtb.walker.walks 0 # Table walker walks requested
338system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
339system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
340system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
341system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
342system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
343system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
344system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
345system.cpu.dtb.inst_hits 0 # ITB inst hits
346system.cpu.dtb.inst_misses 0 # ITB inst misses
347system.cpu.dtb.read_hits 0 # DTB read hits
348system.cpu.dtb.read_misses 0 # DTB read misses
349system.cpu.dtb.write_hits 0 # DTB write hits
350system.cpu.dtb.write_misses 0 # DTB write misses
351system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
352system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
353system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
354system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
355system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
356system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
357system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
358system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
359system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
360system.cpu.dtb.read_accesses 0 # DTB read accesses
361system.cpu.dtb.write_accesses 0 # DTB write accesses
362system.cpu.dtb.inst_accesses 0 # ITB inst accesses
363system.cpu.dtb.hits 0 # DTB hits
364system.cpu.dtb.misses 0 # DTB misses
365system.cpu.dtb.accesses 0 # DTB accesses

366system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

366system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

367system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
375system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
376system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
377system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
378system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
379system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
380system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
381system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
382system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
383system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
384system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
385system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
386system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
387system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
388system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
389system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
390system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
391system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
392system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
393system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
394system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
395system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

396system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

396system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

397system.cpu.itb.walker.walks 0 # Table walker walks requested
398system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
399system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
400system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
401system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
402system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
403system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
404system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
405system.cpu.itb.inst_hits 0 # ITB inst hits
406system.cpu.itb.inst_misses 0 # ITB inst misses
407system.cpu.itb.read_hits 0 # DTB read hits
408system.cpu.itb.read_misses 0 # DTB read misses
409system.cpu.itb.write_hits 0 # DTB write hits
410system.cpu.itb.write_misses 0 # DTB write misses
411system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
412system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
413system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
414system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
415system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
416system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
417system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
418system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
419system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
420system.cpu.itb.read_accesses 0 # DTB read accesses
421system.cpu.itb.write_accesses 0 # DTB write accesses
422system.cpu.itb.inst_accesses 0 # ITB inst accesses
423system.cpu.itb.hits 0 # DTB hits
424system.cpu.itb.misses 0 # DTB misses
425system.cpu.itb.accesses 0 # DTB accesses
426system.cpu.workload.num_syscalls 548 # Number of system calls

427system.cpu.pwrStateResidencyTicks::ON 368600034500 # Cumulative time (in ticks) in various power states
428system.cpu.numCycles 737200069 # number of cpu cycles simulated

427system.cpu.pwrStateResidencyTicks::ON 368600047500 # Cumulative time (in ticks) in various power states
428system.cpu.numCycles 737200095 # number of cpu cycles simulated

429system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
430system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
431system.cpu.committedInsts 506579366 # Number of instructions committed
432system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed
433system.cpu.discardedOps 12939783 # Number of ops (including micro ops) which were discarded before commit
434system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
435system.cpu.cpi 1.455251 # CPI: cycles per instruction
436system.cpu.ipc 0.687167 # IPC: instructions per cycle
437system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
438system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction
439system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
440system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
441system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
442system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
443system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
444system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
445system.cpu.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction
446system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
447system.cpu.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction
448system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
449system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
450system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
451system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
452system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
453system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
454system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
455system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
456system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
457system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
458system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
459system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
460system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
461system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
462system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
463system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
464system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
465system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
466system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
467system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
468system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
469system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
470system.cpu.op_class_0::MemWrite 56860206 10.36% 100.00% # Class of committed instruction
471system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
472system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction
473system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
474system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
475system.cpu.op_class_0::total 548692589 # Class of committed instruction

476system.cpu.tickCycles 694074439 # Number of cycles that the object actually ticked
477system.cpu.idleCycles 43125630 # Total number of cycles that the object has spent stopped
478system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

476system.cpu.tickCycles 694074449 # Number of cycles that the object actually ticked
477system.cpu.idleCycles 43125646 # Total number of cycles that the object has spent stopped
478system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

479system.cpu.dcache.tags.replacements 1141337 # number of replacements

480system.cpu.dcache.tags.tagsinuse 4070.214597 # Cycle average of tags in use
481system.cpu.dcache.tags.total_refs 171083824 # Total number of references to valid blocks.

480system.cpu.dcache.tags.tagsinuse 4070.214598 # Cycle average of tags in use
481system.cpu.dcache.tags.total_refs 171083823 # Total number of references to valid blocks.

482system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks.
483system.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks.
484system.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit.

485system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214597 # Average occupied blocks per requestor

485system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214598 # Average occupied blocks per requestor

486system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy
487system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy
488system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
489system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
490system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
491system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id
492system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id
493system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

494system.cpu.dcache.tags.tag_accesses 346338045 # Number of tag accesses
495system.cpu.dcache.tags.data_accesses 346338045 # Number of data accesses
496system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
497system.cpu.dcache.ReadReq_hits::cpu.data 114566013 # number of ReadReq hits
498system.cpu.dcache.ReadReq_hits::total 114566013 # number of ReadReq hits

494system.cpu.dcache.tags.tag_accesses 346338043 # Number of tag accesses
495system.cpu.dcache.tags.data_accesses 346338043 # Number of data accesses
496system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
497system.cpu.dcache.ReadReq_hits::cpu.data 114566012 # number of ReadReq hits
498system.cpu.dcache.ReadReq_hits::total 114566012 # number of ReadReq hits

499system.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits
500system.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits
501system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits
502system.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits
503system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
504system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
505system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
506system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits

507system.cpu.dcache.demand_hits::cpu.data 168103948 # number of demand (read+write) hits
508system.cpu.dcache.demand_hits::total 168103948 # number of demand (read+write) hits
509system.cpu.dcache.overall_hits::cpu.data 168106742 # number of overall hits
510system.cpu.dcache.overall_hits::total 168106742 # number of overall hits

507system.cpu.dcache.demand_hits::cpu.data 168103947 # number of demand (read+write) hits
508system.cpu.dcache.demand_hits::total 168103947 # number of demand (read+write) hits
509system.cpu.dcache.overall_hits::cpu.data 168106741 # number of overall hits
510system.cpu.dcache.overall_hits::total 168106741 # number of overall hits

511system.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses
512system.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses
513system.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses
514system.cpu.dcache.WriteReq_misses::total 701114 # number of WriteReq misses
515system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses
516system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses
517system.cpu.dcache.demand_misses::cpu.data 1512467 # number of demand (read+write) misses
518system.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses
519system.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses
520system.cpu.dcache.overall_misses::total 1512482 # number of overall misses

521system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511838000 # number of ReadReq miss cycles
522system.cpu.dcache.ReadReq_miss_latency::total 14511838000 # number of ReadReq miss cycles
523system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015669000 # number of WriteReq miss cycles
524system.cpu.dcache.WriteReq_miss_latency::total 24015669000 # number of WriteReq miss cycles
525system.cpu.dcache.demand_miss_latency::cpu.data 38527507000 # number of demand (read+write) miss cycles
526system.cpu.dcache.demand_miss_latency::total 38527507000 # number of demand (read+write) miss cycles
527system.cpu.dcache.overall_miss_latency::cpu.data 38527507000 # number of overall miss cycles
528system.cpu.dcache.overall_miss_latency::total 38527507000 # number of overall miss cycles
529system.cpu.dcache.ReadReq_accesses::cpu.data 115377366 # number of ReadReq accesses(hits+misses)
530system.cpu.dcache.ReadReq_accesses::total 115377366 # number of ReadReq accesses(hits+misses)

521system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511839000 # number of ReadReq miss cycles
522system.cpu.dcache.ReadReq_miss_latency::total 14511839000 # number of ReadReq miss cycles
523system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015670000 # number of WriteReq miss cycles
524system.cpu.dcache.WriteReq_miss_latency::total 24015670000 # number of WriteReq miss cycles
525system.cpu.dcache.demand_miss_latency::cpu.data 38527509000 # number of demand (read+write) miss cycles
526system.cpu.dcache.demand_miss_latency::total 38527509000 # number of demand (read+write) miss cycles
527system.cpu.dcache.overall_miss_latency::cpu.data 38527509000 # number of overall miss cycles
528system.cpu.dcache.overall_miss_latency::total 38527509000 # number of overall miss cycles
529system.cpu.dcache.ReadReq_accesses::cpu.data 115377365 # number of ReadReq accesses(hits+misses)
530system.cpu.dcache.ReadReq_accesses::total 115377365 # number of ReadReq accesses(hits+misses)

531system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
532system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
533system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses)
534system.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses)
535system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
536system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
537system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
538system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)

539system.cpu.dcache.demand_accesses::cpu.data 169616415 # number of demand (read+write) accesses
540system.cpu.dcache.demand_accesses::total 169616415 # number of demand (read+write) accesses
541system.cpu.dcache.overall_accesses::cpu.data 169619224 # number of overall (read+write) accesses
542system.cpu.dcache.overall_accesses::total 169619224 # number of overall (read+write) accesses

539system.cpu.dcache.demand_accesses::cpu.data 169616414 # number of demand (read+write) accesses
540system.cpu.dcache.demand_accesses::total 169616414 # number of demand (read+write) accesses
541system.cpu.dcache.overall_accesses::cpu.data 169619223 # number of overall (read+write) accesses
542system.cpu.dcache.overall_accesses::total 169619223 # number of overall (read+write) accesses

543system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses
544system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses
545system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses
546system.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses
547system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses
548system.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses
549system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses
550system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses
551system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses
552system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses

553system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183 # average ReadReq miss latency
554system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183 # average ReadReq miss latency
555system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435 # average WriteReq miss latency
556system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435 # average WriteReq miss latency
557system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682 # average overall miss latency
558system.cpu.dcache.demand_avg_miss_latency::total 25473.287682 # average overall miss latency
559system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051 # average overall miss latency
560system.cpu.dcache.overall_avg_miss_latency::total 25473.035051 # average overall miss latency

553system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416 # average ReadReq miss latency
554system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416 # average ReadReq miss latency
555system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862 # average WriteReq miss latency
556system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862 # average WriteReq miss latency
557system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004 # average overall miss latency
558system.cpu.dcache.demand_avg_miss_latency::total 25473.289004 # average overall miss latency
559system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373 # average overall miss latency
560system.cpu.dcache.overall_avg_miss_latency::total 25473.036373 # average overall miss latency

561system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
562system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
563system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
564system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
565system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
566system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
567system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks
568system.cpu.dcache.writebacks::total 1068942 # number of writebacks
569system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22320 # number of ReadReq MSHR hits
570system.cpu.dcache.ReadReq_mshr_hits::total 22320 # number of ReadReq MSHR hits
571system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344726 # number of WriteReq MSHR hits
572system.cpu.dcache.WriteReq_mshr_hits::total 344726 # number of WriteReq MSHR hits
573system.cpu.dcache.demand_mshr_hits::cpu.data 367046 # number of demand (read+write) MSHR hits
574system.cpu.dcache.demand_mshr_hits::total 367046 # number of demand (read+write) MSHR hits
575system.cpu.dcache.overall_mshr_hits::cpu.data 367046 # number of overall MSHR hits
576system.cpu.dcache.overall_mshr_hits::total 367046 # number of overall MSHR hits
577system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses
578system.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses
579system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses
580system.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses
581system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses
582system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses
583system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses
584system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses
585system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses
586system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses

587system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416891000 # number of ReadReq MSHR miss cycles
588system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416891000 # number of ReadReq MSHR miss cycles
589system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191000 # number of WriteReq MSHR miss cycles
590system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191000 # number of WriteReq MSHR miss cycles

587system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416892000 # number of ReadReq MSHR miss cycles
588system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416892000 # number of ReadReq MSHR miss cycles
589system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191500 # number of WriteReq MSHR miss cycles
590system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191500 # number of WriteReq MSHR miss cycles

591system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles
592system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles

593system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613082000 # number of demand (read+write) MSHR miss cycles
594system.cpu.dcache.demand_mshr_miss_latency::total 25613082000 # number of demand (read+write) MSHR miss cycles
595system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617379000 # number of overall MSHR miss cycles
596system.cpu.dcache.overall_mshr_miss_latency::total 25617379000 # number of overall MSHR miss cycles

593system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613083500 # number of demand (read+write) MSHR miss cycles
594system.cpu.dcache.demand_mshr_miss_latency::total 25613083500 # number of demand (read+write) MSHR miss cycles
595system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617380500 # number of overall MSHR miss cycles
596system.cpu.dcache.overall_mshr_miss_latency::total 25617380500 # number of overall MSHR miss cycles

597system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses
598system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses
599system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses
600system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses
601system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses
602system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses
603system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses
604system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses
605system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses
606system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses

607system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356 # average ReadReq mshr miss latency
608system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356 # average ReadReq mshr miss latency
609system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713 # average WriteReq mshr miss latency
610system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713 # average WriteReq mshr miss latency

607system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623 # average ReadReq mshr miss latency
608system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623 # average ReadReq mshr miss latency
609system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116 # average WriteReq mshr miss latency
610system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116 # average WriteReq mshr miss latency

611system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency
612system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency

613system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009 # average overall mshr miss latency
614system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009 # average overall mshr miss latency
615system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163 # average overall mshr miss latency
616system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163 # average overall mshr miss latency
617system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

613system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319 # average overall mshr miss latency
614system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319 # average overall mshr miss latency
615system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473 # average overall mshr miss latency
616system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473 # average overall mshr miss latency
617system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

618system.cpu.icache.tags.replacements 18178 # number of replacements

619system.cpu.icache.tags.tagsinuse 1186.508914 # Cycle average of tags in use
620system.cpu.icache.tags.total_refs 199149017 # Total number of references to valid blocks.

619system.cpu.icache.tags.tagsinuse 1186.508929 # Cycle average of tags in use
620system.cpu.icache.tags.total_refs 199149019 # Total number of references to valid blocks.

621system.cpu.icache.tags.sampled_refs 20050 # Sample count of references to valid blocks.

622system.cpu.icache.tags.avg_refs 9932.619302 # Average number of references to valid blocks.

622system.cpu.icache.tags.avg_refs 9932.619401 # Average number of references to valid blocks.

623system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

624system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508914 # Average occupied blocks per requestor

624system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508929 # Average occupied blocks per requestor

625system.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy
626system.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy
627system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id
628system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
629system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
630system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
631system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id
632system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id
633system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id

634system.cpu.icache.tags.tag_accesses 398358184 # Number of tag accesses
635system.cpu.icache.tags.data_accesses 398358184 # Number of data accesses
636system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states
637system.cpu.icache.ReadReq_hits::cpu.inst 199149017 # number of ReadReq hits
638system.cpu.icache.ReadReq_hits::total 199149017 # number of ReadReq hits
639system.cpu.icache.demand_hits::cpu.inst 199149017 # number of demand (read+write) hits
640system.cpu.icache.demand_hits::total 199149017 # number of demand (read+write) hits
641system.cpu.icache.overall_hits::cpu.inst 199149017 # number of overall hits
642system.cpu.icache.overall_hits::total 199149017 # number of overall hits

634system.cpu.icache.tags.tag_accesses 398358188 # Number of tag accesses
635system.cpu.icache.tags.data_accesses 398358188 # Number of data accesses
636system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states
637system.cpu.icache.ReadReq_hits::cpu.inst 199149019 # number of ReadReq hits
638system.cpu.icache.ReadReq_hits::total 199149019 # number of ReadReq hits
639system.cpu.icache.demand_hits::cpu.inst 199149019 # number of demand (read+write) hits
640system.cpu.icache.demand_hits::total 199149019 # number of demand (read+write) hits
641system.cpu.icache.overall_hits::cpu.inst 199149019 # number of overall hits
642system.cpu.icache.overall_hits::total 199149019 # number of overall hits

643system.cpu.icache.ReadReq_misses::cpu.inst 20050 # number of ReadReq misses
644system.cpu.icache.ReadReq_misses::total 20050 # number of ReadReq misses
645system.cpu.icache.demand_misses::cpu.inst 20050 # number of demand (read+write) misses
646system.cpu.icache.demand_misses::total 20050 # number of demand (read+write) misses
647system.cpu.icache.overall_misses::cpu.inst 20050 # number of overall misses
648system.cpu.icache.overall_misses::total 20050 # number of overall misses

649system.cpu.icache.ReadReq_miss_latency::cpu.inst 544281000 # number of ReadReq miss cycles
650system.cpu.icache.ReadReq_miss_latency::total 544281000 # number of ReadReq miss cycles
651system.cpu.icache.demand_miss_latency::cpu.inst 544281000 # number of demand (read+write) miss cycles
652system.cpu.icache.demand_miss_latency::total 544281000 # number of demand (read+write) miss cycles
653system.cpu.icache.overall_miss_latency::cpu.inst 544281000 # number of overall miss cycles
654system.cpu.icache.overall_miss_latency::total 544281000 # number of overall miss cycles
655system.cpu.icache.ReadReq_accesses::cpu.inst 199169067 # number of ReadReq accesses(hits+misses)
656system.cpu.icache.ReadReq_accesses::total 199169067 # number of ReadReq accesses(hits+misses)
657system.cpu.icache.demand_accesses::cpu.inst 199169067 # number of demand (read+write) accesses
658system.cpu.icache.demand_accesses::total 199169067 # number of demand (read+write) accesses
659system.cpu.icache.overall_accesses::cpu.inst 199169067 # number of overall (read+write) accesses
660system.cpu.icache.overall_accesses::total 199169067 # number of overall (read+write) accesses

649system.cpu.icache.ReadReq_miss_latency::cpu.inst 544279500 # number of ReadReq miss cycles
650system.cpu.icache.ReadReq_miss_latency::total 544279500 # number of ReadReq miss cycles
651system.cpu.icache.demand_miss_latency::cpu.inst 544279500 # number of demand (read+write) miss cycles
652system.cpu.icache.demand_miss_latency::total 544279500 # number of demand (read+write) miss cycles
653system.cpu.icache.overall_miss_latency::cpu.inst 544279500 # number of overall miss cycles
654system.cpu.icache.overall_miss_latency::total 544279500 # number of overall miss cycles
655system.cpu.icache.ReadReq_accesses::cpu.inst 199169069 # number of ReadReq accesses(hits+misses)
656system.cpu.icache.ReadReq_accesses::total 199169069 # number of ReadReq accesses(hits+misses)
657system.cpu.icache.demand_accesses::cpu.inst 199169069 # number of demand (read+write) accesses
658system.cpu.icache.demand_accesses::total 199169069 # number of demand (read+write) accesses
659system.cpu.icache.overall_accesses::cpu.inst 199169069 # number of overall (read+write) accesses
660system.cpu.icache.overall_accesses::total 199169069 # number of overall (read+write) accesses

661system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses
662system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses
663system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses
664system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses
665system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses
666system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses

667system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539 # average ReadReq miss latency
668system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539 # average ReadReq miss latency
669system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency
670system.cpu.icache.demand_avg_miss_latency::total 27146.184539 # average overall miss latency
671system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency
672system.cpu.icache.overall_avg_miss_latency::total 27146.184539 # average overall miss latency

667system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.109726 # average ReadReq miss latency
668system.cpu.icache.ReadReq_avg_miss_latency::total 27146.109726 # average ReadReq miss latency
669system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency
670system.cpu.icache.demand_avg_miss_latency::total 27146.109726 # average overall miss latency
671system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency
672system.cpu.icache.overall_avg_miss_latency::total 27146.109726 # average overall miss latency

673system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
674system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
675system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
676system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
677system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
678system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
679system.cpu.icache.writebacks::writebacks 18178 # number of writebacks
680system.cpu.icache.writebacks::total 18178 # number of writebacks
681system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20050 # number of ReadReq MSHR misses
682system.cpu.icache.ReadReq_mshr_misses::total 20050 # number of ReadReq MSHR misses
683system.cpu.icache.demand_mshr_misses::cpu.inst 20050 # number of demand (read+write) MSHR misses
684system.cpu.icache.demand_mshr_misses::total 20050 # number of demand (read+write) MSHR misses
685system.cpu.icache.overall_mshr_misses::cpu.inst 20050 # number of overall MSHR misses
686system.cpu.icache.overall_mshr_misses::total 20050 # number of overall MSHR misses

687system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524231000 # number of ReadReq MSHR miss cycles
688system.cpu.icache.ReadReq_mshr_miss_latency::total 524231000 # number of ReadReq MSHR miss cycles
689system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524231000 # number of demand (read+write) MSHR miss cycles
690system.cpu.icache.demand_mshr_miss_latency::total 524231000 # number of demand (read+write) MSHR miss cycles
691system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524231000 # number of overall MSHR miss cycles
692system.cpu.icache.overall_mshr_miss_latency::total 524231000 # number of overall MSHR miss cycles

687system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524229500 # number of ReadReq MSHR miss cycles
688system.cpu.icache.ReadReq_mshr_miss_latency::total 524229500 # number of ReadReq MSHR miss cycles
689system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524229500 # number of demand (read+write) MSHR miss cycles
690system.cpu.icache.demand_mshr_miss_latency::total 524229500 # number of demand (read+write) MSHR miss cycles
691system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524229500 # number of overall MSHR miss cycles
692system.cpu.icache.overall_mshr_miss_latency::total 524229500 # number of overall MSHR miss cycles

693system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses
694system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses
695system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses
696system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses
697system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses
698system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses

699system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539 # average ReadReq mshr miss latency
700system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539 # average ReadReq mshr miss latency
701system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency
702system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency
703system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency
704system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency
705system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

699system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.109726 # average ReadReq mshr miss latency
700system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.109726 # average ReadReq mshr miss latency
701system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency
702system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency
703system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency
704system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency
705system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

706system.cpu.l2cache.tags.replacements 112761 # number of replacements

707system.cpu.l2cache.tags.tagsinuse 29076.847904 # Cycle average of tags in use

707system.cpu.l2cache.tags.tagsinuse 29076.848035 # Cycle average of tags in use

708system.cpu.l2cache.tags.total_refs 2174458 # Total number of references to valid blocks.
709system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks.
710system.cpu.l2cache.tags.avg_refs 14.941750 # Average number of references to valid blocks.
711system.cpu.l2cache.tags.warmup_cycle 102118428000 # Cycle when the warmup percentage was hit.

712system.cpu.l2cache.tags.occ_blocks::writebacks 133.889042 # Average occupied blocks per requestor
713system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541070 # Average occupied blocks per requestor
714system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793 # Average occupied blocks per requestor

712system.cpu.l2cache.tags.occ_blocks::writebacks 133.889045 # Average occupied blocks per requestor
713system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541066 # Average occupied blocks per requestor
714system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417923 # Average occupied blocks per requestor

715system.cpu.l2cache.tags.occ_percent::writebacks 0.004086 # Average percentage of cache occupancy
716system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009385 # Average percentage of cache occupancy
717system.cpu.l2cache.tags.occ_percent::cpu.data 0.873884 # Average percentage of cache occupancy
718system.cpu.l2cache.tags.occ_percent::total 0.887355 # Average percentage of cache occupancy
719system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
720system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
721system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id
722system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id
723system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id
724system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
725system.cpu.l2cache.tags.tag_accesses 18705537 # Number of tag accesses
726system.cpu.l2cache.tags.data_accesses 18705537 # Number of data accesses

727system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

727system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

728system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits
729system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits
730system.cpu.l2cache.WritebackClean_hits::writebacks 17940 # number of WritebackClean hits
731system.cpu.l2cache.WritebackClean_hits::total 17940 # number of WritebackClean hits
732system.cpu.l2cache.ReadExReq_hits::cpu.data 255660 # number of ReadExReq hits
733system.cpu.l2cache.ReadExReq_hits::total 255660 # number of ReadExReq hits
734system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17239 # number of ReadCleanReq hits
735system.cpu.l2cache.ReadCleanReq_hits::total 17239 # number of ReadCleanReq hits
736system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748301 # number of ReadSharedReq hits
737system.cpu.l2cache.ReadSharedReq_hits::total 748301 # number of ReadSharedReq hits
738system.cpu.l2cache.demand_hits::cpu.inst 17239 # number of demand (read+write) hits
739system.cpu.l2cache.demand_hits::cpu.data 1003961 # number of demand (read+write) hits
740system.cpu.l2cache.demand_hits::total 1021200 # number of demand (read+write) hits
741system.cpu.l2cache.overall_hits::cpu.inst 17239 # number of overall hits
742system.cpu.l2cache.overall_hits::cpu.data 1003961 # number of overall hits
743system.cpu.l2cache.overall_hits::total 1021200 # number of overall hits
744system.cpu.l2cache.ReadExReq_misses::cpu.data 100978 # number of ReadExReq misses
745system.cpu.l2cache.ReadExReq_misses::total 100978 # number of ReadExReq misses
746system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses
747system.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses
748system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40494 # number of ReadSharedReq misses
749system.cpu.l2cache.ReadSharedReq_misses::total 40494 # number of ReadSharedReq misses
750system.cpu.l2cache.demand_misses::cpu.inst 2811 # number of demand (read+write) misses
751system.cpu.l2cache.demand_misses::cpu.data 141472 # number of demand (read+write) misses
752system.cpu.l2cache.demand_misses::total 144283 # number of demand (read+write) misses
753system.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses
754system.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses
755system.cpu.l2cache.overall_misses::total 144283 # number of overall misses

756system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653000 # number of ReadExReq miss cycles
757system.cpu.l2cache.ReadExReq_miss_latency::total 8979653000 # number of ReadExReq miss cycles
758system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312477500 # number of ReadCleanReq miss cycles
759system.cpu.l2cache.ReadCleanReq_miss_latency::total 312477500 # number of ReadCleanReq miss cycles
760system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360667500 # number of ReadSharedReq miss cycles
761system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360667500 # number of ReadSharedReq miss cycles
762system.cpu.l2cache.demand_miss_latency::cpu.inst 312477500 # number of demand (read+write) miss cycles
763system.cpu.l2cache.demand_miss_latency::cpu.data 13340320500 # number of demand (read+write) miss cycles

756system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653500 # number of ReadExReq miss cycles
757system.cpu.l2cache.ReadExReq_miss_latency::total 8979653500 # number of ReadExReq miss cycles
758system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312476000 # number of ReadCleanReq miss cycles
759system.cpu.l2cache.ReadCleanReq_miss_latency::total 312476000 # number of ReadCleanReq miss cycles
760system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360668500 # number of ReadSharedReq miss cycles
761system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360668500 # number of ReadSharedReq miss cycles
762system.cpu.l2cache.demand_miss_latency::cpu.inst 312476000 # number of demand (read+write) miss cycles
763system.cpu.l2cache.demand_miss_latency::cpu.data 13340322000 # number of demand (read+write) miss cycles

764system.cpu.l2cache.demand_miss_latency::total 13652798000 # number of demand (read+write) miss cycles

765system.cpu.l2cache.overall_miss_latency::cpu.inst 312477500 # number of overall miss cycles
766system.cpu.l2cache.overall_miss_latency::cpu.data 13340320500 # number of overall miss cycles

765system.cpu.l2cache.overall_miss_latency::cpu.inst 312476000 # number of overall miss cycles
766system.cpu.l2cache.overall_miss_latency::cpu.data 13340322000 # number of overall miss cycles

767system.cpu.l2cache.overall_miss_latency::total 13652798000 # number of overall miss cycles
768system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses)
769system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses)
770system.cpu.l2cache.WritebackClean_accesses::writebacks 17940 # number of WritebackClean accesses(hits+misses)
771system.cpu.l2cache.WritebackClean_accesses::total 17940 # number of WritebackClean accesses(hits+misses)
772system.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses)
773system.cpu.l2cache.ReadExReq_accesses::total 356638 # number of ReadExReq accesses(hits+misses)
774system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20050 # number of ReadCleanReq accesses(hits+misses)
775system.cpu.l2cache.ReadCleanReq_accesses::total 20050 # number of ReadCleanReq accesses(hits+misses)
776system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788795 # number of ReadSharedReq accesses(hits+misses)
777system.cpu.l2cache.ReadSharedReq_accesses::total 788795 # number of ReadSharedReq accesses(hits+misses)
778system.cpu.l2cache.demand_accesses::cpu.inst 20050 # number of demand (read+write) accesses
779system.cpu.l2cache.demand_accesses::cpu.data 1145433 # number of demand (read+write) accesses
780system.cpu.l2cache.demand_accesses::total 1165483 # number of demand (read+write) accesses
781system.cpu.l2cache.overall_accesses::cpu.inst 20050 # number of overall (read+write) accesses
782system.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses
783system.cpu.l2cache.overall_accesses::total 1165483 # number of overall (read+write) accesses
784system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses
785system.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses
786system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140200 # miss rate for ReadCleanReq accesses
787system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140200 # miss rate for ReadCleanReq accesses
788system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses
789system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses
790system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140200 # miss rate for demand accesses
791system.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses
792system.cpu.l2cache.demand_miss_rate::total 0.123797 # miss rate for demand accesses
793system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140200 # miss rate for overall accesses
794system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses
795system.cpu.l2cache.overall_miss_rate::total 0.123797 # miss rate for overall accesses

796system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645 # average ReadExReq miss latency
797system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645 # average ReadExReq miss latency
798system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723 # average ReadCleanReq miss latency
799system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723 # average ReadCleanReq miss latency
800system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063 # average ReadSharedReq miss latency
801system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063 # average ReadSharedReq miss latency
802system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency
803system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency

796system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.830597 # average ReadExReq miss latency
797system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.830597 # average ReadExReq miss latency
798system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111161.864105 # average ReadCleanReq miss latency
799system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111161.864105 # average ReadCleanReq miss latency
800system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.780758 # average ReadSharedReq miss latency
801system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.780758 # average ReadSharedReq miss latency
802system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency
803system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency

804system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552 # average overall miss latency

805system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency
806system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency

805system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency
806system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency

807system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552 # average overall miss latency
808system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
809system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
810system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
811system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
812system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
813system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
814system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks
815system.cpu.l2cache.writebacks::total 97528 # number of writebacks
816system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
817system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
818system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits
819system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits
820system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
821system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits
822system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
823system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
824system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits
825system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
826system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses
827system.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses
828system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses
829system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses
830system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses
831system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses
832system.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses
833system.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses
834system.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses
835system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses
836system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses
837system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses

838system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873000 # number of ReadExReq MSHR miss cycles
839system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873000 # number of ReadExReq MSHR miss cycles
840system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284302500 # number of ReadCleanReq MSHR miss cycles
841system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284302500 # number of ReadCleanReq MSHR miss cycles
842system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953965500 # number of ReadSharedReq MSHR miss cycles
843system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953965500 # number of ReadSharedReq MSHR miss cycles
844system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284302500 # number of demand (read+write) MSHR miss cycles
845system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923838500 # number of demand (read+write) MSHR miss cycles

838system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873500 # number of ReadExReq MSHR miss cycles
839system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873500 # number of ReadExReq MSHR miss cycles
840system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284301000 # number of ReadCleanReq MSHR miss cycles
841system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284301000 # number of ReadCleanReq MSHR miss cycles
842system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953966500 # number of ReadSharedReq MSHR miss cycles
843system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953966500 # number of ReadSharedReq MSHR miss cycles
844system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284301000 # number of demand (read+write) MSHR miss cycles
845system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923840000 # number of demand (read+write) MSHR miss cycles

846system.cpu.l2cache.demand_mshr_miss_latency::total 12208141000 # number of demand (read+write) MSHR miss cycles

847system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284302500 # number of overall MSHR miss cycles
848system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923838500 # number of overall MSHR miss cycles

847system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284301000 # number of overall MSHR miss cycles
848system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923840000 # number of overall MSHR miss cycles

849system.cpu.l2cache.overall_mshr_miss_latency::total 12208141000 # number of overall MSHR miss cycles
850system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses
851system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses
852system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for ReadCleanReq accesses
853system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140150 # mshr miss rate for ReadCleanReq accesses
854system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses
855system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses
856system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for demand accesses
857system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses
858system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses
859system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for overall accesses
860system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses
861system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses

862system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645 # average ReadExReq mshr miss latency
863system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645 # average ReadExReq mshr miss latency
864system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904 # average ReadCleanReq mshr miss latency
865system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904 # average ReadCleanReq mshr miss latency
866system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430 # average ReadSharedReq mshr miss latency
867system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430 # average ReadSharedReq mshr miss latency
868system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency
869system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency

862system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.830597 # average ReadExReq mshr miss latency
863system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.830597 # average ReadExReq mshr miss latency
864system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101174.733096 # average ReadCleanReq mshr miss latency
865system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101174.733096 # average ReadCleanReq mshr miss latency
866system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.625133 # average ReadSharedReq mshr miss latency
867system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.625133 # average ReadSharedReq mshr miss latency
868system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency
869system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency

870system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency

871system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency
872system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency

871system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency
872system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency

873system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency
874system.cpu.toL2Bus.snoop_filter.tot_requests 2324998 # Total number of requests made to the snoop filter.
875system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159585 # Number of requests hitting in the snoop filter with a single holder of the requested data.
876system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
877system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter.
878system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
879system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

880system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

880system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

881system.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution
882system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution
883system.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution
884system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution
885system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution
886system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution
887system.cpu.toL2Bus.trans_dist::ReadCleanReq 20050 # Transaction distribution
888system.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution
889system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58278 # Packet count per connected master and slave (bytes)
890system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes)
891system.cpu.toL2Bus.pkt_count::total 3490481 # Packet count per connected master and slave (bytes)
892system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446592 # Cumulative packet size per connected master and slave (bytes)
893system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes)
894system.cpu.toL2Bus.pkt_size::total 144166592 # Cumulative packet size per connected master and slave (bytes)
895system.cpu.toL2Bus.snoops 112761 # Total snoops (count)
896system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes)
897system.cpu.toL2Bus.snoop_fanout::samples 1278244 # Request fanout histogram
898system.cpu.toL2Bus.snoop_fanout::mean 0.006015 # Request fanout histogram
899system.cpu.toL2Bus.snoop_fanout::stdev 0.077350 # Request fanout histogram
900system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
901system.cpu.toL2Bus.snoop_fanout::0 1270559 99.40% 99.40% # Request fanout histogram
902system.cpu.toL2Bus.snoop_fanout::1 7682 0.60% 100.00% # Request fanout histogram
903system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram
904system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
905system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
906system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
907system.cpu.toL2Bus.snoop_fanout::total 1278244 # Request fanout histogram
908system.cpu.toL2Bus.reqLayer0.occupancy 2249619000 # Layer occupancy (ticks)
909system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
910system.cpu.toL2Bus.respLayer0.occupancy 30098453 # Layer occupancy (ticks)
911system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
912system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks)
913system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
914system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter.
915system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data.
916system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
917system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
918system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
919system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

920system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states

920system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states

921system.membus.trans_dist::ReadResp 43291 # Transaction distribution
922system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution
923system.membus.trans_dist::CleanEvict 12615 # Transaction distribution
924system.membus.trans_dist::ReadExReq 100978 # Transaction distribution
925system.membus.trans_dist::ReadExResp 100978 # Transaction distribution
926system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution
927system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes)
928system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes)
929system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes)
930system.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes)
931system.membus.snoops 0 # Total snoops (count)
932system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
933system.membus.snoop_fanout::samples 144269 # Request fanout histogram
934system.membus.snoop_fanout::mean 0 # Request fanout histogram
935system.membus.snoop_fanout::stdev 0 # Request fanout histogram
936system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
937system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram
938system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
939system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
940system.membus.snoop_fanout::min_value 0 # Request fanout histogram
941system.membus.snoop_fanout::max_value 0 # Request fanout histogram
942system.membus.snoop_fanout::total 144269 # Request fanout histogram

943system.membus.reqLayer0.occupancy 685124000 # Layer occupancy (ticks)

943system.membus.reqLayer0.occupancy 685127000 # Layer occupancy (ticks)

944system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)

945system.membus.respLayer1.occupancy 765885250 # Layer occupancy (ticks)

945system.membus.respLayer1.occupancy 765884750 # Layer occupancy (ticks)