Cross Reference: /gem5/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt

stats.txt (10812:bacaefeb126a)	stats.txt (10827:7f5467f2f8b8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.366340 # Number of seconds simulated 4sim_ticks 366339500500 # Number of ticks simulated 5final_tick 366339500500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.366340 # Number of seconds simulated 4sim_ticks 366339500500 # Number of ticks simulated 5final_tick 366339500500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 174606 # Simulator instruction rate (inst/s) 8host_op_rate 189122 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 126268215 # Simulator tick rate (ticks/s) 10host_mem_usage 309684 # Number of bytes of host memory used 11host_seconds 2901.28 # Real time elapsed on the host	7host_inst_rate 237525 # Simulator instruction rate (inst/s) 8host_op_rate 257271 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 171768388 # Simulator tick rate (ticks/s) 10host_mem_usage 317860 # Number of bytes of host memory used 11host_seconds 2132.75 # Real time elapsed on the host
12sim_insts 506582156 # Number of instructions simulated 13sim_ops 548695379 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 222208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9004736 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9226944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 222208 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 222208 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6180224 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6180224 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3472 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 140699 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 144171 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 96566 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 96566 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 606563 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 24580303 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 25186866 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 606563 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 606563 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 16870209 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 16870209 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 16870209 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 606563 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 24580303 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 42057075 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 144171 # Number of read requests accepted 40system.physmem.writeReqs 96566 # Number of write requests accepted 41system.physmem.readBursts 144171 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 96566 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue 45system.physmem.bytesWritten 6179072 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 9226944 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 6180224 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 9343 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8971 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8989 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8699 # Per bank write bursts 55system.physmem.perBankRdBursts::4 9456 # Per bank write bursts 56system.physmem.perBankRdBursts::5 9348 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8947 # Per bank write bursts 58system.physmem.perBankRdBursts::7 8105 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8575 # Per bank write bursts 60system.physmem.perBankRdBursts::9 8682 # Per bank write bursts 61system.physmem.perBankRdBursts::10 8775 # Per bank write bursts 62system.physmem.perBankRdBursts::11 9479 # Per bank write bursts 63system.physmem.perBankRdBursts::12 9376 # Per bank write bursts 64system.physmem.perBankRdBursts::13 9525 # Per bank write bursts 65system.physmem.perBankRdBursts::14 8707 # Per bank write bursts 66system.physmem.perBankRdBursts::15 9090 # Per bank write bursts 67system.physmem.perBankWrBursts::0 6188 # Per bank write bursts 68system.physmem.perBankWrBursts::1 6094 # Per bank write bursts 69system.physmem.perBankWrBursts::2 6005 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5814 # Per bank write bursts 71system.physmem.perBankWrBursts::4 6162 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6175 # Per bank write bursts 73system.physmem.perBankWrBursts::6 6015 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5497 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5730 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5822 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5962 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6449 # Per bank write bursts 79system.physmem.perBankWrBursts::12 6307 # Per bank write bursts 80system.physmem.perBankWrBursts::13 6278 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5993 # Per bank write bursts 82system.physmem.perBankWrBursts::15 6057 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 366339471500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 144171 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 96566 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 2905 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 3091 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5560 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5651 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5674 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5678 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5665 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5690 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5705 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5677 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5683 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5667 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5666 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5663 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5600 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5592 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 65255 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 235.982530 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 156.409511 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 241.771416 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 24814 38.03% 38.03% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 18186 27.87% 65.90% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 6968 10.68% 76.57% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7930 12.15% 88.73% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2060 3.16% 91.88% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1157 1.77% 93.66% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 782 1.20% 94.85% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 601 0.92% 95.78% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 2757 4.22% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65255 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5574 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 25.846071 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 382.003663 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5571 99.95% 99.95% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5574 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5574 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.321134 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.221070 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 2.354740 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16-17 2655 47.63% 47.63% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18-19 2759 49.50% 97.13% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::20-21 73 1.31% 98.44% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::22-23 16 0.29% 98.73% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-25 14 0.25% 98.98% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::26-27 15 0.27% 99.25% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::28-29 8 0.14% 99.39% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::30-31 5 0.09% 99.48% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-33 9 0.16% 99.64% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-37 1 0.02% 99.77% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::38-39 2 0.04% 99.80% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::40-41 1 0.02% 99.82% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::42-43 1 0.02% 99.84% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::44-45 2 0.04% 99.87% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::54-55 1 0.02% 99.93% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::64-65 1 0.02% 99.96% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::66-67 1 0.02% 99.98% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::70-71 1 0.02% 100.00% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::total 5574 # Writes before turning the bus around for reads 244system.physmem.totQLat 1547962750 # Total ticks spent queuing 245system.physmem.totMemAccLat 4249219000 # Total ticks spent from burst creation until serviced by the DRAM 246system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers 247system.physmem.avgQLat 10744.74 # Average queueing delay per DRAM burst 248system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 249system.physmem.avgMemAccLat 29494.74 # Average memory access latency per DRAM burst 250system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s 251system.physmem.avgWrBW 16.87 # Average achieved write bandwidth in MiByte/s 252system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s 253system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s 254system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 255system.physmem.busUtil 0.33 # Data bus utilization in percentage 256system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 257system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 258system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 259system.physmem.avgWrQLen 20.02 # Average write queue length when enqueuing 260system.physmem.readRowHits 110904 # Number of row buffer hits during reads 261system.physmem.writeRowHits 64452 # Number of row buffer hits during writes 262system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads 263system.physmem.writeRowHitRate 66.74 # Row buffer hit rate for writes 264system.physmem.avgGap 1521741.45 # Average gap between requests 265system.physmem.pageHitRate 72.87 # Row buffer hit rate, read and write combined 266system.physmem_0.actEnergy 247983120 # Energy for activate commands per rank (pJ) 267system.physmem_0.preEnergy 135308250 # Energy for precharge commands per rank (pJ) 268system.physmem_0.readEnergy 560305200 # Energy for read commands per rank (pJ) 269system.physmem_0.writeEnergy 310528080 # Energy for write commands per rank (pJ) 270system.physmem_0.refreshEnergy 23927239440 # Energy for refresh commands per rank (pJ) 271system.physmem_0.actBackEnergy 47721013605 # Energy for active background per rank (pJ) 272system.physmem_0.preBackEnergy 177940783500 # Energy for precharge background per rank (pJ) 273system.physmem_0.totalEnergy 250843161195 # Total energy per rank (pJ) 274system.physmem_0.averagePower 684.736086 # Core power per rank (mW) 275system.physmem_0.memoryStateTime::IDLE 295712636000 # Time in different power states 276system.physmem_0.memoryStateTime::REF 12232740000 # Time in different power states 277system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 278system.physmem_0.memoryStateTime::ACT 58390260500 # Time in different power states 279system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 280system.physmem_1.actEnergy 245095200 # Energy for activate commands per rank (pJ) 281system.physmem_1.preEnergy 133732500 # Energy for precharge commands per rank (pJ) 282system.physmem_1.readEnergy 563066400 # Energy for read commands per rank (pJ) 283system.physmem_1.writeEnergy 314791920 # Energy for write commands per rank (pJ) 284system.physmem_1.refreshEnergy 23927239440 # Energy for refresh commands per rank (pJ) 285system.physmem_1.actBackEnergy 47027452140 # Energy for active background per rank (pJ) 286system.physmem_1.preBackEnergy 178549170750 # Energy for precharge background per rank (pJ) 287system.physmem_1.totalEnergy 250760548350 # Total energy per rank (pJ) 288system.physmem_1.averagePower 684.510574 # Core power per rank (mW) 289system.physmem_1.memoryStateTime::IDLE 296727601000 # Time in different power states 290system.physmem_1.memoryStateTime::REF 12232740000 # Time in different power states 291system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 292system.physmem_1.memoryStateTime::ACT 57375209000 # Time in different power states 293system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 294system.cpu.branchPred.lookups 132583064 # Number of BP lookups 295system.cpu.branchPred.condPredicted 98508784 # Number of conditional branches predicted 296system.cpu.branchPred.condIncorrect 6555218 # Number of conditional branches incorrect 297system.cpu.branchPred.BTBLookups 69071756 # Number of BTB lookups 298system.cpu.branchPred.BTBHits 64847878 # Number of BTB hits 299system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 300system.cpu.branchPred.BTBHitPct 93.884797 # BTB Hit Percentage 301system.cpu.branchPred.usedRAS 10016520 # Number of times the RAS was used to get a target. 302system.cpu.branchPred.RASInCorrect 18156 # Number of incorrect RAS predictions. 303system.cpu_clk_domain.clock 500 # Clock period in ticks 304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 313system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 314system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 315system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 316system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 317system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 322system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 323system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 324system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 333system.cpu.dtb.walker.walks 0 # Table walker walks requested 334system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.inst_hits 0 # ITB inst hits 342system.cpu.dtb.inst_misses 0 # ITB inst misses 343system.cpu.dtb.read_hits 0 # DTB read hits 344system.cpu.dtb.read_misses 0 # DTB read misses 345system.cpu.dtb.write_hits 0 # DTB write hits 346system.cpu.dtb.write_misses 0 # DTB write misses 347system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 348system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 349system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 350system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 351system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 352system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 353system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 354system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 355system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 356system.cpu.dtb.read_accesses 0 # DTB read accesses 357system.cpu.dtb.write_accesses 0 # DTB write accesses 358system.cpu.dtb.inst_accesses 0 # ITB inst accesses 359system.cpu.dtb.hits 0 # DTB hits 360system.cpu.dtb.misses 0 # DTB misses 361system.cpu.dtb.accesses 0 # DTB accesses 362system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 371system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 372system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 373system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 374system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 375system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 376system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 377system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 378system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 379system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 380system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 381system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 382system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 383system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 384system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 386system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 387system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 388system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 389system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 390system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 391system.cpu.itb.walker.walks 0 # Table walker walks requested 392system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.inst_hits 0 # ITB inst hits 400system.cpu.itb.inst_misses 0 # ITB inst misses 401system.cpu.itb.read_hits 0 # DTB read hits 402system.cpu.itb.read_misses 0 # DTB read misses 403system.cpu.itb.write_hits 0 # DTB write hits 404system.cpu.itb.write_misses 0 # DTB write misses 405system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 406system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 408system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 409system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 410system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu.itb.read_accesses 0 # DTB read accesses 415system.cpu.itb.write_accesses 0 # DTB write accesses 416system.cpu.itb.inst_accesses 0 # ITB inst accesses 417system.cpu.itb.hits 0 # DTB hits 418system.cpu.itb.misses 0 # DTB misses 419system.cpu.itb.accesses 0 # DTB accesses 420system.cpu.workload.num_syscalls 548 # Number of system calls 421system.cpu.numCycles 732679001 # number of cpu cycles simulated 422system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 423system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 424system.cpu.committedInsts 506582156 # Number of instructions committed 425system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed 426system.cpu.discardedOps 13461102 # Number of ops (including micro ops) which were discarded before commit 427system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 428system.cpu.cpi 1.446318 # CPI: cycles per instruction 429system.cpu.ipc 0.691411 # IPC: instructions per cycle 430system.cpu.tickCycles 695769824 # Number of cycles that the object actually ticked 431system.cpu.idleCycles 36909177 # Total number of cycles that the object has spent stopped 432system.cpu.dcache.tags.replacements 1139845 # number of replacements 433system.cpu.dcache.tags.tagsinuse 4070.953673 # Cycle average of tags in use 434system.cpu.dcache.tags.total_refs 171282385 # Total number of references to valid blocks. 435system.cpu.dcache.tags.sampled_refs 1143941 # Sample count of references to valid blocks. 436system.cpu.dcache.tags.avg_refs 149.730087 # Average number of references to valid blocks. 437system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. 438system.cpu.dcache.tags.occ_blocks::cpu.data 4070.953673 # Average occupied blocks per requestor 439system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy 440system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy 441system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 442system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id 445system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id 446system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 447system.cpu.dcache.tags.tag_accesses 346819443 # Number of tag accesses 448system.cpu.dcache.tags.data_accesses 346819443 # Number of data accesses 449system.cpu.dcache.ReadReq_hits::cpu.data 114763887 # number of ReadReq hits 450system.cpu.dcache.ReadReq_hits::total 114763887 # number of ReadReq hits 451system.cpu.dcache.WriteReq_hits::cpu.data 53538651 # number of WriteReq hits 452system.cpu.dcache.WriteReq_hits::total 53538651 # number of WriteReq hits 453system.cpu.dcache.SoftPFReq_hits::cpu.data 2765 # number of SoftPFReq hits 454system.cpu.dcache.SoftPFReq_hits::total 2765 # number of SoftPFReq hits 455system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 456system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 457system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 458system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 459system.cpu.dcache.demand_hits::cpu.data 168302538 # number of demand (read+write) hits 460system.cpu.dcache.demand_hits::total 168302538 # number of demand (read+write) hits 461system.cpu.dcache.overall_hits::cpu.data 168305303 # number of overall hits 462system.cpu.dcache.overall_hits::total 168305303 # number of overall hits 463system.cpu.dcache.ReadReq_misses::cpu.data 854696 # number of ReadReq misses 464system.cpu.dcache.ReadReq_misses::total 854696 # number of ReadReq misses 465system.cpu.dcache.WriteReq_misses::cpu.data 700655 # number of WriteReq misses 466system.cpu.dcache.WriteReq_misses::total 700655 # number of WriteReq misses 467system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 468system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses 469system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses 470system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses 471system.cpu.dcache.overall_misses::cpu.data 1555366 # number of overall misses 472system.cpu.dcache.overall_misses::total 1555366 # number of overall misses 473system.cpu.dcache.ReadReq_miss_latency::cpu.data 14025171732 # number of ReadReq miss cycles 474system.cpu.dcache.ReadReq_miss_latency::total 14025171732 # number of ReadReq miss cycles 475system.cpu.dcache.WriteReq_miss_latency::cpu.data 22048092000 # number of WriteReq miss cycles 476system.cpu.dcache.WriteReq_miss_latency::total 22048092000 # number of WriteReq miss cycles 477system.cpu.dcache.demand_miss_latency::cpu.data 36073263732 # number of demand (read+write) miss cycles 478system.cpu.dcache.demand_miss_latency::total 36073263732 # number of demand (read+write) miss cycles 479system.cpu.dcache.overall_miss_latency::cpu.data 36073263732 # number of overall miss cycles 480system.cpu.dcache.overall_miss_latency::total 36073263732 # number of overall miss cycles 481system.cpu.dcache.ReadReq_accesses::cpu.data 115618583 # number of ReadReq accesses(hits+misses) 482system.cpu.dcache.ReadReq_accesses::total 115618583 # number of ReadReq accesses(hits+misses) 483system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 484system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 485system.cpu.dcache.SoftPFReq_accesses::cpu.data 2780 # number of SoftPFReq accesses(hits+misses) 486system.cpu.dcache.SoftPFReq_accesses::total 2780 # number of SoftPFReq accesses(hits+misses) 487system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 488system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 489system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 490system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 491system.cpu.dcache.demand_accesses::cpu.data 169857889 # number of demand (read+write) accesses 492system.cpu.dcache.demand_accesses::total 169857889 # number of demand (read+write) accesses 493system.cpu.dcache.overall_accesses::cpu.data 169860669 # number of overall (read+write) accesses 494system.cpu.dcache.overall_accesses::total 169860669 # number of overall (read+write) accesses 495system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007392 # miss rate for ReadReq accesses 496system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses 497system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses 498system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses 499system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005396 # miss rate for SoftPFReq accesses 500system.cpu.dcache.SoftPFReq_miss_rate::total 0.005396 # miss rate for SoftPFReq accesses 501system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses 502system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses 503system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses 504system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses 505system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16409.544133 # average ReadReq miss latency 506system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.544133 # average ReadReq miss latency 507system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31467.829388 # average WriteReq miss latency 508system.cpu.dcache.WriteReq_avg_miss_latency::total 31467.829388 # average WriteReq miss latency 509system.cpu.dcache.demand_avg_miss_latency::cpu.data 23193.005136 # average overall miss latency 510system.cpu.dcache.demand_avg_miss_latency::total 23193.005136 # average overall miss latency 511system.cpu.dcache.overall_avg_miss_latency::cpu.data 23192.781462 # average overall miss latency 512system.cpu.dcache.overall_avg_miss_latency::total 23192.781462 # average overall miss latency 513system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 517system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 518system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 519system.cpu.dcache.fast_writes 0 # number of fast writes performed 520system.cpu.dcache.cache_copies 0 # number of cache copies performed 521system.cpu.dcache.writebacks::writebacks 1068547 # number of writebacks 522system.cpu.dcache.writebacks::total 1068547 # number of writebacks 523system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66929 # number of ReadReq MSHR hits 524system.cpu.dcache.ReadReq_mshr_hits::total 66929 # number of ReadReq MSHR hits 525system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344493 # number of WriteReq MSHR hits 526system.cpu.dcache.WriteReq_mshr_hits::total 344493 # number of WriteReq MSHR hits 527system.cpu.dcache.demand_mshr_hits::cpu.data 411422 # number of demand (read+write) MSHR hits 528system.cpu.dcache.demand_mshr_hits::total 411422 # number of demand (read+write) MSHR hits 529system.cpu.dcache.overall_mshr_hits::cpu.data 411422 # number of overall MSHR hits 530system.cpu.dcache.overall_mshr_hits::total 411422 # number of overall MSHR hits 531system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787767 # number of ReadReq MSHR misses 532system.cpu.dcache.ReadReq_mshr_misses::total 787767 # number of ReadReq MSHR misses 533system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356162 # number of WriteReq MSHR misses 534system.cpu.dcache.WriteReq_mshr_misses::total 356162 # number of WriteReq MSHR misses 535system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 536system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 537system.cpu.dcache.demand_mshr_misses::cpu.data 1143929 # number of demand (read+write) MSHR misses 538system.cpu.dcache.demand_mshr_misses::total 1143929 # number of demand (read+write) MSHR misses 539system.cpu.dcache.overall_mshr_misses::cpu.data 1143941 # number of overall MSHR misses 540system.cpu.dcache.overall_mshr_misses::total 1143941 # number of overall MSHR misses 541system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930909015 # number of ReadReq MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930909015 # number of ReadReq MSHR miss cycles 543system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10976099750 # number of WriteReq MSHR miss cycles 544system.cpu.dcache.WriteReq_mshr_miss_latency::total 10976099750 # number of WriteReq MSHR miss cycles 545system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 986500 # number of SoftPFReq MSHR miss cycles 546system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 986500 # number of SoftPFReq MSHR miss cycles 547system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22907008765 # number of demand (read+write) MSHR miss cycles 548system.cpu.dcache.demand_mshr_miss_latency::total 22907008765 # number of demand (read+write) MSHR miss cycles 549system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22907995265 # number of overall MSHR miss cycles 550system.cpu.dcache.overall_mshr_miss_latency::total 22907995265 # number of overall MSHR miss cycles 551system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses 552system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses 553system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses 554system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses 555system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004317 # mshr miss rate for SoftPFReq accesses 556system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004317 # mshr miss rate for SoftPFReq accesses 557system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses 558system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses 559system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses 560system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses 561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15145.225701 # average ReadReq mshr miss latency 562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15145.225701 # average ReadReq mshr miss latency 563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30817.717078 # average WriteReq mshr miss latency 564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30817.717078 # average WriteReq mshr miss latency 565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 82208.333333 # average SoftPFReq mshr miss latency 566system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 82208.333333 # average SoftPFReq mshr miss latency 567system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20024.851861 # average overall mshr miss latency 568system.cpu.dcache.demand_avg_mshr_miss_latency::total 20024.851861 # average overall mshr miss latency 569system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.504169 # average overall mshr miss latency 570system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.504169 # average overall mshr miss latency 571system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 572system.cpu.icache.tags.replacements 17672 # number of replacements 573system.cpu.icache.tags.tagsinuse 1190.163457 # Cycle average of tags in use 574system.cpu.icache.tags.total_refs 200929857 # Total number of references to valid blocks. 575system.cpu.icache.tags.sampled_refs 19544 # Sample count of references to valid blocks. 576system.cpu.icache.tags.avg_refs 10280.897309 # Average number of references to valid blocks. 577system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 578system.cpu.icache.tags.occ_blocks::cpu.inst 1190.163457 # Average occupied blocks per requestor 579system.cpu.icache.tags.occ_percent::cpu.inst 0.581135 # Average percentage of cache occupancy 580system.cpu.icache.tags.occ_percent::total 0.581135 # Average percentage of cache occupancy 581system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 582system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 583system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 584system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id 585system.cpu.icache.tags.age_task_id_blocks_1024::3 306 # Occupied blocks per task id 586system.cpu.icache.tags.age_task_id_blocks_1024::4 1407 # Occupied blocks per task id 587system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id 588system.cpu.icache.tags.tag_accesses 401918346 # Number of tag accesses 589system.cpu.icache.tags.data_accesses 401918346 # Number of data accesses 590system.cpu.icache.ReadReq_hits::cpu.inst 200929857 # number of ReadReq hits 591system.cpu.icache.ReadReq_hits::total 200929857 # number of ReadReq hits 592system.cpu.icache.demand_hits::cpu.inst 200929857 # number of demand (read+write) hits 593system.cpu.icache.demand_hits::total 200929857 # number of demand (read+write) hits 594system.cpu.icache.overall_hits::cpu.inst 200929857 # number of overall hits 595system.cpu.icache.overall_hits::total 200929857 # number of overall hits 596system.cpu.icache.ReadReq_misses::cpu.inst 19544 # number of ReadReq misses 597system.cpu.icache.ReadReq_misses::total 19544 # number of ReadReq misses 598system.cpu.icache.demand_misses::cpu.inst 19544 # number of demand (read+write) misses 599system.cpu.icache.demand_misses::total 19544 # number of demand (read+write) misses 600system.cpu.icache.overall_misses::cpu.inst 19544 # number of overall misses 601system.cpu.icache.overall_misses::total 19544 # number of overall misses 602system.cpu.icache.ReadReq_miss_latency::cpu.inst 494847996 # number of ReadReq miss cycles 603system.cpu.icache.ReadReq_miss_latency::total 494847996 # number of ReadReq miss cycles 604system.cpu.icache.demand_miss_latency::cpu.inst 494847996 # number of demand (read+write) miss cycles 605system.cpu.icache.demand_miss_latency::total 494847996 # number of demand (read+write) miss cycles 606system.cpu.icache.overall_miss_latency::cpu.inst 494847996 # number of overall miss cycles 607system.cpu.icache.overall_miss_latency::total 494847996 # number of overall miss cycles 608system.cpu.icache.ReadReq_accesses::cpu.inst 200949401 # number of ReadReq accesses(hits+misses) 609system.cpu.icache.ReadReq_accesses::total 200949401 # number of ReadReq accesses(hits+misses) 610system.cpu.icache.demand_accesses::cpu.inst 200949401 # number of demand (read+write) accesses 611system.cpu.icache.demand_accesses::total 200949401 # number of demand (read+write) accesses 612system.cpu.icache.overall_accesses::cpu.inst 200949401 # number of overall (read+write) accesses 613system.cpu.icache.overall_accesses::total 200949401 # number of overall (read+write) accesses 614system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses 615system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses 616system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses 617system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses 618system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses 619system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses 620system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25319.688702 # average ReadReq miss latency 621system.cpu.icache.ReadReq_avg_miss_latency::total 25319.688702 # average ReadReq miss latency 622system.cpu.icache.demand_avg_miss_latency::cpu.inst 25319.688702 # average overall miss latency 623system.cpu.icache.demand_avg_miss_latency::total 25319.688702 # average overall miss latency 624system.cpu.icache.overall_avg_miss_latency::cpu.inst 25319.688702 # average overall miss latency 625system.cpu.icache.overall_avg_miss_latency::total 25319.688702 # average overall miss latency 626system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 627system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 628system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 629system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 630system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 631system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 632system.cpu.icache.fast_writes 0 # number of fast writes performed 633system.cpu.icache.cache_copies 0 # number of cache copies performed 634system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19544 # number of ReadReq MSHR misses 635system.cpu.icache.ReadReq_mshr_misses::total 19544 # number of ReadReq MSHR misses 636system.cpu.icache.demand_mshr_misses::cpu.inst 19544 # number of demand (read+write) MSHR misses 637system.cpu.icache.demand_mshr_misses::total 19544 # number of demand (read+write) MSHR misses 638system.cpu.icache.overall_mshr_misses::cpu.inst 19544 # number of overall MSHR misses 639system.cpu.icache.overall_mshr_misses::total 19544 # number of overall MSHR misses 640system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 464144004 # number of ReadReq MSHR miss cycles 641system.cpu.icache.ReadReq_mshr_miss_latency::total 464144004 # number of ReadReq MSHR miss cycles 642system.cpu.icache.demand_mshr_miss_latency::cpu.inst 464144004 # number of demand (read+write) MSHR miss cycles 643system.cpu.icache.demand_mshr_miss_latency::total 464144004 # number of demand (read+write) MSHR miss cycles 644system.cpu.icache.overall_mshr_miss_latency::cpu.inst 464144004 # number of overall MSHR miss cycles 645system.cpu.icache.overall_mshr_miss_latency::total 464144004 # number of overall MSHR miss cycles 646system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses 647system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses 648system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses 649system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses 650system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses 651system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses 652system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23748.669873 # average ReadReq mshr miss latency 653system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23748.669873 # average ReadReq mshr miss latency 654system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23748.669873 # average overall mshr miss latency 655system.cpu.icache.demand_avg_mshr_miss_latency::total 23748.669873 # average overall mshr miss latency 656system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23748.669873 # average overall mshr miss latency 657system.cpu.icache.overall_avg_mshr_miss_latency::total 23748.669873 # average overall mshr miss latency 658system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 659system.cpu.l2cache.tags.replacements 111417 # number of replacements 660system.cpu.l2cache.tags.tagsinuse 27648.763503 # Cycle average of tags in use 661system.cpu.l2cache.tags.total_refs 1684506 # Total number of references to valid blocks. 662system.cpu.l2cache.tags.sampled_refs 142603 # Sample count of references to valid blocks. 663system.cpu.l2cache.tags.avg_refs 11.812557 # Average number of references to valid blocks. 664system.cpu.l2cache.tags.warmup_cycle 163802727000 # Cycle when the warmup percentage was hit. 665system.cpu.l2cache.tags.occ_blocks::writebacks 23521.944211 # Average occupied blocks per requestor 666system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.271354 # Average occupied blocks per requestor 667system.cpu.l2cache.tags.occ_blocks::cpu.data 3736.547938 # Average occupied blocks per requestor 668system.cpu.l2cache.tags.occ_percent::writebacks 0.717833 # Average percentage of cache occupancy 669system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011910 # Average percentage of cache occupancy 670system.cpu.l2cache.tags.occ_percent::cpu.data 0.114030 # Average percentage of cache occupancy 671system.cpu.l2cache.tags.occ_percent::total 0.843773 # Average percentage of cache occupancy 672system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id 673system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 674system.cpu.l2cache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id 675system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4943 # Occupied blocks per task id 676system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25856 # Occupied blocks per task id 677system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id 678system.cpu.l2cache.tags.tag_accesses 18355274 # Number of tag accesses 679system.cpu.l2cache.tags.data_accesses 18355274 # Number of data accesses 680system.cpu.l2cache.ReadReq_hits::cpu.inst 16070 # number of ReadReq hits 681system.cpu.l2cache.ReadReq_hits::cpu.data 747693 # number of ReadReq hits 682system.cpu.l2cache.ReadReq_hits::total 763763 # number of ReadReq hits 683system.cpu.l2cache.Writeback_hits::writebacks 1068547 # number of Writeback hits 684system.cpu.l2cache.Writeback_hits::total 1068547 # number of Writeback hits 685system.cpu.l2cache.ReadExReq_hits::cpu.data 255534 # number of ReadExReq hits 686system.cpu.l2cache.ReadExReq_hits::total 255534 # number of ReadExReq hits 687system.cpu.l2cache.demand_hits::cpu.inst 16070 # number of demand (read+write) hits 688system.cpu.l2cache.demand_hits::cpu.data 1003227 # number of demand (read+write) hits 689system.cpu.l2cache.demand_hits::total 1019297 # number of demand (read+write) hits 690system.cpu.l2cache.overall_hits::cpu.inst 16070 # number of overall hits 691system.cpu.l2cache.overall_hits::cpu.data 1003227 # number of overall hits 692system.cpu.l2cache.overall_hits::total 1019297 # number of overall hits 693system.cpu.l2cache.ReadReq_misses::cpu.inst 3474 # number of ReadReq misses 694system.cpu.l2cache.ReadReq_misses::cpu.data 39833 # number of ReadReq misses 695system.cpu.l2cache.ReadReq_misses::total 43307 # number of ReadReq misses 696system.cpu.l2cache.ReadExReq_misses::cpu.data 100881 # number of ReadExReq misses 697system.cpu.l2cache.ReadExReq_misses::total 100881 # number of ReadExReq misses 698system.cpu.l2cache.demand_misses::cpu.inst 3474 # number of demand (read+write) misses 699system.cpu.l2cache.demand_misses::cpu.data 140714 # number of demand (read+write) misses 700system.cpu.l2cache.demand_misses::total 144188 # number of demand (read+write) misses 701system.cpu.l2cache.overall_misses::cpu.inst 3474 # number of overall misses 702system.cpu.l2cache.overall_misses::cpu.data 140714 # number of overall misses 703system.cpu.l2cache.overall_misses::total 144188 # number of overall misses 704system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 275801500 # number of ReadReq miss cycles 705system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3286544500 # number of ReadReq miss cycles 706system.cpu.l2cache.ReadReq_miss_latency::total 3562346000 # number of ReadReq miss cycles 707system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7939327250 # number of ReadExReq miss cycles 708system.cpu.l2cache.ReadExReq_miss_latency::total 7939327250 # number of ReadExReq miss cycles 709system.cpu.l2cache.demand_miss_latency::cpu.inst 275801500 # number of demand (read+write) miss cycles 710system.cpu.l2cache.demand_miss_latency::cpu.data 11225871750 # number of demand (read+write) miss cycles 711system.cpu.l2cache.demand_miss_latency::total 11501673250 # number of demand (read+write) miss cycles 712system.cpu.l2cache.overall_miss_latency::cpu.inst 275801500 # number of overall miss cycles 713system.cpu.l2cache.overall_miss_latency::cpu.data 11225871750 # number of overall miss cycles 714system.cpu.l2cache.overall_miss_latency::total 11501673250 # number of overall miss cycles 715system.cpu.l2cache.ReadReq_accesses::cpu.inst 19544 # number of ReadReq accesses(hits+misses) 716system.cpu.l2cache.ReadReq_accesses::cpu.data 787526 # number of ReadReq accesses(hits+misses) 717system.cpu.l2cache.ReadReq_accesses::total 807070 # number of ReadReq accesses(hits+misses) 718system.cpu.l2cache.Writeback_accesses::writebacks 1068547 # number of Writeback accesses(hits+misses) 719system.cpu.l2cache.Writeback_accesses::total 1068547 # number of Writeback accesses(hits+misses) 720system.cpu.l2cache.ReadExReq_accesses::cpu.data 356415 # number of ReadExReq accesses(hits+misses) 721system.cpu.l2cache.ReadExReq_accesses::total 356415 # number of ReadExReq accesses(hits+misses) 722system.cpu.l2cache.demand_accesses::cpu.inst 19544 # number of demand (read+write) accesses 723system.cpu.l2cache.demand_accesses::cpu.data 1143941 # number of demand (read+write) accesses 724system.cpu.l2cache.demand_accesses::total 1163485 # number of demand (read+write) accesses 725system.cpu.l2cache.overall_accesses::cpu.inst 19544 # number of overall (read+write) accesses 726system.cpu.l2cache.overall_accesses::cpu.data 1143941 # number of overall (read+write) accesses 727system.cpu.l2cache.overall_accesses::total 1163485 # number of overall (read+write) accesses 728system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177753 # miss rate for ReadReq accesses 729system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050580 # miss rate for ReadReq accesses 730system.cpu.l2cache.ReadReq_miss_rate::total 0.053660 # miss rate for ReadReq accesses 731system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283044 # miss rate for ReadExReq accesses 732system.cpu.l2cache.ReadExReq_miss_rate::total 0.283044 # miss rate for ReadExReq accesses 733system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177753 # miss rate for demand accesses 734system.cpu.l2cache.demand_miss_rate::cpu.data 0.123008 # miss rate for demand accesses 735system.cpu.l2cache.demand_miss_rate::total 0.123928 # miss rate for demand accesses 736system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177753 # miss rate for overall accesses 737system.cpu.l2cache.overall_miss_rate::cpu.data 0.123008 # miss rate for overall accesses 738system.cpu.l2cache.overall_miss_rate::total 0.123928 # miss rate for overall accesses 739system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79390.184226 # average ReadReq miss latency 740system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82508.083750 # average ReadReq miss latency 741system.cpu.l2cache.ReadReq_avg_miss_latency::total 82257.972152 # average ReadReq miss latency 742system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78699.926151 # average ReadExReq miss latency 743system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78699.926151 # average ReadExReq miss latency 744system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79390.184226 # average overall miss latency 745system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79777.930767 # average overall miss latency 746system.cpu.l2cache.demand_avg_miss_latency::total 79768.588579 # average overall miss latency 747system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79390.184226 # average overall miss latency 748system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79777.930767 # average overall miss latency 749system.cpu.l2cache.overall_avg_miss_latency::total 79768.588579 # average overall miss latency 750system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 753system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 755system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.cpu.l2cache.fast_writes 0 # number of fast writes performed 757system.cpu.l2cache.cache_copies 0 # number of cache copies performed 758system.cpu.l2cache.writebacks::writebacks 96566 # number of writebacks 759system.cpu.l2cache.writebacks::total 96566 # number of writebacks 760system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 761system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits 762system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 763system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 764system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits 765system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 766system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 767system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits 768system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 769system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3472 # number of ReadReq MSHR misses 770system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39818 # number of ReadReq MSHR misses 771system.cpu.l2cache.ReadReq_mshr_misses::total 43290 # number of ReadReq MSHR misses 772system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100881 # number of ReadExReq MSHR misses 773system.cpu.l2cache.ReadExReq_mshr_misses::total 100881 # number of ReadExReq MSHR misses 774system.cpu.l2cache.demand_mshr_misses::cpu.inst 3472 # number of demand (read+write) MSHR misses 775system.cpu.l2cache.demand_mshr_misses::cpu.data 140699 # number of demand (read+write) MSHR misses 776system.cpu.l2cache.demand_mshr_misses::total 144171 # number of demand (read+write) MSHR misses 777system.cpu.l2cache.overall_mshr_misses::cpu.inst 3472 # number of overall MSHR misses 778system.cpu.l2cache.overall_mshr_misses::cpu.data 140699 # number of overall MSHR misses 779system.cpu.l2cache.overall_mshr_misses::total 144171 # number of overall MSHR misses 780system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 232222500 # number of ReadReq MSHR miss cycles 781system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2786510500 # number of ReadReq MSHR miss cycles 782system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3018733000 # number of ReadReq MSHR miss cycles 783system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6677694250 # number of ReadExReq MSHR miss cycles 784system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6677694250 # number of ReadExReq MSHR miss cycles 785system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 232222500 # number of demand (read+write) MSHR miss cycles 786system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9464204750 # number of demand (read+write) MSHR miss cycles 787system.cpu.l2cache.demand_mshr_miss_latency::total 9696427250 # number of demand (read+write) MSHR miss cycles 788system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 232222500 # number of overall MSHR miss cycles 789system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9464204750 # number of overall MSHR miss cycles 790system.cpu.l2cache.overall_mshr_miss_latency::total 9696427250 # number of overall MSHR miss cycles 791system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for ReadReq accesses 792system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050561 # mshr miss rate for ReadReq accesses 793system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053638 # mshr miss rate for ReadReq accesses 794system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283044 # mshr miss rate for ReadExReq accesses 795system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283044 # mshr miss rate for ReadExReq accesses 796system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for demand accesses 797system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122995 # mshr miss rate for demand accesses 798system.cpu.l2cache.demand_mshr_miss_rate::total 0.123913 # mshr miss rate for demand accesses 799system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for overall accesses 800system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122995 # mshr miss rate for overall accesses 801system.cpu.l2cache.overall_mshr_miss_rate::total 0.123913 # mshr miss rate for overall accesses 802system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66884.360599 # average ReadReq mshr miss latency 803system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69981.176855 # average ReadReq mshr miss latency 804system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69732.802033 # average ReadReq mshr miss latency 805system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66193.775339 # average ReadExReq mshr miss latency 806system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66193.775339 # average ReadExReq mshr miss latency 807system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66884.360599 # average overall mshr miss latency 808system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67265.614894 # average overall mshr miss latency 809system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67256.433333 # average overall mshr miss latency 810system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66884.360599 # average overall mshr miss latency 811system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67265.614894 # average overall mshr miss latency 812system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67256.433333 # average overall mshr miss latency 813system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 814system.cpu.toL2Bus.trans_dist::ReadReq 807070 # Transaction distribution 815system.cpu.toL2Bus.trans_dist::ReadResp 807070 # Transaction distribution 816system.cpu.toL2Bus.trans_dist::Writeback 1068547 # Transaction distribution 817system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution 818system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution 819system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39088 # Packet count per connected master and slave (bytes) 820system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356429 # Packet count per connected master and slave (bytes) 821system.cpu.toL2Bus.pkt_count::total 3395517 # Packet count per connected master and slave (bytes) 822system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250816 # Cumulative packet size per connected master and slave (bytes) 823system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141599232 # Cumulative packet size per connected master and slave (bytes) 824system.cpu.toL2Bus.pkt_size::total 142850048 # Cumulative packet size per connected master and slave (bytes) 825system.cpu.toL2Bus.snoops 0 # Total snoops (count) 826system.cpu.toL2Bus.snoop_fanout::samples 2232032 # Request fanout histogram	12sim_insts 506582156 # Number of instructions simulated 13sim_ops 548695379 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 222208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9004736 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9226944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 222208 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 222208 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6180224 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6180224 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3472 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 140699 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 144171 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 96566 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 96566 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 606563 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 24580303 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 25186866 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 606563 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 606563 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 16870209 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 16870209 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 16870209 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 606563 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 24580303 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 42057075 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 144171 # Number of read requests accepted 40system.physmem.writeReqs 96566 # Number of write requests accepted 41system.physmem.readBursts 144171 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 96566 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue 45system.physmem.bytesWritten 6179072 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 9226944 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 6180224 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 9343 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8971 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8989 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8699 # Per bank write bursts 55system.physmem.perBankRdBursts::4 9456 # Per bank write bursts 56system.physmem.perBankRdBursts::5 9348 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8947 # Per bank write bursts 58system.physmem.perBankRdBursts::7 8105 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8575 # Per bank write bursts 60system.physmem.perBankRdBursts::9 8682 # Per bank write bursts 61system.physmem.perBankRdBursts::10 8775 # Per bank write bursts 62system.physmem.perBankRdBursts::11 9479 # Per bank write bursts 63system.physmem.perBankRdBursts::12 9376 # Per bank write bursts 64system.physmem.perBankRdBursts::13 9525 # Per bank write bursts 65system.physmem.perBankRdBursts::14 8707 # Per bank write bursts 66system.physmem.perBankRdBursts::15 9090 # Per bank write bursts 67system.physmem.perBankWrBursts::0 6188 # Per bank write bursts 68system.physmem.perBankWrBursts::1 6094 # Per bank write bursts 69system.physmem.perBankWrBursts::2 6005 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5814 # Per bank write bursts 71system.physmem.perBankWrBursts::4 6162 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6175 # Per bank write bursts 73system.physmem.perBankWrBursts::6 6015 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5497 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5730 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5822 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5962 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6449 # Per bank write bursts 79system.physmem.perBankWrBursts::12 6307 # Per bank write bursts 80system.physmem.perBankWrBursts::13 6278 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5993 # Per bank write bursts 82system.physmem.perBankWrBursts::15 6057 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 366339471500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 144171 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 96566 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 2905 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 3091 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5560 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5651 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5674 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5678 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5665 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5690 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5705 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5677 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5683 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5667 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5666 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5663 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5600 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5592 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 65255 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 235.982530 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 156.409511 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 241.771416 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 24814 38.03% 38.03% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 18186 27.87% 65.90% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 6968 10.68% 76.57% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7930 12.15% 88.73% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2060 3.16% 91.88% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1157 1.77% 93.66% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 782 1.20% 94.85% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 601 0.92% 95.78% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 2757 4.22% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65255 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5574 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 25.846071 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 382.003663 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5571 99.95% 99.95% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5574 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5574 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.321134 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.221070 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 2.354740 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16-17 2655 47.63% 47.63% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18-19 2759 49.50% 97.13% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::20-21 73 1.31% 98.44% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::22-23 16 0.29% 98.73% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-25 14 0.25% 98.98% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::26-27 15 0.27% 99.25% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::28-29 8 0.14% 99.39% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::30-31 5 0.09% 99.48% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-33 9 0.16% 99.64% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-37 1 0.02% 99.77% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::38-39 2 0.04% 99.80% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::40-41 1 0.02% 99.82% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::42-43 1 0.02% 99.84% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::44-45 2 0.04% 99.87% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::54-55 1 0.02% 99.93% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::64-65 1 0.02% 99.96% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::66-67 1 0.02% 99.98% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::70-71 1 0.02% 100.00% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::total 5574 # Writes before turning the bus around for reads 244system.physmem.totQLat 1547962750 # Total ticks spent queuing 245system.physmem.totMemAccLat 4249219000 # Total ticks spent from burst creation until serviced by the DRAM 246system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers 247system.physmem.avgQLat 10744.74 # Average queueing delay per DRAM burst 248system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 249system.physmem.avgMemAccLat 29494.74 # Average memory access latency per DRAM burst 250system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s 251system.physmem.avgWrBW 16.87 # Average achieved write bandwidth in MiByte/s 252system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s 253system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s 254system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 255system.physmem.busUtil 0.33 # Data bus utilization in percentage 256system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 257system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 258system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 259system.physmem.avgWrQLen 20.02 # Average write queue length when enqueuing 260system.physmem.readRowHits 110904 # Number of row buffer hits during reads 261system.physmem.writeRowHits 64452 # Number of row buffer hits during writes 262system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads 263system.physmem.writeRowHitRate 66.74 # Row buffer hit rate for writes 264system.physmem.avgGap 1521741.45 # Average gap between requests 265system.physmem.pageHitRate 72.87 # Row buffer hit rate, read and write combined 266system.physmem_0.actEnergy 247983120 # Energy for activate commands per rank (pJ) 267system.physmem_0.preEnergy 135308250 # Energy for precharge commands per rank (pJ) 268system.physmem_0.readEnergy 560305200 # Energy for read commands per rank (pJ) 269system.physmem_0.writeEnergy 310528080 # Energy for write commands per rank (pJ) 270system.physmem_0.refreshEnergy 23927239440 # Energy for refresh commands per rank (pJ) 271system.physmem_0.actBackEnergy 47721013605 # Energy for active background per rank (pJ) 272system.physmem_0.preBackEnergy 177940783500 # Energy for precharge background per rank (pJ) 273system.physmem_0.totalEnergy 250843161195 # Total energy per rank (pJ) 274system.physmem_0.averagePower 684.736086 # Core power per rank (mW) 275system.physmem_0.memoryStateTime::IDLE 295712636000 # Time in different power states 276system.physmem_0.memoryStateTime::REF 12232740000 # Time in different power states 277system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 278system.physmem_0.memoryStateTime::ACT 58390260500 # Time in different power states 279system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 280system.physmem_1.actEnergy 245095200 # Energy for activate commands per rank (pJ) 281system.physmem_1.preEnergy 133732500 # Energy for precharge commands per rank (pJ) 282system.physmem_1.readEnergy 563066400 # Energy for read commands per rank (pJ) 283system.physmem_1.writeEnergy 314791920 # Energy for write commands per rank (pJ) 284system.physmem_1.refreshEnergy 23927239440 # Energy for refresh commands per rank (pJ) 285system.physmem_1.actBackEnergy 47027452140 # Energy for active background per rank (pJ) 286system.physmem_1.preBackEnergy 178549170750 # Energy for precharge background per rank (pJ) 287system.physmem_1.totalEnergy 250760548350 # Total energy per rank (pJ) 288system.physmem_1.averagePower 684.510574 # Core power per rank (mW) 289system.physmem_1.memoryStateTime::IDLE 296727601000 # Time in different power states 290system.physmem_1.memoryStateTime::REF 12232740000 # Time in different power states 291system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 292system.physmem_1.memoryStateTime::ACT 57375209000 # Time in different power states 293system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 294system.cpu.branchPred.lookups 132583064 # Number of BP lookups 295system.cpu.branchPred.condPredicted 98508784 # Number of conditional branches predicted 296system.cpu.branchPred.condIncorrect 6555218 # Number of conditional branches incorrect 297system.cpu.branchPred.BTBLookups 69071756 # Number of BTB lookups 298system.cpu.branchPred.BTBHits 64847878 # Number of BTB hits 299system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 300system.cpu.branchPred.BTBHitPct 93.884797 # BTB Hit Percentage 301system.cpu.branchPred.usedRAS 10016520 # Number of times the RAS was used to get a target. 302system.cpu.branchPred.RASInCorrect 18156 # Number of incorrect RAS predictions. 303system.cpu_clk_domain.clock 500 # Clock period in ticks 304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 313system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 314system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 315system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 316system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 317system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 322system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 323system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 324system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 333system.cpu.dtb.walker.walks 0 # Table walker walks requested 334system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.inst_hits 0 # ITB inst hits 342system.cpu.dtb.inst_misses 0 # ITB inst misses 343system.cpu.dtb.read_hits 0 # DTB read hits 344system.cpu.dtb.read_misses 0 # DTB read misses 345system.cpu.dtb.write_hits 0 # DTB write hits 346system.cpu.dtb.write_misses 0 # DTB write misses 347system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 348system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 349system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 350system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 351system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 352system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 353system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 354system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 355system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 356system.cpu.dtb.read_accesses 0 # DTB read accesses 357system.cpu.dtb.write_accesses 0 # DTB write accesses 358system.cpu.dtb.inst_accesses 0 # ITB inst accesses 359system.cpu.dtb.hits 0 # DTB hits 360system.cpu.dtb.misses 0 # DTB misses 361system.cpu.dtb.accesses 0 # DTB accesses 362system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 371system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 372system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 373system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 374system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 375system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 376system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 377system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 378system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 379system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 380system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 381system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 382system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 383system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 384system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 386system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 387system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 388system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 389system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 390system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 391system.cpu.itb.walker.walks 0 # Table walker walks requested 392system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.inst_hits 0 # ITB inst hits 400system.cpu.itb.inst_misses 0 # ITB inst misses 401system.cpu.itb.read_hits 0 # DTB read hits 402system.cpu.itb.read_misses 0 # DTB read misses 403system.cpu.itb.write_hits 0 # DTB write hits 404system.cpu.itb.write_misses 0 # DTB write misses 405system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 406system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 408system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 409system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 410system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu.itb.read_accesses 0 # DTB read accesses 415system.cpu.itb.write_accesses 0 # DTB write accesses 416system.cpu.itb.inst_accesses 0 # ITB inst accesses 417system.cpu.itb.hits 0 # DTB hits 418system.cpu.itb.misses 0 # DTB misses 419system.cpu.itb.accesses 0 # DTB accesses 420system.cpu.workload.num_syscalls 548 # Number of system calls 421system.cpu.numCycles 732679001 # number of cpu cycles simulated 422system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 423system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 424system.cpu.committedInsts 506582156 # Number of instructions committed 425system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed 426system.cpu.discardedOps 13461102 # Number of ops (including micro ops) which were discarded before commit 427system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 428system.cpu.cpi 1.446318 # CPI: cycles per instruction 429system.cpu.ipc 0.691411 # IPC: instructions per cycle 430system.cpu.tickCycles 695769824 # Number of cycles that the object actually ticked 431system.cpu.idleCycles 36909177 # Total number of cycles that the object has spent stopped 432system.cpu.dcache.tags.replacements 1139845 # number of replacements 433system.cpu.dcache.tags.tagsinuse 4070.953673 # Cycle average of tags in use 434system.cpu.dcache.tags.total_refs 171282385 # Total number of references to valid blocks. 435system.cpu.dcache.tags.sampled_refs 1143941 # Sample count of references to valid blocks. 436system.cpu.dcache.tags.avg_refs 149.730087 # Average number of references to valid blocks. 437system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. 438system.cpu.dcache.tags.occ_blocks::cpu.data 4070.953673 # Average occupied blocks per requestor 439system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy 440system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy 441system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 442system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id 445system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id 446system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 447system.cpu.dcache.tags.tag_accesses 346819443 # Number of tag accesses 448system.cpu.dcache.tags.data_accesses 346819443 # Number of data accesses 449system.cpu.dcache.ReadReq_hits::cpu.data 114763887 # number of ReadReq hits 450system.cpu.dcache.ReadReq_hits::total 114763887 # number of ReadReq hits 451system.cpu.dcache.WriteReq_hits::cpu.data 53538651 # number of WriteReq hits 452system.cpu.dcache.WriteReq_hits::total 53538651 # number of WriteReq hits 453system.cpu.dcache.SoftPFReq_hits::cpu.data 2765 # number of SoftPFReq hits 454system.cpu.dcache.SoftPFReq_hits::total 2765 # number of SoftPFReq hits 455system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 456system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 457system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 458system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 459system.cpu.dcache.demand_hits::cpu.data 168302538 # number of demand (read+write) hits 460system.cpu.dcache.demand_hits::total 168302538 # number of demand (read+write) hits 461system.cpu.dcache.overall_hits::cpu.data 168305303 # number of overall hits 462system.cpu.dcache.overall_hits::total 168305303 # number of overall hits 463system.cpu.dcache.ReadReq_misses::cpu.data 854696 # number of ReadReq misses 464system.cpu.dcache.ReadReq_misses::total 854696 # number of ReadReq misses 465system.cpu.dcache.WriteReq_misses::cpu.data 700655 # number of WriteReq misses 466system.cpu.dcache.WriteReq_misses::total 700655 # number of WriteReq misses 467system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 468system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses 469system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses 470system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses 471system.cpu.dcache.overall_misses::cpu.data 1555366 # number of overall misses 472system.cpu.dcache.overall_misses::total 1555366 # number of overall misses 473system.cpu.dcache.ReadReq_miss_latency::cpu.data 14025171732 # number of ReadReq miss cycles 474system.cpu.dcache.ReadReq_miss_latency::total 14025171732 # number of ReadReq miss cycles 475system.cpu.dcache.WriteReq_miss_latency::cpu.data 22048092000 # number of WriteReq miss cycles 476system.cpu.dcache.WriteReq_miss_latency::total 22048092000 # number of WriteReq miss cycles 477system.cpu.dcache.demand_miss_latency::cpu.data 36073263732 # number of demand (read+write) miss cycles 478system.cpu.dcache.demand_miss_latency::total 36073263732 # number of demand (read+write) miss cycles 479system.cpu.dcache.overall_miss_latency::cpu.data 36073263732 # number of overall miss cycles 480system.cpu.dcache.overall_miss_latency::total 36073263732 # number of overall miss cycles 481system.cpu.dcache.ReadReq_accesses::cpu.data 115618583 # number of ReadReq accesses(hits+misses) 482system.cpu.dcache.ReadReq_accesses::total 115618583 # number of ReadReq accesses(hits+misses) 483system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 484system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 485system.cpu.dcache.SoftPFReq_accesses::cpu.data 2780 # number of SoftPFReq accesses(hits+misses) 486system.cpu.dcache.SoftPFReq_accesses::total 2780 # number of SoftPFReq accesses(hits+misses) 487system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 488system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 489system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 490system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 491system.cpu.dcache.demand_accesses::cpu.data 169857889 # number of demand (read+write) accesses 492system.cpu.dcache.demand_accesses::total 169857889 # number of demand (read+write) accesses 493system.cpu.dcache.overall_accesses::cpu.data 169860669 # number of overall (read+write) accesses 494system.cpu.dcache.overall_accesses::total 169860669 # number of overall (read+write) accesses 495system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007392 # miss rate for ReadReq accesses 496system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses 497system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses 498system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses 499system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005396 # miss rate for SoftPFReq accesses 500system.cpu.dcache.SoftPFReq_miss_rate::total 0.005396 # miss rate for SoftPFReq accesses 501system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses 502system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses 503system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses 504system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses 505system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16409.544133 # average ReadReq miss latency 506system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.544133 # average ReadReq miss latency 507system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31467.829388 # average WriteReq miss latency 508system.cpu.dcache.WriteReq_avg_miss_latency::total 31467.829388 # average WriteReq miss latency 509system.cpu.dcache.demand_avg_miss_latency::cpu.data 23193.005136 # average overall miss latency 510system.cpu.dcache.demand_avg_miss_latency::total 23193.005136 # average overall miss latency 511system.cpu.dcache.overall_avg_miss_latency::cpu.data 23192.781462 # average overall miss latency 512system.cpu.dcache.overall_avg_miss_latency::total 23192.781462 # average overall miss latency 513system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 517system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 518system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 519system.cpu.dcache.fast_writes 0 # number of fast writes performed 520system.cpu.dcache.cache_copies 0 # number of cache copies performed 521system.cpu.dcache.writebacks::writebacks 1068547 # number of writebacks 522system.cpu.dcache.writebacks::total 1068547 # number of writebacks 523system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66929 # number of ReadReq MSHR hits 524system.cpu.dcache.ReadReq_mshr_hits::total 66929 # number of ReadReq MSHR hits 525system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344493 # number of WriteReq MSHR hits 526system.cpu.dcache.WriteReq_mshr_hits::total 344493 # number of WriteReq MSHR hits 527system.cpu.dcache.demand_mshr_hits::cpu.data 411422 # number of demand (read+write) MSHR hits 528system.cpu.dcache.demand_mshr_hits::total 411422 # number of demand (read+write) MSHR hits 529system.cpu.dcache.overall_mshr_hits::cpu.data 411422 # number of overall MSHR hits 530system.cpu.dcache.overall_mshr_hits::total 411422 # number of overall MSHR hits 531system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787767 # number of ReadReq MSHR misses 532system.cpu.dcache.ReadReq_mshr_misses::total 787767 # number of ReadReq MSHR misses 533system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356162 # number of WriteReq MSHR misses 534system.cpu.dcache.WriteReq_mshr_misses::total 356162 # number of WriteReq MSHR misses 535system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 536system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 537system.cpu.dcache.demand_mshr_misses::cpu.data 1143929 # number of demand (read+write) MSHR misses 538system.cpu.dcache.demand_mshr_misses::total 1143929 # number of demand (read+write) MSHR misses 539system.cpu.dcache.overall_mshr_misses::cpu.data 1143941 # number of overall MSHR misses 540system.cpu.dcache.overall_mshr_misses::total 1143941 # number of overall MSHR misses 541system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930909015 # number of ReadReq MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930909015 # number of ReadReq MSHR miss cycles 543system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10976099750 # number of WriteReq MSHR miss cycles 544system.cpu.dcache.WriteReq_mshr_miss_latency::total 10976099750 # number of WriteReq MSHR miss cycles 545system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 986500 # number of SoftPFReq MSHR miss cycles 546system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 986500 # number of SoftPFReq MSHR miss cycles 547system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22907008765 # number of demand (read+write) MSHR miss cycles 548system.cpu.dcache.demand_mshr_miss_latency::total 22907008765 # number of demand (read+write) MSHR miss cycles 549system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22907995265 # number of overall MSHR miss cycles 550system.cpu.dcache.overall_mshr_miss_latency::total 22907995265 # number of overall MSHR miss cycles 551system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses 552system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses 553system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses 554system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses 555system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004317 # mshr miss rate for SoftPFReq accesses 556system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004317 # mshr miss rate for SoftPFReq accesses 557system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses 558system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses 559system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses 560system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses 561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15145.225701 # average ReadReq mshr miss latency 562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15145.225701 # average ReadReq mshr miss latency 563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30817.717078 # average WriteReq mshr miss latency 564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30817.717078 # average WriteReq mshr miss latency 565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 82208.333333 # average SoftPFReq mshr miss latency 566system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 82208.333333 # average SoftPFReq mshr miss latency 567system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20024.851861 # average overall mshr miss latency 568system.cpu.dcache.demand_avg_mshr_miss_latency::total 20024.851861 # average overall mshr miss latency 569system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.504169 # average overall mshr miss latency 570system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.504169 # average overall mshr miss latency 571system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 572system.cpu.icache.tags.replacements 17672 # number of replacements 573system.cpu.icache.tags.tagsinuse 1190.163457 # Cycle average of tags in use 574system.cpu.icache.tags.total_refs 200929857 # Total number of references to valid blocks. 575system.cpu.icache.tags.sampled_refs 19544 # Sample count of references to valid blocks. 576system.cpu.icache.tags.avg_refs 10280.897309 # Average number of references to valid blocks. 577system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 578system.cpu.icache.tags.occ_blocks::cpu.inst 1190.163457 # Average occupied blocks per requestor 579system.cpu.icache.tags.occ_percent::cpu.inst 0.581135 # Average percentage of cache occupancy 580system.cpu.icache.tags.occ_percent::total 0.581135 # Average percentage of cache occupancy 581system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 582system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 583system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 584system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id 585system.cpu.icache.tags.age_task_id_blocks_1024::3 306 # Occupied blocks per task id 586system.cpu.icache.tags.age_task_id_blocks_1024::4 1407 # Occupied blocks per task id 587system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id 588system.cpu.icache.tags.tag_accesses 401918346 # Number of tag accesses 589system.cpu.icache.tags.data_accesses 401918346 # Number of data accesses 590system.cpu.icache.ReadReq_hits::cpu.inst 200929857 # number of ReadReq hits 591system.cpu.icache.ReadReq_hits::total 200929857 # number of ReadReq hits 592system.cpu.icache.demand_hits::cpu.inst 200929857 # number of demand (read+write) hits 593system.cpu.icache.demand_hits::total 200929857 # number of demand (read+write) hits 594system.cpu.icache.overall_hits::cpu.inst 200929857 # number of overall hits 595system.cpu.icache.overall_hits::total 200929857 # number of overall hits 596system.cpu.icache.ReadReq_misses::cpu.inst 19544 # number of ReadReq misses 597system.cpu.icache.ReadReq_misses::total 19544 # number of ReadReq misses 598system.cpu.icache.demand_misses::cpu.inst 19544 # number of demand (read+write) misses 599system.cpu.icache.demand_misses::total 19544 # number of demand (read+write) misses 600system.cpu.icache.overall_misses::cpu.inst 19544 # number of overall misses 601system.cpu.icache.overall_misses::total 19544 # number of overall misses 602system.cpu.icache.ReadReq_miss_latency::cpu.inst 494847996 # number of ReadReq miss cycles 603system.cpu.icache.ReadReq_miss_latency::total 494847996 # number of ReadReq miss cycles 604system.cpu.icache.demand_miss_latency::cpu.inst 494847996 # number of demand (read+write) miss cycles 605system.cpu.icache.demand_miss_latency::total 494847996 # number of demand (read+write) miss cycles 606system.cpu.icache.overall_miss_latency::cpu.inst 494847996 # number of overall miss cycles 607system.cpu.icache.overall_miss_latency::total 494847996 # number of overall miss cycles 608system.cpu.icache.ReadReq_accesses::cpu.inst 200949401 # number of ReadReq accesses(hits+misses) 609system.cpu.icache.ReadReq_accesses::total 200949401 # number of ReadReq accesses(hits+misses) 610system.cpu.icache.demand_accesses::cpu.inst 200949401 # number of demand (read+write) accesses 611system.cpu.icache.demand_accesses::total 200949401 # number of demand (read+write) accesses 612system.cpu.icache.overall_accesses::cpu.inst 200949401 # number of overall (read+write) accesses 613system.cpu.icache.overall_accesses::total 200949401 # number of overall (read+write) accesses 614system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses 615system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses 616system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses 617system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses 618system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses 619system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses 620system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25319.688702 # average ReadReq miss latency 621system.cpu.icache.ReadReq_avg_miss_latency::total 25319.688702 # average ReadReq miss latency 622system.cpu.icache.demand_avg_miss_latency::cpu.inst 25319.688702 # average overall miss latency 623system.cpu.icache.demand_avg_miss_latency::total 25319.688702 # average overall miss latency 624system.cpu.icache.overall_avg_miss_latency::cpu.inst 25319.688702 # average overall miss latency 625system.cpu.icache.overall_avg_miss_latency::total 25319.688702 # average overall miss latency 626system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 627system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 628system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 629system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 630system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 631system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 632system.cpu.icache.fast_writes 0 # number of fast writes performed 633system.cpu.icache.cache_copies 0 # number of cache copies performed 634system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19544 # number of ReadReq MSHR misses 635system.cpu.icache.ReadReq_mshr_misses::total 19544 # number of ReadReq MSHR misses 636system.cpu.icache.demand_mshr_misses::cpu.inst 19544 # number of demand (read+write) MSHR misses 637system.cpu.icache.demand_mshr_misses::total 19544 # number of demand (read+write) MSHR misses 638system.cpu.icache.overall_mshr_misses::cpu.inst 19544 # number of overall MSHR misses 639system.cpu.icache.overall_mshr_misses::total 19544 # number of overall MSHR misses 640system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 464144004 # number of ReadReq MSHR miss cycles 641system.cpu.icache.ReadReq_mshr_miss_latency::total 464144004 # number of ReadReq MSHR miss cycles 642system.cpu.icache.demand_mshr_miss_latency::cpu.inst 464144004 # number of demand (read+write) MSHR miss cycles 643system.cpu.icache.demand_mshr_miss_latency::total 464144004 # number of demand (read+write) MSHR miss cycles 644system.cpu.icache.overall_mshr_miss_latency::cpu.inst 464144004 # number of overall MSHR miss cycles 645system.cpu.icache.overall_mshr_miss_latency::total 464144004 # number of overall MSHR miss cycles 646system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses 647system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses 648system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses 649system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses 650system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses 651system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses 652system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23748.669873 # average ReadReq mshr miss latency 653system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23748.669873 # average ReadReq mshr miss latency 654system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23748.669873 # average overall mshr miss latency 655system.cpu.icache.demand_avg_mshr_miss_latency::total 23748.669873 # average overall mshr miss latency 656system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23748.669873 # average overall mshr miss latency 657system.cpu.icache.overall_avg_mshr_miss_latency::total 23748.669873 # average overall mshr miss latency 658system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 659system.cpu.l2cache.tags.replacements 111417 # number of replacements 660system.cpu.l2cache.tags.tagsinuse 27648.763503 # Cycle average of tags in use 661system.cpu.l2cache.tags.total_refs 1684506 # Total number of references to valid blocks. 662system.cpu.l2cache.tags.sampled_refs 142603 # Sample count of references to valid blocks. 663system.cpu.l2cache.tags.avg_refs 11.812557 # Average number of references to valid blocks. 664system.cpu.l2cache.tags.warmup_cycle 163802727000 # Cycle when the warmup percentage was hit. 665system.cpu.l2cache.tags.occ_blocks::writebacks 23521.944211 # Average occupied blocks per requestor 666system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.271354 # Average occupied blocks per requestor 667system.cpu.l2cache.tags.occ_blocks::cpu.data 3736.547938 # Average occupied blocks per requestor 668system.cpu.l2cache.tags.occ_percent::writebacks 0.717833 # Average percentage of cache occupancy 669system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011910 # Average percentage of cache occupancy 670system.cpu.l2cache.tags.occ_percent::cpu.data 0.114030 # Average percentage of cache occupancy 671system.cpu.l2cache.tags.occ_percent::total 0.843773 # Average percentage of cache occupancy 672system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id 673system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 674system.cpu.l2cache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id 675system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4943 # Occupied blocks per task id 676system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25856 # Occupied blocks per task id 677system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id 678system.cpu.l2cache.tags.tag_accesses 18355274 # Number of tag accesses 679system.cpu.l2cache.tags.data_accesses 18355274 # Number of data accesses 680system.cpu.l2cache.ReadReq_hits::cpu.inst 16070 # number of ReadReq hits 681system.cpu.l2cache.ReadReq_hits::cpu.data 747693 # number of ReadReq hits 682system.cpu.l2cache.ReadReq_hits::total 763763 # number of ReadReq hits 683system.cpu.l2cache.Writeback_hits::writebacks 1068547 # number of Writeback hits 684system.cpu.l2cache.Writeback_hits::total 1068547 # number of Writeback hits 685system.cpu.l2cache.ReadExReq_hits::cpu.data 255534 # number of ReadExReq hits 686system.cpu.l2cache.ReadExReq_hits::total 255534 # number of ReadExReq hits 687system.cpu.l2cache.demand_hits::cpu.inst 16070 # number of demand (read+write) hits 688system.cpu.l2cache.demand_hits::cpu.data 1003227 # number of demand (read+write) hits 689system.cpu.l2cache.demand_hits::total 1019297 # number of demand (read+write) hits 690system.cpu.l2cache.overall_hits::cpu.inst 16070 # number of overall hits 691system.cpu.l2cache.overall_hits::cpu.data 1003227 # number of overall hits 692system.cpu.l2cache.overall_hits::total 1019297 # number of overall hits 693system.cpu.l2cache.ReadReq_misses::cpu.inst 3474 # number of ReadReq misses 694system.cpu.l2cache.ReadReq_misses::cpu.data 39833 # number of ReadReq misses 695system.cpu.l2cache.ReadReq_misses::total 43307 # number of ReadReq misses 696system.cpu.l2cache.ReadExReq_misses::cpu.data 100881 # number of ReadExReq misses 697system.cpu.l2cache.ReadExReq_misses::total 100881 # number of ReadExReq misses 698system.cpu.l2cache.demand_misses::cpu.inst 3474 # number of demand (read+write) misses 699system.cpu.l2cache.demand_misses::cpu.data 140714 # number of demand (read+write) misses 700system.cpu.l2cache.demand_misses::total 144188 # number of demand (read+write) misses 701system.cpu.l2cache.overall_misses::cpu.inst 3474 # number of overall misses 702system.cpu.l2cache.overall_misses::cpu.data 140714 # number of overall misses 703system.cpu.l2cache.overall_misses::total 144188 # number of overall misses 704system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 275801500 # number of ReadReq miss cycles 705system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3286544500 # number of ReadReq miss cycles 706system.cpu.l2cache.ReadReq_miss_latency::total 3562346000 # number of ReadReq miss cycles 707system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7939327250 # number of ReadExReq miss cycles 708system.cpu.l2cache.ReadExReq_miss_latency::total 7939327250 # number of ReadExReq miss cycles 709system.cpu.l2cache.demand_miss_latency::cpu.inst 275801500 # number of demand (read+write) miss cycles 710system.cpu.l2cache.demand_miss_latency::cpu.data 11225871750 # number of demand (read+write) miss cycles 711system.cpu.l2cache.demand_miss_latency::total 11501673250 # number of demand (read+write) miss cycles 712system.cpu.l2cache.overall_miss_latency::cpu.inst 275801500 # number of overall miss cycles 713system.cpu.l2cache.overall_miss_latency::cpu.data 11225871750 # number of overall miss cycles 714system.cpu.l2cache.overall_miss_latency::total 11501673250 # number of overall miss cycles 715system.cpu.l2cache.ReadReq_accesses::cpu.inst 19544 # number of ReadReq accesses(hits+misses) 716system.cpu.l2cache.ReadReq_accesses::cpu.data 787526 # number of ReadReq accesses(hits+misses) 717system.cpu.l2cache.ReadReq_accesses::total 807070 # number of ReadReq accesses(hits+misses) 718system.cpu.l2cache.Writeback_accesses::writebacks 1068547 # number of Writeback accesses(hits+misses) 719system.cpu.l2cache.Writeback_accesses::total 1068547 # number of Writeback accesses(hits+misses) 720system.cpu.l2cache.ReadExReq_accesses::cpu.data 356415 # number of ReadExReq accesses(hits+misses) 721system.cpu.l2cache.ReadExReq_accesses::total 356415 # number of ReadExReq accesses(hits+misses) 722system.cpu.l2cache.demand_accesses::cpu.inst 19544 # number of demand (read+write) accesses 723system.cpu.l2cache.demand_accesses::cpu.data 1143941 # number of demand (read+write) accesses 724system.cpu.l2cache.demand_accesses::total 1163485 # number of demand (read+write) accesses 725system.cpu.l2cache.overall_accesses::cpu.inst 19544 # number of overall (read+write) accesses 726system.cpu.l2cache.overall_accesses::cpu.data 1143941 # number of overall (read+write) accesses 727system.cpu.l2cache.overall_accesses::total 1163485 # number of overall (read+write) accesses 728system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177753 # miss rate for ReadReq accesses 729system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050580 # miss rate for ReadReq accesses 730system.cpu.l2cache.ReadReq_miss_rate::total 0.053660 # miss rate for ReadReq accesses 731system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283044 # miss rate for ReadExReq accesses 732system.cpu.l2cache.ReadExReq_miss_rate::total 0.283044 # miss rate for ReadExReq accesses 733system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177753 # miss rate for demand accesses 734system.cpu.l2cache.demand_miss_rate::cpu.data 0.123008 # miss rate for demand accesses 735system.cpu.l2cache.demand_miss_rate::total 0.123928 # miss rate for demand accesses 736system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177753 # miss rate for overall accesses 737system.cpu.l2cache.overall_miss_rate::cpu.data 0.123008 # miss rate for overall accesses 738system.cpu.l2cache.overall_miss_rate::total 0.123928 # miss rate for overall accesses 739system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79390.184226 # average ReadReq miss latency 740system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82508.083750 # average ReadReq miss latency 741system.cpu.l2cache.ReadReq_avg_miss_latency::total 82257.972152 # average ReadReq miss latency 742system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78699.926151 # average ReadExReq miss latency 743system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78699.926151 # average ReadExReq miss latency 744system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79390.184226 # average overall miss latency 745system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79777.930767 # average overall miss latency 746system.cpu.l2cache.demand_avg_miss_latency::total 79768.588579 # average overall miss latency 747system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79390.184226 # average overall miss latency 748system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79777.930767 # average overall miss latency 749system.cpu.l2cache.overall_avg_miss_latency::total 79768.588579 # average overall miss latency 750system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 753system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 755system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.cpu.l2cache.fast_writes 0 # number of fast writes performed 757system.cpu.l2cache.cache_copies 0 # number of cache copies performed 758system.cpu.l2cache.writebacks::writebacks 96566 # number of writebacks 759system.cpu.l2cache.writebacks::total 96566 # number of writebacks 760system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 761system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits 762system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 763system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 764system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits 765system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 766system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 767system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits 768system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 769system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3472 # number of ReadReq MSHR misses 770system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39818 # number of ReadReq MSHR misses 771system.cpu.l2cache.ReadReq_mshr_misses::total 43290 # number of ReadReq MSHR misses 772system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100881 # number of ReadExReq MSHR misses 773system.cpu.l2cache.ReadExReq_mshr_misses::total 100881 # number of ReadExReq MSHR misses 774system.cpu.l2cache.demand_mshr_misses::cpu.inst 3472 # number of demand (read+write) MSHR misses 775system.cpu.l2cache.demand_mshr_misses::cpu.data 140699 # number of demand (read+write) MSHR misses 776system.cpu.l2cache.demand_mshr_misses::total 144171 # number of demand (read+write) MSHR misses 777system.cpu.l2cache.overall_mshr_misses::cpu.inst 3472 # number of overall MSHR misses 778system.cpu.l2cache.overall_mshr_misses::cpu.data 140699 # number of overall MSHR misses 779system.cpu.l2cache.overall_mshr_misses::total 144171 # number of overall MSHR misses 780system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 232222500 # number of ReadReq MSHR miss cycles 781system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2786510500 # number of ReadReq MSHR miss cycles 782system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3018733000 # number of ReadReq MSHR miss cycles 783system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6677694250 # number of ReadExReq MSHR miss cycles 784system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6677694250 # number of ReadExReq MSHR miss cycles 785system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 232222500 # number of demand (read+write) MSHR miss cycles 786system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9464204750 # number of demand (read+write) MSHR miss cycles 787system.cpu.l2cache.demand_mshr_miss_latency::total 9696427250 # number of demand (read+write) MSHR miss cycles 788system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 232222500 # number of overall MSHR miss cycles 789system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9464204750 # number of overall MSHR miss cycles 790system.cpu.l2cache.overall_mshr_miss_latency::total 9696427250 # number of overall MSHR miss cycles 791system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for ReadReq accesses 792system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050561 # mshr miss rate for ReadReq accesses 793system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053638 # mshr miss rate for ReadReq accesses 794system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283044 # mshr miss rate for ReadExReq accesses 795system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283044 # mshr miss rate for ReadExReq accesses 796system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for demand accesses 797system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122995 # mshr miss rate for demand accesses 798system.cpu.l2cache.demand_mshr_miss_rate::total 0.123913 # mshr miss rate for demand accesses 799system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for overall accesses 800system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122995 # mshr miss rate for overall accesses 801system.cpu.l2cache.overall_mshr_miss_rate::total 0.123913 # mshr miss rate for overall accesses 802system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66884.360599 # average ReadReq mshr miss latency 803system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69981.176855 # average ReadReq mshr miss latency 804system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69732.802033 # average ReadReq mshr miss latency 805system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66193.775339 # average ReadExReq mshr miss latency 806system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66193.775339 # average ReadExReq mshr miss latency 807system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66884.360599 # average overall mshr miss latency 808system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67265.614894 # average overall mshr miss latency 809system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67256.433333 # average overall mshr miss latency 810system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66884.360599 # average overall mshr miss latency 811system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67265.614894 # average overall mshr miss latency 812system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67256.433333 # average overall mshr miss latency 813system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 814system.cpu.toL2Bus.trans_dist::ReadReq 807070 # Transaction distribution 815system.cpu.toL2Bus.trans_dist::ReadResp 807070 # Transaction distribution 816system.cpu.toL2Bus.trans_dist::Writeback 1068547 # Transaction distribution 817system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution 818system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution 819system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39088 # Packet count per connected master and slave (bytes) 820system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356429 # Packet count per connected master and slave (bytes) 821system.cpu.toL2Bus.pkt_count::total 3395517 # Packet count per connected master and slave (bytes) 822system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250816 # Cumulative packet size per connected master and slave (bytes) 823system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141599232 # Cumulative packet size per connected master and slave (bytes) 824system.cpu.toL2Bus.pkt_size::total 142850048 # Cumulative packet size per connected master and slave (bytes) 825system.cpu.toL2Bus.snoops 0 # Total snoops (count) 826system.cpu.toL2Bus.snoop_fanout::samples 2232032 # Request fanout histogram
827system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram	827system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
828system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 829system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 830system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram	828system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 829system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 830system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
831system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 832system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 833system.cpu.toL2Bus.snoop_fanout::3 2232032 100.00% 100.00% # Request fanout histogram 834system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram	831system.cpu.toL2Bus.snoop_fanout::1 2232032 100.00% 100.00% # Request fanout histogram 832system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
835system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram	833system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
836system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 837system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram	834system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 835system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
838system.cpu.toL2Bus.snoop_fanout::total 2232032 # Request fanout histogram 839system.cpu.toL2Bus.reqLayer0.occupancy 2184563000 # Layer occupancy (ticks) 840system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 841system.cpu.toL2Bus.respLayer0.occupancy 30009996 # Layer occupancy (ticks) 842system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 843system.cpu.toL2Bus.respLayer1.occupancy 1744692235 # Layer occupancy (ticks) 844system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 845system.membus.trans_dist::ReadReq 43290 # Transaction distribution 846system.membus.trans_dist::ReadResp 43290 # Transaction distribution 847system.membus.trans_dist::Writeback 96566 # Transaction distribution 848system.membus.trans_dist::ReadExReq 100881 # Transaction distribution 849system.membus.trans_dist::ReadExResp 100881 # Transaction distribution 850system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384908 # Packet count per connected master and slave (bytes) 851system.membus.pkt_count::total 384908 # Packet count per connected master and slave (bytes) 852system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407168 # Cumulative packet size per connected master and slave (bytes) 853system.membus.pkt_size::total 15407168 # Cumulative packet size per connected master and slave (bytes) 854system.membus.snoops 0 # Total snoops (count) 855system.membus.snoop_fanout::samples 240737 # Request fanout histogram 856system.membus.snoop_fanout::mean 0 # Request fanout histogram 857system.membus.snoop_fanout::stdev 0 # Request fanout histogram 858system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 859system.membus.snoop_fanout::0 240737 100.00% 100.00% # Request fanout histogram 860system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 861system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 862system.membus.snoop_fanout::min_value 0 # Request fanout histogram 863system.membus.snoop_fanout::max_value 0 # Request fanout histogram 864system.membus.snoop_fanout::total 240737 # Request fanout histogram 865system.membus.reqLayer0.occupancy 679133000 # Layer occupancy (ticks) 866system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 867system.membus.respLayer1.occupancy 765318250 # Layer occupancy (ticks) 868system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 869 870---------- End Simulation Statistics ----------	836system.cpu.toL2Bus.snoop_fanout::total 2232032 # Request fanout histogram 837system.cpu.toL2Bus.reqLayer0.occupancy 2184563000 # Layer occupancy (ticks) 838system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 839system.cpu.toL2Bus.respLayer0.occupancy 30009996 # Layer occupancy (ticks) 840system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 841system.cpu.toL2Bus.respLayer1.occupancy 1744692235 # Layer occupancy (ticks) 842system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 843system.membus.trans_dist::ReadReq 43290 # Transaction distribution 844system.membus.trans_dist::ReadResp 43290 # Transaction distribution 845system.membus.trans_dist::Writeback 96566 # Transaction distribution 846system.membus.trans_dist::ReadExReq 100881 # Transaction distribution 847system.membus.trans_dist::ReadExResp 100881 # Transaction distribution 848system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384908 # Packet count per connected master and slave (bytes) 849system.membus.pkt_count::total 384908 # Packet count per connected master and slave (bytes) 850system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407168 # Cumulative packet size per connected master and slave (bytes) 851system.membus.pkt_size::total 15407168 # Cumulative packet size per connected master and slave (bytes) 852system.membus.snoops 0 # Total snoops (count) 853system.membus.snoop_fanout::samples 240737 # Request fanout histogram 854system.membus.snoop_fanout::mean 0 # Request fanout histogram 855system.membus.snoop_fanout::stdev 0 # Request fanout histogram 856system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 857system.membus.snoop_fanout::0 240737 100.00% 100.00% # Request fanout histogram 858system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 859system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 860system.membus.snoop_fanout::min_value 0 # Request fanout histogram 861system.membus.snoop_fanout::max_value 0 # Request fanout histogram 862system.membus.snoop_fanout::total 240737 # Request fanout histogram 863system.membus.reqLayer0.occupancy 679133000 # Layer occupancy (ticks) 864system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 865system.membus.respLayer1.occupancy 765318250 # Layer occupancy (ticks) 866system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 867 868---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.366340 # Number of seconds simulated
4sim_ticks 366339500500 # Number of ticks simulated
5final_tick 366339500500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 174606 # Simulator instruction rate (inst/s)
8host_op_rate 189122 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 126268215 # Simulator tick rate (ticks/s)
10host_mem_usage 309684 # Number of bytes of host memory used
11host_seconds 2901.28 # Real time elapsed on the host

7host_inst_rate 237525 # Simulator instruction rate (inst/s)
8host_op_rate 257271 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 171768388 # Simulator tick rate (ticks/s)
10host_mem_usage 317860 # Number of bytes of host memory used
11host_seconds 2132.75 # Real time elapsed on the host

12sim_insts 506582156 # Number of instructions simulated
13sim_ops 548695379 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 222208 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9004736 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9226944 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 222208 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 222208 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 6180224 # Number of bytes written to this memory
22system.physmem.bytes_written::total 6180224 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 3472 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 140699 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 144171 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 96566 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 96566 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 606563 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 24580303 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 25186866 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 606563 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 606563 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 16870209 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 16870209 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 16870209 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 606563 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 24580303 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 42057075 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 144171 # Number of read requests accepted
40system.physmem.writeReqs 96566 # Number of write requests accepted
41system.physmem.readBursts 144171 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 96566 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue
45system.physmem.bytesWritten 6179072 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 9226944 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 6180224 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 9343 # Per bank write bursts
52system.physmem.perBankRdBursts::1 8971 # Per bank write bursts
53system.physmem.perBankRdBursts::2 8989 # Per bank write bursts
54system.physmem.perBankRdBursts::3 8699 # Per bank write bursts
55system.physmem.perBankRdBursts::4 9456 # Per bank write bursts
56system.physmem.perBankRdBursts::5 9348 # Per bank write bursts
57system.physmem.perBankRdBursts::6 8947 # Per bank write bursts
58system.physmem.perBankRdBursts::7 8105 # Per bank write bursts
59system.physmem.perBankRdBursts::8 8575 # Per bank write bursts
60system.physmem.perBankRdBursts::9 8682 # Per bank write bursts
61system.physmem.perBankRdBursts::10 8775 # Per bank write bursts
62system.physmem.perBankRdBursts::11 9479 # Per bank write bursts
63system.physmem.perBankRdBursts::12 9376 # Per bank write bursts
64system.physmem.perBankRdBursts::13 9525 # Per bank write bursts
65system.physmem.perBankRdBursts::14 8707 # Per bank write bursts
66system.physmem.perBankRdBursts::15 9090 # Per bank write bursts
67system.physmem.perBankWrBursts::0 6188 # Per bank write bursts
68system.physmem.perBankWrBursts::1 6094 # Per bank write bursts
69system.physmem.perBankWrBursts::2 6005 # Per bank write bursts
70system.physmem.perBankWrBursts::3 5814 # Per bank write bursts
71system.physmem.perBankWrBursts::4 6162 # Per bank write bursts
72system.physmem.perBankWrBursts::5 6175 # Per bank write bursts
73system.physmem.perBankWrBursts::6 6015 # Per bank write bursts
74system.physmem.perBankWrBursts::7 5497 # Per bank write bursts
75system.physmem.perBankWrBursts::8 5730 # Per bank write bursts
76system.physmem.perBankWrBursts::9 5822 # Per bank write bursts
77system.physmem.perBankWrBursts::10 5962 # Per bank write bursts
78system.physmem.perBankWrBursts::11 6449 # Per bank write bursts
79system.physmem.perBankWrBursts::12 6307 # Per bank write bursts
80system.physmem.perBankWrBursts::13 6278 # Per bank write bursts
81system.physmem.perBankWrBursts::14 5993 # Per bank write bursts
82system.physmem.perBankWrBursts::15 6057 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 366339471500 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 144171 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 96566 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 2905 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 3091 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 5560 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 5651 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 5674 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 5678 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 5665 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 5690 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 5705 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 5677 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 5683 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 5667 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 5666 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 5663 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 5600 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::32 5592 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196system.physmem.bytesPerActivate::samples 65255 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::mean 235.982530 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::gmean 156.409511 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::stdev 241.771416 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::0-127 24814 38.03% 38.03% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::128-255 18186 27.87% 65.90% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::256-383 6968 10.68% 76.57% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::384-511 7930 12.15% 88.73% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::512-639 2060 3.16% 91.88% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::640-767 1157 1.77% 93.66% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::768-895 782 1.20% 94.85% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::896-1023 601 0.92% 95.78% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1024-1151 2757 4.22% 100.00% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::total 65255 # Bytes accessed per row activation
210system.physmem.rdPerTurnAround::samples 5574 # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::mean 25.846071 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::stdev 382.003663 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::0-1023 5571 99.95% 99.95% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::total 5574 # Reads before turning the bus around for writes
217system.physmem.wrPerTurnAround::samples 5574 # Writes before turning the bus around for reads
218system.physmem.wrPerTurnAround::mean 17.321134 # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::gmean 17.221070 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::stdev 2.354740 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::16-17 2655 47.63% 47.63% # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::18-19 2759 49.50% 97.13% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::20-21 73 1.31% 98.44% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::22-23 16 0.29% 98.73% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::24-25 14 0.25% 98.98% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::26-27 15 0.27% 99.25% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::28-29 8 0.14% 99.39% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::30-31 5 0.09% 99.48% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::32-33 9 0.16% 99.64% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::36-37 1 0.02% 99.77% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::38-39 2 0.04% 99.80% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::40-41 1 0.02% 99.82% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::42-43 1 0.02% 99.84% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::44-45 2 0.04% 99.87% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::54-55 1 0.02% 99.93% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::64-65 1 0.02% 99.96% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::66-67 1 0.02% 99.98% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::70-71 1 0.02% 100.00% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::total 5574 # Writes before turning the bus around for reads
244system.physmem.totQLat 1547962750 # Total ticks spent queuing
245system.physmem.totMemAccLat 4249219000 # Total ticks spent from burst creation until serviced by the DRAM
246system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers
247system.physmem.avgQLat 10744.74 # Average queueing delay per DRAM burst
248system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
249system.physmem.avgMemAccLat 29494.74 # Average memory access latency per DRAM burst
250system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s
251system.physmem.avgWrBW 16.87 # Average achieved write bandwidth in MiByte/s
252system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s
253system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s
254system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
255system.physmem.busUtil 0.33 # Data bus utilization in percentage
256system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
257system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
258system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
259system.physmem.avgWrQLen 20.02 # Average write queue length when enqueuing
260system.physmem.readRowHits 110904 # Number of row buffer hits during reads
261system.physmem.writeRowHits 64452 # Number of row buffer hits during writes
262system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads
263system.physmem.writeRowHitRate 66.74 # Row buffer hit rate for writes
264system.physmem.avgGap 1521741.45 # Average gap between requests
265system.physmem.pageHitRate 72.87 # Row buffer hit rate, read and write combined
266system.physmem_0.actEnergy 247983120 # Energy for activate commands per rank (pJ)
267system.physmem_0.preEnergy 135308250 # Energy for precharge commands per rank (pJ)
268system.physmem_0.readEnergy 560305200 # Energy for read commands per rank (pJ)
269system.physmem_0.writeEnergy 310528080 # Energy for write commands per rank (pJ)
270system.physmem_0.refreshEnergy 23927239440 # Energy for refresh commands per rank (pJ)
271system.physmem_0.actBackEnergy 47721013605 # Energy for active background per rank (pJ)
272system.physmem_0.preBackEnergy 177940783500 # Energy for precharge background per rank (pJ)
273system.physmem_0.totalEnergy 250843161195 # Total energy per rank (pJ)
274system.physmem_0.averagePower 684.736086 # Core power per rank (mW)
275system.physmem_0.memoryStateTime::IDLE 295712636000 # Time in different power states
276system.physmem_0.memoryStateTime::REF 12232740000 # Time in different power states
277system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
278system.physmem_0.memoryStateTime::ACT 58390260500 # Time in different power states
279system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
280system.physmem_1.actEnergy 245095200 # Energy for activate commands per rank (pJ)
281system.physmem_1.preEnergy 133732500 # Energy for precharge commands per rank (pJ)
282system.physmem_1.readEnergy 563066400 # Energy for read commands per rank (pJ)
283system.physmem_1.writeEnergy 314791920 # Energy for write commands per rank (pJ)
284system.physmem_1.refreshEnergy 23927239440 # Energy for refresh commands per rank (pJ)
285system.physmem_1.actBackEnergy 47027452140 # Energy for active background per rank (pJ)
286system.physmem_1.preBackEnergy 178549170750 # Energy for precharge background per rank (pJ)
287system.physmem_1.totalEnergy 250760548350 # Total energy per rank (pJ)
288system.physmem_1.averagePower 684.510574 # Core power per rank (mW)
289system.physmem_1.memoryStateTime::IDLE 296727601000 # Time in different power states
290system.physmem_1.memoryStateTime::REF 12232740000 # Time in different power states
291system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
292system.physmem_1.memoryStateTime::ACT 57375209000 # Time in different power states
293system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
294system.cpu.branchPred.lookups 132583064 # Number of BP lookups
295system.cpu.branchPred.condPredicted 98508784 # Number of conditional branches predicted
296system.cpu.branchPred.condIncorrect 6555218 # Number of conditional branches incorrect
297system.cpu.branchPred.BTBLookups 69071756 # Number of BTB lookups
298system.cpu.branchPred.BTBHits 64847878 # Number of BTB hits
299system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
300system.cpu.branchPred.BTBHitPct 93.884797 # BTB Hit Percentage
301system.cpu.branchPred.usedRAS 10016520 # Number of times the RAS was used to get a target.
302system.cpu.branchPred.RASInCorrect 18156 # Number of incorrect RAS predictions.
303system.cpu_clk_domain.clock 500 # Clock period in ticks
304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
312system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
313system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
314system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
315system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
316system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
317system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
322system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
323system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
324system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
333system.cpu.dtb.walker.walks 0 # Table walker walks requested
334system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
335system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
336system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
337system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
338system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
339system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
340system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
341system.cpu.dtb.inst_hits 0 # ITB inst hits
342system.cpu.dtb.inst_misses 0 # ITB inst misses
343system.cpu.dtb.read_hits 0 # DTB read hits
344system.cpu.dtb.read_misses 0 # DTB read misses
345system.cpu.dtb.write_hits 0 # DTB write hits
346system.cpu.dtb.write_misses 0 # DTB write misses
347system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
348system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
349system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
350system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
351system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
352system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
353system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
354system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
355system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
356system.cpu.dtb.read_accesses 0 # DTB read accesses
357system.cpu.dtb.write_accesses 0 # DTB write accesses
358system.cpu.dtb.inst_accesses 0 # ITB inst accesses
359system.cpu.dtb.hits 0 # DTB hits
360system.cpu.dtb.misses 0 # DTB misses
361system.cpu.dtb.accesses 0 # DTB accesses
362system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
370system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
371system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
372system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
373system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
374system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
375system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
376system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
377system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
378system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
379system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
380system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
381system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
382system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
383system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
384system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
385system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
386system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
387system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
388system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
389system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
390system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
391system.cpu.itb.walker.walks 0 # Table walker walks requested
392system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
393system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
394system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
395system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
396system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
397system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
398system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
399system.cpu.itb.inst_hits 0 # ITB inst hits
400system.cpu.itb.inst_misses 0 # ITB inst misses
401system.cpu.itb.read_hits 0 # DTB read hits
402system.cpu.itb.read_misses 0 # DTB read misses
403system.cpu.itb.write_hits 0 # DTB write hits
404system.cpu.itb.write_misses 0 # DTB write misses
405system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
406system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
407system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
408system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
409system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
410system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
411system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
412system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
413system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
414system.cpu.itb.read_accesses 0 # DTB read accesses
415system.cpu.itb.write_accesses 0 # DTB write accesses
416system.cpu.itb.inst_accesses 0 # ITB inst accesses
417system.cpu.itb.hits 0 # DTB hits
418system.cpu.itb.misses 0 # DTB misses
419system.cpu.itb.accesses 0 # DTB accesses
420system.cpu.workload.num_syscalls 548 # Number of system calls
421system.cpu.numCycles 732679001 # number of cpu cycles simulated
422system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
423system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
424system.cpu.committedInsts 506582156 # Number of instructions committed
425system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed
426system.cpu.discardedOps 13461102 # Number of ops (including micro ops) which were discarded before commit
427system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
428system.cpu.cpi 1.446318 # CPI: cycles per instruction
429system.cpu.ipc 0.691411 # IPC: instructions per cycle
430system.cpu.tickCycles 695769824 # Number of cycles that the object actually ticked
431system.cpu.idleCycles 36909177 # Total number of cycles that the object has spent stopped
432system.cpu.dcache.tags.replacements 1139845 # number of replacements
433system.cpu.dcache.tags.tagsinuse 4070.953673 # Cycle average of tags in use
434system.cpu.dcache.tags.total_refs 171282385 # Total number of references to valid blocks.
435system.cpu.dcache.tags.sampled_refs 1143941 # Sample count of references to valid blocks.
436system.cpu.dcache.tags.avg_refs 149.730087 # Average number of references to valid blocks.
437system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit.
438system.cpu.dcache.tags.occ_blocks::cpu.data 4070.953673 # Average occupied blocks per requestor
439system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy
440system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy
441system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
442system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
443system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
444system.cpu.dcache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id
445system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id
446system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
447system.cpu.dcache.tags.tag_accesses 346819443 # Number of tag accesses
448system.cpu.dcache.tags.data_accesses 346819443 # Number of data accesses
449system.cpu.dcache.ReadReq_hits::cpu.data 114763887 # number of ReadReq hits
450system.cpu.dcache.ReadReq_hits::total 114763887 # number of ReadReq hits
451system.cpu.dcache.WriteReq_hits::cpu.data 53538651 # number of WriteReq hits
452system.cpu.dcache.WriteReq_hits::total 53538651 # number of WriteReq hits
453system.cpu.dcache.SoftPFReq_hits::cpu.data 2765 # number of SoftPFReq hits
454system.cpu.dcache.SoftPFReq_hits::total 2765 # number of SoftPFReq hits
455system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
456system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
457system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
458system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
459system.cpu.dcache.demand_hits::cpu.data 168302538 # number of demand (read+write) hits
460system.cpu.dcache.demand_hits::total 168302538 # number of demand (read+write) hits
461system.cpu.dcache.overall_hits::cpu.data 168305303 # number of overall hits
462system.cpu.dcache.overall_hits::total 168305303 # number of overall hits
463system.cpu.dcache.ReadReq_misses::cpu.data 854696 # number of ReadReq misses
464system.cpu.dcache.ReadReq_misses::total 854696 # number of ReadReq misses
465system.cpu.dcache.WriteReq_misses::cpu.data 700655 # number of WriteReq misses
466system.cpu.dcache.WriteReq_misses::total 700655 # number of WriteReq misses
467system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses
468system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses
469system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses
470system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses
471system.cpu.dcache.overall_misses::cpu.data 1555366 # number of overall misses
472system.cpu.dcache.overall_misses::total 1555366 # number of overall misses
473system.cpu.dcache.ReadReq_miss_latency::cpu.data 14025171732 # number of ReadReq miss cycles
474system.cpu.dcache.ReadReq_miss_latency::total 14025171732 # number of ReadReq miss cycles
475system.cpu.dcache.WriteReq_miss_latency::cpu.data 22048092000 # number of WriteReq miss cycles
476system.cpu.dcache.WriteReq_miss_latency::total 22048092000 # number of WriteReq miss cycles
477system.cpu.dcache.demand_miss_latency::cpu.data 36073263732 # number of demand (read+write) miss cycles
478system.cpu.dcache.demand_miss_latency::total 36073263732 # number of demand (read+write) miss cycles
479system.cpu.dcache.overall_miss_latency::cpu.data 36073263732 # number of overall miss cycles
480system.cpu.dcache.overall_miss_latency::total 36073263732 # number of overall miss cycles
481system.cpu.dcache.ReadReq_accesses::cpu.data 115618583 # number of ReadReq accesses(hits+misses)
482system.cpu.dcache.ReadReq_accesses::total 115618583 # number of ReadReq accesses(hits+misses)
483system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
484system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
485system.cpu.dcache.SoftPFReq_accesses::cpu.data 2780 # number of SoftPFReq accesses(hits+misses)
486system.cpu.dcache.SoftPFReq_accesses::total 2780 # number of SoftPFReq accesses(hits+misses)
487system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
488system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
489system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
490system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
491system.cpu.dcache.demand_accesses::cpu.data 169857889 # number of demand (read+write) accesses
492system.cpu.dcache.demand_accesses::total 169857889 # number of demand (read+write) accesses
493system.cpu.dcache.overall_accesses::cpu.data 169860669 # number of overall (read+write) accesses
494system.cpu.dcache.overall_accesses::total 169860669 # number of overall (read+write) accesses
495system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007392 # miss rate for ReadReq accesses
496system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses
497system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses
498system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses
499system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005396 # miss rate for SoftPFReq accesses
500system.cpu.dcache.SoftPFReq_miss_rate::total 0.005396 # miss rate for SoftPFReq accesses
501system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses
502system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses
503system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses
504system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses
505system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16409.544133 # average ReadReq miss latency
506system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.544133 # average ReadReq miss latency
507system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31467.829388 # average WriteReq miss latency
508system.cpu.dcache.WriteReq_avg_miss_latency::total 31467.829388 # average WriteReq miss latency
509system.cpu.dcache.demand_avg_miss_latency::cpu.data 23193.005136 # average overall miss latency
510system.cpu.dcache.demand_avg_miss_latency::total 23193.005136 # average overall miss latency
511system.cpu.dcache.overall_avg_miss_latency::cpu.data 23192.781462 # average overall miss latency
512system.cpu.dcache.overall_avg_miss_latency::total 23192.781462 # average overall miss latency
513system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
514system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
515system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
516system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
517system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
518system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
519system.cpu.dcache.fast_writes 0 # number of fast writes performed
520system.cpu.dcache.cache_copies 0 # number of cache copies performed
521system.cpu.dcache.writebacks::writebacks 1068547 # number of writebacks
522system.cpu.dcache.writebacks::total 1068547 # number of writebacks
523system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66929 # number of ReadReq MSHR hits
524system.cpu.dcache.ReadReq_mshr_hits::total 66929 # number of ReadReq MSHR hits
525system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344493 # number of WriteReq MSHR hits
526system.cpu.dcache.WriteReq_mshr_hits::total 344493 # number of WriteReq MSHR hits
527system.cpu.dcache.demand_mshr_hits::cpu.data 411422 # number of demand (read+write) MSHR hits
528system.cpu.dcache.demand_mshr_hits::total 411422 # number of demand (read+write) MSHR hits
529system.cpu.dcache.overall_mshr_hits::cpu.data 411422 # number of overall MSHR hits
530system.cpu.dcache.overall_mshr_hits::total 411422 # number of overall MSHR hits
531system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787767 # number of ReadReq MSHR misses
532system.cpu.dcache.ReadReq_mshr_misses::total 787767 # number of ReadReq MSHR misses
533system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356162 # number of WriteReq MSHR misses
534system.cpu.dcache.WriteReq_mshr_misses::total 356162 # number of WriteReq MSHR misses
535system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses
536system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses
537system.cpu.dcache.demand_mshr_misses::cpu.data 1143929 # number of demand (read+write) MSHR misses
538system.cpu.dcache.demand_mshr_misses::total 1143929 # number of demand (read+write) MSHR misses
539system.cpu.dcache.overall_mshr_misses::cpu.data 1143941 # number of overall MSHR misses
540system.cpu.dcache.overall_mshr_misses::total 1143941 # number of overall MSHR misses
541system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930909015 # number of ReadReq MSHR miss cycles
542system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930909015 # number of ReadReq MSHR miss cycles
543system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10976099750 # number of WriteReq MSHR miss cycles
544system.cpu.dcache.WriteReq_mshr_miss_latency::total 10976099750 # number of WriteReq MSHR miss cycles
545system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 986500 # number of SoftPFReq MSHR miss cycles
546system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 986500 # number of SoftPFReq MSHR miss cycles
547system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22907008765 # number of demand (read+write) MSHR miss cycles
548system.cpu.dcache.demand_mshr_miss_latency::total 22907008765 # number of demand (read+write) MSHR miss cycles
549system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22907995265 # number of overall MSHR miss cycles
550system.cpu.dcache.overall_mshr_miss_latency::total 22907995265 # number of overall MSHR miss cycles
551system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses
552system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses
553system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses
554system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses
555system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004317 # mshr miss rate for SoftPFReq accesses
556system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004317 # mshr miss rate for SoftPFReq accesses
557system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses
558system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses
559system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses
560system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses
561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15145.225701 # average ReadReq mshr miss latency
562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15145.225701 # average ReadReq mshr miss latency
563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30817.717078 # average WriteReq mshr miss latency
564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30817.717078 # average WriteReq mshr miss latency
565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 82208.333333 # average SoftPFReq mshr miss latency
566system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 82208.333333 # average SoftPFReq mshr miss latency
567system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20024.851861 # average overall mshr miss latency
568system.cpu.dcache.demand_avg_mshr_miss_latency::total 20024.851861 # average overall mshr miss latency
569system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.504169 # average overall mshr miss latency
570system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.504169 # average overall mshr miss latency
571system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
572system.cpu.icache.tags.replacements 17672 # number of replacements
573system.cpu.icache.tags.tagsinuse 1190.163457 # Cycle average of tags in use
574system.cpu.icache.tags.total_refs 200929857 # Total number of references to valid blocks.
575system.cpu.icache.tags.sampled_refs 19544 # Sample count of references to valid blocks.
576system.cpu.icache.tags.avg_refs 10280.897309 # Average number of references to valid blocks.
577system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
578system.cpu.icache.tags.occ_blocks::cpu.inst 1190.163457 # Average occupied blocks per requestor
579system.cpu.icache.tags.occ_percent::cpu.inst 0.581135 # Average percentage of cache occupancy
580system.cpu.icache.tags.occ_percent::total 0.581135 # Average percentage of cache occupancy
581system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id
582system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
583system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
584system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
585system.cpu.icache.tags.age_task_id_blocks_1024::3 306 # Occupied blocks per task id
586system.cpu.icache.tags.age_task_id_blocks_1024::4 1407 # Occupied blocks per task id
587system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id
588system.cpu.icache.tags.tag_accesses 401918346 # Number of tag accesses
589system.cpu.icache.tags.data_accesses 401918346 # Number of data accesses
590system.cpu.icache.ReadReq_hits::cpu.inst 200929857 # number of ReadReq hits
591system.cpu.icache.ReadReq_hits::total 200929857 # number of ReadReq hits
592system.cpu.icache.demand_hits::cpu.inst 200929857 # number of demand (read+write) hits
593system.cpu.icache.demand_hits::total 200929857 # number of demand (read+write) hits
594system.cpu.icache.overall_hits::cpu.inst 200929857 # number of overall hits
595system.cpu.icache.overall_hits::total 200929857 # number of overall hits
596system.cpu.icache.ReadReq_misses::cpu.inst 19544 # number of ReadReq misses
597system.cpu.icache.ReadReq_misses::total 19544 # number of ReadReq misses
598system.cpu.icache.demand_misses::cpu.inst 19544 # number of demand (read+write) misses
599system.cpu.icache.demand_misses::total 19544 # number of demand (read+write) misses
600system.cpu.icache.overall_misses::cpu.inst 19544 # number of overall misses
601system.cpu.icache.overall_misses::total 19544 # number of overall misses
602system.cpu.icache.ReadReq_miss_latency::cpu.inst 494847996 # number of ReadReq miss cycles
603system.cpu.icache.ReadReq_miss_latency::total 494847996 # number of ReadReq miss cycles
604system.cpu.icache.demand_miss_latency::cpu.inst 494847996 # number of demand (read+write) miss cycles
605system.cpu.icache.demand_miss_latency::total 494847996 # number of demand (read+write) miss cycles
606system.cpu.icache.overall_miss_latency::cpu.inst 494847996 # number of overall miss cycles
607system.cpu.icache.overall_miss_latency::total 494847996 # number of overall miss cycles
608system.cpu.icache.ReadReq_accesses::cpu.inst 200949401 # number of ReadReq accesses(hits+misses)
609system.cpu.icache.ReadReq_accesses::total 200949401 # number of ReadReq accesses(hits+misses)
610system.cpu.icache.demand_accesses::cpu.inst 200949401 # number of demand (read+write) accesses
611system.cpu.icache.demand_accesses::total 200949401 # number of demand (read+write) accesses
612system.cpu.icache.overall_accesses::cpu.inst 200949401 # number of overall (read+write) accesses
613system.cpu.icache.overall_accesses::total 200949401 # number of overall (read+write) accesses
614system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses
615system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses
616system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses
617system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses
618system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses
619system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses
620system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25319.688702 # average ReadReq miss latency
621system.cpu.icache.ReadReq_avg_miss_latency::total 25319.688702 # average ReadReq miss latency
622system.cpu.icache.demand_avg_miss_latency::cpu.inst 25319.688702 # average overall miss latency
623system.cpu.icache.demand_avg_miss_latency::total 25319.688702 # average overall miss latency
624system.cpu.icache.overall_avg_miss_latency::cpu.inst 25319.688702 # average overall miss latency
625system.cpu.icache.overall_avg_miss_latency::total 25319.688702 # average overall miss latency
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627system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
628system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
629system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
630system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
631system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
632system.cpu.icache.fast_writes 0 # number of fast writes performed
633system.cpu.icache.cache_copies 0 # number of cache copies performed
634system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19544 # number of ReadReq MSHR misses
635system.cpu.icache.ReadReq_mshr_misses::total 19544 # number of ReadReq MSHR misses
636system.cpu.icache.demand_mshr_misses::cpu.inst 19544 # number of demand (read+write) MSHR misses
637system.cpu.icache.demand_mshr_misses::total 19544 # number of demand (read+write) MSHR misses
638system.cpu.icache.overall_mshr_misses::cpu.inst 19544 # number of overall MSHR misses
639system.cpu.icache.overall_mshr_misses::total 19544 # number of overall MSHR misses
640system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 464144004 # number of ReadReq MSHR miss cycles
641system.cpu.icache.ReadReq_mshr_miss_latency::total 464144004 # number of ReadReq MSHR miss cycles
642system.cpu.icache.demand_mshr_miss_latency::cpu.inst 464144004 # number of demand (read+write) MSHR miss cycles
643system.cpu.icache.demand_mshr_miss_latency::total 464144004 # number of demand (read+write) MSHR miss cycles
644system.cpu.icache.overall_mshr_miss_latency::cpu.inst 464144004 # number of overall MSHR miss cycles
645system.cpu.icache.overall_mshr_miss_latency::total 464144004 # number of overall MSHR miss cycles
646system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses
647system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses
648system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses
649system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses
650system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses
651system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses
652system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23748.669873 # average ReadReq mshr miss latency
653system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23748.669873 # average ReadReq mshr miss latency
654system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23748.669873 # average overall mshr miss latency
655system.cpu.icache.demand_avg_mshr_miss_latency::total 23748.669873 # average overall mshr miss latency
656system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23748.669873 # average overall mshr miss latency
657system.cpu.icache.overall_avg_mshr_miss_latency::total 23748.669873 # average overall mshr miss latency
658system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
659system.cpu.l2cache.tags.replacements 111417 # number of replacements
660system.cpu.l2cache.tags.tagsinuse 27648.763503 # Cycle average of tags in use
661system.cpu.l2cache.tags.total_refs 1684506 # Total number of references to valid blocks.
662system.cpu.l2cache.tags.sampled_refs 142603 # Sample count of references to valid blocks.
663system.cpu.l2cache.tags.avg_refs 11.812557 # Average number of references to valid blocks.
664system.cpu.l2cache.tags.warmup_cycle 163802727000 # Cycle when the warmup percentage was hit.
665system.cpu.l2cache.tags.occ_blocks::writebacks 23521.944211 # Average occupied blocks per requestor
666system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.271354 # Average occupied blocks per requestor
667system.cpu.l2cache.tags.occ_blocks::cpu.data 3736.547938 # Average occupied blocks per requestor
668system.cpu.l2cache.tags.occ_percent::writebacks 0.717833 # Average percentage of cache occupancy
669system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011910 # Average percentage of cache occupancy
670system.cpu.l2cache.tags.occ_percent::cpu.data 0.114030 # Average percentage of cache occupancy
671system.cpu.l2cache.tags.occ_percent::total 0.843773 # Average percentage of cache occupancy
672system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id
673system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
674system.cpu.l2cache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id
675system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4943 # Occupied blocks per task id
676system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25856 # Occupied blocks per task id
677system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id
678system.cpu.l2cache.tags.tag_accesses 18355274 # Number of tag accesses
679system.cpu.l2cache.tags.data_accesses 18355274 # Number of data accesses
680system.cpu.l2cache.ReadReq_hits::cpu.inst 16070 # number of ReadReq hits
681system.cpu.l2cache.ReadReq_hits::cpu.data 747693 # number of ReadReq hits
682system.cpu.l2cache.ReadReq_hits::total 763763 # number of ReadReq hits
683system.cpu.l2cache.Writeback_hits::writebacks 1068547 # number of Writeback hits
684system.cpu.l2cache.Writeback_hits::total 1068547 # number of Writeback hits
685system.cpu.l2cache.ReadExReq_hits::cpu.data 255534 # number of ReadExReq hits
686system.cpu.l2cache.ReadExReq_hits::total 255534 # number of ReadExReq hits
687system.cpu.l2cache.demand_hits::cpu.inst 16070 # number of demand (read+write) hits
688system.cpu.l2cache.demand_hits::cpu.data 1003227 # number of demand (read+write) hits
689system.cpu.l2cache.demand_hits::total 1019297 # number of demand (read+write) hits
690system.cpu.l2cache.overall_hits::cpu.inst 16070 # number of overall hits
691system.cpu.l2cache.overall_hits::cpu.data 1003227 # number of overall hits
692system.cpu.l2cache.overall_hits::total 1019297 # number of overall hits
693system.cpu.l2cache.ReadReq_misses::cpu.inst 3474 # number of ReadReq misses
694system.cpu.l2cache.ReadReq_misses::cpu.data 39833 # number of ReadReq misses
695system.cpu.l2cache.ReadReq_misses::total 43307 # number of ReadReq misses
696system.cpu.l2cache.ReadExReq_misses::cpu.data 100881 # number of ReadExReq misses
697system.cpu.l2cache.ReadExReq_misses::total 100881 # number of ReadExReq misses
698system.cpu.l2cache.demand_misses::cpu.inst 3474 # number of demand (read+write) misses
699system.cpu.l2cache.demand_misses::cpu.data 140714 # number of demand (read+write) misses
700system.cpu.l2cache.demand_misses::total 144188 # number of demand (read+write) misses
701system.cpu.l2cache.overall_misses::cpu.inst 3474 # number of overall misses
702system.cpu.l2cache.overall_misses::cpu.data 140714 # number of overall misses
703system.cpu.l2cache.overall_misses::total 144188 # number of overall misses
704system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 275801500 # number of ReadReq miss cycles
705system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3286544500 # number of ReadReq miss cycles
706system.cpu.l2cache.ReadReq_miss_latency::total 3562346000 # number of ReadReq miss cycles
707system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7939327250 # number of ReadExReq miss cycles
708system.cpu.l2cache.ReadExReq_miss_latency::total 7939327250 # number of ReadExReq miss cycles
709system.cpu.l2cache.demand_miss_latency::cpu.inst 275801500 # number of demand (read+write) miss cycles
710system.cpu.l2cache.demand_miss_latency::cpu.data 11225871750 # number of demand (read+write) miss cycles
711system.cpu.l2cache.demand_miss_latency::total 11501673250 # number of demand (read+write) miss cycles
712system.cpu.l2cache.overall_miss_latency::cpu.inst 275801500 # number of overall miss cycles
713system.cpu.l2cache.overall_miss_latency::cpu.data 11225871750 # number of overall miss cycles
714system.cpu.l2cache.overall_miss_latency::total 11501673250 # number of overall miss cycles
715system.cpu.l2cache.ReadReq_accesses::cpu.inst 19544 # number of ReadReq accesses(hits+misses)
716system.cpu.l2cache.ReadReq_accesses::cpu.data 787526 # number of ReadReq accesses(hits+misses)
717system.cpu.l2cache.ReadReq_accesses::total 807070 # number of ReadReq accesses(hits+misses)
718system.cpu.l2cache.Writeback_accesses::writebacks 1068547 # number of Writeback accesses(hits+misses)
719system.cpu.l2cache.Writeback_accesses::total 1068547 # number of Writeback accesses(hits+misses)
720system.cpu.l2cache.ReadExReq_accesses::cpu.data 356415 # number of ReadExReq accesses(hits+misses)
721system.cpu.l2cache.ReadExReq_accesses::total 356415 # number of ReadExReq accesses(hits+misses)
722system.cpu.l2cache.demand_accesses::cpu.inst 19544 # number of demand (read+write) accesses
723system.cpu.l2cache.demand_accesses::cpu.data 1143941 # number of demand (read+write) accesses
724system.cpu.l2cache.demand_accesses::total 1163485 # number of demand (read+write) accesses
725system.cpu.l2cache.overall_accesses::cpu.inst 19544 # number of overall (read+write) accesses
726system.cpu.l2cache.overall_accesses::cpu.data 1143941 # number of overall (read+write) accesses
727system.cpu.l2cache.overall_accesses::total 1163485 # number of overall (read+write) accesses
728system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177753 # miss rate for ReadReq accesses
729system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050580 # miss rate for ReadReq accesses
730system.cpu.l2cache.ReadReq_miss_rate::total 0.053660 # miss rate for ReadReq accesses
731system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283044 # miss rate for ReadExReq accesses
732system.cpu.l2cache.ReadExReq_miss_rate::total 0.283044 # miss rate for ReadExReq accesses
733system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177753 # miss rate for demand accesses
734system.cpu.l2cache.demand_miss_rate::cpu.data 0.123008 # miss rate for demand accesses
735system.cpu.l2cache.demand_miss_rate::total 0.123928 # miss rate for demand accesses
736system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177753 # miss rate for overall accesses
737system.cpu.l2cache.overall_miss_rate::cpu.data 0.123008 # miss rate for overall accesses
738system.cpu.l2cache.overall_miss_rate::total 0.123928 # miss rate for overall accesses
739system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79390.184226 # average ReadReq miss latency
740system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82508.083750 # average ReadReq miss latency
741system.cpu.l2cache.ReadReq_avg_miss_latency::total 82257.972152 # average ReadReq miss latency
742system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78699.926151 # average ReadExReq miss latency
743system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78699.926151 # average ReadExReq miss latency
744system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79390.184226 # average overall miss latency
745system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79777.930767 # average overall miss latency
746system.cpu.l2cache.demand_avg_miss_latency::total 79768.588579 # average overall miss latency
747system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79390.184226 # average overall miss latency
748system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79777.930767 # average overall miss latency
749system.cpu.l2cache.overall_avg_miss_latency::total 79768.588579 # average overall miss latency
750system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
751system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
752system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
753system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
754system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
755system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
756system.cpu.l2cache.fast_writes 0 # number of fast writes performed
757system.cpu.l2cache.cache_copies 0 # number of cache copies performed
758system.cpu.l2cache.writebacks::writebacks 96566 # number of writebacks
759system.cpu.l2cache.writebacks::total 96566 # number of writebacks
760system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
761system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits
762system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
763system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
764system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits
765system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
766system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
767system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
768system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
769system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3472 # number of ReadReq MSHR misses
770system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39818 # number of ReadReq MSHR misses
771system.cpu.l2cache.ReadReq_mshr_misses::total 43290 # number of ReadReq MSHR misses
772system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100881 # number of ReadExReq MSHR misses
773system.cpu.l2cache.ReadExReq_mshr_misses::total 100881 # number of ReadExReq MSHR misses
774system.cpu.l2cache.demand_mshr_misses::cpu.inst 3472 # number of demand (read+write) MSHR misses
775system.cpu.l2cache.demand_mshr_misses::cpu.data 140699 # number of demand (read+write) MSHR misses
776system.cpu.l2cache.demand_mshr_misses::total 144171 # number of demand (read+write) MSHR misses
777system.cpu.l2cache.overall_mshr_misses::cpu.inst 3472 # number of overall MSHR misses
778system.cpu.l2cache.overall_mshr_misses::cpu.data 140699 # number of overall MSHR misses
779system.cpu.l2cache.overall_mshr_misses::total 144171 # number of overall MSHR misses
780system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 232222500 # number of ReadReq MSHR miss cycles
781system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2786510500 # number of ReadReq MSHR miss cycles
782system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3018733000 # number of ReadReq MSHR miss cycles
783system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6677694250 # number of ReadExReq MSHR miss cycles
784system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6677694250 # number of ReadExReq MSHR miss cycles
785system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 232222500 # number of demand (read+write) MSHR miss cycles
786system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9464204750 # number of demand (read+write) MSHR miss cycles
787system.cpu.l2cache.demand_mshr_miss_latency::total 9696427250 # number of demand (read+write) MSHR miss cycles
788system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 232222500 # number of overall MSHR miss cycles
789system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9464204750 # number of overall MSHR miss cycles
790system.cpu.l2cache.overall_mshr_miss_latency::total 9696427250 # number of overall MSHR miss cycles
791system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for ReadReq accesses
792system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050561 # mshr miss rate for ReadReq accesses
793system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053638 # mshr miss rate for ReadReq accesses
794system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283044 # mshr miss rate for ReadExReq accesses
795system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283044 # mshr miss rate for ReadExReq accesses
796system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for demand accesses
797system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122995 # mshr miss rate for demand accesses
798system.cpu.l2cache.demand_mshr_miss_rate::total 0.123913 # mshr miss rate for demand accesses
799system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177650 # mshr miss rate for overall accesses
800system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122995 # mshr miss rate for overall accesses
801system.cpu.l2cache.overall_mshr_miss_rate::total 0.123913 # mshr miss rate for overall accesses
802system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66884.360599 # average ReadReq mshr miss latency
803system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69981.176855 # average ReadReq mshr miss latency
804system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69732.802033 # average ReadReq mshr miss latency
805system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66193.775339 # average ReadExReq mshr miss latency
806system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66193.775339 # average ReadExReq mshr miss latency
807system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66884.360599 # average overall mshr miss latency
808system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67265.614894 # average overall mshr miss latency
809system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67256.433333 # average overall mshr miss latency
810system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66884.360599 # average overall mshr miss latency
811system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67265.614894 # average overall mshr miss latency
812system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67256.433333 # average overall mshr miss latency
813system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
814system.cpu.toL2Bus.trans_dist::ReadReq 807070 # Transaction distribution
815system.cpu.toL2Bus.trans_dist::ReadResp 807070 # Transaction distribution
816system.cpu.toL2Bus.trans_dist::Writeback 1068547 # Transaction distribution
817system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution
818system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution
819system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39088 # Packet count per connected master and slave (bytes)
820system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356429 # Packet count per connected master and slave (bytes)
821system.cpu.toL2Bus.pkt_count::total 3395517 # Packet count per connected master and slave (bytes)
822system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250816 # Cumulative packet size per connected master and slave (bytes)
823system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141599232 # Cumulative packet size per connected master and slave (bytes)
824system.cpu.toL2Bus.pkt_size::total 142850048 # Cumulative packet size per connected master and slave (bytes)
825system.cpu.toL2Bus.snoops 0 # Total snoops (count)
826system.cpu.toL2Bus.snoop_fanout::samples 2232032 # Request fanout histogram

827system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram

827system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram

828system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
829system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
830system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

831system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
832system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
833system.cpu.toL2Bus.snoop_fanout::3 2232032 100.00% 100.00% # Request fanout histogram
834system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram

831system.cpu.toL2Bus.snoop_fanout::1 2232032 100.00% 100.00% # Request fanout histogram
832system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram

835system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

833system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

836system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
837system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

834system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
835system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram