1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.365317 # Number of seconds simulated
4sim_ticks 365317233000 # Number of ticks simulated
5final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 157262 # Simulator instruction rate (inst/s)
8host_op_rate 170335 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 113407877 # Simulator tick rate (ticks/s)
10host_mem_usage 304680 # Number of bytes of host memory used
11host_seconds 3221.27 # Real time elapsed on the host
12sim_insts 506582155 # Number of instructions simulated
13sim_ops 548695378 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 222144 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9003904 # Number of bytes read from this memory
18system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory
22system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 3471 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 140686 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 608085 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 24646809 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 608085 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 24646809 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 144157 # Number of read requests accepted
40system.physmem.writeReqs 96561 # Number of write requests accepted
41system.physmem.readBursts 144157 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 96561 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 9219904 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue
45system.physmem.bytesWritten 6178688 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 9226048 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 6179904 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 9347 # Per bank write bursts
52system.physmem.perBankRdBursts::1 8970 # Per bank write bursts
53system.physmem.perBankRdBursts::2 8998 # Per bank write bursts
54system.physmem.perBankRdBursts::3 8695 # Per bank write bursts
55system.physmem.perBankRdBursts::4 9455 # Per bank write bursts
56system.physmem.perBankRdBursts::5 9342 # Per bank write bursts
57system.physmem.perBankRdBursts::6 8947 # Per bank write bursts
58system.physmem.perBankRdBursts::7 8101 # Per bank write bursts
59system.physmem.perBankRdBursts::8 8578 # Per bank write bursts
60system.physmem.perBankRdBursts::9 8679 # Per bank write bursts
61system.physmem.perBankRdBursts::10 8774 # Per bank write bursts
62system.physmem.perBankRdBursts::11 9477 # Per bank write bursts
63system.physmem.perBankRdBursts::12 9374 # Per bank write bursts
64system.physmem.perBankRdBursts::13 9525 # Per bank write bursts
65system.physmem.perBankRdBursts::14 8712 # Per bank write bursts
66system.physmem.perBankRdBursts::15 9087 # Per bank write bursts
67system.physmem.perBankWrBursts::0 6196 # Per bank write bursts
68system.physmem.perBankWrBursts::1 6092 # Per bank write bursts
69system.physmem.perBankWrBursts::2 6006 # Per bank write bursts
70system.physmem.perBankWrBursts::3 5813 # Per bank write bursts
71system.physmem.perBankWrBursts::4 6163 # Per bank write bursts
72system.physmem.perBankWrBursts::5 6172 # Per bank write bursts
73system.physmem.perBankWrBursts::6 6014 # Per bank write bursts
74system.physmem.perBankWrBursts::7 5493 # Per bank write bursts
75system.physmem.perBankWrBursts::8 5728 # Per bank write bursts
76system.physmem.perBankWrBursts::9 5823 # Per bank write bursts
77system.physmem.perBankWrBursts::10 5962 # Per bank write bursts
78system.physmem.perBankWrBursts::11 6445 # Per bank write bursts
79system.physmem.perBankWrBursts::12 6308 # Per bank write bursts
80system.physmem.perBankWrBursts::13 6282 # Per bank write bursts
81system.physmem.perBankWrBursts::14 5997 # Per bank write bursts
82system.physmem.perBankWrBursts::15 6048 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 365317203500 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 144157 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 96561 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see

--- 28 unchanged lines hidden (view full) ---

139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 2939 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 5543 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 5664 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 5672 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 5680 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 5680 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 5691 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 5692 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 5666 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 5669 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 5692 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 5677 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 5643 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 5596 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196system.physmem.bytesPerActivate::samples 65080 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::mean 236.601352 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::gmean 156.588709 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::stdev 242.751381 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::0-127 24737 38.01% 38.01% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::128-255 18138 27.87% 65.88% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::256-383 6930 10.65% 76.53% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::384-511 7871 12.09% 88.62% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::512-639 2125 3.27% 91.89% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::640-767 1134 1.74% 93.63% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::768-895 708 1.09% 94.72% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::896-1023 644 0.99% 95.71% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1024-1151 2793 4.29% 100.00% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::total 65080 # Bytes accessed per row activation
210system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::mean 25.854092 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::stdev 382.114973 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes
217system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads
218system.physmem.wrPerTurnAround::mean 17.326274 # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::gmean 17.230410 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::stdev 2.286782 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::16-17 2628 47.16% 47.16% # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::18-19 2789 50.05% 97.22% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::20-21 53 0.95% 98.17% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::22-23 30 0.54% 98.71% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::24-25 23 0.41% 99.12% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::26-27 9 0.16% 99.28% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::28-29 9 0.16% 99.44% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::30-31 6 0.11% 99.55% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::32-33 7 0.13% 99.68% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::34-35 3 0.05% 99.73% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::36-37 1 0.02% 99.75% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::38-39 4 0.07% 99.82% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::42-43 2 0.04% 99.87% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::44-45 2 0.04% 99.91% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::46-47 2 0.04% 99.95% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::54-55 1 0.02% 99.96% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads
241system.physmem.totQLat 1534207250 # Total ticks spent queuing
242system.physmem.totMemAccLat 4235351000 # Total ticks spent from burst creation until serviced by the DRAM
243system.physmem.totBusLat 720305000 # Total ticks spent in databus transfers
244system.physmem.avgQLat 10649.71 # Average queueing delay per DRAM burst
245system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
246system.physmem.avgMemAccLat 29399.71 # Average memory access latency per DRAM burst
247system.physmem.avgRdBW 25.24 # Average DRAM read bandwidth in MiByte/s
248system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s
249system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s
250system.physmem.avgWrBWSys 16.92 # Average system write bandwidth in MiByte/s
251system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
252system.physmem.busUtil 0.33 # Data bus utilization in percentage
253system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
254system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
255system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
256system.physmem.avgWrQLen 20.29 # Average write queue length when enqueuing
257system.physmem.readRowHits 111019 # Number of row buffer hits during reads
258system.physmem.writeRowHits 64498 # Number of row buffer hits during writes
259system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads
260system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes
261system.physmem.avgGap 1517614.82 # Average gap between requests
262system.physmem.pageHitRate 72.94 # Row buffer hit rate, read and write combined
263system.physmem_0.actEnergy 247892400 # Energy for activate commands per rank (pJ)
264system.physmem_0.preEnergy 135258750 # Energy for precharge commands per rank (pJ)
265system.physmem_0.readEnergy 560445600 # Energy for read commands per rank (pJ)
266system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ)
267system.physmem_0.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ)
268system.physmem_0.actBackEnergy 47138982615 # Energy for active background per rank (pJ)
269system.physmem_0.preBackEnergy 177839337750 # Energy for precharge background per rank (pJ)
270system.physmem_0.totalEnergy 250093102155 # Total energy per rank (pJ)
271system.physmem_0.averagePower 684.594758 # Core power per rank (mW)
272system.physmem_0.memoryStateTime::IDLE 295545266000 # Time in different power states
273system.physmem_0.memoryStateTime::REF 12198680000 # Time in different power states
274system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
275system.physmem_0.memoryStateTime::ACT 57571800000 # Time in different power states
276system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
277system.physmem_1.actEnergy 244014120 # Energy for activate commands per rank (pJ)
278system.physmem_1.preEnergy 133142625 # Energy for precharge commands per rank (pJ)
279system.physmem_1.readEnergy 563058600 # Energy for read commands per rank (pJ)
280system.physmem_1.writeEnergy 314817840 # Energy for write commands per rank (pJ)
281system.physmem_1.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ)
282system.physmem_1.actBackEnergy 46734210225 # Energy for active background per rank (pJ)
283system.physmem_1.preBackEnergy 178194401250 # Energy for precharge background per rank (pJ)
284system.physmem_1.totalEnergy 250044262740 # Total energy per rank (pJ)
285system.physmem_1.averagePower 684.461067 # Core power per rank (mW)
286system.physmem_1.memoryStateTime::IDLE 296138902500 # Time in different power states
287system.physmem_1.memoryStateTime::REF 12198680000 # Time in different power states
288system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
289system.physmem_1.memoryStateTime::ACT 56977968750 # Time in different power states
290system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
291system.cpu.branchPred.lookups 132578917 # Number of BP lookups
292system.cpu.branchPred.condPredicted 98507789 # Number of conditional branches predicted
293system.cpu.branchPred.condIncorrect 6555100 # Number of conditional branches incorrect
294system.cpu.branchPred.BTBLookups 69037584 # Number of BTB lookups
295system.cpu.branchPred.BTBHits 64855119 # Number of BTB hits
296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
297system.cpu.branchPred.BTBHitPct 93.941756 # BTB Hit Percentage
298system.cpu.branchPred.usedRAS 10014942 # Number of times the RAS was used to get a target.
299system.cpu.branchPred.RASInCorrect 17500 # Number of incorrect RAS predictions.
300system.cpu_clk_domain.clock 500 # Clock period in ticks
301system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

410system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
411system.cpu.itb.read_accesses 0 # DTB read accesses
412system.cpu.itb.write_accesses 0 # DTB write accesses
413system.cpu.itb.inst_accesses 0 # ITB inst accesses
414system.cpu.itb.hits 0 # DTB hits
415system.cpu.itb.misses 0 # DTB misses
416system.cpu.itb.accesses 0 # DTB accesses
417system.cpu.workload.num_syscalls 548 # Number of system calls
418system.cpu.numCycles 730634466 # number of cpu cycles simulated
419system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
420system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
421system.cpu.committedInsts 506582155 # Number of instructions committed
422system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed
423system.cpu.discardedOps 13461155 # Number of ops (including micro ops) which were discarded before commit
424system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
425system.cpu.cpi 1.442282 # CPI: cycles per instruction
426system.cpu.ipc 0.693346 # IPC: instructions per cycle
427system.cpu.tickCycles 695780172 # Number of cycles that the object actually ticked
428system.cpu.idleCycles 34854294 # Total number of cycles that the object has spent stopped
429system.cpu.dcache.tags.replacements 1139812 # number of replacements
430system.cpu.dcache.tags.tagsinuse 4071.074819 # Cycle average of tags in use
431system.cpu.dcache.tags.total_refs 171281876 # Total number of references to valid blocks.
432system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks.
433system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks.
434system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit.
435system.cpu.dcache.tags.occ_blocks::cpu.data 4071.074819 # Average occupied blocks per requestor
436system.cpu.dcache.tags.occ_percent::cpu.data 0.993915 # Average percentage of cache occupancy
437system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy
438system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
439system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
440system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
441system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id
442system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 # Occupied blocks per task id
443system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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445system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses
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447system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits
448system.cpu.dcache.WriteReq_hits::cpu.data 53538710 # number of WriteReq hits
449system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits
450system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
451system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
452system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
453system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
454system.cpu.dcache.demand_hits::cpu.data 168304794 # number of demand (read+write) hits
455system.cpu.dcache.demand_hits::total 168304794 # number of demand (read+write) hits
456system.cpu.dcache.overall_hits::cpu.data 168304794 # number of overall hits
457system.cpu.dcache.overall_hits::total 168304794 # number of overall hits
458system.cpu.dcache.ReadReq_misses::cpu.data 854755 # number of ReadReq misses
459system.cpu.dcache.ReadReq_misses::total 854755 # number of ReadReq misses
460system.cpu.dcache.WriteReq_misses::cpu.data 700596 # number of WriteReq misses
461system.cpu.dcache.WriteReq_misses::total 700596 # number of WriteReq misses
462system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses
463system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses
464system.cpu.dcache.overall_misses::cpu.data 1555351 # number of overall misses
465system.cpu.dcache.overall_misses::total 1555351 # number of overall misses
466system.cpu.dcache.ReadReq_miss_latency::cpu.data 13707430482 # number of ReadReq miss cycles
467system.cpu.dcache.ReadReq_miss_latency::total 13707430482 # number of ReadReq miss cycles
468system.cpu.dcache.WriteReq_miss_latency::cpu.data 20521575250 # number of WriteReq miss cycles
469system.cpu.dcache.WriteReq_miss_latency::total 20521575250 # number of WriteReq miss cycles
470system.cpu.dcache.demand_miss_latency::cpu.data 34229005732 # number of demand (read+write) miss cycles
471system.cpu.dcache.demand_miss_latency::total 34229005732 # number of demand (read+write) miss cycles
472system.cpu.dcache.overall_miss_latency::cpu.data 34229005732 # number of overall miss cycles
473system.cpu.dcache.overall_miss_latency::total 34229005732 # number of overall miss cycles
474system.cpu.dcache.ReadReq_accesses::cpu.data 115620839 # number of ReadReq accesses(hits+misses)
475system.cpu.dcache.ReadReq_accesses::total 115620839 # number of ReadReq accesses(hits+misses)
476system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
477system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
478system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
479system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
480system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
481system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
482system.cpu.dcache.demand_accesses::cpu.data 169860145 # number of demand (read+write) accesses
483system.cpu.dcache.demand_accesses::total 169860145 # number of demand (read+write) accesses
484system.cpu.dcache.overall_accesses::cpu.data 169860145 # number of overall (read+write) accesses
485system.cpu.dcache.overall_accesses::total 169860145 # number of overall (read+write) accesses
486system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses
487system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses
488system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses
489system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses
490system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses
491system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses
492system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses
493system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses
494system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16036.677740 # average ReadReq miss latency
495system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740 # average ReadReq miss latency
496system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29291.596369 # average WriteReq miss latency
497system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369 # average WriteReq miss latency
498system.cpu.dcache.demand_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency
499system.cpu.dcache.demand_avg_miss_latency::total 22007.254782 # average overall miss latency
500system.cpu.dcache.overall_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency
501system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency
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503system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
504system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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506system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
507system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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509system.cpu.dcache.cache_copies 0 # number of cache copies performed
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511system.cpu.dcache.writebacks::total 1068525 # number of writebacks
512system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66991 # number of ReadReq MSHR hits
513system.cpu.dcache.ReadReq_mshr_hits::total 66991 # number of ReadReq MSHR hits
514system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344452 # number of WriteReq MSHR hits
515system.cpu.dcache.WriteReq_mshr_hits::total 344452 # number of WriteReq MSHR hits
516system.cpu.dcache.demand_mshr_hits::cpu.data 411443 # number of demand (read+write) MSHR hits
517system.cpu.dcache.demand_mshr_hits::total 411443 # number of demand (read+write) MSHR hits
518system.cpu.dcache.overall_mshr_hits::cpu.data 411443 # number of overall MSHR hits
519system.cpu.dcache.overall_mshr_hits::total 411443 # number of overall MSHR hits
520system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787764 # number of ReadReq MSHR misses
521system.cpu.dcache.ReadReq_mshr_misses::total 787764 # number of ReadReq MSHR misses
522system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356144 # number of WriteReq MSHR misses
523system.cpu.dcache.WriteReq_mshr_misses::total 356144 # number of WriteReq MSHR misses
524system.cpu.dcache.demand_mshr_misses::cpu.data 1143908 # number of demand (read+write) MSHR misses
525system.cpu.dcache.demand_mshr_misses::total 1143908 # number of demand (read+write) MSHR misses
526system.cpu.dcache.overall_mshr_misses::cpu.data 1143908 # number of overall MSHR misses
527system.cpu.dcache.overall_mshr_misses::total 1143908 # number of overall MSHR misses
528system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11252029015 # number of ReadReq MSHR miss cycles
529system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252029015 # number of ReadReq MSHR miss cycles
530system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10073374750 # number of WriteReq MSHR miss cycles
531system.cpu.dcache.WriteReq_mshr_miss_latency::total 10073374750 # number of WriteReq MSHR miss cycles
532system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21325403765 # number of demand (read+write) MSHR miss cycles
533system.cpu.dcache.demand_mshr_miss_latency::total 21325403765 # number of demand (read+write) MSHR miss cycles
534system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21325403765 # number of overall MSHR miss cycles
535system.cpu.dcache.overall_mshr_miss_latency::total 21325403765 # number of overall MSHR miss cycles
536system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses
537system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses
538system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses
539system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses
540system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for demand accesses
541system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses
542system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for overall accesses
543system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses
544system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14283.502439 # average ReadReq mshr miss latency
545system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14283.502439 # average ReadReq mshr miss latency
546system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28284.555545 # average WriteReq mshr miss latency
547system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28284.555545 # average WriteReq mshr miss latency
548system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency
549system.cpu.dcache.demand_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency
550system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency
551system.cpu.dcache.overall_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency
552system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
553system.cpu.icache.tags.replacements 17690 # number of replacements
554system.cpu.icache.tags.tagsinuse 1190.635807 # Cycle average of tags in use
555system.cpu.icache.tags.total_refs 200942292 # Total number of references to valid blocks.
556system.cpu.icache.tags.sampled_refs 19563 # Sample count of references to valid blocks.
557system.cpu.icache.tags.avg_refs 10271.547922 # Average number of references to valid blocks.
558system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
559system.cpu.icache.tags.occ_blocks::cpu.inst 1190.635807 # Average occupied blocks per requestor
560system.cpu.icache.tags.occ_percent::cpu.inst 0.581365 # Average percentage of cache occupancy
561system.cpu.icache.tags.occ_percent::total 0.581365 # Average percentage of cache occupancy
562system.cpu.icache.tags.occ_task_id_blocks::1024 1873 # Occupied blocks per task id
563system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
564system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
565system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
566system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id
567system.cpu.icache.tags.age_task_id_blocks_1024::4 1406 # Occupied blocks per task id
568system.cpu.icache.tags.occ_task_id_percent::1024 0.914551 # Percentage of cache occupancy per task id
569system.cpu.icache.tags.tag_accesses 401943273 # Number of tag accesses
570system.cpu.icache.tags.data_accesses 401943273 # Number of data accesses
571system.cpu.icache.ReadReq_hits::cpu.inst 200942292 # number of ReadReq hits
572system.cpu.icache.ReadReq_hits::total 200942292 # number of ReadReq hits
573system.cpu.icache.demand_hits::cpu.inst 200942292 # number of demand (read+write) hits
574system.cpu.icache.demand_hits::total 200942292 # number of demand (read+write) hits
575system.cpu.icache.overall_hits::cpu.inst 200942292 # number of overall hits
576system.cpu.icache.overall_hits::total 200942292 # number of overall hits
577system.cpu.icache.ReadReq_misses::cpu.inst 19563 # number of ReadReq misses
578system.cpu.icache.ReadReq_misses::total 19563 # number of ReadReq misses
579system.cpu.icache.demand_misses::cpu.inst 19563 # number of demand (read+write) misses
580system.cpu.icache.demand_misses::total 19563 # number of demand (read+write) misses
581system.cpu.icache.overall_misses::cpu.inst 19563 # number of overall misses
582system.cpu.icache.overall_misses::total 19563 # number of overall misses
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584system.cpu.icache.ReadReq_miss_latency::total 469537995 # number of ReadReq miss cycles
585system.cpu.icache.demand_miss_latency::cpu.inst 469537995 # number of demand (read+write) miss cycles
586system.cpu.icache.demand_miss_latency::total 469537995 # number of demand (read+write) miss cycles
587system.cpu.icache.overall_miss_latency::cpu.inst 469537995 # number of overall miss cycles
588system.cpu.icache.overall_miss_latency::total 469537995 # number of overall miss cycles
589system.cpu.icache.ReadReq_accesses::cpu.inst 200961855 # number of ReadReq accesses(hits+misses)
590system.cpu.icache.ReadReq_accesses::total 200961855 # number of ReadReq accesses(hits+misses)
591system.cpu.icache.demand_accesses::cpu.inst 200961855 # number of demand (read+write) accesses
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596system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses
597system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses
598system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses
599system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses
600system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses
601system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24001.328784 # average ReadReq miss latency
602system.cpu.icache.ReadReq_avg_miss_latency::total 24001.328784 # average ReadReq miss latency
603system.cpu.icache.demand_avg_miss_latency::cpu.inst 24001.328784 # average overall miss latency
604system.cpu.icache.demand_avg_miss_latency::total 24001.328784 # average overall miss latency
605system.cpu.icache.overall_avg_miss_latency::cpu.inst 24001.328784 # average overall miss latency
606system.cpu.icache.overall_avg_miss_latency::total 24001.328784 # average overall miss latency
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612system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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617system.cpu.icache.demand_mshr_misses::cpu.inst 19563 # number of demand (read+write) MSHR misses
618system.cpu.icache.demand_mshr_misses::total 19563 # number of demand (read+write) MSHR misses
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626system.cpu.icache.overall_mshr_miss_latency::total 429024005 # number of overall MSHR miss cycles
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628system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses
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632system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses
633system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21930.379032 # average ReadReq mshr miss latency
634system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21930.379032 # average ReadReq mshr miss latency
635system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21930.379032 # average overall mshr miss latency
636system.cpu.icache.demand_avg_mshr_miss_latency::total 21930.379032 # average overall mshr miss latency
637system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21930.379032 # average overall mshr miss latency
638system.cpu.icache.overall_avg_mshr_miss_latency::total 21930.379032 # average overall mshr miss latency
639system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
640system.cpu.l2cache.tags.replacements 111403 # number of replacements
641system.cpu.l2cache.tags.tagsinuse 27648.458293 # Cycle average of tags in use
642system.cpu.l2cache.tags.total_refs 1684717 # Total number of references to valid blocks.
643system.cpu.l2cache.tags.sampled_refs 142590 # Sample count of references to valid blocks.
644system.cpu.l2cache.tags.avg_refs 11.815113 # Average number of references to valid blocks.
645system.cpu.l2cache.tags.warmup_cycle 163177408500 # Cycle when the warmup percentage was hit.
646system.cpu.l2cache.tags.occ_blocks::writebacks 23523.224801 # Average occupied blocks per requestor
647system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.561382 # Average occupied blocks per requestor
648system.cpu.l2cache.tags.occ_blocks::cpu.data 3735.672111 # Average occupied blocks per requestor
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653system.cpu.l2cache.tags.occ_task_id_blocks::1024 31187 # Occupied blocks per task id
654system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
655system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id
656system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4940 # Occupied blocks per task id
657system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25856 # Occupied blocks per task id
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665system.cpu.l2cache.Writeback_hits::total 1068525 # number of Writeback hits
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667system.cpu.l2cache.ReadExReq_hits::total 255530 # number of ReadExReq hits
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673system.cpu.l2cache.overall_hits::total 1019297 # number of overall hits
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675system.cpu.l2cache.ReadReq_misses::cpu.data 39833 # number of ReadReq misses
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678system.cpu.l2cache.ReadExReq_misses::total 100868 # number of ReadExReq misses
679system.cpu.l2cache.demand_misses::cpu.inst 3473 # number of demand (read+write) misses
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681system.cpu.l2cache.demand_misses::total 144174 # number of demand (read+write) misses
682system.cpu.l2cache.overall_misses::cpu.inst 3473 # number of overall misses
683system.cpu.l2cache.overall_misses::cpu.data 140701 # number of overall misses
684system.cpu.l2cache.overall_misses::total 144174 # number of overall misses
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686system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2980751000 # number of ReadReq miss cycles
687system.cpu.l2cache.ReadReq_miss_latency::total 3229271000 # number of ReadReq miss cycles
688system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7164307250 # number of ReadExReq miss cycles
689system.cpu.l2cache.ReadExReq_miss_latency::total 7164307250 # number of ReadExReq miss cycles
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691system.cpu.l2cache.demand_miss_latency::cpu.data 10145058250 # number of demand (read+write) miss cycles
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697system.cpu.l2cache.ReadReq_accesses::cpu.data 787510 # number of ReadReq accesses(hits+misses)
698system.cpu.l2cache.ReadReq_accesses::total 807073 # number of ReadReq accesses(hits+misses)
699system.cpu.l2cache.Writeback_accesses::writebacks 1068525 # number of Writeback accesses(hits+misses)
700system.cpu.l2cache.Writeback_accesses::total 1068525 # number of Writeback accesses(hits+misses)
701system.cpu.l2cache.ReadExReq_accesses::cpu.data 356398 # number of ReadExReq accesses(hits+misses)
702system.cpu.l2cache.ReadExReq_accesses::total 356398 # number of ReadExReq accesses(hits+misses)
703system.cpu.l2cache.demand_accesses::cpu.inst 19563 # number of demand (read+write) accesses
704system.cpu.l2cache.demand_accesses::cpu.data 1143908 # number of demand (read+write) accesses
705system.cpu.l2cache.demand_accesses::total 1163471 # number of demand (read+write) accesses
706system.cpu.l2cache.overall_accesses::cpu.inst 19563 # number of overall (read+write) accesses
707system.cpu.l2cache.overall_accesses::cpu.data 1143908 # number of overall (read+write) accesses
708system.cpu.l2cache.overall_accesses::total 1163471 # number of overall (read+write) accesses
709system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177529 # miss rate for ReadReq accesses
710system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050581 # miss rate for ReadReq accesses
711system.cpu.l2cache.ReadReq_miss_rate::total 0.053658 # miss rate for ReadReq accesses
712system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283021 # miss rate for ReadExReq accesses
713system.cpu.l2cache.ReadExReq_miss_rate::total 0.283021 # miss rate for ReadExReq accesses
714system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177529 # miss rate for demand accesses
715system.cpu.l2cache.demand_miss_rate::cpu.data 0.123000 # miss rate for demand accesses
716system.cpu.l2cache.demand_miss_rate::total 0.123917 # miss rate for demand accesses
717system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177529 # miss rate for overall accesses
718system.cpu.l2cache.overall_miss_rate::cpu.data 0.123000 # miss rate for overall accesses
719system.cpu.l2cache.overall_miss_rate::total 0.123917 # miss rate for overall accesses
720system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71557.731068 # average ReadReq miss latency
721system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74831.195240 # average ReadReq miss latency
722system.cpu.l2cache.ReadReq_avg_miss_latency::total 74568.674087 # average ReadReq miss latency
723system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71026.561942 # average ReadExReq miss latency
724system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71026.561942 # average ReadExReq miss latency
725system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71557.731068 # average overall miss latency
726system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72103.668417 # average overall miss latency
727system.cpu.l2cache.demand_avg_miss_latency::total 72090.517361 # average overall miss latency
728system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71557.731068 # average overall miss latency
729system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72103.668417 # average overall miss latency
730system.cpu.l2cache.overall_avg_miss_latency::total 72090.517361 # average overall miss latency
731system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
732system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
733system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
734system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
735system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
736system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
737system.cpu.l2cache.fast_writes 0 # number of fast writes performed
738system.cpu.l2cache.cache_copies 0 # number of cache copies performed
739system.cpu.l2cache.writebacks::writebacks 96561 # number of writebacks
740system.cpu.l2cache.writebacks::total 96561 # number of writebacks
741system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
742system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits
743system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
744system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
745system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits
746system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
747system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
748system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
749system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
750system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3471 # number of ReadReq MSHR misses
751system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39818 # number of ReadReq MSHR misses
752system.cpu.l2cache.ReadReq_mshr_misses::total 43289 # number of ReadReq MSHR misses
753system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100868 # number of ReadExReq MSHR misses
754system.cpu.l2cache.ReadExReq_mshr_misses::total 100868 # number of ReadExReq MSHR misses
755system.cpu.l2cache.demand_mshr_misses::cpu.inst 3471 # number of demand (read+write) MSHR misses
756system.cpu.l2cache.demand_mshr_misses::cpu.data 140686 # number of demand (read+write) MSHR misses
757system.cpu.l2cache.demand_mshr_misses::total 144157 # number of demand (read+write) MSHR misses
758system.cpu.l2cache.overall_mshr_misses::cpu.inst 3471 # number of overall MSHR misses
759system.cpu.l2cache.overall_mshr_misses::cpu.data 140686 # number of overall MSHR misses
760system.cpu.l2cache.overall_mshr_misses::total 144157 # number of overall MSHR misses
761system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 204743500 # number of ReadReq MSHR miss cycles
762system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2475547000 # number of ReadReq MSHR miss cycles
763system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2680290500 # number of ReadReq MSHR miss cycles
764system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5883442250 # number of ReadExReq MSHR miss cycles
765system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5883442250 # number of ReadExReq MSHR miss cycles
766system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204743500 # number of demand (read+write) MSHR miss cycles
767system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8358989250 # number of demand (read+write) MSHR miss cycles
768system.cpu.l2cache.demand_mshr_miss_latency::total 8563732750 # number of demand (read+write) MSHR miss cycles
769system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204743500 # number of overall MSHR miss cycles
770system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8358989250 # number of overall MSHR miss cycles
771system.cpu.l2cache.overall_mshr_miss_latency::total 8563732750 # number of overall MSHR miss cycles
772system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for ReadReq accesses
773system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050562 # mshr miss rate for ReadReq accesses
774system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053637 # mshr miss rate for ReadReq accesses
775system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283021 # mshr miss rate for ReadExReq accesses
776system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283021 # mshr miss rate for ReadExReq accesses
777system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for demand accesses
778system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for demand accesses
779system.cpu.l2cache.demand_mshr_miss_rate::total 0.123903 # mshr miss rate for demand accesses
780system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for overall accesses
781system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for overall accesses
782system.cpu.l2cache.overall_mshr_miss_rate::total 0.123903 # mshr miss rate for overall accesses
783system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58986.891386 # average ReadReq mshr miss latency
784system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62171.555578 # average ReadReq mshr miss latency
785system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730 # average ReadReq mshr miss latency
786system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58328.134294 # average ReadExReq mshr miss latency
787system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency
788system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency
789system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency
790system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency
791system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency
792system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency
793system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency
794system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
795system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution
796system.cpu.toL2Bus.trans_dist::ReadResp 807073 # Transaction distribution
797system.cpu.toL2Bus.trans_dist::Writeback 1068525 # Transaction distribution
798system.cpu.toL2Bus.trans_dist::ReadExReq 356398 # Transaction distribution
799system.cpu.toL2Bus.trans_dist::ReadExResp 356398 # Transaction distribution
800system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39126 # Packet count per connected master and slave (bytes)
801system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356341 # Packet count per connected master and slave (bytes)
802system.cpu.toL2Bus.pkt_count::total 3395467 # Packet count per connected master and slave (bytes)
803system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252032 # Cumulative packet size per connected master and slave (bytes)
804system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141595712 # Cumulative packet size per connected master and slave (bytes)
805system.cpu.toL2Bus.pkt_size::total 142847744 # Cumulative packet size per connected master and slave (bytes)
806system.cpu.toL2Bus.snoops 0 # Total snoops (count)
807system.cpu.toL2Bus.snoop_fanout::samples 2231996 # Request fanout histogram
808system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
809system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
810system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
811system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
812system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
813system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
814system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
815system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
816system.cpu.toL2Bus.snoop_fanout::5 2231996 100.00% 100.00% # Request fanout histogram
817system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
818system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
819system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
820system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
821system.cpu.toL2Bus.snoop_fanout::total 2231996 # Request fanout histogram
822system.cpu.toL2Bus.reqLayer0.occupancy 2184523000 # Layer occupancy (ticks)
823system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
824system.cpu.toL2Bus.respLayer0.occupancy 30038495 # Layer occupancy (ticks)
825system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
826system.cpu.toL2Bus.respLayer1.occupancy 1744651235 # Layer occupancy (ticks)
827system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
828system.membus.trans_dist::ReadReq 43289 # Transaction distribution
829system.membus.trans_dist::ReadResp 43289 # Transaction distribution
830system.membus.trans_dist::Writeback 96561 # Transaction distribution
831system.membus.trans_dist::ReadExReq 100868 # Transaction distribution
832system.membus.trans_dist::ReadExResp 100868 # Transaction distribution
833system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384875 # Packet count per connected master and slave (bytes)
834system.membus.pkt_count::total 384875 # Packet count per connected master and slave (bytes)
835system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15405952 # Cumulative packet size per connected master and slave (bytes)
836system.membus.pkt_size::total 15405952 # Cumulative packet size per connected master and slave (bytes)
837system.membus.snoops 0 # Total snoops (count)
838system.membus.snoop_fanout::samples 240718 # Request fanout histogram
839system.membus.snoop_fanout::mean 0 # Request fanout histogram
840system.membus.snoop_fanout::stdev 0 # Request fanout histogram
841system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
842system.membus.snoop_fanout::0 240718 100.00% 100.00% # Request fanout histogram
843system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
844system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
845system.membus.snoop_fanout::min_value 0 # Request fanout histogram
846system.membus.snoop_fanout::max_value 0 # Request fanout histogram
847system.membus.snoop_fanout::total 240718 # Request fanout histogram
848system.membus.reqLayer0.occupancy 1081999000 # Layer occupancy (ticks)
849system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
850system.membus.respLayer1.occupancy 1366864750 # Layer occupancy (ticks)
851system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
852
853---------- End Simulation Statistics ----------