1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 716 unchanged lines hidden (view full) --- 725block_size=64 726clk_domain=system.cpu_clk_domain 727eventq_index=0 728hit_latency=20 729sequential_access=false 730size=2097152 731 732[system.cpu.toL2Bus] |
733type=CoherentXBar |
734clk_domain=system.cpu_clk_domain 735eventq_index=0 736header_cycles=1 |
737snoop_filter=Null |
738system=system 739use_default_range=false 740width=32 741master=system.cpu.l2cache.cpu_side 742slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 743 744[system.cpu.tracer] 745type=ExeTracer --- 13 unchanged lines hidden (view full) --- 759input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in 760max_stack_size=67108864 761output=cout 762pid=100 763ppid=99 764simpoint=114600000000 765system=system 766uid=100 |
767useArchPT=false |
768 769[system.cpu_clk_domain] 770type=SrcClockDomain 771clock=500 772domain_id=-1 773eventq_index=0 774init_perf_level=0 775voltage_domain=system.voltage_domain 776 777[system.dvfs_handler] 778type=DVFSHandler 779domains= 780enable=false 781eventq_index=0 782sys_clk_domain=system.clk_domain 783transition_latency=100000000 784 785[system.membus] |
786type=CoherentXBar |
787clk_domain=system.clk_domain 788eventq_index=0 789header_cycles=1 |
790snoop_filter=Null |
791system=system 792use_default_range=false 793width=8 794master=system.physmem.port 795slave=system.system_port system.cpu.l2cache.mem_side 796 797[system.physmem] 798type=DRAMCtrl |
799IDD0=0.075000 800IDD02=0.000000 801IDD2N=0.050000 802IDD2N2=0.000000 803IDD2P0=0.000000 804IDD2P02=0.000000 805IDD2P1=0.000000 806IDD2P12=0.000000 807IDD3N=0.057000 808IDD3N2=0.000000 809IDD3P0=0.000000 810IDD3P02=0.000000 811IDD3P1=0.000000 812IDD3P12=0.000000 813IDD4R=0.187000 814IDD4R2=0.000000 815IDD4W=0.165000 816IDD4W2=0.000000 817IDD5=0.220000 818IDD52=0.000000 819IDD6=0.000000 820IDD62=0.000000 821VDD=1.500000 822VDD2=0.000000 |
823activation_limit=4 824addr_mapping=RoRaBaChCo |
825bank_groups_per_rank=0 |
826banks_per_rank=8 827burst_length=8 828channels=1 829clk_domain=system.clk_domain 830conf_table_reported=true 831device_bus_width=8 832device_rowbuffer_size=1024 833devices_per_rank=8 |
834dll=true |
835eventq_index=0 836in_addr_map=true 837max_accesses_per_row=16 838mem_sched_policy=frfcfs 839min_writes_per_switch=16 840null=false 841page_policy=open_adaptive 842range=0:134217727 843ranks_per_channel=2 844read_buffer_size=32 845static_backend_latency=10000 846static_frontend_latency=10000 847tBURST=5000 |
848tCCD_L=0 |
849tCK=1250 850tCL=13750 |
851tCS=2500 |
852tRAS=35000 853tRCD=13750 854tREFI=7800000 855tRFC=260000 856tRP=13750 857tRRD=6000 |
858tRRD_L=0 |
859tRTP=7500 860tRTW=2500 861tWR=15000 862tWTR=7500 863tXAW=30000 |
864tXP=0 865tXPDLL=0 866tXS=0 867tXSDLL=0 |
868write_buffer_size=64 869write_high_thresh_perc=85 870write_low_thresh_perc=50 871port=system.membus.master[0] 872 873[system.voltage_domain] 874type=VoltageDomain 875eventq_index=0 876voltage=1.000000 877 |