stats.txt (9702:094d0280e481) | stats.txt (9729:e2fafd224f43) |
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1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated 4sim_ticks 365989065000 # Number of ticks simulated 5final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 466388 # Simulator instruction rate (inst/s) 8host_op_rate 821234 # Simulator op (including micro ops) rate (op/s) --- 20 unchanged lines hidden (view full) --- 29system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated 4sim_ticks 365989065000 # Number of ticks simulated 5final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 466388 # Simulator instruction rate (inst/s) 8host_op_rate 821234 # Simulator op (including micro ops) rate (op/s) --- 20 unchanged lines hidden (view full) --- 29system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) |
37system.membus.throughput 5272114 # Throughput (bytes/s) 38system.membus.trans_dist::ReadReq 1025 # Transaction distribution 39system.membus.trans_dist::ReadResp 1025 # Transaction distribution 40system.membus.trans_dist::Writeback 100 # Transaction distribution 41system.membus.trans_dist::ReadExReq 29024 # Transaction distribution 42system.membus.trans_dist::ReadExResp 29024 # Transaction distribution 43system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) 44system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count::system.physmem.port 60198 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) 47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) 48system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) 49system.membus.tot_pkt_size::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) 50system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) 51system.membus.data_through_bus 1929536 # Total data (bytes) 52system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 53system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) 54system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 55system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) 56system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
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37system.cpu.workload.num_syscalls 444 # Number of system calls 38system.cpu.numCycles 731978130 # number of cpu cycles simulated 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 157988548 # Number of instructions committed 42system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses 44system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses --- 323 unchanged lines hidden (view full) --- 368system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency 369system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency 370system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency 371system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 372system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 373system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 374system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 375system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 57system.cpu.workload.num_syscalls 444 # Number of system calls 58system.cpu.numCycles 731978130 # number of cpu cycles simulated 59system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 60system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 61system.cpu.committedInsts 157988548 # Number of instructions committed 62system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 63system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses 64system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses --- 323 unchanged lines hidden (view full) --- 388system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency 389system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency 390system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency 391system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 392system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 393system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 394system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 395system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
396system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s) 397system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution 398system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 399system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution 400system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 401system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 402system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1616 # Packet count per connected master and slave (bytes) 403system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6196142 # Packet count per connected master and slave (bytes) 404system.cpu.toL2Bus.pkt_count 6197758 # Packet count per connected master and slave (bytes) 405system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51712 # Cumulative packet size per connected master and slave (bytes) 406system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 264276032 # Cumulative packet size per connected master and slave (bytes) 407system.cpu.toL2Bus.tot_pkt_size 264327744 # Cumulative packet size per connected master and slave (bytes) 408system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes) 409system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 410system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) 411system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 412system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 413system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 414system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 415system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
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376 377---------- End Simulation Statistics ---------- | 416 417---------- End Simulation Statistics ---------- |