| stats.txt (9322:01c8c5ff2c3b) | stats.txt (9373:26ba525347fe) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated |
| 4sim_ticks 365989063000 # Number of ticks simulated 5final_tick 365989063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 365989064000 # Number of ticks simulated 5final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 621192 # Simulator instruction rate (inst/s) 8host_op_rate 1093819 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1439024491 # Simulator tick rate (ticks/s) 10host_mem_usage 361884 # Number of bytes of host memory used 11host_seconds 254.33 # Real time elapsed on the host | 7host_inst_rate 426513 # Simulator instruction rate (inst/s) 8host_op_rate 751021 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 988040650 # Simulator tick rate (ticks/s) 10host_mem_usage 411308 # Number of bytes of host memory used 11host_seconds 370.42 # Real time elapsed on the host |
| 12sim_insts 157988548 # Number of instructions simulated | 12sim_insts 157988548 # Number of instructions simulated |
| 13sim_ops 278192463 # Number of ops (including micro ops) simulated | 13sim_ops 278192464 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6400 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory --- 8 unchanged lines hidden (view full) --- 30system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.workload.num_syscalls 444 # Number of system calls | 14system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6400 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory --- 8 unchanged lines hidden (view full) --- 30system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.workload.num_syscalls 444 # Number of system calls |
| 38system.cpu.numCycles 731978126 # number of cpu cycles simulated | 38system.cpu.numCycles 731978128 # number of cpu cycles simulated |
| 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 157988548 # Number of instructions committed | 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 157988548 # Number of instructions committed |
| 42system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses | 42system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses |
| 44system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 45system.cpu.num_func_calls 0 # number of times a function call or return occured 46system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls | 44system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 45system.cpu.num_func_calls 0 # number of times a function call or return occured 46system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls |
| 47system.cpu.num_int_insts 278186171 # number of integer instructions | 47system.cpu.num_int_insts 278186173 # number of integer instructions |
| 48system.cpu.num_fp_insts 40 # number of float instructions | 48system.cpu.num_fp_insts 40 # number of float instructions |
| 49system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read 50system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written | 49system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read 50system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written |
| 51system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 52system.cpu.num_fp_register_writes 26 # number of times the floating registers were written | 51system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 52system.cpu.num_fp_register_writes 26 # number of times the floating registers were written |
| 53system.cpu.num_mem_refs 122219135 # number of memory refs | 53system.cpu.num_mem_refs 122219136 # number of memory refs |
| 54system.cpu.num_load_insts 90779384 # Number of load instructions | 54system.cpu.num_load_insts 90779384 # Number of load instructions |
| 55system.cpu.num_store_insts 31439751 # Number of store instructions | 55system.cpu.num_store_insts 31439752 # Number of store instructions |
| 56system.cpu.num_idle_cycles 0 # Number of idle cycles | 56system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 57system.cpu.num_busy_cycles 731978126 # Number of busy cycles | 57system.cpu.num_busy_cycles 731978128 # Number of busy cycles |
| 58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 59system.cpu.idle_fraction 0 # Percentage of idle cycles 60system.cpu.icache.replacements 24 # number of replacements | 58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 59system.cpu.idle_fraction 0 # Percentage of idle cycles 60system.cpu.icache.replacements 24 # number of replacements |
| 61system.cpu.icache.tagsinuse 665.632511 # Cycle average of tags in use | 61system.cpu.icache.tagsinuse 665.632509 # Cycle average of tags in use |
| 62system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. 63system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. 64system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. 65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 62system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. 63system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. 64system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. 65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 66system.cpu.icache.occ_blocks::cpu.inst 665.632511 # Average occupied blocks per requestor | 66system.cpu.icache.occ_blocks::cpu.inst 665.632509 # Average occupied blocks per requestor |
| 67system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 68system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy 69system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits 70system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits 71system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits 72system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits 73system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits 74system.cpu.icache.overall_hits::total 217695357 # number of overall hits --- 56 unchanged lines hidden (view full) --- 131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency 132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency 133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 134system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 136system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.dcache.replacements 2062733 # number of replacements | 67system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 68system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy 69system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits 70system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits 71system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits 72system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits 73system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits 74system.cpu.icache.overall_hits::total 217695357 # number of overall hits --- 56 unchanged lines hidden (view full) --- 131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency 132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency 133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 134system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 136system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.dcache.replacements 2062733 # number of replacements |
| 139system.cpu.dcache.tagsinuse 4076.488641 # Cycle average of tags in use 140system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks. | 139system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use 140system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks. |
| 141system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. | 141system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. |
| 142system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks. 143system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit. 144system.cpu.dcache.occ_blocks::cpu.data 4076.488641 # Average occupied blocks per requestor | 142system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks. 143system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit. 144system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor |
| 145system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy 146system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy 147system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits 148system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits | 145system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy 146system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy 147system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits 148system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits |
| 149system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits 150system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits 151system.cpu.dcache.demand_hits::cpu.data 120152368 # number of demand (read+write) hits 152system.cpu.dcache.demand_hits::total 120152368 # number of demand (read+write) hits 153system.cpu.dcache.overall_hits::cpu.data 120152368 # number of overall hits 154system.cpu.dcache.overall_hits::total 120152368 # number of overall hits | 149system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 150system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 151system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits 152system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits 153system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits 154system.cpu.dcache.overall_hits::total 120152369 # number of overall hits |
| 155system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 156system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 157system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 158system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 159system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 160system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 161system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 162system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 163system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles 164system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles 165system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles 166system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles 167system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles 168system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles 169system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles 170system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles 171system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses) 172system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses) | 155system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 156system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 157system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 158system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 159system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 160system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 161system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 162system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 163system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles 164system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles 165system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles 166system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles 167system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles 168system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles 169system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles 170system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles 171system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses) 172system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses) |
| 173system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) 175system.cpu.dcache.demand_accesses::cpu.data 122219197 # number of demand (read+write) accesses 176system.cpu.dcache.demand_accesses::total 122219197 # number of demand (read+write) accesses 177system.cpu.dcache.overall_accesses::cpu.data 122219197 # number of overall (read+write) accesses 178system.cpu.dcache.overall_accesses::total 122219197 # number of overall (read+write) accesses | 173system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 175system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses 176system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses 177system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses 178system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses |
| 179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 180system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 182system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 183system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 184system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 185system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 186system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses --- 44 unchanged lines hidden (view full) --- 231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency 232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency 233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 234system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 236system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 238system.cpu.l2cache.replacements 318 # number of replacements | 179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 180system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 182system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 183system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 184system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 185system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 186system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses --- 44 unchanged lines hidden (view full) --- 231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency 232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency 233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 234system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 236system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 238system.cpu.l2cache.replacements 318 # number of replacements |
| 239system.cpu.l2cache.tagsinuse 20041.899874 # Cycle average of tags in use | 239system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use |
| 240system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks. 241system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks. 242system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks. 243system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 240system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks. 241system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks. 242system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks. 243system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 244system.cpu.l2cache.occ_blocks::writebacks 19330.353270 # Average occupied blocks per requestor 245system.cpu.l2cache.occ_blocks::cpu.inst 557.646384 # Average occupied blocks per requestor | 244system.cpu.l2cache.occ_blocks::writebacks 19330.353217 # Average occupied blocks per requestor 245system.cpu.l2cache.occ_blocks::cpu.inst 557.646383 # Average occupied blocks per requestor |
| 246system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor 247system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy 248system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy 249system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy 250system.cpu.l2cache.occ_percent::total 0.611630 # Average percentage of cache occupancy 251system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits 252system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits 253system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits --- 124 unchanged lines hidden --- | 246system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor 247system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy 248system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy 249system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy 250system.cpu.l2cache.occ_percent::total 0.611630 # Average percentage of cache occupancy 251system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits 252system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits 253system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits --- 124 unchanged lines hidden --- |