Cross Reference: /gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.365994 # Number of seconds simulated
4sim_ticks 365994481000 # Number of ticks simulated
5final_tick 365994481000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.365989 # Number of seconds simulated
4sim_ticks 365989063000 # Number of ticks simulated
5final_tick 365989063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 452383 # Simulator instruction rate (inst/s)
8host_op_rate 796575 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1047986231 # Simulator tick rate (ticks/s)
10host_mem_usage 363904 # Number of bytes of host memory used
11host_seconds 349.24 # Real time elapsed on the host

7host_inst_rate 621192 # Simulator instruction rate (inst/s)
8host_op_rate 1093819 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1439024491 # Simulator tick rate (ticks/s)
10host_mem_usage 361884 # Number of bytes of host memory used
11host_seconds 254.33 # Real time elapsed on the host

12sim_insts 157988548 # Number of instructions simulated
13sim_ops 278192463 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory
16system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 14528 # Number of bytes written to this memory
20system.physmem.bytes_written::total 14528 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 29370 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 227 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 141292 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 5135815 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 5277107 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 141292 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 141292 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 39695 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 39695 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 39695 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 141292 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 5135815 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 5316801 # Total bandwidth to/from this memory (bytes/s)

14system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
16system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory
20system.physmem.bytes_written::total 6400 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 100 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)

37system.cpu.workload.num_syscalls 444 # Number of system calls

38system.cpu.numCycles 731988962 # number of cpu cycles simulated

38system.cpu.numCycles 731978126 # number of cpu cycles simulated

39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
41system.cpu.committedInsts 157988548 # Number of instructions committed
42system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed
43system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses
44system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
45system.cpu.num_func_calls 0 # number of times a function call or return occured
46system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
47system.cpu.num_int_insts 278186171 # number of integer instructions
48system.cpu.num_fp_insts 40 # number of float instructions
49system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read
50system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written
51system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
52system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
53system.cpu.num_mem_refs 122219135 # number of memory refs
54system.cpu.num_load_insts 90779384 # Number of load instructions
55system.cpu.num_store_insts 31439751 # Number of store instructions
56system.cpu.num_idle_cycles 0 # Number of idle cycles

57system.cpu.num_busy_cycles 731988962 # Number of busy cycles

57system.cpu.num_busy_cycles 731978126 # Number of busy cycles

58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
59system.cpu.idle_fraction 0 # Percentage of idle cycles
60system.cpu.icache.replacements 24 # number of replacements

61system.cpu.icache.tagsinuse 665.633473 # Cycle average of tags in use

61system.cpu.icache.tagsinuse 665.632511 # Cycle average of tags in use

62system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
63system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
64system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

66system.cpu.icache.occ_blocks::cpu.inst 665.633473 # Average occupied blocks per requestor

66system.cpu.icache.occ_blocks::cpu.inst 665.632511 # Average occupied blocks per requestor

67system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
68system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
69system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
70system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
71system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
72system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits
73system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits
74system.cpu.icache.overall_hits::total 217695357 # number of overall hits
75system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
76system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
77system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
78system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
79system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
80system.cpu.icache.overall_misses::total 808 # number of overall misses

81system.cpu.icache.ReadReq_miss_latency::cpu.inst 44440000 # number of ReadReq miss cycles
82system.cpu.icache.ReadReq_miss_latency::total 44440000 # number of ReadReq miss cycles
83system.cpu.icache.demand_miss_latency::cpu.inst 44440000 # number of demand (read+write) miss cycles
84system.cpu.icache.demand_miss_latency::total 44440000 # number of demand (read+write) miss cycles
85system.cpu.icache.overall_miss_latency::cpu.inst 44440000 # number of overall miss cycles
86system.cpu.icache.overall_miss_latency::total 44440000 # number of overall miss cycles

81system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles
82system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles
83system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles
84system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles
85system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles
86system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles

87system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses)
88system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses)
89system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses
90system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses
91system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses
92system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses
93system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
94system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
95system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
96system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
97system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
98system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses

99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
100system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
102system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
103system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
104system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency

99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency
100system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
102system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency
103system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
104system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency

105system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
106system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
107system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
108system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
109system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
110system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
111system.cpu.icache.fast_writes 0 # number of fast writes performed
112system.cpu.icache.cache_copies 0 # number of cache copies performed
113system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
114system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
115system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
116system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
117system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
118system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses

119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles
120system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles
121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles
122system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles
123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
124system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles

119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles
120system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles
121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles
122system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles
123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles
124system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles

125system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
126system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
127system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
128system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
129system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
130system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses

131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
134system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency

131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
134system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency

137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
138system.cpu.dcache.replacements 2062733 # number of replacements

139system.cpu.dcache.tagsinuse 4076.488929 # Cycle average of tags in use

139system.cpu.dcache.tagsinuse 4076.488641 # Cycle average of tags in use

140system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks.
141system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
142system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks.
143system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit.

144system.cpu.dcache.occ_blocks::cpu.data 4076.488929 # Average occupied blocks per requestor
145system.cpu.dcache.occ_percent::cpu.data 0.995237 # Average percentage of cache occupancy
146system.cpu.dcache.occ_percent::total 0.995237 # Average percentage of cache occupancy

144system.cpu.dcache.occ_blocks::cpu.data 4076.488641 # Average occupied blocks per requestor
145system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
146system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy

147system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
148system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
149system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
150system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
151system.cpu.dcache.demand_hits::cpu.data 120152368 # number of demand (read+write) hits
152system.cpu.dcache.demand_hits::total 120152368 # number of demand (read+write) hits
153system.cpu.dcache.overall_hits::cpu.data 120152368 # number of overall hits
154system.cpu.dcache.overall_hits::total 120152368 # number of overall hits
155system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
156system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
157system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
158system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
159system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
160system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
161system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
162system.cpu.dcache.overall_misses::total 2066829 # number of overall misses

163system.cpu.dcache.ReadReq_miss_latency::cpu.data 25503766000 # number of ReadReq miss cycles
164system.cpu.dcache.ReadReq_miss_latency::total 25503766000 # number of ReadReq miss cycles
165system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598582000 # number of WriteReq miss cycles
166system.cpu.dcache.WriteReq_miss_latency::total 2598582000 # number of WriteReq miss cycles
167system.cpu.dcache.demand_miss_latency::cpu.data 28102348000 # number of demand (read+write) miss cycles
168system.cpu.dcache.demand_miss_latency::total 28102348000 # number of demand (read+write) miss cycles
169system.cpu.dcache.overall_miss_latency::cpu.data 28102348000 # number of overall miss cycles
170system.cpu.dcache.overall_miss_latency::total 28102348000 # number of overall miss cycles

163system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles
164system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles
165system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles
166system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles
167system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles
168system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
169system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
170system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles

171system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
172system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
173system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
174system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
175system.cpu.dcache.demand_accesses::cpu.data 122219197 # number of demand (read+write) accesses
176system.cpu.dcache.demand_accesses::total 122219197 # number of demand (read+write) accesses
177system.cpu.dcache.overall_accesses::cpu.data 122219197 # number of overall (read+write) accesses
178system.cpu.dcache.overall_accesses::total 122219197 # number of overall (read+write) accesses
179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
180system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
182system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
183system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
184system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
185system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
186system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses

187system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.347301 # average ReadReq miss latency
188system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.347301 # average ReadReq miss latency
189system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24489.741681 # average WriteReq miss latency
190system.cpu.dcache.WriteReq_avg_miss_latency::total 24489.741681 # average WriteReq miss latency
191system.cpu.dcache.demand_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency
192system.cpu.dcache.demand_avg_miss_latency::total 13596.842313 # average overall miss latency
193system.cpu.dcache.overall_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency
194system.cpu.dcache.overall_avg_miss_latency::total 13596.842313 # average overall miss latency

187system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency
188system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency
189system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency
190system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency
191system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
192system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency
193system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
194system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency

195system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
196system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
197system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
198system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
199system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
200system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
201system.cpu.dcache.fast_writes 0 # number of fast writes performed
202system.cpu.dcache.cache_copies 0 # number of cache copies performed

203system.cpu.dcache.writebacks::writebacks 2061794 # number of writebacks
204system.cpu.dcache.writebacks::total 2061794 # number of writebacks

203system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks
204system.cpu.dcache.writebacks::total 2062484 # number of writebacks

205system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
206system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
207system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
208system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
209system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
210system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
211system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
212system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses

213system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles
214system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles
215system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386364000 # number of WriteReq MSHR miss cycles
216system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386364000 # number of WriteReq MSHR miss cycles
217system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968690000 # number of demand (read+write) MSHR miss cycles
218system.cpu.dcache.demand_mshr_miss_latency::total 23968690000 # number of demand (read+write) MSHR miss cycles
219system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968690000 # number of overall MSHR miss cycles
220system.cpu.dcache.overall_mshr_miss_latency::total 23968690000 # number of overall MSHR miss cycles

213system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles
214system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles
215system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles
216system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles
217system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles
218system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles
219system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles
220system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles

221system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
222system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
223system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
224system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
225system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
226system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
227system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
228system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses

229system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301 # average ReadReq mshr miss latency
230system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301 # average ReadReq mshr miss latency
231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.741681 # average WriteReq mshr miss latency
232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.741681 # average WriteReq mshr miss latency
233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency
234system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency
235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency
236system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency

229system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency
230system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency
231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency
232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency
233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
234system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
236system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency

237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

238system.cpu.l2cache.replacements 1081 # number of replacements
239system.cpu.l2cache.tagsinuse 19679.255550 # Cycle average of tags in use
240system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks.
241system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks.
242system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks.

238system.cpu.l2cache.replacements 318 # number of replacements
239system.cpu.l2cache.tagsinuse 20041.899874 # Cycle average of tags in use
240system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks.
241system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks.
242system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks.

243system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

244system.cpu.l2cache.occ_blocks::writebacks 19326.193704 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 210.694953 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 142.366893 # Average occupied blocks per requestor
247system.cpu.l2cache.occ_percent::writebacks 0.589789 # Average percentage of cache occupancy
248system.cpu.l2cache.occ_percent::cpu.inst 0.006430 # Average percentage of cache occupancy
249system.cpu.l2cache.occ_percent::cpu.data 0.004345 # Average percentage of cache occupancy
250system.cpu.l2cache.occ_percent::total 0.600563 # Average percentage of cache occupancy
251system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits
252system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits
253system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits
254system.cpu.l2cache.Writeback_hits::total 2061794 # number of Writeback hits
255system.cpu.l2cache.ReadExReq_hits::cpu.data 77082 # number of ReadExReq hits
256system.cpu.l2cache.ReadExReq_hits::total 77082 # number of ReadExReq hits
257system.cpu.l2cache.demand_hits::cpu.data 2037459 # number of demand (read+write) hits
258system.cpu.l2cache.demand_hits::total 2037459 # number of demand (read+write) hits
259system.cpu.l2cache.overall_hits::cpu.data 2037459 # number of overall hits
260system.cpu.l2cache.overall_hits::total 2037459 # number of overall hits
261system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
262system.cpu.l2cache.ReadReq_misses::cpu.data 343 # number of ReadReq misses
263system.cpu.l2cache.ReadReq_misses::total 1151 # number of ReadReq misses
264system.cpu.l2cache.ReadExReq_misses::cpu.data 29027 # number of ReadExReq misses
265system.cpu.l2cache.ReadExReq_misses::total 29027 # number of ReadExReq misses
266system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
267system.cpu.l2cache.demand_misses::cpu.data 29370 # number of demand (read+write) misses
268system.cpu.l2cache.demand_misses::total 30178 # number of demand (read+write) misses
269system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses
270system.cpu.l2cache.overall_misses::cpu.data 29370 # number of overall misses
271system.cpu.l2cache.overall_misses::total 30178 # number of overall misses
272system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles
273system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17836000 # number of ReadReq miss cycles
274system.cpu.l2cache.ReadReq_miss_latency::total 59852000 # number of ReadReq miss cycles
275system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509435000 # number of ReadExReq miss cycles
276system.cpu.l2cache.ReadExReq_miss_latency::total 1509435000 # number of ReadExReq miss cycles
277system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles
278system.cpu.l2cache.demand_miss_latency::cpu.data 1527271000 # number of demand (read+write) miss cycles
279system.cpu.l2cache.demand_miss_latency::total 1569287000 # number of demand (read+write) miss cycles
280system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles
281system.cpu.l2cache.overall_miss_latency::cpu.data 1527271000 # number of overall miss cycles
282system.cpu.l2cache.overall_miss_latency::total 1569287000 # number of overall miss cycles

244system.cpu.l2cache.occ_blocks::writebacks 19330.353270 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 557.646384 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor
247system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
248system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
249system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
250system.cpu.l2cache.occ_percent::total 0.611630 # Average percentage of cache occupancy
251system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
252system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits
253system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits
254system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits
255system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits
256system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
257system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
258system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
259system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits
260system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits
261system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
262system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits
263system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits
264system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
265system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses
266system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses
267system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses
268system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
269system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
270system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses
271system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses
272system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
273system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses
274system.cpu.l2cache.overall_misses::total 30049 # number of overall misses
275system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles
276system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles
277system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles
278system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles
279system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles
280system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles
281system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles
282system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles
283system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles
284system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles
285system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles

283system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
284system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
285system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)

286system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
287system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
288system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)

286system.cpu.l2cache.Writeback_accesses::writebacks 2061794 # number of Writeback accesses(hits+misses)
287system.cpu.l2cache.Writeback_accesses::total 2061794 # number of Writeback accesses(hits+misses)

289system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses)
290system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses)

288system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
289system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
290system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
291system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
292system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
293system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
294system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
295system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses

291system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
292system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
293system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
294system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
295system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
296system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
297system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
298system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses

296system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
297system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000175 # miss rate for ReadReq accesses
298system.cpu.l2cache.ReadReq_miss_rate::total 0.000587 # miss rate for ReadReq accesses
299system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273558 # miss rate for ReadExReq accesses
300system.cpu.l2cache.ReadExReq_miss_rate::total 0.273558 # miss rate for ReadExReq accesses
301system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
302system.cpu.l2cache.demand_miss_rate::cpu.data 0.014210 # miss rate for demand accesses
303system.cpu.l2cache.demand_miss_rate::total 0.014595 # miss rate for demand accesses
304system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
305system.cpu.l2cache.overall_miss_rate::cpu.data 0.014210 # miss rate for overall accesses
306system.cpu.l2cache.overall_miss_rate::total 0.014595 # miss rate for overall accesses

299system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses
300system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses
301system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses
302system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses
303system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
304system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
305system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses
306system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses
307system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
308system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses
309system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses

307system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
308system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
309system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency

310system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
311system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
312system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency

310system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.067971 # average ReadExReq miss latency
311system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.067971 # average ReadExReq miss latency

313system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency
314system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency

312system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency

315system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency

313system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency
314system.cpu.l2cache.demand_avg_miss_latency::total 52001.027238 # average overall miss latency

316system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
317system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency

315system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency

318system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency

316system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency
317system.cpu.l2cache.overall_avg_miss_latency::total 52001.027238 # average overall miss latency

319system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
320system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency

318system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
319system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
320system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
321system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
322system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
323system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
324system.cpu.l2cache.fast_writes 0 # number of fast writes performed
325system.cpu.l2cache.cache_copies 0 # number of cache copies performed

321system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
322system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
323system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
324system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
325system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
326system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
327system.cpu.l2cache.fast_writes 0 # number of fast writes performed
328system.cpu.l2cache.cache_copies 0 # number of cache copies performed

326system.cpu.l2cache.writebacks::writebacks 227 # number of writebacks
327system.cpu.l2cache.writebacks::total 227 # number of writebacks
328system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
329system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 343 # number of ReadReq MSHR misses
330system.cpu.l2cache.ReadReq_mshr_misses::total 1151 # number of ReadReq MSHR misses
331system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29027 # number of ReadExReq MSHR misses
332system.cpu.l2cache.ReadExReq_mshr_misses::total 29027 # number of ReadExReq MSHR misses
333system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
334system.cpu.l2cache.demand_mshr_misses::cpu.data 29370 # number of demand (read+write) MSHR misses
335system.cpu.l2cache.demand_mshr_misses::total 30178 # number of demand (read+write) MSHR misses
336system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
337system.cpu.l2cache.overall_mshr_misses::cpu.data 29370 # number of overall MSHR misses
338system.cpu.l2cache.overall_mshr_misses::total 30178 # number of overall MSHR misses
339system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles
340system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13720000 # number of ReadReq MSHR miss cycles
341system.cpu.l2cache.ReadReq_mshr_miss_latency::total 46040000 # number of ReadReq MSHR miss cycles
342system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1161080000 # number of ReadExReq MSHR miss cycles
343system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1161080000 # number of ReadExReq MSHR miss cycles
344system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles
345system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1174800000 # number of demand (read+write) MSHR miss cycles
346system.cpu.l2cache.demand_mshr_miss_latency::total 1207120000 # number of demand (read+write) MSHR miss cycles
347system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles
348system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1174800000 # number of overall MSHR miss cycles
349system.cpu.l2cache.overall_mshr_miss_latency::total 1207120000 # number of overall MSHR miss cycles
350system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
351system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000175 # mshr miss rate for ReadReq accesses
352system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadReq accesses
353system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273558 # mshr miss rate for ReadExReq accesses
354system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273558 # mshr miss rate for ReadExReq accesses
355system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
356system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for demand accesses
357system.cpu.l2cache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses
358system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
359system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for overall accesses
360system.cpu.l2cache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses

329system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks
330system.cpu.l2cache.writebacks::total 100 # number of writebacks
331system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
332system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses
333system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses
334system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
335system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
336system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
337system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses
338system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses
339system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
340system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses
341system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses
342system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles
343system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles
344system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles
345system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles
346system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles
347system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles
348system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles
349system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles
350system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles
351system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles
352system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles
353system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses
354system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses
355system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses
356system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
357system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
358system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
359system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses
360system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses
361system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
362system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses
363system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses