| stats.txt (11201:b1bd4afb6b16) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.366199 # Number of seconds simulated 4sim_ticks 366199170500 # Number of ticks simulated 5final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.366199 # Number of seconds simulated 4sim_ticks 366199170500 # Number of ticks simulated 5final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 639917 # Simulator instruction rate (inst/s) 8host_op_rate 1126791 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1483253517 # Simulator tick rate (ticks/s) 10host_mem_usage 455604 # Number of bytes of host memory used 11host_seconds 246.89 # Real time elapsed on the host | 7host_inst_rate 703769 # Simulator instruction rate (inst/s) 8host_op_rate 1239225 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1631255376 # Simulator tick rate (ticks/s) 10host_mem_usage 410416 # Number of bytes of host memory used 11host_seconds 224.49 # Real time elapsed on the host |
| 12sim_insts 157988548 # Number of instructions simulated 13sim_ops 278192465 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory --- 145 unchanged lines hidden (view full) --- 165system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency 167system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 168system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 169system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 157988548 # Number of instructions simulated 13sim_ops 278192465 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory --- 145 unchanged lines hidden (view full) --- 165system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency 167system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 168system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 169system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 173system.cpu.dcache.fast_writes 0 # number of fast writes performed 174system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 175system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks 176system.cpu.dcache.writebacks::total 2062482 # number of writebacks 177system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 178system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 181system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 182system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses --- 18 unchanged lines hidden (view full) --- 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency | 173system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks 174system.cpu.dcache.writebacks::total 2062482 # number of writebacks 175system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 176system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 177system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 178system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 179system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 180system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses --- 18 unchanged lines hidden (view full) --- 199system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency 200system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency 201system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency 202system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency 203system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency 204system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency 205system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency 206system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency |
| 209system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 210system.cpu.icache.tags.replacements 24 # number of replacements 211system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use 212system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. 213system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 214system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. 215system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor 217system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 260system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency 261system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency 262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 207system.cpu.icache.tags.replacements 24 # number of replacements 208system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use 209system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. 210system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 211system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. 212system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 213system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor 214system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 257system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency 258system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency 259system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 260system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 261system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 262system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 263system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 264system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 268system.cpu.icache.fast_writes 0 # number of fast writes performed 269system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 270system.cpu.icache.writebacks::writebacks 24 # number of writebacks 271system.cpu.icache.writebacks::total 24 # number of writebacks 272system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 273system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 274system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 275system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 276system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 277system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 288system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 289system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 290system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency 291system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency 292system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency 293system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency 294system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency 295system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency | 265system.cpu.icache.writebacks::writebacks 24 # number of writebacks 266system.cpu.icache.writebacks::total 24 # number of writebacks 267system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 268system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 269system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 270system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 271system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 272system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 283system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 284system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 285system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency 286system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency 287system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency 288system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency 289system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency 290system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency |
| 296system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 297system.cpu.l2cache.tags.replacements 313 # number of replacements 298system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use 299system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. 300system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. 301system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. 302system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 303system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor 304system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 397system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency 398system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency 399system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 400system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 401system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 402system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 403system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 404system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 291system.cpu.l2cache.tags.replacements 313 # number of replacements 292system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use 293system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. 294system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. 295system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. 296system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 297system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor 298system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 391system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency 392system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency 393system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 394system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 395system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 396system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 397system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 398system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 405system.cpu.l2cache.fast_writes 0 # number of fast writes performed 406system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 407system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks 408system.cpu.l2cache.writebacks::total 102 # number of writebacks 409system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 410system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 411system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses 412system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses 413system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses 414system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses --- 34 unchanged lines hidden (view full) --- 449system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 450system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 451system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency 452system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency 453system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency 454system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency 455system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency 456system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency | 399system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks 400system.cpu.l2cache.writebacks::total 102 # number of writebacks 401system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 402system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 403system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses 404system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses 405system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses 406system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses --- 34 unchanged lines hidden (view full) --- 441system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 442system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 443system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency 444system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency 445system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency 446system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency 447system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency 448system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency |
| 457system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 458system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. 459system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. 460system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 461system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. 462system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 463system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 464system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution --- 59 unchanged lines hidden --- | 449system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. 450system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. 451system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 452system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. 453system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 454system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 455system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 456system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution --- 59 unchanged lines hidden --- |