| stats.txt (10488:7c27480a5031) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated |
| 4sim_ticks 365989065000 # Number of ticks simulated 5final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 365989065500 # Number of ticks simulated 5final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 756908 # Simulator instruction rate (inst/s) 8host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1753418925 # Simulator tick rate (ticks/s) 10host_mem_usage 446124 # Number of bytes of host memory used 11host_seconds 208.73 # Real time elapsed on the host | 7host_inst_rate 638452 # Simulator instruction rate (inst/s) 8host_op_rate 1124211 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1479007835 # Simulator tick rate (ticks/s) 10host_mem_usage 450980 # Number of bytes of host memory used 11host_seconds 247.46 # Real time elapsed on the host |
| 12sim_insts 157988548 # Number of instructions simulated 13sim_ops 278192465 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory --- 11 unchanged lines hidden (view full) --- 31system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 157988548 # Number of instructions simulated 13sim_ops 278192465 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory --- 11 unchanged lines hidden (view full) --- 31system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) |
| 39system.membus.trans_dist::ReadReq 1025 # Transaction distribution 40system.membus.trans_dist::ReadResp 1025 # Transaction distribution 41system.membus.trans_dist::Writeback 100 # Transaction distribution 42system.membus.trans_dist::ReadExReq 29024 # Transaction distribution 43system.membus.trans_dist::ReadExResp 29024 # Transaction distribution 44system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) 47system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) 48system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) 49system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) 50system.membus.snoops 0 # Total snoops (count) 51system.membus.snoop_fanout::samples 30149 # Request fanout histogram 52system.membus.snoop_fanout::mean 0 # Request fanout histogram 53system.membus.snoop_fanout::stdev 0 # Request fanout histogram 54system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 55system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram 56system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 57system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 58system.membus.snoop_fanout::min_value 0 # Request fanout histogram 59system.membus.snoop_fanout::max_value 0 # Request fanout histogram 60system.membus.snoop_fanout::total 30149 # Request fanout histogram 61system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) 62system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 63system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) 64system.membus.respLayer1.utilization 0.1 # Layer utilization (%) | |
| 65system.cpu_clk_domain.clock 500 # Clock period in ticks 66system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 67system.cpu.workload.num_syscalls 444 # Number of system calls | 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 41system.cpu.workload.num_syscalls 444 # Number of system calls |
| 68system.cpu.numCycles 731978130 # number of cpu cycles simulated | 42system.cpu.numCycles 731978131 # number of cpu cycles simulated |
| 69system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 70system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 71system.cpu.committedInsts 157988548 # Number of instructions committed 72system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 73system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses 74system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 75system.cpu.num_func_calls 8475189 # number of times a function call or return occured 76system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 81system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 82system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 83system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 84system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 85system.cpu.num_mem_refs 122219137 # number of memory refs 86system.cpu.num_load_insts 90779385 # Number of load instructions 87system.cpu.num_store_insts 31439752 # Number of store instructions 88system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 157988548 # Number of instructions committed 46system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 49system.cpu.num_func_calls 8475189 # number of times a function call or return occured 50system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 55system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 56system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 57system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 58system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 59system.cpu.num_mem_refs 122219137 # number of memory refs 60system.cpu.num_load_insts 90779385 # Number of load instructions 61system.cpu.num_store_insts 31439752 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 89system.cpu.num_busy_cycles 731978129.998000 # Number of busy cycles | 63system.cpu.num_busy_cycles 731978130.998000 # Number of busy cycles |
| 90system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 91system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 92system.cpu.Branches 29309705 # Number of branches fetched 93system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 94system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 95system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 96system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 97system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 120system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction 121system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction 122system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 123system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction 124system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction 125system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 126system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 127system.cpu.op_class::total 278192465 # Class of executed instruction | 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 29309705 # Number of branches fetched 67system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 68system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 69system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 70system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 71system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 94system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 97system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction 98system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 278192465 # Class of executed instruction |
| 102system.cpu.dcache.tags.replacements 2062733 # number of replacements 103system.cpu.dcache.tags.tagsinuse 4076.488607 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 126079702000 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488607 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 116system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 117system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses 118system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses 119system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits 120system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits 121system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 122system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 123system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits 124system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits 125system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits 126system.cpu.dcache.overall_hits::total 120152370 # number of overall hits 127system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 128system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 129system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 130system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 131system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 132system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 133system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 134system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 135system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles 136system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles 137system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles 139system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles 140system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles 141system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles 142system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles 143system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) 144system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) 145system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 146system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 147system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses 148system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses 149system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 150system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses 151system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 152system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 153system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 154system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 155system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 156system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 157system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 158system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 159system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency 160system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency 161system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency 163system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 164system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency 165system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency 167system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 168system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 169system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 173system.cpu.dcache.fast_writes 0 # number of fast writes performed 174system.cpu.dcache.cache_copies 0 # number of cache copies performed 175system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks 176system.cpu.dcache.writebacks::total 2062484 # number of writebacks 177system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 178system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 181system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 182system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 183system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 184system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 185system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22557604000 # number of ReadReq MSHR miss cycles 186system.cpu.dcache.ReadReq_mshr_miss_latency::total 22557604000 # number of ReadReq MSHR miss cycles 187system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2439292500 # number of WriteReq MSHR miss cycles 188system.cpu.dcache.WriteReq_mshr_miss_latency::total 2439292500 # number of WriteReq MSHR miss cycles 189system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24996896500 # number of demand (read+write) MSHR miss cycles 190system.cpu.dcache.demand_mshr_miss_latency::total 24996896500 # number of demand (read+write) MSHR miss cycles 191system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24996896500 # number of overall MSHR miss cycles 192system.cpu.dcache.overall_mshr_miss_latency::total 24996896500 # number of overall MSHR miss cycles 193system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 194system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 195system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 196system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 197system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 198system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 199system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 200system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396 # average ReadReq mshr miss latency 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396 # average ReadReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223 # average WriteReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223 # average WriteReq mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency 209system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 128system.cpu.icache.tags.replacements 24 # number of replacements | 210system.cpu.icache.tags.replacements 24 # number of replacements |
| 129system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use | 211system.cpu.icache.tags.tagsinuse 665.632506 # Cycle average of tags in use |
| 130system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. 131system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 132system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. 133system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 212system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. 213system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 214system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. 215system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 134system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor | 216system.cpu.icache.tags.occ_blocks::cpu.inst 665.632506 # Average occupied blocks per requestor |
| 135system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 136system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy 137system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 138system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 139system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 140system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 141system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id 142system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses --- 5 unchanged lines hidden (view full) --- 148system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits 149system.cpu.icache.overall_hits::total 217695356 # number of overall hits 150system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 151system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 152system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 153system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 154system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 155system.cpu.icache.overall_misses::total 808 # number of overall misses | 217system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 218system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy 219system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 223system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id 224system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses --- 5 unchanged lines hidden (view full) --- 230system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits 231system.cpu.icache.overall_hits::total 217695356 # number of overall hits 232system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 233system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 234system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 235system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 236system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 237system.cpu.icache.overall_misses::total 808 # number of overall misses |
| 156system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles 157system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles 158system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles 159system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles 160system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles 161system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles | 238system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230500 # number of ReadReq miss cycles 239system.cpu.icache.ReadReq_miss_latency::total 44230500 # number of ReadReq miss cycles 240system.cpu.icache.demand_miss_latency::cpu.inst 44230500 # number of demand (read+write) miss cycles 241system.cpu.icache.demand_miss_latency::total 44230500 # number of demand (read+write) miss cycles 242system.cpu.icache.overall_miss_latency::cpu.inst 44230500 # number of overall miss cycles 243system.cpu.icache.overall_miss_latency::total 44230500 # number of overall miss cycles |
| 162system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) 163system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) 164system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses 165system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses 166system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses 167system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses 168system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 169system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 170system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 171system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 172system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 173system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses | 244system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) 245system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) 246system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses 247system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses 248system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses 249system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses 250system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 251system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 252system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 253system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 254system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 255system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses |
| 174system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency 175system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency 176system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency 177system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency 178system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency 179system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency | 256system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822 # average ReadReq miss latency 257system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822 # average ReadReq miss latency 258system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency 259system.cpu.icache.demand_avg_miss_latency::total 54740.717822 # average overall miss latency 260system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency 261system.cpu.icache.overall_avg_miss_latency::total 54740.717822 # average overall miss latency |
| 180system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 183system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 184system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 185system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 186system.cpu.icache.fast_writes 0 # number of fast writes performed 187system.cpu.icache.cache_copies 0 # number of cache copies performed 188system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 189system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 190system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 191system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 192system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 193system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses | 262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 268system.cpu.icache.fast_writes 0 # number of fast writes performed 269system.cpu.icache.cache_copies 0 # number of cache copies performed 270system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 271system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 272system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 273system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 274system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 275system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses |
| 194system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles 195system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles 196system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles 197system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles 198system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles 199system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles | 276system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43018500 # number of ReadReq MSHR miss cycles 277system.cpu.icache.ReadReq_mshr_miss_latency::total 43018500 # number of ReadReq MSHR miss cycles 278system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43018500 # number of demand (read+write) MSHR miss cycles 279system.cpu.icache.demand_mshr_miss_latency::total 43018500 # number of demand (read+write) MSHR miss cycles 280system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43018500 # number of overall MSHR miss cycles 281system.cpu.icache.overall_mshr_miss_latency::total 43018500 # number of overall MSHR miss cycles |
| 200system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 201system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 202system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 203system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 204system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 205system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses | 282system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 283system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 284system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 285system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 287system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses |
| 206system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency 207system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency 208system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 209system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 210system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 211system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency | 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53240.717822 # average ReadReq mshr miss latency 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53240.717822 # average ReadReq mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency |
| 212system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 213system.cpu.l2cache.tags.replacements 318 # number of replacements | 294system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 295system.cpu.l2cache.tags.replacements 318 # number of replacements |
| 214system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use | 296system.cpu.l2cache.tags.tagsinuse 20041.899592 # Cycle average of tags in use |
| 215system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. 216system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. 217system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. 218system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 297system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. 298system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. 299system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. 300system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 219system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor 220system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor | 301system.cpu.l2cache.tags.occ_blocks::writebacks 19330.352993 # Average occupied blocks per requestor 302system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646380 # Average occupied blocks per requestor |
| 221system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor 222system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy 223system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy 224system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy 225system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy 226system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id 227system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 228system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id --- 22 unchanged lines hidden (view full) --- 251system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses 252system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses 253system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 254system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses 255system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses 256system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses 257system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses 258system.cpu.l2cache.overall_misses::total 30049 # number of overall misses | 303system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor 304system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy 305system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy 306system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id 309system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id --- 22 unchanged lines hidden (view full) --- 333system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses 334system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses 335system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 336system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses 337system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses 338system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses 339system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses 340system.cpu.l2cache.overall_misses::total 30049 # number of overall misses |
| 259system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles 260system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles 261system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles 262system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles 263system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles 264system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles 265system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles 266system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles 267system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles 268system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles 269system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles | 341system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42158000 # number of ReadReq miss cycles 342system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11655000 # number of ReadReq miss cycles 343system.cpu.l2cache.ReadReq_miss_latency::total 53813000 # number of ReadReq miss cycles 344system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1523791000 # number of ReadExReq miss cycles 345system.cpu.l2cache.ReadExReq_miss_latency::total 1523791000 # number of ReadExReq miss cycles 346system.cpu.l2cache.demand_miss_latency::cpu.inst 42158000 # number of demand (read+write) miss cycles 347system.cpu.l2cache.demand_miss_latency::cpu.data 1535446000 # number of demand (read+write) miss cycles 348system.cpu.l2cache.demand_miss_latency::total 1577604000 # number of demand (read+write) miss cycles 349system.cpu.l2cache.overall_miss_latency::cpu.inst 42158000 # number of overall miss cycles 350system.cpu.l2cache.overall_miss_latency::cpu.data 1535446000 # number of overall miss cycles 351system.cpu.l2cache.overall_miss_latency::total 1577604000 # number of overall miss cycles |
| 270system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) 271system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) 272system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) 273system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses) 274system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses) 275system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 276system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 277system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 286system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses 287system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses 288system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses 289system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses 290system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses 291system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses 292system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses 293system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses | 352system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) 353system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) 354system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) 355system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses) 356system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses) 357system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 358system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 359system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 368system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses 369system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses 370system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses 371system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses 372system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses 373system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses 374system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses 375system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses |
| 294system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 295system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 296system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 297system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency 298system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency 299system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 300system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency 301system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency 302system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 303system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency 304system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency | 376system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.622665 # average ReadReq miss latency 377system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency 378system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.487805 # average ReadReq miss latency 379system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency 380system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency 381system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency 382system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency 383system.cpu.l2cache.demand_avg_miss_latency::total 52501.048288 # average overall miss latency 384system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency 385system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency 386system.cpu.l2cache.overall_avg_miss_latency::total 52501.048288 # average overall miss latency |
| 305system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 306system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 307system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 308system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 309system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 310system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 311system.cpu.l2cache.fast_writes 0 # number of fast writes performed 312system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 318system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 319system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 320system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 321system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses 322system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses 323system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 324system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses 325system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses | 387system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 388system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 389system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 391system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 392system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 393system.cpu.l2cache.fast_writes 0 # number of fast writes performed 394system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 400system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 401system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 402system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 403system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses 404system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses 405system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 406system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses 407system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses |
| 326system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles 327system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles 328system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles 329system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles 330system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles 331system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles 332system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles 333system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles 334system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles 335system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles 336system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles | 408system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32521500 # number of ReadReq MSHR miss cycles 409system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8991000 # number of ReadReq MSHR miss cycles 410system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41512500 # number of ReadReq MSHR miss cycles 411system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1175472000 # number of ReadExReq MSHR miss cycles 412system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1175472000 # number of ReadExReq MSHR miss cycles 413system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32521500 # number of demand (read+write) MSHR miss cycles 414system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1184463000 # number of demand (read+write) MSHR miss cycles 415system.cpu.l2cache.demand_mshr_miss_latency::total 1216984500 # number of demand (read+write) MSHR miss cycles 416system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32521500 # number of overall MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1184463000 # number of overall MSHR miss cycles 418system.cpu.l2cache.overall_mshr_miss_latency::total 1216984500 # number of overall MSHR miss cycles |
| 337system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses 338system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses 339system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses 340system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses 341system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses 342system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses 343system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses 344system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses 345system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses 346system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses 347system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses | 419system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses 420system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses 421system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses 422system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses 423system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses 424system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses 425system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses 426system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses 427system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses 428system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses 429system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses |
| 348system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 349system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 350system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 351system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 352system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 353system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 354system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 355system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 356system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 357system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 358system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency | 430system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency 431system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 432system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency 433system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 434system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 435system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 436system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 437system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 438system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 439system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 440system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency |
| 359system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 441system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 360system.cpu.dcache.tags.replacements 2062733 # number of replacements 361system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use 362system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. 363system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. 364system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. 365system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. 366system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor 367system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy 368system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy 369system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 370system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 371system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id 372system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id 373system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 374system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 375system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses 376system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses 377system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits 378system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits 379system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 380system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 381system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits 382system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits 383system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits 384system.cpu.dcache.overall_hits::total 120152370 # number of overall hits 385system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 386system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 387system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 388system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 389system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 390system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 391system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 392system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 393system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles 394system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles 395system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles 396system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles 397system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles 398system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles 399system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles 400system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles 401system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) 402system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) 403system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 404system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 405system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses 406system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses 407system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 408system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses 409system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 410system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 411system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 412system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 413system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 414system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 415system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 416system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 417system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency 418system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency 419system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency 420system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency 421system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 422system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency 423system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 424system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency 425system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 426system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 427system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 428system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 429system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 430system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 431system.cpu.dcache.fast_writes 0 # number of fast writes performed 432system.cpu.dcache.cache_copies 0 # number of cache copies performed 433system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks 434system.cpu.dcache.writebacks::total 2062484 # number of writebacks 435system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 436system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 437system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 438system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 439system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 440system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 441system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 442system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 443system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles 444system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles 445system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles 446system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles 447system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles 448system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles 449system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles 450system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles 451system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 452system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 453system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 454system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 455system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 456system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 457system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 458system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 459system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency 460system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency 461system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency 462system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency 463system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 464system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 465system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 466system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 467system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 468system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 473system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) 474system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) 475system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 491system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 492system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram 493system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) 494system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 495system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 496system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 497system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 498system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) | 442system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 444system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 447system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 465system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 466system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram 467system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) 468system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 469system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 470system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 471system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 472system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 473system.membus.trans_dist::ReadReq 1025 # Transaction distribution 474system.membus.trans_dist::ReadResp 1025 # Transaction distribution 475system.membus.trans_dist::Writeback 100 # Transaction distribution 476system.membus.trans_dist::ReadExReq 29024 # Transaction distribution 477system.membus.trans_dist::ReadExResp 29024 # Transaction distribution 478system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) 479system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) 480system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) 481system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) 482system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) 483system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) 484system.membus.snoops 0 # Total snoops (count) 485system.membus.snoop_fanout::samples 30149 # Request fanout histogram 486system.membus.snoop_fanout::mean 0 # Request fanout histogram 487system.membus.snoop_fanout::stdev 0 # Request fanout histogram 488system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 489system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram 490system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 491system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 492system.membus.snoop_fanout::min_value 0 # Request fanout histogram 493system.membus.snoop_fanout::max_value 0 # Request fanout histogram 494system.membus.snoop_fanout::total 30149 # Request fanout histogram 495system.membus.reqLayer0.occupancy 30585000 # Layer occupancy (ticks) 496system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 497system.membus.respLayer1.occupancy 150276500 # Layer occupancy (ticks) 498system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
|
| 499 500---------- End Simulation Statistics ---------- | 499 500---------- End Simulation Statistics ---------- |