| stats.txt (10409:8c80b91944c5) | stats.txt (10488:7c27480a5031) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated 4sim_ticks 365989065000 # Number of ticks simulated 5final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 756908 # Simulator instruction rate (inst/s) 8host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s) --- 71 unchanged lines hidden (view full) --- 80system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written 81system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 82system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 83system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 84system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 85system.cpu.num_mem_refs 122219137 # number of memory refs 86system.cpu.num_load_insts 90779385 # Number of load instructions 87system.cpu.num_store_insts 31439752 # Number of store instructions | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated 4sim_ticks 365989065000 # Number of ticks simulated 5final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 756908 # Simulator instruction rate (inst/s) 8host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s) --- 71 unchanged lines hidden (view full) --- 80system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written 81system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 82system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 83system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 84system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 85system.cpu.num_mem_refs 122219137 # number of memory refs 86system.cpu.num_load_insts 90779385 # Number of load instructions 87system.cpu.num_store_insts 31439752 # Number of store instructions |
| 88system.cpu.num_idle_cycles 0 # Number of idle cycles 89system.cpu.num_busy_cycles 731978130 # Number of busy cycles 90system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 91system.cpu.idle_fraction 0 # Percentage of idle cycles | 88system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 89system.cpu.num_busy_cycles 731978129.998000 # Number of busy cycles 90system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 91system.cpu.idle_fraction 0.000000 # Percentage of idle cycles |
| 92system.cpu.Branches 29309705 # Number of branches fetched 93system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 94system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 95system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 96system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 97system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction 98system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction 99system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 122system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 123system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction 124system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction 125system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 126system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 127system.cpu.op_class::total 278192465 # Class of executed instruction 128system.cpu.icache.tags.replacements 24 # number of replacements 129system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use | 92system.cpu.Branches 29309705 # Number of branches fetched 93system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 94system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 95system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 96system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 97system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction 98system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction 99system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 122system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 123system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction 124system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction 125system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 126system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 127system.cpu.op_class::total 278192465 # Class of executed instruction 128system.cpu.icache.tags.replacements 24 # number of replacements 129system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use |
| 130system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. | 130system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. |
| 131system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. | 131system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. |
| 132system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. | 132system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. |
| 133system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 134system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor 135system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 136system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy 137system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 138system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 139system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 140system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 141system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id | 133system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 134system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor 135system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 136system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy 137system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 138system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 139system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 140system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 141system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id |
| 142system.cpu.icache.tags.tag_accesses 435393138 # Number of tag accesses 143system.cpu.icache.tags.data_accesses 435393138 # Number of data accesses 144system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits 145system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits 146system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits 147system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits 148system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits 149system.cpu.icache.overall_hits::total 217695357 # number of overall hits | 142system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses 143system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses 144system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits 145system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits 146system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits 147system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits 148system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits 149system.cpu.icache.overall_hits::total 217695356 # number of overall hits |
| 150system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 151system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 152system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 153system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 154system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 155system.cpu.icache.overall_misses::total 808 # number of overall misses 156system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles 157system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles 158system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles 159system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles 160system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles 161system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles | 150system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 151system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 152system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 153system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 154system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 155system.cpu.icache.overall_misses::total 808 # number of overall misses 156system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles 157system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles 158system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles 159system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles 160system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles 161system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles |
| 162system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses) 163system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses) 164system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses 165system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses 166system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses 167system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses | 162system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) 163system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) 164system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses 165system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses 166system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses 167system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses |
| 168system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 169system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 170system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 171system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 172system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 173system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 174system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency 175system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency --- 325 unchanged lines hidden --- | 168system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 169system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 170system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 171system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 172system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 173system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 174system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency 175system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency --- 325 unchanged lines hidden --- |