stats.txt (8835:7c68f84d7c4e) stats.txt (8983:8800b05e1cb3)
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.370011 # Number of seconds simulated
4sim_ticks 370010840000 # Number of ticks simulated
5final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.370011 # Number of seconds simulated
4sim_ticks 370010840000 # Number of ticks simulated
5final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 912216 # Simulator instruction rate (inst/s)
8host_op_rate 1606265 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2136418129 # Simulator tick rate (ticks/s)
10host_mem_usage 353708 # Number of bytes of host memory used
11host_seconds 173.19 # Real time elapsed on the host
7host_inst_rate 306323 # Simulator instruction rate (inst/s)
8host_op_rate 539385 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 717411215 # Simulator tick rate (ticks/s)
10host_mem_usage 359620 # Number of bytes of host memory used
11host_seconds 515.76 # Real time elapsed on the host
12sim_insts 157988583 # Number of instructions simulated
13sim_ops 278192520 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 4900800 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 1885440 # Number of bytes written to this memory
17system.physmem.num_reads 76575 # Number of read requests responded to by this memory
18system.physmem.num_writes 29460 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.workload.num_syscalls 444 # Number of system calls
25system.cpu.numCycles 740021680 # number of cpu cycles simulated
26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
28system.cpu.committedInsts 157988583 # Number of instructions committed
29system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
30system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
31system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
32system.cpu.num_func_calls 0 # number of times a function call or return occured
33system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
34system.cpu.num_int_insts 278186228 # number of integer instructions
35system.cpu.num_fp_insts 40 # number of float instructions
36system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
37system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
38system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
39system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
40system.cpu.num_mem_refs 122219139 # number of memory refs
41system.cpu.num_load_insts 90779388 # Number of load instructions
42system.cpu.num_store_insts 31439751 # Number of store instructions
43system.cpu.num_idle_cycles 0 # Number of idle cycles
44system.cpu.num_busy_cycles 740021680 # Number of busy cycles
45system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
46system.cpu.idle_fraction 0 # Percentage of idle cycles
47system.cpu.icache.replacements 24 # number of replacements
48system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
49system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
50system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
51system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
52system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
53system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor
54system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy
55system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy
56system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
57system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits
58system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits
59system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits
60system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits
61system.cpu.icache.overall_hits::total 217695401 # number of overall hits
62system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
63system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
64system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
65system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
66system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
67system.cpu.icache.overall_misses::total 808 # number of overall misses
68system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles
69system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles
70system.cpu.icache.demand_miss_latency::cpu.inst 45248000 # number of demand (read+write) miss cycles
71system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles
72system.cpu.icache.overall_miss_latency::cpu.inst 45248000 # number of overall miss cycles
73system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles
74system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses)
75system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses)
76system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses
77system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses
78system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses
79system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses
80system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
81system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
82system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
83system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
84system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
85system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
86system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
87system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
88system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
89system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
12sim_insts 157988583 # Number of instructions simulated
13sim_ops 278192520 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 4900800 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 1885440 # Number of bytes written to this memory
17system.physmem.num_reads 76575 # Number of read requests responded to by this memory
18system.physmem.num_writes 29460 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.workload.num_syscalls 444 # Number of system calls
25system.cpu.numCycles 740021680 # number of cpu cycles simulated
26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
28system.cpu.committedInsts 157988583 # Number of instructions committed
29system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
30system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
31system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
32system.cpu.num_func_calls 0 # number of times a function call or return occured
33system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
34system.cpu.num_int_insts 278186228 # number of integer instructions
35system.cpu.num_fp_insts 40 # number of float instructions
36system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
37system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
38system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
39system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
40system.cpu.num_mem_refs 122219139 # number of memory refs
41system.cpu.num_load_insts 90779388 # Number of load instructions
42system.cpu.num_store_insts 31439751 # Number of store instructions
43system.cpu.num_idle_cycles 0 # Number of idle cycles
44system.cpu.num_busy_cycles 740021680 # Number of busy cycles
45system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
46system.cpu.idle_fraction 0 # Percentage of idle cycles
47system.cpu.icache.replacements 24 # number of replacements
48system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
49system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
50system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
51system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
52system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
53system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor
54system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy
55system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy
56system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
57system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits
58system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits
59system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits
60system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits
61system.cpu.icache.overall_hits::total 217695401 # number of overall hits
62system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
63system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
64system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
65system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
66system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
67system.cpu.icache.overall_misses::total 808 # number of overall misses
68system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles
69system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles
70system.cpu.icache.demand_miss_latency::cpu.inst 45248000 # number of demand (read+write) miss cycles
71system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles
72system.cpu.icache.overall_miss_latency::cpu.inst 45248000 # number of overall miss cycles
73system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles
74system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses)
75system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses)
76system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses
77system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses
78system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses
79system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses
80system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
81system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
82system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
83system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
84system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
85system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
86system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
87system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
88system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
89system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
90system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
91system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
90system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
91system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
92system.cpu.icache.fast_writes 0 # number of fast writes performed
93system.cpu.icache.cache_copies 0 # number of cache copies performed
94system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
95system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
96system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
97system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
98system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
99system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
100system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles
101system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles
102system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles
103system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles
104system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
105system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles
106system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
107system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
108system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
109system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
110system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
111system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
112system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
113system.cpu.dcache.replacements 2062733 # number of replacements
114system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
115system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
116system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
117system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
118system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
119system.cpu.dcache.occ_blocks::cpu.data 4076.661903 # Average occupied blocks per requestor
120system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy
121system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy
122system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits
123system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits
124system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
125system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
126system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits
127system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits
128system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits
129system.cpu.dcache.overall_hits::total 120152372 # number of overall hits
130system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
131system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
132system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
133system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
134system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
135system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
136system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
137system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
138system.cpu.dcache.ReadReq_miss_latency::cpu.data 28849058000 # number of ReadReq miss cycles
139system.cpu.dcache.ReadReq_miss_latency::total 28849058000 # number of ReadReq miss cycles
140system.cpu.dcache.WriteReq_miss_latency::cpu.data 3268793000 # number of WriteReq miss cycles
141system.cpu.dcache.WriteReq_miss_latency::total 3268793000 # number of WriteReq miss cycles
142system.cpu.dcache.demand_miss_latency::cpu.data 32117851000 # number of demand (read+write) miss cycles
143system.cpu.dcache.demand_miss_latency::total 32117851000 # number of demand (read+write) miss cycles
144system.cpu.dcache.overall_miss_latency::cpu.data 32117851000 # number of overall miss cycles
145system.cpu.dcache.overall_miss_latency::total 32117851000 # number of overall miss cycles
146system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses)
147system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses)
148system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
149system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
150system.cpu.dcache.demand_accesses::cpu.data 122219201 # number of demand (read+write) accesses
151system.cpu.dcache.demand_accesses::total 122219201 # number of demand (read+write) accesses
152system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses
153system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses
154system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
155system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
156system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
157system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
158system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency
159system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency
160system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
161system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
162system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
163system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
164system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
165system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
92system.cpu.icache.fast_writes 0 # number of fast writes performed
93system.cpu.icache.cache_copies 0 # number of cache copies performed
94system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
95system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
96system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
97system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
98system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
99system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
100system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles
101system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles
102system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles
103system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles
104system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
105system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles
106system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
107system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
108system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
109system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
110system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
111system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
112system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
113system.cpu.dcache.replacements 2062733 # number of replacements
114system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
115system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
116system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
117system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
118system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
119system.cpu.dcache.occ_blocks::cpu.data 4076.661903 # Average occupied blocks per requestor
120system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy
121system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy
122system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits
123system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits
124system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
125system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
126system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits
127system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits
128system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits
129system.cpu.dcache.overall_hits::total 120152372 # number of overall hits
130system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
131system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
132system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
133system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
134system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
135system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
136system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
137system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
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139system.cpu.dcache.ReadReq_miss_latency::total 28849058000 # number of ReadReq miss cycles
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149system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
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175system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
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284system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
285system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses
286system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses
287system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
288system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses
289system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses
290system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles
291system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles
292system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles
293system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles
294system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles
295system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles
296system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles
297system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles
298system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles
299system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles
300system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles
301system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
302system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses
303system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses
304system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
305system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses
306system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
307system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses
308system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
309system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
310system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
311system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
312system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
313system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
314system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
315system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
316
317---------- End Simulation Statistics ----------
275system.cpu.l2cache.fast_writes 0 # number of fast writes performed
276system.cpu.l2cache.cache_copies 0 # number of cache copies performed
277system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks
278system.cpu.l2cache.writebacks::total 29460 # number of writebacks
279system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
280system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33309 # number of ReadReq MSHR misses
281system.cpu.l2cache.ReadReq_mshr_misses::total 34117 # number of ReadReq MSHR misses
282system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42458 # number of ReadExReq MSHR misses
283system.cpu.l2cache.ReadExReq_mshr_misses::total 42458 # number of ReadExReq MSHR misses
284system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
285system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses
286system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses
287system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
288system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses
289system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses
290system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles
291system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles
292system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles
293system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles
294system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles
295system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles
296system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles
297system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles
298system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles
299system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles
300system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles
301system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
302system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses
303system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses
304system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
305system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses
306system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
307system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses
308system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
309system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
310system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
311system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
312system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
313system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
314system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
315system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
316
317---------- End Simulation Statistics ----------