Cross Reference: /gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt

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stats.txt (10726:8a20e2a1562d)	stats.txt (10827:7f5467f2f8b8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated 4sim_ticks 365989065500 # Number of ticks simulated 5final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated 4sim_ticks 365989065500 # Number of ticks simulated 5final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 638452 # Simulator instruction rate (inst/s) 8host_op_rate 1124211 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1479007835 # Simulator tick rate (ticks/s) 10host_mem_usage 450980 # Number of bytes of host memory used 11host_seconds 247.46 # Real time elapsed on the host	7host_inst_rate 678113 # Simulator instruction rate (inst/s) 8host_op_rate 1194048 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1570885616 # Simulator tick rate (ticks/s) 10host_mem_usage 451452 # Number of bytes of host memory used 11host_seconds 232.98 # Real time elapsed on the host
12sim_insts 157988548 # Number of instructions simulated 13sim_ops 278192465 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6400 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 100 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 41system.cpu.workload.num_syscalls 444 # Number of system calls 42system.cpu.numCycles 731978131 # number of cpu cycles simulated 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 157988548 # Number of instructions committed 46system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 49system.cpu.num_func_calls 8475189 # number of times a function call or return occured 50system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls 51system.cpu.num_int_insts 278169482 # number of integer instructions 52system.cpu.num_fp_insts 40 # number of float instructions 53system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read 54system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written 55system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 56system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 57system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 58system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 59system.cpu.num_mem_refs 122219137 # number of memory refs 60system.cpu.num_load_insts 90779385 # Number of load instructions 61system.cpu.num_store_insts 31439752 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 63system.cpu.num_busy_cycles 731978130.998000 # Number of busy cycles 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 29309705 # Number of branches fetched 67system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 68system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 69system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 70system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 71system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction 72system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction 73system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction 74system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction 75system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction 76system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction 77system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction 78system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction 79system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction 80system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction 81system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction 82system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction 83system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction 84system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction 85system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction 86system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction 87system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction 88system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction 89system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction 90system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction 91system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction 92system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction 93system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction 94system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 97system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction 98system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 278192465 # Class of executed instruction 102system.cpu.dcache.tags.replacements 2062733 # number of replacements 103system.cpu.dcache.tags.tagsinuse 4076.488607 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 126079702000 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488607 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 116system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 117system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses 118system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses 119system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits 120system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits 121system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 122system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 123system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits 124system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits 125system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits 126system.cpu.dcache.overall_hits::total 120152370 # number of overall hits 127system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 128system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 129system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 130system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 131system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 132system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 133system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 134system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 135system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles 136system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles 137system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles 139system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles 140system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles 141system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles 142system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles 143system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) 144system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) 145system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 146system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 147system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses 148system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses 149system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 150system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses 151system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 152system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 153system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 154system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 155system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 156system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 157system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 158system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 159system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency 160system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency 161system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency 163system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 164system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency 165system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency 167system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 168system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 169system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 173system.cpu.dcache.fast_writes 0 # number of fast writes performed 174system.cpu.dcache.cache_copies 0 # number of cache copies performed 175system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks 176system.cpu.dcache.writebacks::total 2062484 # number of writebacks 177system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 178system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 181system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 182system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 183system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 184system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 185system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22557604000 # number of ReadReq MSHR miss cycles 186system.cpu.dcache.ReadReq_mshr_miss_latency::total 22557604000 # number of ReadReq MSHR miss cycles 187system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2439292500 # number of WriteReq MSHR miss cycles 188system.cpu.dcache.WriteReq_mshr_miss_latency::total 2439292500 # number of WriteReq MSHR miss cycles 189system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24996896500 # number of demand (read+write) MSHR miss cycles 190system.cpu.dcache.demand_mshr_miss_latency::total 24996896500 # number of demand (read+write) MSHR miss cycles 191system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24996896500 # number of overall MSHR miss cycles 192system.cpu.dcache.overall_mshr_miss_latency::total 24996896500 # number of overall MSHR miss cycles 193system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 194system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 195system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 196system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 197system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 198system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 199system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 200system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396 # average ReadReq mshr miss latency 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396 # average ReadReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223 # average WriteReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223 # average WriteReq mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency 209system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 210system.cpu.icache.tags.replacements 24 # number of replacements 211system.cpu.icache.tags.tagsinuse 665.632506 # Cycle average of tags in use 212system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. 213system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 214system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. 215system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.icache.tags.occ_blocks::cpu.inst 665.632506 # Average occupied blocks per requestor 217system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 218system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy 219system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 223system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id 224system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses 225system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses 226system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits 227system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits 228system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits 229system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits 230system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits 231system.cpu.icache.overall_hits::total 217695356 # number of overall hits 232system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 233system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 234system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 235system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 236system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 237system.cpu.icache.overall_misses::total 808 # number of overall misses 238system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230500 # number of ReadReq miss cycles 239system.cpu.icache.ReadReq_miss_latency::total 44230500 # number of ReadReq miss cycles 240system.cpu.icache.demand_miss_latency::cpu.inst 44230500 # number of demand (read+write) miss cycles 241system.cpu.icache.demand_miss_latency::total 44230500 # number of demand (read+write) miss cycles 242system.cpu.icache.overall_miss_latency::cpu.inst 44230500 # number of overall miss cycles 243system.cpu.icache.overall_miss_latency::total 44230500 # number of overall miss cycles 244system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) 245system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) 246system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses 247system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses 248system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses 249system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses 250system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 251system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 252system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 253system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 254system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 255system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 256system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822 # average ReadReq miss latency 257system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822 # average ReadReq miss latency 258system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency 259system.cpu.icache.demand_avg_miss_latency::total 54740.717822 # average overall miss latency 260system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency 261system.cpu.icache.overall_avg_miss_latency::total 54740.717822 # average overall miss latency 262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 268system.cpu.icache.fast_writes 0 # number of fast writes performed 269system.cpu.icache.cache_copies 0 # number of cache copies performed 270system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 271system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 272system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 273system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 274system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 275system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses 276system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43018500 # number of ReadReq MSHR miss cycles 277system.cpu.icache.ReadReq_mshr_miss_latency::total 43018500 # number of ReadReq MSHR miss cycles 278system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43018500 # number of demand (read+write) MSHR miss cycles 279system.cpu.icache.demand_mshr_miss_latency::total 43018500 # number of demand (read+write) MSHR miss cycles 280system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43018500 # number of overall MSHR miss cycles 281system.cpu.icache.overall_mshr_miss_latency::total 43018500 # number of overall MSHR miss cycles 282system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 283system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 284system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 285system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 287system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53240.717822 # average ReadReq mshr miss latency 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53240.717822 # average ReadReq mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency 294system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 295system.cpu.l2cache.tags.replacements 318 # number of replacements 296system.cpu.l2cache.tags.tagsinuse 20041.899592 # Cycle average of tags in use 297system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. 298system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. 299system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. 300system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 301system.cpu.l2cache.tags.occ_blocks::writebacks 19330.352993 # Average occupied blocks per requestor 302system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646380 # Average occupied blocks per requestor 303system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor 304system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy 305system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy 306system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id 309system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 312system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id 313system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id 314system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id 315system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses 316system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses 317system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits 318system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits 319system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits 320system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits 321system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits 322system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits 323system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits 324system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits 325system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits 326system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits 327system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits 328system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits 329system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits 330system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses 331system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses 332system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses 333system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses 334system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses 335system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 336system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses 337system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses 338system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses 339system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses 340system.cpu.l2cache.overall_misses::total 30049 # number of overall misses 341system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42158000 # number of ReadReq miss cycles 342system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11655000 # number of ReadReq miss cycles 343system.cpu.l2cache.ReadReq_miss_latency::total 53813000 # number of ReadReq miss cycles 344system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1523791000 # number of ReadExReq miss cycles 345system.cpu.l2cache.ReadExReq_miss_latency::total 1523791000 # number of ReadExReq miss cycles 346system.cpu.l2cache.demand_miss_latency::cpu.inst 42158000 # number of demand (read+write) miss cycles 347system.cpu.l2cache.demand_miss_latency::cpu.data 1535446000 # number of demand (read+write) miss cycles 348system.cpu.l2cache.demand_miss_latency::total 1577604000 # number of demand (read+write) miss cycles 349system.cpu.l2cache.overall_miss_latency::cpu.inst 42158000 # number of overall miss cycles 350system.cpu.l2cache.overall_miss_latency::cpu.data 1535446000 # number of overall miss cycles 351system.cpu.l2cache.overall_miss_latency::total 1577604000 # number of overall miss cycles 352system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) 353system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) 354system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) 355system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses) 356system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses) 357system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 358system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 359system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses 360system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses 361system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses 362system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses 363system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses 364system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses 365system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses 366system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses 367system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses 368system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses 369system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses 370system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses 371system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses 372system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses 373system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses 374system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses 375system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses 376system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.622665 # average ReadReq miss latency 377system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency 378system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.487805 # average ReadReq miss latency 379system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency 380system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency 381system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency 382system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency 383system.cpu.l2cache.demand_avg_miss_latency::total 52501.048288 # average overall miss latency 384system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency 385system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency 386system.cpu.l2cache.overall_avg_miss_latency::total 52501.048288 # average overall miss latency 387system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 388system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 389system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 391system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 392system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 393system.cpu.l2cache.fast_writes 0 # number of fast writes performed 394system.cpu.l2cache.cache_copies 0 # number of cache copies performed 395system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks 396system.cpu.l2cache.writebacks::total 100 # number of writebacks 397system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses 398system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses 399system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses 400system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 401system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 402system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 403system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses 404system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses 405system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 406system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses 407system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses 408system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32521500 # number of ReadReq MSHR miss cycles 409system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8991000 # number of ReadReq MSHR miss cycles 410system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41512500 # number of ReadReq MSHR miss cycles 411system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1175472000 # number of ReadExReq MSHR miss cycles 412system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1175472000 # number of ReadExReq MSHR miss cycles 413system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32521500 # number of demand (read+write) MSHR miss cycles 414system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1184463000 # number of demand (read+write) MSHR miss cycles 415system.cpu.l2cache.demand_mshr_miss_latency::total 1216984500 # number of demand (read+write) MSHR miss cycles 416system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32521500 # number of overall MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1184463000 # number of overall MSHR miss cycles 418system.cpu.l2cache.overall_mshr_miss_latency::total 1216984500 # number of overall MSHR miss cycles 419system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses 420system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses 421system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses 422system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses 423system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses 424system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses 425system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses 426system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses 427system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses 428system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses 429system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses 430system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency 431system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 432system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency 433system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 434system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 435system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 436system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 437system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 438system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 439system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 440system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 441system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 444system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 447system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) 450system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) 451system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) 452system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) 453system.cpu.toL2Bus.snoops 0 # Total snoops (count) 454system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram	12sim_insts 157988548 # Number of instructions simulated 13sim_ops 278192465 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6400 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 100 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 41system.cpu.workload.num_syscalls 444 # Number of system calls 42system.cpu.numCycles 731978131 # number of cpu cycles simulated 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 157988548 # Number of instructions committed 46system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 49system.cpu.num_func_calls 8475189 # number of times a function call or return occured 50system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls 51system.cpu.num_int_insts 278169482 # number of integer instructions 52system.cpu.num_fp_insts 40 # number of float instructions 53system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read 54system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written 55system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 56system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 57system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 58system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 59system.cpu.num_mem_refs 122219137 # number of memory refs 60system.cpu.num_load_insts 90779385 # Number of load instructions 61system.cpu.num_store_insts 31439752 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 63system.cpu.num_busy_cycles 731978130.998000 # Number of busy cycles 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 29309705 # Number of branches fetched 67system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 68system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 69system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 70system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 71system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction 72system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction 73system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction 74system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction 75system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction 76system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction 77system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction 78system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction 79system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction 80system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction 81system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction 82system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction 83system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction 84system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction 85system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction 86system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction 87system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction 88system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction 89system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction 90system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction 91system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction 92system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction 93system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction 94system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 97system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction 98system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 278192465 # Class of executed instruction 102system.cpu.dcache.tags.replacements 2062733 # number of replacements 103system.cpu.dcache.tags.tagsinuse 4076.488607 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 126079702000 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488607 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 116system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 117system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses 118system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses 119system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits 120system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits 121system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 122system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 123system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits 124system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits 125system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits 126system.cpu.dcache.overall_hits::total 120152370 # number of overall hits 127system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 128system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 129system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 130system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 131system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 132system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 133system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 134system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 135system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles 136system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles 137system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles 139system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles 140system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles 141system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles 142system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles 143system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) 144system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) 145system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 146system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 147system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses 148system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses 149system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 150system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses 151system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 152system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 153system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 154system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 155system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 156system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 157system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 158system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 159system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency 160system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency 161system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency 163system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 164system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency 165system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency 167system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 168system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 169system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 171system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 173system.cpu.dcache.fast_writes 0 # number of fast writes performed 174system.cpu.dcache.cache_copies 0 # number of cache copies performed 175system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks 176system.cpu.dcache.writebacks::total 2062484 # number of writebacks 177system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 178system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 181system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 182system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 183system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 184system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 185system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22557604000 # number of ReadReq MSHR miss cycles 186system.cpu.dcache.ReadReq_mshr_miss_latency::total 22557604000 # number of ReadReq MSHR miss cycles 187system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2439292500 # number of WriteReq MSHR miss cycles 188system.cpu.dcache.WriteReq_mshr_miss_latency::total 2439292500 # number of WriteReq MSHR miss cycles 189system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24996896500 # number of demand (read+write) MSHR miss cycles 190system.cpu.dcache.demand_mshr_miss_latency::total 24996896500 # number of demand (read+write) MSHR miss cycles 191system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24996896500 # number of overall MSHR miss cycles 192system.cpu.dcache.overall_mshr_miss_latency::total 24996896500 # number of overall MSHR miss cycles 193system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 194system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 195system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 196system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 197system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 198system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 199system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 200system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396 # average ReadReq mshr miss latency 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396 # average ReadReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223 # average WriteReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223 # average WriteReq mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency 209system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 210system.cpu.icache.tags.replacements 24 # number of replacements 211system.cpu.icache.tags.tagsinuse 665.632506 # Cycle average of tags in use 212system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. 213system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 214system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. 215system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.icache.tags.occ_blocks::cpu.inst 665.632506 # Average occupied blocks per requestor 217system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 218system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy 219system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 223system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id 224system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses 225system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses 226system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits 227system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits 228system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits 229system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits 230system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits 231system.cpu.icache.overall_hits::total 217695356 # number of overall hits 232system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 233system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 234system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 235system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 236system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 237system.cpu.icache.overall_misses::total 808 # number of overall misses 238system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230500 # number of ReadReq miss cycles 239system.cpu.icache.ReadReq_miss_latency::total 44230500 # number of ReadReq miss cycles 240system.cpu.icache.demand_miss_latency::cpu.inst 44230500 # number of demand (read+write) miss cycles 241system.cpu.icache.demand_miss_latency::total 44230500 # number of demand (read+write) miss cycles 242system.cpu.icache.overall_miss_latency::cpu.inst 44230500 # number of overall miss cycles 243system.cpu.icache.overall_miss_latency::total 44230500 # number of overall miss cycles 244system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) 245system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) 246system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses 247system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses 248system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses 249system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses 250system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 251system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 252system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 253system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 254system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 255system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 256system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822 # average ReadReq miss latency 257system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822 # average ReadReq miss latency 258system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency 259system.cpu.icache.demand_avg_miss_latency::total 54740.717822 # average overall miss latency 260system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency 261system.cpu.icache.overall_avg_miss_latency::total 54740.717822 # average overall miss latency 262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 268system.cpu.icache.fast_writes 0 # number of fast writes performed 269system.cpu.icache.cache_copies 0 # number of cache copies performed 270system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 271system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 272system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 273system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 274system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 275system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses 276system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43018500 # number of ReadReq MSHR miss cycles 277system.cpu.icache.ReadReq_mshr_miss_latency::total 43018500 # number of ReadReq MSHR miss cycles 278system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43018500 # number of demand (read+write) MSHR miss cycles 279system.cpu.icache.demand_mshr_miss_latency::total 43018500 # number of demand (read+write) MSHR miss cycles 280system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43018500 # number of overall MSHR miss cycles 281system.cpu.icache.overall_mshr_miss_latency::total 43018500 # number of overall MSHR miss cycles 282system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 283system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 284system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 285system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 287system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53240.717822 # average ReadReq mshr miss latency 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53240.717822 # average ReadReq mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency 294system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 295system.cpu.l2cache.tags.replacements 318 # number of replacements 296system.cpu.l2cache.tags.tagsinuse 20041.899592 # Cycle average of tags in use 297system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. 298system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. 299system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. 300system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 301system.cpu.l2cache.tags.occ_blocks::writebacks 19330.352993 # Average occupied blocks per requestor 302system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646380 # Average occupied blocks per requestor 303system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor 304system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy 305system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy 306system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id 309system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 312system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id 313system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id 314system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id 315system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses 316system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses 317system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits 318system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits 319system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits 320system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits 321system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits 322system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits 323system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits 324system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits 325system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits 326system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits 327system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits 328system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits 329system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits 330system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses 331system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses 332system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses 333system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses 334system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses 335system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 336system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses 337system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses 338system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses 339system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses 340system.cpu.l2cache.overall_misses::total 30049 # number of overall misses 341system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42158000 # number of ReadReq miss cycles 342system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11655000 # number of ReadReq miss cycles 343system.cpu.l2cache.ReadReq_miss_latency::total 53813000 # number of ReadReq miss cycles 344system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1523791000 # number of ReadExReq miss cycles 345system.cpu.l2cache.ReadExReq_miss_latency::total 1523791000 # number of ReadExReq miss cycles 346system.cpu.l2cache.demand_miss_latency::cpu.inst 42158000 # number of demand (read+write) miss cycles 347system.cpu.l2cache.demand_miss_latency::cpu.data 1535446000 # number of demand (read+write) miss cycles 348system.cpu.l2cache.demand_miss_latency::total 1577604000 # number of demand (read+write) miss cycles 349system.cpu.l2cache.overall_miss_latency::cpu.inst 42158000 # number of overall miss cycles 350system.cpu.l2cache.overall_miss_latency::cpu.data 1535446000 # number of overall miss cycles 351system.cpu.l2cache.overall_miss_latency::total 1577604000 # number of overall miss cycles 352system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) 353system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) 354system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) 355system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses) 356system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses) 357system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 358system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 359system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses 360system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses 361system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses 362system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses 363system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses 364system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses 365system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses 366system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses 367system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses 368system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses 369system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses 370system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses 371system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses 372system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses 373system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses 374system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses 375system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses 376system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.622665 # average ReadReq miss latency 377system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency 378system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.487805 # average ReadReq miss latency 379system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency 380system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency 381system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency 382system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency 383system.cpu.l2cache.demand_avg_miss_latency::total 52501.048288 # average overall miss latency 384system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency 385system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency 386system.cpu.l2cache.overall_avg_miss_latency::total 52501.048288 # average overall miss latency 387system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 388system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 389system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 391system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 392system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 393system.cpu.l2cache.fast_writes 0 # number of fast writes performed 394system.cpu.l2cache.cache_copies 0 # number of cache copies performed 395system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks 396system.cpu.l2cache.writebacks::total 100 # number of writebacks 397system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses 398system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses 399system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses 400system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 401system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 402system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 403system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses 404system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses 405system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 406system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses 407system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses 408system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32521500 # number of ReadReq MSHR miss cycles 409system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8991000 # number of ReadReq MSHR miss cycles 410system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41512500 # number of ReadReq MSHR miss cycles 411system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1175472000 # number of ReadExReq MSHR miss cycles 412system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1175472000 # number of ReadExReq MSHR miss cycles 413system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32521500 # number of demand (read+write) MSHR miss cycles 414system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1184463000 # number of demand (read+write) MSHR miss cycles 415system.cpu.l2cache.demand_mshr_miss_latency::total 1216984500 # number of demand (read+write) MSHR miss cycles 416system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32521500 # number of overall MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1184463000 # number of overall MSHR miss cycles 418system.cpu.l2cache.overall_mshr_miss_latency::total 1216984500 # number of overall MSHR miss cycles 419system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses 420system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses 421system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses 422system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses 423system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses 424system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses 425system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses 426system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses 427system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses 428system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses 429system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses 430system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency 431system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 432system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency 433system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 434system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 435system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 436system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 437system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 438system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 439system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 440system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 441system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 444system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 447system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) 450system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) 451system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) 452system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) 453system.cpu.toL2Bus.snoops 0 # Total snoops (count) 454system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram
455system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram	455system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
456system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram	456system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
459system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 461system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram 462system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram	459system.cpu.toL2Bus.snoop_fanout::1 4130121 100.00% 100.00% # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
463system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram	461system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
464system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 465system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram	462system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 463system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
466system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram 467system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) 468system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 469system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 470system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 471system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 472system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 473system.membus.trans_dist::ReadReq 1025 # Transaction distribution 474system.membus.trans_dist::ReadResp 1025 # Transaction distribution 475system.membus.trans_dist::Writeback 100 # Transaction distribution 476system.membus.trans_dist::ReadExReq 29024 # Transaction distribution 477system.membus.trans_dist::ReadExResp 29024 # Transaction distribution 478system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) 479system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) 480system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) 481system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) 482system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) 483system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) 484system.membus.snoops 0 # Total snoops (count) 485system.membus.snoop_fanout::samples 30149 # Request fanout histogram 486system.membus.snoop_fanout::mean 0 # Request fanout histogram 487system.membus.snoop_fanout::stdev 0 # Request fanout histogram 488system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 489system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram 490system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 491system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 492system.membus.snoop_fanout::min_value 0 # Request fanout histogram 493system.membus.snoop_fanout::max_value 0 # Request fanout histogram 494system.membus.snoop_fanout::total 30149 # Request fanout histogram 495system.membus.reqLayer0.occupancy 30585000 # Layer occupancy (ticks) 496system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 497system.membus.respLayer1.occupancy 150276500 # Layer occupancy (ticks) 498system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 499 500---------- End Simulation Statistics ----------	464system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram 465system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) 466system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 467system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 468system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 469system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 470system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 471system.membus.trans_dist::ReadReq 1025 # Transaction distribution 472system.membus.trans_dist::ReadResp 1025 # Transaction distribution 473system.membus.trans_dist::Writeback 100 # Transaction distribution 474system.membus.trans_dist::ReadExReq 29024 # Transaction distribution 475system.membus.trans_dist::ReadExResp 29024 # Transaction distribution 476system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) 477system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) 478system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) 479system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) 480system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) 481system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) 482system.membus.snoops 0 # Total snoops (count) 483system.membus.snoop_fanout::samples 30149 # Request fanout histogram 484system.membus.snoop_fanout::mean 0 # Request fanout histogram 485system.membus.snoop_fanout::stdev 0 # Request fanout histogram 486system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 487system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram 488system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 489system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 490system.membus.snoop_fanout::min_value 0 # Request fanout histogram 491system.membus.snoop_fanout::max_value 0 # Request fanout histogram 492system.membus.snoop_fanout::total 30149 # Request fanout histogram 493system.membus.reqLayer0.occupancy 30585000 # Layer occupancy (ticks) 494system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 495system.membus.respLayer1.occupancy 150276500 # Layer occupancy (ticks) 496system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 497 498---------- End Simulation Statistics ----------