Cross Reference: /gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt

stats.txt (10220:9eab5efc02e8)	stats.txt (10409:8c80b91944c5)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated 4sim_ticks 365989065000 # Number of ticks simulated 5final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated 4sim_ticks 365989065000 # Number of ticks simulated 5final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 596728 # Simulator instruction rate (inst/s) 8host_op_rate 1050742 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1382352440 # Simulator tick rate (ticks/s) 10host_mem_usage 424660 # Number of bytes of host memory used 11host_seconds 264.76 # Real time elapsed on the host	7host_inst_rate 756908 # Simulator instruction rate (inst/s) 8host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1753418925 # Simulator tick rate (ticks/s) 10host_mem_usage 446124 # Number of bytes of host memory used 11host_seconds 208.73 # Real time elapsed on the host
12sim_insts 157988548 # Number of instructions simulated 13sim_ops 278192465 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6400 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 100 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)	12sim_insts 157988548 # Number of instructions simulated 13sim_ops 278192465 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6400 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 100 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
39system.membus.throughput 5272114 # Throughput (bytes/s)
40system.membus.trans_dist::ReadReq 1025 # Transaction distribution 41system.membus.trans_dist::ReadResp 1025 # Transaction distribution 42system.membus.trans_dist::Writeback 100 # Transaction distribution 43system.membus.trans_dist::ReadExReq 29024 # Transaction distribution 44system.membus.trans_dist::ReadExResp 29024 # Transaction distribution 45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) 47system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)	39system.membus.trans_dist::ReadReq 1025 # Transaction distribution 40system.membus.trans_dist::ReadResp 1025 # Transaction distribution 41system.membus.trans_dist::Writeback 100 # Transaction distribution 42system.membus.trans_dist::ReadExReq 29024 # Transaction distribution 43system.membus.trans_dist::ReadExResp 29024 # Transaction distribution 44system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
48system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) 49system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) 50system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) 51system.membus.data_through_bus 1929536 # Total data (bytes) 52system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)	47system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) 48system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) 49system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) 50system.membus.snoops 0 # Total snoops (count) 51system.membus.snoop_fanout::samples 30149 # Request fanout histogram 52system.membus.snoop_fanout::mean 0 # Request fanout histogram 53system.membus.snoop_fanout::stdev 0 # Request fanout histogram 54system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 55system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram 56system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 57system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 58system.membus.snoop_fanout::min_value 0 # Request fanout histogram 59system.membus.snoop_fanout::max_value 0 # Request fanout histogram 60system.membus.snoop_fanout::total 30149 # Request fanout histogram
53system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) 54system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 55system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) 56system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 57system.cpu_clk_domain.clock 500 # Clock period in ticks 58system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 59system.cpu.workload.num_syscalls 444 # Number of system calls 60system.cpu.numCycles 731978130 # number of cpu cycles simulated 61system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 62system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 63system.cpu.committedInsts 157988548 # Number of instructions committed 64system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 65system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses 66system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 67system.cpu.num_func_calls 8475189 # number of times a function call or return occured 68system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls 69system.cpu.num_int_insts 278169482 # number of integer instructions 70system.cpu.num_fp_insts 40 # number of float instructions 71system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read 72system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written 73system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 74system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 75system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 76system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 77system.cpu.num_mem_refs 122219137 # number of memory refs 78system.cpu.num_load_insts 90779385 # Number of load instructions 79system.cpu.num_store_insts 31439752 # Number of store instructions 80system.cpu.num_idle_cycles 0 # Number of idle cycles 81system.cpu.num_busy_cycles 731978130 # Number of busy cycles 82system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 83system.cpu.idle_fraction 0 # Percentage of idle cycles 84system.cpu.Branches 29309705 # Number of branches fetched 85system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 86system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 87system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 88system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 89system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction 90system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction 91system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction 92system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction 93system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction 94system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction 95system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction 96system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction 97system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction 98system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction 99system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction 100system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction 101system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction 102system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction 103system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction 104system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction 105system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction 106system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction 107system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction 108system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction 109system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction 110system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction 111system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction 112system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction 113system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction 114system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 115system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction 116system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction 117system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 118system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 119system.cpu.op_class::total 278192465 # Class of executed instruction 120system.cpu.icache.tags.replacements 24 # number of replacements 121system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use 122system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. 123system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 124system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. 125system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 126system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor 127system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 128system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy 129system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 130system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 131system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 132system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 133system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id 134system.cpu.icache.tags.tag_accesses 435393138 # Number of tag accesses 135system.cpu.icache.tags.data_accesses 435393138 # Number of data accesses 136system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits 137system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits 138system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits 139system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits 140system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits 141system.cpu.icache.overall_hits::total 217695357 # number of overall hits 142system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 143system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 144system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 145system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 146system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 147system.cpu.icache.overall_misses::total 808 # number of overall misses 148system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles 149system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles 150system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles 151system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles 152system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles 153system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles 154system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses) 155system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses) 156system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses 157system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses 158system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses 159system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses 160system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 161system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 162system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 163system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 164system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 165system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 166system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency 167system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency 168system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency 169system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency 170system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency 171system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency 172system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 173system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 174system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 175system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 176system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 177system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 178system.cpu.icache.fast_writes 0 # number of fast writes performed 179system.cpu.icache.cache_copies 0 # number of cache copies performed 180system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 181system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 182system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 183system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 184system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 185system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses 186system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles 187system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles 188system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles 189system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles 190system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles 191system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles 192system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 193system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 194system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 195system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 196system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 197system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 198system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency 199system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency 200system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 201system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 202system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 203system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 204system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 205system.cpu.l2cache.tags.replacements 318 # number of replacements 206system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use 207system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. 208system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. 209system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. 210system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 211system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor 212system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor 213system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor 214system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy 215system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy 216system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy 217system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy 218system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id 219system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 220system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 221system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 222system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id 223system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id 224system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id 225system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses 226system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses 227system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits 228system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits 229system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits 230system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits 231system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits 232system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits 233system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits 234system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits 235system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits 236system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits 237system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits 238system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits 239system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits 240system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses 241system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses 242system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses 243system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses 244system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses 245system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 246system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses 247system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses 248system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses 249system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses 250system.cpu.l2cache.overall_misses::total 30049 # number of overall misses 251system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles 252system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles 253system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles 254system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles 255system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles 256system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles 257system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles 258system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles 259system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles 260system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles 261system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles 262system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) 263system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) 264system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) 265system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses) 266system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses) 267system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 268system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 269system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses 270system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses 271system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses 272system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses 273system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses 274system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses 275system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses 276system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses 277system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses 278system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses 279system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses 280system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses 281system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses 282system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses 283system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses 284system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses 285system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses 286system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 287system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 288system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 289system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency 290system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency 291system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 292system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency 293system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency 294system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 295system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency 296system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency 297system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 303system.cpu.l2cache.fast_writes 0 # number of fast writes performed 304system.cpu.l2cache.cache_copies 0 # number of cache copies performed 305system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks 306system.cpu.l2cache.writebacks::total 100 # number of writebacks 307system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses 308system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses 309system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses 310system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 311system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 312system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 313system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses 314system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses 315system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 316system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses 317system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses 318system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles 319system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles 320system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles 321system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles 322system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles 323system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles 324system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles 325system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles 326system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles 327system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles 328system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles 329system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses 330system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses 331system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses 332system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses 333system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses 334system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses 335system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses 336system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses 337system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses 338system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses 339system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses 340system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 341system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 342system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 343system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 344system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 345system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 346system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 347system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 348system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 349system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 350system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 351system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 352system.cpu.dcache.tags.replacements 2062733 # number of replacements 353system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use 354system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. 355system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. 356system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. 357system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. 358system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor 359system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy 360system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy 361system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 362system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 363system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id 364system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id 365system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 366system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 367system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses 368system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses 369system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits 370system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits 371system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 372system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 373system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits 374system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits 375system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits 376system.cpu.dcache.overall_hits::total 120152370 # number of overall hits 377system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 378system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 379system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 380system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 381system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 382system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 383system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 384system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 385system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles 386system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles 387system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles 388system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles 389system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles 390system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles 391system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles 392system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles 393system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) 394system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) 395system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 396system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 397system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses 398system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses 399system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 400system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses 401system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 402system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 403system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 404system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 405system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 406system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 407system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 408system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 409system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency 410system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency 411system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency 412system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency 413system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 414system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency 415system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 416system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency 417system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 418system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 419system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 420system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 421system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 422system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 423system.cpu.dcache.fast_writes 0 # number of fast writes performed 424system.cpu.dcache.cache_copies 0 # number of cache copies performed 425system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks 426system.cpu.dcache.writebacks::total 2062484 # number of writebacks 427system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 428system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 429system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 430system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 431system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 432system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 433system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 434system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 435system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles 436system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles 437system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles 438system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles 439system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles 440system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles 441system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles 442system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles 443system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 444system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 445system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 446system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 447system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 448system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 449system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 450system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency 452system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency 453system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency 454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency 455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 456system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 457system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 458system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 459system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate	61system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) 62system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 63system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) 64system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 65system.cpu_clk_domain.clock 500 # Clock period in ticks 66system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 67system.cpu.workload.num_syscalls 444 # Number of system calls 68system.cpu.numCycles 731978130 # number of cpu cycles simulated 69system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 70system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 71system.cpu.committedInsts 157988548 # Number of instructions committed 72system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 73system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses 74system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 75system.cpu.num_func_calls 8475189 # number of times a function call or return occured 76system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls 77system.cpu.num_int_insts 278169482 # number of integer instructions 78system.cpu.num_fp_insts 40 # number of float instructions 79system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read 80system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written 81system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 82system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 83system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 84system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 85system.cpu.num_mem_refs 122219137 # number of memory refs 86system.cpu.num_load_insts 90779385 # Number of load instructions 87system.cpu.num_store_insts 31439752 # Number of store instructions 88system.cpu.num_idle_cycles 0 # Number of idle cycles 89system.cpu.num_busy_cycles 731978130 # Number of busy cycles 90system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 91system.cpu.idle_fraction 0 # Percentage of idle cycles 92system.cpu.Branches 29309705 # Number of branches fetched 93system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 94system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 95system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 96system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 97system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction 98system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction 99system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction 100system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction 101system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction 102system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction 103system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction 104system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction 105system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction 106system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction 107system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction 108system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction 109system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction 110system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction 111system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction 112system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction 113system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction 114system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction 115system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction 116system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction 117system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction 118system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction 119system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction 120system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction 121system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction 122system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 123system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction 124system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction 125system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 126system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 127system.cpu.op_class::total 278192465 # Class of executed instruction 128system.cpu.icache.tags.replacements 24 # number of replacements 129system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use 130system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. 131system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 132system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. 133system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 134system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor 135system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 136system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy 137system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 138system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 139system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 140system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 141system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id 142system.cpu.icache.tags.tag_accesses 435393138 # Number of tag accesses 143system.cpu.icache.tags.data_accesses 435393138 # Number of data accesses 144system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits 145system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits 146system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits 147system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits 148system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits 149system.cpu.icache.overall_hits::total 217695357 # number of overall hits 150system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 151system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 152system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 153system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 154system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 155system.cpu.icache.overall_misses::total 808 # number of overall misses 156system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles 157system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles 158system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles 159system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles 160system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles 161system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles 162system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses) 163system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses) 164system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses 165system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses 166system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses 167system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses 168system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 169system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 170system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 171system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 172system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 173system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 174system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency 175system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency 176system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency 177system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency 178system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency 179system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency 180system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 183system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 184system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 185system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 186system.cpu.icache.fast_writes 0 # number of fast writes performed 187system.cpu.icache.cache_copies 0 # number of cache copies performed 188system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 189system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 190system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 191system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 192system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 193system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses 194system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles 195system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles 196system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles 197system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles 198system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles 199system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles 200system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 201system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 202system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 203system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 204system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 205system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 206system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency 207system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency 208system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 209system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 210system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 211system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 212system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 213system.cpu.l2cache.tags.replacements 318 # number of replacements 214system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use 215system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. 216system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. 217system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. 218system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 219system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor 220system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor 221system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor 222system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy 223system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy 224system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy 225system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy 226system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id 227system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 228system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 229system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 230system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id 231system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id 232system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id 233system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses 234system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses 235system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits 236system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits 237system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits 238system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits 239system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits 240system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits 241system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits 242system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits 243system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits 244system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits 245system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits 246system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits 247system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits 248system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses 249system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses 250system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses 251system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses 252system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses 253system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 254system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses 255system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses 256system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses 257system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses 258system.cpu.l2cache.overall_misses::total 30049 # number of overall misses 259system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles 260system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles 261system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles 262system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles 263system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles 264system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles 265system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles 266system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles 267system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles 268system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles 269system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles 270system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) 271system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) 272system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) 273system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses) 274system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses) 275system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 276system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 277system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses 278system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses 279system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses 280system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses 281system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses 282system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses 283system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses 284system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses 285system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses 286system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses 287system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses 288system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses 289system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses 290system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses 291system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses 292system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses 293system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses 294system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 295system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 296system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 297system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency 298system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency 299system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 300system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency 301system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency 302system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 303system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency 304system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency 305system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 306system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 307system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 308system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 309system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 310system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 311system.cpu.l2cache.fast_writes 0 # number of fast writes performed 312system.cpu.l2cache.cache_copies 0 # number of cache copies performed 313system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks 314system.cpu.l2cache.writebacks::total 100 # number of writebacks 315system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses 316system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses 317system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses 318system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 319system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 320system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 321system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses 322system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses 323system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 324system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses 325system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses 326system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles 327system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles 328system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles 329system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles 330system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles 331system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles 332system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles 333system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles 334system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles 335system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles 336system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles 337system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses 338system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses 339system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses 340system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses 341system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses 342system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses 343system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses 344system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses 345system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses 346system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses 347system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses 348system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 349system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 350system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 351system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 352system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 353system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 354system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 355system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 356system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 357system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 358system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 359system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 360system.cpu.dcache.tags.replacements 2062733 # number of replacements 361system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use 362system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. 363system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. 364system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. 365system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. 366system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor 367system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy 368system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy 369system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 370system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 371system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id 372system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id 373system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 374system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 375system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses 376system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses 377system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits 378system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits 379system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 380system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 381system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits 382system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits 383system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits 384system.cpu.dcache.overall_hits::total 120152370 # number of overall hits 385system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 386system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 387system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 388system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 389system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 390system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 391system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 392system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 393system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles 394system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles 395system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles 396system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles 397system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles 398system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles 399system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles 400system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles 401system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) 402system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) 403system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 404system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 405system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses 406system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses 407system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 408system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses 409system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 410system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 411system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 412system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 413system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 414system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 415system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 416system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 417system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency 418system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency 419system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency 420system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency 421system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 422system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency 423system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 424system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency 425system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 426system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 427system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 428system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 429system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 430system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 431system.cpu.dcache.fast_writes 0 # number of fast writes performed 432system.cpu.dcache.cache_copies 0 # number of cache copies performed 433system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks 434system.cpu.dcache.writebacks::total 2062484 # number of writebacks 435system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 436system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 437system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 438system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 439system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 440system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 441system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 442system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 443system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles 444system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles 445system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles 446system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles 447system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles 448system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles 449system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles 450system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles 451system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 452system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 453system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 454system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 455system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 456system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 457system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 458system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 459system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency 460system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency 461system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency 462system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency 463system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 464system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 465system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 466system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 467system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
460system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s)
461system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 466system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) 467system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) 468system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes)	468system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 473system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) 474system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) 475system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes)
469system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) 470system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) 471system.cpu.toL2Bus.tot_pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) 472system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes) 473system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)	476system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) 478system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) 479system.cpu.toL2Bus.snoops 0 # Total snoops (count) 480system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 482system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 483system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 484system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 485system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 487system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram 488system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 490system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 491system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 492system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram
474system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) 475system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 476system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 477system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 478system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 479system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 480 481---------- End Simulation Statistics ----------	493system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) 494system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 495system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 496system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 497system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 498system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 499 500---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.365989 # Number of seconds simulated
4sim_ticks 365989065000 # Number of ticks simulated
5final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 596728 # Simulator instruction rate (inst/s)
8host_op_rate 1050742 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1382352440 # Simulator tick rate (ticks/s)
10host_mem_usage 424660 # Number of bytes of host memory used
11host_seconds 264.76 # Real time elapsed on the host

7host_inst_rate 756908 # Simulator instruction rate (inst/s)
8host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1753418925 # Simulator tick rate (ticks/s)
10host_mem_usage 446124 # Number of bytes of host memory used
11host_seconds 208.73 # Real time elapsed on the host

12sim_insts 157988548 # Number of instructions simulated
13sim_ops 278192465 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
18system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory
22system.physmem.bytes_written::total 6400 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 100 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)

39system.membus.throughput 5272114 # Throughput (bytes/s)

40system.membus.trans_dist::ReadReq 1025 # Transaction distribution
41system.membus.trans_dist::ReadResp 1025 # Transaction distribution
42system.membus.trans_dist::Writeback 100 # Transaction distribution
43system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
44system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
46system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
47system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)

39system.membus.trans_dist::ReadReq 1025 # Transaction distribution
40system.membus.trans_dist::ReadResp 1025 # Transaction distribution
41system.membus.trans_dist::Writeback 100 # Transaction distribution
42system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
43system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
44system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
45system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
46system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)

48system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
49system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
50system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
51system.membus.data_through_bus 1929536 # Total data (bytes)
52system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)

47system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
48system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
49system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
50system.membus.snoops 0 # Total snoops (count)
51system.membus.snoop_fanout::samples 30149 # Request fanout histogram
52system.membus.snoop_fanout::mean 0 # Request fanout histogram
53system.membus.snoop_fanout::stdev 0 # Request fanout histogram
54system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
55system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram
56system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
57system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
58system.membus.snoop_fanout::min_value 0 # Request fanout histogram
59system.membus.snoop_fanout::max_value 0 # Request fanout histogram
60system.membus.snoop_fanout::total 30149 # Request fanout histogram

53system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks)
54system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
55system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks)
56system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
57system.cpu_clk_domain.clock 500 # Clock period in ticks
58system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
59system.cpu.workload.num_syscalls 444 # Number of system calls
60system.cpu.numCycles 731978130 # number of cpu cycles simulated
61system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
62system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
63system.cpu.committedInsts 157988548 # Number of instructions committed
64system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
65system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
66system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
67system.cpu.num_func_calls 8475189 # number of times a function call or return occured
68system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
69system.cpu.num_int_insts 278169482 # number of integer instructions
70system.cpu.num_fp_insts 40 # number of float instructions
71system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
72system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
73system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
74system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
75system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
76system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
77system.cpu.num_mem_refs 122219137 # number of memory refs
78system.cpu.num_load_insts 90779385 # Number of load instructions
79system.cpu.num_store_insts 31439752 # Number of store instructions
80system.cpu.num_idle_cycles 0 # Number of idle cycles
81system.cpu.num_busy_cycles 731978130 # Number of busy cycles
82system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
83system.cpu.idle_fraction 0 # Percentage of idle cycles
84system.cpu.Branches 29309705 # Number of branches fetched
85system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
86system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
87system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
88system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
89system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
90system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
91system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
92system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
93system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
94system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
95system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
96system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
97system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
98system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
99system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
100system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
101system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
102system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
103system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
104system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
105system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
106system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
107system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
108system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
109system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
110system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
111system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
112system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
113system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
114system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
115system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction
116system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction
117system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
118system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
119system.cpu.op_class::total 278192465 # Class of executed instruction
120system.cpu.icache.tags.replacements 24 # number of replacements
121system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use
122system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks.
123system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
124system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks.
125system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
126system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
127system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
128system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy
129system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id
130system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
131system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
132system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id
133system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
134system.cpu.icache.tags.tag_accesses 435393138 # Number of tag accesses
135system.cpu.icache.tags.data_accesses 435393138 # Number of data accesses
136system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
137system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
138system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
139system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits
140system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits
141system.cpu.icache.overall_hits::total 217695357 # number of overall hits
142system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
143system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
144system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
145system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
146system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
147system.cpu.icache.overall_misses::total 808 # number of overall misses
148system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles
149system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles
150system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles
151system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles
152system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles
153system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles
154system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses)
155system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses)
156system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses
157system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses
158system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses
159system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses
160system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
161system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
162system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
163system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
164system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
165system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
166system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency
167system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency
168system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
169system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency
170system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
171system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency
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173system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
174system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
175system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
176system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
177system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
178system.cpu.icache.fast_writes 0 # number of fast writes performed
179system.cpu.icache.cache_copies 0 # number of cache copies performed
180system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
181system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
182system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
183system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
184system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
185system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
186system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles
187system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles
188system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles
189system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles
190system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles
191system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles
192system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
193system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
194system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
195system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
196system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
197system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
198system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency
199system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency
200system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
201system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
202system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
203system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
204system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
205system.cpu.l2cache.tags.replacements 318 # number of replacements
206system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use
207system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks.
208system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks.
209system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks.
210system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
211system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor
212system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor
213system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor
214system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
215system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
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219system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
220system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
221system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
222system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id
223system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id
224system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
225system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses
226system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses
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228system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits
229system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits
230system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits
231system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits
232system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
233system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
234system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
235system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits
236system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits
237system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
238system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits
239system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits
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244system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
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256system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles
257system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles
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259system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles
260system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles
261system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles
262system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
263system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
264system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
265system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses)
266system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses)
267system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
268system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
269system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
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272system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
273system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
274system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
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276system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses
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278system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses
279system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
280system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
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283system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
284system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses
285system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses
286system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
287system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
288system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
289system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency
290system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency
291system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
292system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
293system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency
294system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
295system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
296system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency
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298system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
299system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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301system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
302system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
303system.cpu.l2cache.fast_writes 0 # number of fast writes performed
304system.cpu.l2cache.cache_copies 0 # number of cache copies performed
305system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks
306system.cpu.l2cache.writebacks::total 100 # number of writebacks
307system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
308system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses
309system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses
310system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
311system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
312system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
313system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses
314system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses
315system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
316system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses
317system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses
318system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles
319system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles
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321system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles
322system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles
323system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles
324system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles
325system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles
326system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles
327system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles
328system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles
329system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses
330system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses
331system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses
332system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
333system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
334system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
335system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses
336system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses
337system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
338system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses
339system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses
340system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
341system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
342system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
343system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
344system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
345system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
346system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
347system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
348system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
349system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
350system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
351system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
352system.cpu.dcache.tags.replacements 2062733 # number of replacements
353system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use
354system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
355system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
356system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
357system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit.
358system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor
359system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
360system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy
361system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
362system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
363system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id
364system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id
365system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
366system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
367system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses
368system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses
369system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
370system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
371system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
372system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
373system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits
374system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits
375system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits
376system.cpu.dcache.overall_hits::total 120152370 # number of overall hits
377system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
378system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
379system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
380system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
381system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
382system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
383system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
384system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
385system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles
386system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles
387system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles
388system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles
389system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles
390system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
391system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
392system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
393system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses)
394system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses)
395system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
396system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
397system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses
398system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses
399system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses
400system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses
401system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
402system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
403system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
404system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
405system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
406system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
407system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
408system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
409system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency
410system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency
411system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency
412system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency
413system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
414system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency
415system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
416system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency
417system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
418system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
419system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
420system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
421system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
422system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
423system.cpu.dcache.fast_writes 0 # number of fast writes performed
424system.cpu.dcache.cache_copies 0 # number of cache copies performed
425system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks
426system.cpu.dcache.writebacks::total 2062484 # number of writebacks
427system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
428system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
429system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
430system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
431system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
432system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
433system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
434system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
435system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles
436system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles
437system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles
438system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles
439system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles
440system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles
441system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles
442system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles
443system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
444system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
445system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
446system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
447system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
448system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
449system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
450system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency
452system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency
453system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency
454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency
455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
456system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
457system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
458system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
459system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

61system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks)
62system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
63system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks)
64system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
65system.cpu_clk_domain.clock 500 # Clock period in ticks
66system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
67system.cpu.workload.num_syscalls 444 # Number of system calls
68system.cpu.numCycles 731978130 # number of cpu cycles simulated
69system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
70system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
71system.cpu.committedInsts 157988548 # Number of instructions committed
72system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
73system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
74system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
75system.cpu.num_func_calls 8475189 # number of times a function call or return occured
76system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
77system.cpu.num_int_insts 278169482 # number of integer instructions
78system.cpu.num_fp_insts 40 # number of float instructions
79system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
80system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
81system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
82system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
83system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
84system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
85system.cpu.num_mem_refs 122219137 # number of memory refs
86system.cpu.num_load_insts 90779385 # Number of load instructions
87system.cpu.num_store_insts 31439752 # Number of store instructions
88system.cpu.num_idle_cycles 0 # Number of idle cycles
89system.cpu.num_busy_cycles 731978130 # Number of busy cycles
90system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
91system.cpu.idle_fraction 0 # Percentage of idle cycles
92system.cpu.Branches 29309705 # Number of branches fetched
93system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
94system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
95system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
96system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
97system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
98system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
99system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
100system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
101system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
102system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
103system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
104system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
105system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
106system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
107system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
108system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
109system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
110system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
111system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
112system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
113system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
114system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
115system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
116system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
117system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
118system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
119system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
120system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
121system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
122system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
123system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction
124system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction
125system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
126system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
127system.cpu.op_class::total 278192465 # Class of executed instruction
128system.cpu.icache.tags.replacements 24 # number of replacements
129system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use
130system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks.
131system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
132system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks.
133system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
134system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
135system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
136system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy
137system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id
138system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
139system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
140system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id
141system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
142system.cpu.icache.tags.tag_accesses 435393138 # Number of tag accesses
143system.cpu.icache.tags.data_accesses 435393138 # Number of data accesses
144system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
145system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
146system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
147system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits
148system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits
149system.cpu.icache.overall_hits::total 217695357 # number of overall hits
150system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
151system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
152system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
153system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
154system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
155system.cpu.icache.overall_misses::total 808 # number of overall misses
156system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles
157system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles
158system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles
159system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles
160system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles
161system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles
162system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses)
163system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses)
164system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses
165system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses
166system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses
167system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses
168system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
169system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
170system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
171system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
172system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
173system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
174system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency
175system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency
176system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
177system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency
178system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
179system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency
180system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
181system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
182system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
183system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
184system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
185system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
186system.cpu.icache.fast_writes 0 # number of fast writes performed
187system.cpu.icache.cache_copies 0 # number of cache copies performed
188system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
189system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
190system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
191system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
192system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
193system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
194system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles
195system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles
196system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles
197system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles
198system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles
199system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles
200system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
201system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
202system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
203system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
204system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
205system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
206system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency
207system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency
208system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
209system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
210system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
211system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
212system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
213system.cpu.l2cache.tags.replacements 318 # number of replacements
214system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use
215system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks.
216system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks.
217system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks.
218system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
219system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor
220system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor
221system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor
222system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
223system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
224system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
225system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy
226system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id
227system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
228system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
229system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
230system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id
231system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id
232system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
233system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses
234system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses
235system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
236system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits
237system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits
238system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits
239system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits
240system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
241system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
242system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
243system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits
244system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits
245system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
246system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits
247system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits
248system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
249system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses
250system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses
251system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses
252system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
253system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
254system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses
255system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses
256system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
257system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses
258system.cpu.l2cache.overall_misses::total 30049 # number of overall misses
259system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles
260system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles
261system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles
262system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles
263system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles
264system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles
265system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles
266system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles
267system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles
268system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles
269system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles
270system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
271system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
272system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
273system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses)
274system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses)
275system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
276system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
277system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
278system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
279system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
280system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
281system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
282system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
283system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses
284system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses
285system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses
286system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses
287system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
288system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
289system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses
290system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses
291system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
292system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses
293system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses
294system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
295system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
296system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
297system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency
298system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency
299system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
300system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
301system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency
302system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
303system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
304system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency
305system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
306system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
307system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
308system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
309system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
310system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
311system.cpu.l2cache.fast_writes 0 # number of fast writes performed
312system.cpu.l2cache.cache_copies 0 # number of cache copies performed
313system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks
314system.cpu.l2cache.writebacks::total 100 # number of writebacks
315system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
316system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses
317system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses
318system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
319system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
320system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
321system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses
322system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses
323system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
324system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses
325system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses
326system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles
327system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles
328system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles
329system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles
330system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles
331system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles
332system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles
333system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles
334system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles
335system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles
336system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles
337system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses
338system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses
339system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses
340system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
341system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
342system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
343system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses
344system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses
345system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
346system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses
347system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses
348system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
349system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
350system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
351system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
352system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
353system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
354system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
355system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
356system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
357system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
358system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
359system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
360system.cpu.dcache.tags.replacements 2062733 # number of replacements
361system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use
362system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
363system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
364system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
365system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit.
366system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor
367system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
368system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy
369system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
370system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
371system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id
372system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id
373system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
374system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
375system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses
376system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses
377system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
378system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
379system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
380system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
381system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits
382system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits
383system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits
384system.cpu.dcache.overall_hits::total 120152370 # number of overall hits
385system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
386system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
387system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
388system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
389system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
390system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
391system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
392system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
393system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles
394system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles
395system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles
396system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles
397system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles
398system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
399system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
400system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
401system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses)
402system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses)
403system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
404system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
405system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses
406system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses
407system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses
408system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses
409system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
410system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
411system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
412system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
413system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
414system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
415system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
416system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
417system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency
418system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency
419system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency
420system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency
421system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
422system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency
423system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
424system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency
425system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
426system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
427system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
428system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
429system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
430system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
431system.cpu.dcache.fast_writes 0 # number of fast writes performed
432system.cpu.dcache.cache_copies 0 # number of cache copies performed
433system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks
434system.cpu.dcache.writebacks::total 2062484 # number of writebacks
435system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
436system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
437system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
438system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
439system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
440system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
441system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
442system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
443system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles
444system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles
445system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles
446system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles
447system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles
448system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles
449system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles
450system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles
451system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
452system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
453system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
454system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
455system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
456system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
457system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
458system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
459system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency
460system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency
461system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency
462system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency
463system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
464system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
465system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
466system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
467system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

460system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s)

461system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
463system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution
464system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
465system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
466system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes)
467system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes)
468system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes)

468system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution
469system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
470system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution
471system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
472system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
473system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes)
474system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes)
475system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes)

469system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes)
470system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes)
471system.cpu.toL2Bus.tot_pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
472system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes)
473system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)

476system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes)
477system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes)
478system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
479system.cpu.toL2Bus.snoops 0 # Total snoops (count)
480system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
482system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
483system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
484system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
485system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
486system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
487system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram
488system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
489system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
490system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
491system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
492system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram