| stats.txt (9978:81d7551dd3be) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.065614 # Number of seconds simulated 4sim_ticks 65613727000 # Number of ticks simulated 5final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.065614 # Number of seconds simulated 4sim_ticks 65613727000 # Number of ticks simulated 5final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 90206 # Simulator instruction rate (inst/s) 8host_op_rate 158838 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37463203 # Simulator tick rate (ticks/s) 10host_mem_usage 416624 # Number of bytes of host memory used 11host_seconds 1751.42 # Real time elapsed on the host | 7host_inst_rate 72100 # Simulator instruction rate (inst/s) 8host_op_rate 126957 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 29943715 # Simulator tick rate (ticks/s) 10host_mem_usage 436724 # Number of bytes of host memory used 11host_seconds 2191.24 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 10688 # Number of bytes written to this memory --- 271 unchanged lines hidden (view full) --- 291system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61004 # Packet count per connected master and slave (bytes) 292system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61004 # Packet count per connected master and slave (bytes) 293system.membus.pkt_count::total 61004 # Packet count per connected master and slave (bytes) 294system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957440 # Cumulative packet size per connected master and slave (bytes) 295system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 # Cumulative packet size per connected master and slave (bytes) 296system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes) 297system.membus.data_through_bus 1957440 # Total data (bytes) 298system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 10688 # Number of bytes written to this memory --- 271 unchanged lines hidden (view full) --- 291system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61004 # Packet count per connected master and slave (bytes) 292system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61004 # Packet count per connected master and slave (bytes) 293system.membus.pkt_count::total 61004 # Packet count per connected master and slave (bytes) 294system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957440 # Cumulative packet size per connected master and slave (bytes) 295system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 # Cumulative packet size per connected master and slave (bytes) 296system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes) 297system.membus.data_through_bus 1957440 # Total data (bytes) 298system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 299system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks) | 299system.membus.reqLayer0.occupancy 34950500 # Layer occupancy (ticks) |
| 300system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 300system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 301system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks) | 301system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks) |
| 302system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 303system.cpu.branchPred.lookups 33859770 # Number of BP lookups 304system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 19306649 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 19202709 # Number of BTB hits 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 309system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage --- 58 unchanged lines hidden (view full) --- 368system.cpu.rename.UndoneMaps 37975386 # Number of HB maps that are undone due to squashing 369system.cpu.rename.serializingInsts 483 # count of serializing insts renamed 370system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed 371system.cpu.rename.skidInsts 62628696 # count of insts added to the skid buffer 372system.cpu.memDep0.insertedLoads 101555761 # Number of loads inserted to the mem dependence unit. 373system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit. 374system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads. 375system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores. | 302system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 303system.cpu.branchPred.lookups 33859770 # Number of BP lookups 304system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 19306649 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 19202709 # Number of BTB hits 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 309system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage --- 58 unchanged lines hidden (view full) --- 368system.cpu.rename.UndoneMaps 37975386 # Number of HB maps that are undone due to squashing 369system.cpu.rename.serializingInsts 483 # count of serializing insts renamed 370system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed 371system.cpu.rename.skidInsts 62628696 # count of insts added to the skid buffer 372system.cpu.memDep0.insertedLoads 101555761 # Number of loads inserted to the mem dependence unit. 373system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit. 374system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads. 375system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores. |
| 376system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec) | 376system.cpu.iq.iqInstsAdded 311484166 # Number of instructions added to the IQ (excludes non-spec) |
| 377system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ | 377system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ |
| 378system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued | 378system.cpu.iq.iqInstsIssued 300275524 # Number of instructions issued |
| 379system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued | 379system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued |
| 380system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling 381system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph | 380system.cpu.iq.iqSquashedInstsExamined 32714418 # Number of squashed instructions iterated over during squash; mainly for profiling 381system.cpu.iq.iqSquashedOperandsExamined 46115217 # Number of squashed operands that are examined and possibly removed from graph |
| 382system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed 383system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle | 382system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed 383system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle |
| 388system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle | 388system.cpu.iq.issued_per_cycle::1 23163237 17.67% 36.25% # Number of insts issued each cycle |
| 389system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle | 389system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle |
| 390system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle | 390system.cpu.iq.issued_per_cycle::3 25864200 19.73% 75.44% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::4 18882898 14.40% 89.85% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::5 8250397 6.29% 96.14% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::6 3948647 3.01% 99.15% # Number of insts issued each cycle |
| 394system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::total 131122211 # Number of insts issued each cycle 400system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 401system.cpu.iq.fu_full::IntAlu 31436 1.53% 1.53% # attempts to use FU when none available --- 20 unchanged lines hidden (view full) --- 422system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available | 394system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::total 131122211 # Number of insts issued each cycle 400system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 401system.cpu.iq.fu_full::IntAlu 31436 1.53% 1.53% # attempts to use FU when none available --- 20 unchanged lines hidden (view full) --- 422system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available |
| 430system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available | 430system.cpu.iq.fu_full::MemRead 1917677 93.05% 94.57% # attempts to use FU when none available |
| 431system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available 432system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 433system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 434system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued | 431system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available 432system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 433system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 434system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued |
| 435system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued | 435system.cpu.iq.FU_type_0::IntAlu 169841029 56.56% 56.57% # Type of FU issued |
| 436system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued 437system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued 440system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued 443system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 456system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued | 436system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued 437system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued 440system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued 443system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 456system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued |
| 464system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued | 464system.cpu.iq.FU_type_0::MemRead 97301451 32.40% 88.98% # Type of FU issued |
| 465system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued 466system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 467system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 465system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued 466system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 467system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 468system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued | 468system.cpu.iq.FU_type_0::total 300275524 # Type of FU issued |
| 469system.cpu.iq.rate 2.288206 # Inst issue rate | 469system.cpu.iq.rate 2.288206 # Inst issue rate |
| 470system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested | 470system.cpu.iq.fu_busy_cnt 2060962 # FU busy when requested |
| 471system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst) | 471system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst) |
| 472system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads 473system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes 474system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses | 472system.cpu.iq.int_inst_queue_reads 733823004 # Number of integer instruction queue reads 473system.cpu.iq.int_inst_queue_writes 344232038 # Number of integer instruction queue writes 474system.cpu.iq.int_inst_queue_wakeup_accesses 298020704 # Number of integer instruction queue wakeup accesses |
| 475system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads 476system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes 477system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses | 475system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads 476system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes 477system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses |
| 478system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses | 478system.cpu.iq.int_alu_accesses 302304968 # Number of integer alu accesses |
| 479system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses 480system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores 481system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 482system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed | 479system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses 480system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores 481system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 482system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed |
| 483system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed 484system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations | 483system.cpu.iew.lsq.thread0.ignoredResponses 31265 # Number of memory responses ignored because the instruction is squashed 484system.cpu.iew.lsq.thread0.memOrderViolation 33344 # Number of memory ordering violations |
| 485system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed 486system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 487system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 488system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled 489system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked 490system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 491system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing 492system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking 493system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking | 485system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed 486system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 487system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 488system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled 489system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked 490system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 491system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing 492system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking 493system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking |
| 494system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ | 494system.cpu.iew.iewDispatchedInsts 311485804 # Number of instructions dispatched to IQ |
| 495system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch 496system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions 497system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions 498system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions 499system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall 500system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall | 495system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch 496system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions 497system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions 498system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions 499system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall 500system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall |
| 501system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations | 501system.cpu.iew.memOrderViolationEvents 33344 # Number of memory order violations |
| 502system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly 503system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly 504system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute | 502system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly 503system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly 504system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute |
| 505system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions 506system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed 507system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute | 505system.cpu.iew.iewExecutedInsts 298872684 # Number of executed instructions 506system.cpu.iew.iewExecLoadInsts 96891554 # Number of load instructions executed 507system.cpu.iew.iewExecSquashedInsts 1402840 # Number of squashed instructions skipped in execute |
| 508system.cpu.iew.exec_swp 0 # number of swp insts executed 509system.cpu.iew.exec_nop 0 # number of nop insts executed | 508system.cpu.iew.exec_swp 0 # number of swp insts executed 509system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 510system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed | 510system.cpu.iew.exec_refs 129817497 # number of memory reference insts executed |
| 511system.cpu.iew.exec_branches 30820824 # Number of branches executed | 511system.cpu.iew.exec_branches 30820824 # Number of branches executed |
| 512system.cpu.iew.exec_stores 32925944 # Number of stores executed | 512system.cpu.iew.exec_stores 32925943 # Number of stores executed |
| 513system.cpu.iew.exec_rate 2.277516 # Inst execution rate | 513system.cpu.iew.exec_rate 2.277516 # Inst execution rate |
| 514system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit 515system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back 516system.cpu.iew.wb_producers 218260008 # num instructions producing a value 517system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value | 514system.cpu.iew.wb_sent 298390596 # cumulative count of insts sent to commit 515system.cpu.iew.wb_count 298020860 # cumulative count of insts written-back 516system.cpu.iew.wb_producers 218260006 # num instructions producing a value 517system.cpu.iew.wb_consumers 296755223 # num instructions consuming a value |
| 518system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 519system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle 520system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back 521system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 518system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 519system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle 520system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back 521system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 522system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit | 522system.cpu.commit.commitSquashedInsts 33306189 # The number of squashed insts skipped by commit |
| 523system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 524system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted 525system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::mean 2.197795 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::stdev 2.970921 # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::0 58251121 46.02% 46.02% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::1 19170530 15.15% 61.17% # Number of insts commited each cycle --- 15 unchanged lines hidden (view full) --- 546system.cpu.commit.loads 90779385 # Number of loads committed 547system.cpu.commit.membars 0 # Number of memory barriers committed 548system.cpu.commit.branches 29309705 # Number of branches committed 549system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 550system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 551system.cpu.commit.function_calls 4237596 # Number of function calls committed. 552system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached 553system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 523system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 524system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted 525system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::mean 2.197795 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::stdev 2.970921 # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::0 58251121 46.02% 46.02% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::1 19170530 15.15% 61.17% # Number of insts commited each cycle --- 15 unchanged lines hidden (view full) --- 546system.cpu.commit.loads 90779385 # Number of loads committed 547system.cpu.commit.membars 0 # Number of memory barriers committed 548system.cpu.commit.branches 29309705 # Number of branches committed 549system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 550system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 551system.cpu.commit.function_calls 4237596 # Number of function calls committed. 552system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached 553system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 554system.cpu.rob.rob_reads 415950983 # The number of ROB reads 555system.cpu.rob.rob_writes 627545403 # The number of ROB writes | 554system.cpu.rob.rob_reads 415950981 # The number of ROB reads 555system.cpu.rob.rob_writes 627545399 # The number of ROB writes |
| 556system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself 557system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling 558system.cpu.committedInsts 157988547 # Number of Instructions Simulated 559system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 560system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated 561system.cpu.cpi 0.830614 # CPI: Cycles Per Instruction 562system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads 563system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle 564system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads | 556system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself 557system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling 558system.cpu.committedInsts 157988547 # Number of Instructions Simulated 559system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 560system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated 561system.cpu.cpi 0.830614 # CPI: Cycles Per Instruction 562system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads 563system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle 564system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads |
| 565system.cpu.int_regfile_reads 483744134 # number of integer regfile reads 566system.cpu.int_regfile_writes 234595253 # number of integer regfile writes | 565system.cpu.int_regfile_reads 483744129 # number of integer regfile reads 566system.cpu.int_regfile_writes 234595251 # number of integer regfile writes |
| 567system.cpu.fp_regfile_reads 141 # number of floating regfile reads 568system.cpu.fp_regfile_writes 77 # number of floating regfile writes 569system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads 570system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes | 567system.cpu.fp_regfile_reads 141 # number of floating regfile reads 568system.cpu.fp_regfile_writes 77 # number of floating regfile writes 569system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads 570system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes |
| 571system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads | 571system.cpu.misc_regfile_reads 191827908 # number of misc regfile reads |
| 572system.cpu.misc_regfile_writes 1 # number of misc regfile writes 573system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s) 574system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadResp 1995298 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::Writeback 2066887 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::ReadExReq 82323 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::ReadExResp 82323 # Transaction distribution 579system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2022 # Packet count per connected master and slave (bytes) --- 26 unchanged lines hidden (view full) --- 606system.cpu.icache.overall_hits::cpu.inst 25574088 # number of overall hits 607system.cpu.icache.overall_hits::total 25574088 # number of overall hits 608system.cpu.icache.ReadReq_misses::cpu.inst 1305 # number of ReadReq misses 609system.cpu.icache.ReadReq_misses::total 1305 # number of ReadReq misses 610system.cpu.icache.demand_misses::cpu.inst 1305 # number of demand (read+write) misses 611system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses 612system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses 613system.cpu.icache.overall_misses::total 1305 # number of overall misses | 572system.cpu.misc_regfile_writes 1 # number of misc regfile writes 573system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s) 574system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadResp 1995298 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::Writeback 2066887 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::ReadExReq 82323 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::ReadExResp 82323 # Transaction distribution 579system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2022 # Packet count per connected master and slave (bytes) --- 26 unchanged lines hidden (view full) --- 606system.cpu.icache.overall_hits::cpu.inst 25574088 # number of overall hits 607system.cpu.icache.overall_hits::total 25574088 # number of overall hits 608system.cpu.icache.ReadReq_misses::cpu.inst 1305 # number of ReadReq misses 609system.cpu.icache.ReadReq_misses::total 1305 # number of ReadReq misses 610system.cpu.icache.demand_misses::cpu.inst 1305 # number of demand (read+write) misses 611system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses 612system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses 613system.cpu.icache.overall_misses::total 1305 # number of overall misses |
| 614system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles 615system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles 616system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles 617system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles 618system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles 619system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles | 614system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661748 # number of ReadReq miss cycles 615system.cpu.icache.ReadReq_miss_latency::total 88661748 # number of ReadReq miss cycles 616system.cpu.icache.demand_miss_latency::cpu.inst 88661748 # number of demand (read+write) miss cycles 617system.cpu.icache.demand_miss_latency::total 88661748 # number of demand (read+write) miss cycles 618system.cpu.icache.overall_miss_latency::cpu.inst 88661748 # number of overall miss cycles 619system.cpu.icache.overall_miss_latency::total 88661748 # number of overall miss cycles |
| 620system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses) 621system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses) 622system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses 623system.cpu.icache.demand_accesses::total 25575393 # number of demand (read+write) accesses 624system.cpu.icache.overall_accesses::cpu.inst 25575393 # number of overall (read+write) accesses 625system.cpu.icache.overall_accesses::total 25575393 # number of overall (read+write) accesses 626system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 627system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 628system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 629system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 630system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 631system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses | 620system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses) 621system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses) 622system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses 623system.cpu.icache.demand_accesses::total 25575393 # number of demand (read+write) accesses 624system.cpu.icache.overall_accesses::cpu.inst 25575393 # number of overall (read+write) accesses 625system.cpu.icache.overall_accesses::total 25575393 # number of overall (read+write) accesses 626system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 627system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 628system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 629system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 630system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 631system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses |
| 632system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency 633system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency 634system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency 635system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency 636system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency 637system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency | 632system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67940.036782 # average ReadReq miss latency 633system.cpu.icache.ReadReq_avg_miss_latency::total 67940.036782 # average ReadReq miss latency 634system.cpu.icache.demand_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency 635system.cpu.icache.demand_avg_miss_latency::total 67940.036782 # average overall miss latency 636system.cpu.icache.overall_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency 637system.cpu.icache.overall_avg_miss_latency::total 67940.036782 # average overall miss latency |
| 638system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked 639system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 640system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 641system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 642system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked 643system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 644system.cpu.icache.fast_writes 0 # number of fast writes performed 645system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 650system.cpu.icache.overall_mshr_hits::cpu.inst 294 # number of overall MSHR hits 651system.cpu.icache.overall_mshr_hits::total 294 # number of overall MSHR hits 652system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1011 # number of ReadReq MSHR misses 653system.cpu.icache.ReadReq_mshr_misses::total 1011 # number of ReadReq MSHR misses 654system.cpu.icache.demand_mshr_misses::cpu.inst 1011 # number of demand (read+write) MSHR misses 655system.cpu.icache.demand_mshr_misses::total 1011 # number of demand (read+write) MSHR misses 656system.cpu.icache.overall_mshr_misses::cpu.inst 1011 # number of overall MSHR misses 657system.cpu.icache.overall_mshr_misses::total 1011 # number of overall MSHR misses | 638system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked 639system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 640system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 641system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 642system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked 643system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 644system.cpu.icache.fast_writes 0 # number of fast writes performed 645system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 650system.cpu.icache.overall_mshr_hits::cpu.inst 294 # number of overall MSHR hits 651system.cpu.icache.overall_mshr_hits::total 294 # number of overall MSHR hits 652system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1011 # number of ReadReq MSHR misses 653system.cpu.icache.ReadReq_mshr_misses::total 1011 # number of ReadReq MSHR misses 654system.cpu.icache.demand_mshr_misses::cpu.inst 1011 # number of demand (read+write) MSHR misses 655system.cpu.icache.demand_mshr_misses::total 1011 # number of demand (read+write) MSHR misses 656system.cpu.icache.overall_mshr_misses::cpu.inst 1011 # number of overall MSHR misses 657system.cpu.icache.overall_mshr_misses::total 1011 # number of overall MSHR misses |
| 658system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226001 # number of ReadReq MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226001 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.demand_mshr_miss_latency::total 69226001 # number of demand (read+write) MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles 663system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles | 658system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226501 # number of ReadReq MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_latency::total 69226501 # number of ReadReq MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226501 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.demand_mshr_miss_latency::total 69226501 # number of demand (read+write) MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226501 # number of overall MSHR miss cycles 663system.cpu.icache.overall_mshr_miss_latency::total 69226501 # number of overall MSHR miss cycles |
| 664system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 665system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 666system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 667system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 668system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 669system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 664system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 665system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 666system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 667system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 668system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 669system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 670system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68472.800198 # average ReadReq mshr miss latency 671system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency 673system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency 674system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency 675system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency | 670system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68473.294758 # average ReadReq mshr miss latency 671system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68473.294758 # average ReadReq mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency 673system.cpu.icache.demand_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency 674system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency 675system.cpu.icache.overall_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency |
| 676system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 677system.cpu.l2cache.tags.replacements 479 # number of replacements 678system.cpu.l2cache.tags.tagsinuse 20806.493932 # Cycle average of tags in use 679system.cpu.l2cache.tags.total_refs 4029616 # Total number of references to valid blocks. 680system.cpu.l2cache.tags.sampled_refs 30401 # Sample count of references to valid blocks. 681system.cpu.l2cache.tags.avg_refs 132.548798 # Average number of references to valid blocks. 682system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 683system.cpu.l2cache.tags.occ_blocks::writebacks 19891.107618 # Average occupied blocks per requestor --- 22 unchanged lines hidden (view full) --- 706system.cpu.l2cache.ReadExReq_misses::cpu.data 29003 # number of ReadExReq misses 707system.cpu.l2cache.ReadExReq_misses::total 29003 # number of ReadExReq misses 708system.cpu.l2cache.demand_misses::cpu.inst 994 # number of demand (read+write) misses 709system.cpu.l2cache.demand_misses::cpu.data 29425 # number of demand (read+write) misses 710system.cpu.l2cache.demand_misses::total 30419 # number of demand (read+write) misses 711system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses 712system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses 713system.cpu.l2cache.overall_misses::total 30419 # number of overall misses | 676system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 677system.cpu.l2cache.tags.replacements 479 # number of replacements 678system.cpu.l2cache.tags.tagsinuse 20806.493932 # Cycle average of tags in use 679system.cpu.l2cache.tags.total_refs 4029616 # Total number of references to valid blocks. 680system.cpu.l2cache.tags.sampled_refs 30401 # Sample count of references to valid blocks. 681system.cpu.l2cache.tags.avg_refs 132.548798 # Average number of references to valid blocks. 682system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 683system.cpu.l2cache.tags.occ_blocks::writebacks 19891.107618 # Average occupied blocks per requestor --- 22 unchanged lines hidden (view full) --- 706system.cpu.l2cache.ReadExReq_misses::cpu.data 29003 # number of ReadExReq misses 707system.cpu.l2cache.ReadExReq_misses::total 29003 # number of ReadExReq misses 708system.cpu.l2cache.demand_misses::cpu.inst 994 # number of demand (read+write) misses 709system.cpu.l2cache.demand_misses::cpu.data 29425 # number of demand (read+write) misses 710system.cpu.l2cache.demand_misses::total 30419 # number of demand (read+write) misses 711system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses 712system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses 713system.cpu.l2cache.overall_misses::total 30419 # number of overall misses |
| 714system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68040500 # number of ReadReq miss cycles | 714system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68041000 # number of ReadReq miss cycles |
| 715system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29989500 # number of ReadReq miss cycles | 715system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29989500 # number of ReadReq miss cycles |
| 716system.cpu.l2cache.ReadReq_miss_latency::total 98030000 # number of ReadReq miss cycles | 716system.cpu.l2cache.ReadReq_miss_latency::total 98030500 # number of ReadReq miss cycles |
| 717system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876802500 # number of ReadExReq miss cycles 718system.cpu.l2cache.ReadExReq_miss_latency::total 1876802500 # number of ReadExReq miss cycles | 717system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876802500 # number of ReadExReq miss cycles 718system.cpu.l2cache.ReadExReq_miss_latency::total 1876802500 # number of ReadExReq miss cycles |
| 719system.cpu.l2cache.demand_miss_latency::cpu.inst 68040500 # number of demand (read+write) miss cycles | 719system.cpu.l2cache.demand_miss_latency::cpu.inst 68041000 # number of demand (read+write) miss cycles |
| 720system.cpu.l2cache.demand_miss_latency::cpu.data 1906792000 # number of demand (read+write) miss cycles | 720system.cpu.l2cache.demand_miss_latency::cpu.data 1906792000 # number of demand (read+write) miss cycles |
| 721system.cpu.l2cache.demand_miss_latency::total 1974832500 # number of demand (read+write) miss cycles 722system.cpu.l2cache.overall_miss_latency::cpu.inst 68040500 # number of overall miss cycles | 721system.cpu.l2cache.demand_miss_latency::total 1974833000 # number of demand (read+write) miss cycles 722system.cpu.l2cache.overall_miss_latency::cpu.inst 68041000 # number of overall miss cycles |
| 723system.cpu.l2cache.overall_miss_latency::cpu.data 1906792000 # number of overall miss cycles | 723system.cpu.l2cache.overall_miss_latency::cpu.data 1906792000 # number of overall miss cycles |
| 724system.cpu.l2cache.overall_miss_latency::total 1974832500 # number of overall miss cycles | 724system.cpu.l2cache.overall_miss_latency::total 1974833000 # number of overall miss cycles |
| 725system.cpu.l2cache.ReadReq_accesses::cpu.inst 1011 # number of ReadReq accesses(hits+misses) 726system.cpu.l2cache.ReadReq_accesses::cpu.data 1994288 # number of ReadReq accesses(hits+misses) 727system.cpu.l2cache.ReadReq_accesses::total 1995299 # number of ReadReq accesses(hits+misses) 728system.cpu.l2cache.Writeback_accesses::writebacks 2066887 # number of Writeback accesses(hits+misses) 729system.cpu.l2cache.Writeback_accesses::total 2066887 # number of Writeback accesses(hits+misses) 730system.cpu.l2cache.ReadExReq_accesses::cpu.data 82323 # number of ReadExReq accesses(hits+misses) 731system.cpu.l2cache.ReadExReq_accesses::total 82323 # number of ReadExReq accesses(hits+misses) 732system.cpu.l2cache.demand_accesses::cpu.inst 1011 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 741system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352307 # miss rate for ReadExReq accesses 742system.cpu.l2cache.ReadExReq_miss_rate::total 0.352307 # miss rate for ReadExReq accesses 743system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983185 # miss rate for demand accesses 744system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses 745system.cpu.l2cache.demand_miss_rate::total 0.014641 # miss rate for demand accesses 746system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983185 # miss rate for overall accesses 747system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses 748system.cpu.l2cache.overall_miss_rate::total 0.014641 # miss rate for overall accesses | 725system.cpu.l2cache.ReadReq_accesses::cpu.inst 1011 # number of ReadReq accesses(hits+misses) 726system.cpu.l2cache.ReadReq_accesses::cpu.data 1994288 # number of ReadReq accesses(hits+misses) 727system.cpu.l2cache.ReadReq_accesses::total 1995299 # number of ReadReq accesses(hits+misses) 728system.cpu.l2cache.Writeback_accesses::writebacks 2066887 # number of Writeback accesses(hits+misses) 729system.cpu.l2cache.Writeback_accesses::total 2066887 # number of Writeback accesses(hits+misses) 730system.cpu.l2cache.ReadExReq_accesses::cpu.data 82323 # number of ReadExReq accesses(hits+misses) 731system.cpu.l2cache.ReadExReq_accesses::total 82323 # number of ReadExReq accesses(hits+misses) 732system.cpu.l2cache.demand_accesses::cpu.inst 1011 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 741system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352307 # miss rate for ReadExReq accesses 742system.cpu.l2cache.ReadExReq_miss_rate::total 0.352307 # miss rate for ReadExReq accesses 743system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983185 # miss rate for demand accesses 744system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses 745system.cpu.l2cache.demand_miss_rate::total 0.014641 # miss rate for demand accesses 746system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983185 # miss rate for overall accesses 747system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses 748system.cpu.l2cache.overall_miss_rate::total 0.014641 # miss rate for overall accesses |
| 749system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.207243 # average ReadReq miss latency | 749system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.710262 # average ReadReq miss latency |
| 750system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71065.165877 # average ReadReq miss latency | 750system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71065.165877 # average ReadReq miss latency |
| 751system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.225989 # average ReadReq miss latency | 751system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.579096 # average ReadReq miss latency |
| 752system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64710.633383 # average ReadExReq miss latency 753system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64710.633383 # average ReadExReq miss latency | 752system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64710.633383 # average ReadExReq miss latency 753system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64710.633383 # average ReadExReq miss latency |
| 754system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency | 754system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency |
| 755system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency | 755system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency |
| 756system.cpu.l2cache.demand_avg_miss_latency::total 64921.019757 # average overall miss latency 757system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency | 756system.cpu.l2cache.demand_avg_miss_latency::total 64921.036194 # average overall miss latency 757system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency |
| 758system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency | 758system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency |
| 759system.cpu.l2cache.overall_avg_miss_latency::total 64921.019757 # average overall miss latency | 759system.cpu.l2cache.overall_avg_miss_latency::total 64921.036194 # average overall miss latency |
| 760system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 761system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 763system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 764system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 765system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.cpu.l2cache.fast_writes 0 # number of fast writes performed 767system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 41 unchanged lines hidden (view full) --- 809system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency 810system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency 811system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency 812system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency 813system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency 814system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 815system.cpu.dcache.tags.replacements 2072514 # number of replacements 816system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use | 760system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 761system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 763system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 764system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 765system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.cpu.l2cache.fast_writes 0 # number of fast writes performed 767system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 41 unchanged lines hidden (view full) --- 809system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency 810system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency 811system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency 812system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency 813system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency 814system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 815system.cpu.dcache.tags.replacements 2072514 # number of replacements 816system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use |
| 817system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks. | 817system.cpu.dcache.tags.total_refs 71413623 # Total number of references to valid blocks. |
| 818system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks. 819system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks. 820system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit. 821system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor 822system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy 823system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy | 818system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks. 819system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks. 820system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit. 821system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor 822system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy 823system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy |
| 824system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits 825system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits | 824system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits 825system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits |
| 826system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits 827system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits | 826system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits 827system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits |
| 828system.cpu.dcache.demand_hits::cpu.data 71413624 # number of demand (read+write) hits 829system.cpu.dcache.demand_hits::total 71413624 # number of demand (read+write) hits 830system.cpu.dcache.overall_hits::cpu.data 71413624 # number of overall hits 831system.cpu.dcache.overall_hits::total 71413624 # number of overall hits | 828system.cpu.dcache.demand_hits::cpu.data 71413623 # number of demand (read+write) hits 829system.cpu.dcache.demand_hits::total 71413623 # number of demand (read+write) hits 830system.cpu.dcache.overall_hits::cpu.data 71413623 # number of overall hits 831system.cpu.dcache.overall_hits::total 71413623 # number of overall hits |
| 832system.cpu.dcache.ReadReq_misses::cpu.data 2625746 # number of ReadReq misses 833system.cpu.dcache.ReadReq_misses::total 2625746 # number of ReadReq misses 834system.cpu.dcache.WriteReq_misses::cpu.data 98059 # number of WriteReq misses 835system.cpu.dcache.WriteReq_misses::total 98059 # number of WriteReq misses 836system.cpu.dcache.demand_misses::cpu.data 2723805 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 2723805 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 2723805 # number of overall misses 839system.cpu.dcache.overall_misses::total 2723805 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 31399016250 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 31399016250 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 2779679498 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 2779679498 # number of WriteReq miss cycles 844system.cpu.dcache.demand_miss_latency::cpu.data 34178695748 # number of demand (read+write) miss cycles 845system.cpu.dcache.demand_miss_latency::total 34178695748 # number of demand (read+write) miss cycles 846system.cpu.dcache.overall_miss_latency::cpu.data 34178695748 # number of overall miss cycles 847system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles | 832system.cpu.dcache.ReadReq_misses::cpu.data 2625746 # number of ReadReq misses 833system.cpu.dcache.ReadReq_misses::total 2625746 # number of ReadReq misses 834system.cpu.dcache.WriteReq_misses::cpu.data 98059 # number of WriteReq misses 835system.cpu.dcache.WriteReq_misses::total 98059 # number of WriteReq misses 836system.cpu.dcache.demand_misses::cpu.data 2723805 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 2723805 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 2723805 # number of overall misses 839system.cpu.dcache.overall_misses::total 2723805 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 31399016250 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 31399016250 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 2779679498 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 2779679498 # number of WriteReq miss cycles 844system.cpu.dcache.demand_miss_latency::cpu.data 34178695748 # number of demand (read+write) miss cycles 845system.cpu.dcache.demand_miss_latency::total 34178695748 # number of demand (read+write) miss cycles 846system.cpu.dcache.overall_miss_latency::cpu.data 34178695748 # number of overall miss cycles 847system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles |
| 848system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses) | 848system.cpu.dcache.ReadReq_accesses::cpu.data 42697676 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.ReadReq_accesses::total 42697676 # number of ReadReq accesses(hits+misses) |
| 850system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) | 850system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) |
| 852system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses 853system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses 854system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses 855system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses | 852system.cpu.dcache.demand_accesses::cpu.data 74137428 # number of demand (read+write) accesses 853system.cpu.dcache.demand_accesses::total 74137428 # number of demand (read+write) accesses 854system.cpu.dcache.overall_accesses::cpu.data 74137428 # number of overall (read+write) accesses 855system.cpu.dcache.overall_accesses::total 74137428 # number of overall (read+write) accesses |
| 856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses 857system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses 858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses 859system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses 860system.cpu.dcache.demand_miss_rate::cpu.data 0.036740 # miss rate for demand accesses 861system.cpu.dcache.demand_miss_rate::total 0.036740 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.036740 # miss rate for overall accesses 863system.cpu.dcache.overall_miss_rate::total 0.036740 # miss rate for overall accesses --- 61 unchanged lines hidden --- | 856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses 857system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses 858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses 859system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses 860system.cpu.dcache.demand_miss_rate::cpu.data 0.036740 # miss rate for demand accesses 861system.cpu.dcache.demand_miss_rate::total 0.036740 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.036740 # miss rate for overall accesses 863system.cpu.dcache.overall_miss_rate::total 0.036740 # miss rate for overall accesses --- 61 unchanged lines hidden --- |