| stats.txt (9924:31ef410b6843) | stats.txt (9978:81d7551dd3be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.065497 # Number of seconds simulated 4sim_ticks 65497052500 # Number of ticks simulated 5final_tick 65497052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.065614 # Number of seconds simulated 4sim_ticks 65613727000 # Number of ticks simulated 5final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 99498 # Simulator instruction rate (inst/s) 8host_op_rate 175200 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41248682 # Simulator tick rate (ticks/s) 10host_mem_usage 388584 # Number of bytes of host memory used 11host_seconds 1587.86 # Real time elapsed on the host | 7host_inst_rate 90206 # Simulator instruction rate (inst/s) 8host_op_rate 158838 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37463203 # Simulator tick rate (ticks/s) 10host_mem_usage 416624 # Number of bytes of host memory used 11host_seconds 1751.42 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 63296 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1882240 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1945536 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 63296 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 63296 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 9984 # Number of bytes written to this memory 20system.physmem.bytes_written::total 9984 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 989 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29410 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30399 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 156 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 156 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 966395 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 28737782 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 29704176 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 966395 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 966395 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 152434 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 152434 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 152434 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 966395 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 28737782 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 29856611 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 30400 # Total number of read requests accepted by DRAM controller 38system.physmem.writeReqs 156 # Total number of write requests accepted by DRAM controller 39system.physmem.readBursts 30400 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 40system.physmem.writeBursts 156 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 41system.physmem.bytesRead 1945536 # Total number of bytes read from memory 42system.physmem.bytesWritten 9984 # Total number of bytes written to memory 43system.physmem.bytesConsumedRd 1945536 # bytesRead derated as per pkt->getSize() 44system.physmem.bytesConsumedWr 9984 # bytesWritten derated as per pkt->getSize() 45system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by write Q 46system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 47system.physmem.perBankRdReqs::0 1924 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::2 2025 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::3 1924 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::5 1898 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::7 1861 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::9 1932 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::14 1820 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis 63system.physmem.perBankWrReqs::0 14 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::3 4 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 79system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 80system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 81system.physmem.totGap 65497035500 # Total gap between requests 82system.physmem.readPktSize::0 0 # Categorize read packet sizes 83system.physmem.readPktSize::1 0 # Categorize read packet sizes 84system.physmem.readPktSize::2 0 # Categorize read packet sizes 85system.physmem.readPktSize::3 0 # Categorize read packet sizes 86system.physmem.readPktSize::4 0 # Categorize read packet sizes 87system.physmem.readPktSize::5 0 # Categorize read packet sizes 88system.physmem.readPktSize::6 30400 # Categorize read packet sizes 89system.physmem.writePktSize::0 0 # Categorize write packet sizes 90system.physmem.writePktSize::1 0 # Categorize write packet sizes 91system.physmem.writePktSize::2 0 # Categorize write packet sizes 92system.physmem.writePktSize::3 0 # Categorize write packet sizes 93system.physmem.writePktSize::4 0 # Categorize write packet sizes 94system.physmem.writePktSize::5 0 # Categorize write packet sizes 95system.physmem.writePktSize::6 156 # Categorize write packet sizes 96system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 365 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 65 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see | 14system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 10688 # Number of bytes written to this memory 20system.physmem.bytes_written::total 10688 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30418 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 167 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 167 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 969553 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 28700336 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 29669889 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 969553 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 969553 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 162893 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 162893 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 162893 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 969553 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 28700336 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 29832782 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 30419 # Number of read requests accepted 38system.physmem.writeReqs 167 # Number of write requests accepted 39system.physmem.readBursts 30419 # Number of DRAM read bursts, including those serviced by the write queue 40system.physmem.writeBursts 167 # Number of DRAM write bursts, including those merged in the write queue 41system.physmem.bytesReadDRAM 1943936 # Total number of bytes read from DRAM 42system.physmem.bytesReadWrQ 2880 # Total number of bytes read from write queue 43system.physmem.bytesWritten 9856 # Total number of bytes written to DRAM 44system.physmem.bytesReadSys 1946816 # Total read bytes from the system interface side 45system.physmem.bytesWrittenSys 10688 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 45 # Number of DRAM read bursts serviced by the write queue 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 49system.physmem.perBankRdBursts::0 1928 # Per bank write bursts 50system.physmem.perBankRdBursts::1 2077 # Per bank write bursts 51system.physmem.perBankRdBursts::2 2029 # Per bank write bursts 52system.physmem.perBankRdBursts::3 1927 # Per bank write bursts 53system.physmem.perBankRdBursts::4 2026 # Per bank write bursts 54system.physmem.perBankRdBursts::5 1899 # Per bank write bursts 55system.physmem.perBankRdBursts::6 1963 # Per bank write bursts 56system.physmem.perBankRdBursts::7 1862 # Per bank write bursts 57system.physmem.perBankRdBursts::8 1939 # Per bank write bursts 58system.physmem.perBankRdBursts::9 1933 # Per bank write bursts 59system.physmem.perBankRdBursts::10 1805 # Per bank write bursts 60system.physmem.perBankRdBursts::11 1795 # Per bank write bursts 61system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 62system.physmem.perBankRdBursts::13 1800 # Per bank write bursts 63system.physmem.perBankRdBursts::14 1821 # Per bank write bursts 64system.physmem.perBankRdBursts::15 1778 # Per bank write bursts 65system.physmem.perBankWrBursts::0 15 # Per bank write bursts 66system.physmem.perBankWrBursts::1 95 # Per bank write bursts 67system.physmem.perBankWrBursts::2 7 # Per bank write bursts 68system.physmem.perBankWrBursts::3 11 # Per bank write bursts 69system.physmem.perBankWrBursts::4 6 # Per bank write bursts 70system.physmem.perBankWrBursts::5 0 # Per bank write bursts 71system.physmem.perBankWrBursts::6 12 # Per bank write bursts 72system.physmem.perBankWrBursts::7 0 # Per bank write bursts 73system.physmem.perBankWrBursts::8 0 # Per bank write bursts 74system.physmem.perBankWrBursts::9 5 # Per bank write bursts 75system.physmem.perBankWrBursts::10 3 # Per bank write bursts 76system.physmem.perBankWrBursts::11 0 # Per bank write bursts 77system.physmem.perBankWrBursts::12 0 # Per bank write bursts 78system.physmem.perBankWrBursts::13 0 # Per bank write bursts 79system.physmem.perBankWrBursts::14 0 # Per bank write bursts 80system.physmem.perBankWrBursts::15 0 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 83system.physmem.totGap 65613689500 # Total gap between requests 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) 90system.physmem.readPktSize::6 30419 # Read request sizes (log2) 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 167 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 29918 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 362 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 73 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 102system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 122system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 128system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see | 130system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see |
| 141system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see |
| 146system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 153system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 160system.physmem.bytesPerActivate::samples 535 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::mean 3610.915888 # Bytes accessed per row activation 162system.physmem.bytesPerActivate::gmean 887.471357 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::stdev 3852.235562 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::64-65 128 23.93% 23.93% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::128-129 47 8.79% 32.71% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::192-193 24 4.49% 37.20% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::256-257 12 2.24% 39.44% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::320-321 11 2.06% 41.50% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::384-385 11 2.06% 43.55% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::448-449 8 1.50% 45.05% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::512-513 3 0.56% 45.61% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::576-577 9 1.68% 47.29% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::640-641 10 1.87% 49.16% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::704-705 2 0.37% 49.53% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::768-769 7 1.31% 50.84% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::832-833 1 0.19% 51.03% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::896-897 3 0.56% 51.59% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::960-961 3 0.56% 52.15% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1088-1089 1 0.19% 52.34% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1152-1153 9 1.68% 54.02% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1216-1217 2 0.37% 54.39% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1344-1345 1 0.19% 54.58% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1408-1409 1 0.19% 54.77% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1472-1473 1 0.19% 54.95% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1536-1537 2 0.37% 55.33% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1600-1601 1 0.19% 55.51% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1664-1665 1 0.19% 55.70% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1856-1857 2 0.37% 56.07% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::2112-2113 1 0.19% 56.26% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::2304-2305 2 0.37% 56.64% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2368-2369 1 0.19% 56.82% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2432-2433 1 0.19% 57.01% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2624-2625 1 0.19% 57.20% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2880-2881 2 0.37% 57.57% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2944-2945 1 0.19% 57.76% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::3264-3265 1 0.19% 57.94% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::4032-4033 1 0.19% 58.13% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::4096-4097 1 0.19% 58.32% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::4608-4609 1 0.19% 58.50% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::5312-5313 2 0.37% 58.88% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::5888-5889 1 0.19% 59.07% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::6144-6145 2 0.37% 59.44% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::7232-7233 1 0.19% 59.63% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::8000-8001 1 0.19% 59.81% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::8192-8193 215 40.19% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 535 # Bytes accessed per row activation 207system.physmem.totQLat 5969250 # Total cycles spent in queuing delays 208system.physmem.totMemAccLat 581474250 # Sum of mem lat for all requests 209system.physmem.totBusLat 151785000 # Total cycles spent in databus access 210system.physmem.totBankLat 423720000 # Total cycles spent in bank access 211system.physmem.avgQLat 196.64 # Average queueing delay per request 212system.physmem.avgBankLat 13957.90 # Average bank access latency per request 213system.physmem.avgBusLat 5000.00 # Average bus latency per request 214system.physmem.avgMemAccLat 19154.54 # Average memory access latency 215system.physmem.avgRdBW 29.70 # Average achieved read bandwidth in MB/s 216system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s 217system.physmem.avgConsumedRdBW 29.70 # Average consumed read bandwidth in MB/s 218system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s 219system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 162system.physmem.bytesPerActivate::samples 1275 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::mean 1527.767843 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::gmean 562.023414 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::stdev 1657.823974 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::64 326 25.57% 25.57% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::128 105 8.24% 33.80% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::192 43 3.37% 37.18% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::256 28 2.20% 39.37% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::320 22 1.73% 41.10% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::384 22 1.73% 42.82% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::448 19 1.49% 44.31% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::512 15 1.18% 45.49% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::576 17 1.33% 46.82% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::640 13 1.02% 47.84% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::704 46 3.61% 51.45% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::768 12 0.94% 52.39% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::832 8 0.63% 53.02% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::896 7 0.55% 53.57% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::960 12 0.94% 54.51% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1024 11 0.86% 55.37% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1088 8 0.63% 56.00% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1152 16 1.25% 57.25% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1216 7 0.55% 57.80% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1280 9 0.71% 58.51% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1344 9 0.71% 59.22% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1408 7 0.55% 59.76% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1472 11 0.86% 60.63% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1536 6 0.47% 61.10% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1600 14 1.10% 62.20% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1664 4 0.31% 62.51% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1728 9 0.71% 63.22% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1792 6 0.47% 63.69% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1856 3 0.24% 63.92% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1920 12 0.94% 64.86% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1984 12 0.94% 65.80% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2048 8 0.63% 66.43% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2112 32 2.51% 68.94% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2176 7 0.55% 69.49% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2240 7 0.55% 70.04% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2304 5 0.39% 70.43% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2368 6 0.47% 70.90% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2432 10 0.78% 71.69% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2496 5 0.39% 72.08% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2560 7 0.55% 72.63% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2624 3 0.24% 72.86% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2688 9 0.71% 73.57% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2752 7 0.55% 74.12% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2816 6 0.47% 74.59% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2880 5 0.39% 74.98% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2944 11 0.86% 75.84% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3008 9 0.71% 76.55% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3072 7 0.55% 77.10% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3136 5 0.39% 77.49% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3200 5 0.39% 77.88% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3264 8 0.63% 78.51% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3328 11 0.86% 79.37% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3392 9 0.71% 80.08% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3456 10 0.78% 80.86% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3520 12 0.94% 81.80% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3584 15 1.18% 82.98% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3648 10 0.78% 83.76% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3712 14 1.10% 84.86% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3776 9 0.71% 85.57% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3840 8 0.63% 86.20% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3904 8 0.63% 86.82% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3968 15 1.18% 88.00% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4032 13 1.02% 89.02% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4096 11 0.86% 89.88% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4160 21 1.65% 91.53% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4224 10 0.78% 92.31% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4288 6 0.47% 92.78% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4352 7 0.55% 93.33% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4416 4 0.31% 93.65% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4480 5 0.39% 94.04% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4544 4 0.31% 94.35% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4608 4 0.31% 94.67% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4672 6 0.47% 95.14% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4736 7 0.55% 95.69% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4800 5 0.39% 96.08% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4864 6 0.47% 96.55% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4928 5 0.39% 96.94% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4992 6 0.47% 97.41% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5056 5 0.39% 97.80% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5120 6 0.47% 98.27% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5184 4 0.31% 98.59% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5248 2 0.16% 98.75% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5312 2 0.16% 98.90% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5376 2 0.16% 99.06% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5440 2 0.16% 99.22% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5568 1 0.08% 99.29% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5696 1 0.08% 99.37% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5952 1 0.08% 99.45% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::6016 1 0.08% 99.53% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::6080 1 0.08% 99.61% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::6208 1 0.08% 99.69% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::6592 1 0.08% 99.76% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::6656 3 0.24% 100.00% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::total 1275 # Bytes accessed per row activation 260system.physmem.totQLat 92483500 # Total ticks spent queuing 261system.physmem.totMemAccLat 678771000 # Total ticks spent from burst creation until serviced by the DRAM 262system.physmem.totBusLat 151870000 # Total ticks spent in databus transfers 263system.physmem.totBankLat 434417500 # Total ticks spent accessing banks 264system.physmem.avgQLat 3044.82 # Average queueing delay per DRAM burst 265system.physmem.avgBankLat 14302.28 # Average bank access latency per DRAM burst 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 267system.physmem.avgMemAccLat 22347.11 # Average memory access latency per DRAM burst 268system.physmem.avgRdBW 29.63 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 29.67 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 0.16 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 220system.physmem.busUtil 0.23 # Data bus utilization in percentage | 273system.physmem.busUtil 0.23 # Data bus utilization in percentage |
| 221system.physmem.avgRdQLen 0.01 # Average read queue length over time 222system.physmem.avgWrQLen 12.39 # Average write queue length over time 223system.physmem.readRowHits 29864 # Number of row buffer hits during reads 224system.physmem.writeRowHits 96 # Number of row buffer hits during writes 225system.physmem.readRowHitRate 98.38 # Row buffer hit rate for reads 226system.physmem.writeRowHitRate 61.54 # Row buffer hit rate for writes 227system.physmem.avgGap 2143508.17 # Average gap between requests 228system.membus.throughput 29855634 # Throughput (bytes/s) 229system.membus.trans_dist::ReadReq 1399 # Transaction distribution 230system.membus.trans_dist::ReadResp 1397 # Transaction distribution 231system.membus.trans_dist::Writeback 156 # Transaction distribution 232system.membus.trans_dist::ReadExReq 29001 # Transaction distribution 233system.membus.trans_dist::ReadExResp 29001 # Transaction distribution 234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60954 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60954 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 60954 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1955456 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1955456 # Cumulative packet size per connected master and slave (bytes) 239system.membus.tot_pkt_size::total 1955456 # Cumulative packet size per connected master and slave (bytes) 240system.membus.data_through_bus 1955456 # Total data (bytes) | 274system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 276system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing 277system.physmem.avgWrQLen 9.96 # Average write queue length when enqueuing 278system.physmem.readRowHits 29156 # Number of row buffer hits during reads 279system.physmem.writeRowHits 97 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes 282system.physmem.avgGap 2145219.69 # Average gap between requests 283system.physmem.pageHitRate 95.78 # Row buffer hit rate, read and write combined 284system.physmem.prechargeAllPercent 0.92 # Percentage of time for which DRAM has all the banks in precharge state 285system.membus.throughput 29832782 # Throughput (bytes/s) 286system.membus.trans_dist::ReadReq 1416 # Transaction distribution 287system.membus.trans_dist::ReadResp 1415 # Transaction distribution 288system.membus.trans_dist::Writeback 167 # Transaction distribution 289system.membus.trans_dist::ReadExReq 29003 # Transaction distribution 290system.membus.trans_dist::ReadExResp 29003 # Transaction distribution 291system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61004 # Packet count per connected master and slave (bytes) 292system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61004 # Packet count per connected master and slave (bytes) 293system.membus.pkt_count::total 61004 # Packet count per connected master and slave (bytes) 294system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957440 # Cumulative packet size per connected master and slave (bytes) 295system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 # Cumulative packet size per connected master and slave (bytes) 296system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes) 297system.membus.data_through_bus 1957440 # Total data (bytes) |
| 241system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 298system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 242system.membus.reqLayer0.occupancy 35006500 # Layer occupancy (ticks) | 299system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks) |
| 243system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) | 300system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 244system.membus.respLayer1.occupancy 284183250 # Layer occupancy (ticks) | 301system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks) |
| 245system.membus.respLayer1.utilization 0.4 # Layer utilization (%) | 302system.membus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 246system.cpu.branchPred.lookups 33858224 # Number of BP lookups 247system.cpu.branchPred.condPredicted 33858224 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 774589 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 19295548 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 19203800 # Number of BTB hits | 303system.cpu.branchPred.lookups 33859770 # Number of BP lookups 304system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 19306649 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 19202709 # Number of BTB hits |
| 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 252system.cpu.branchPred.BTBHitPct 99.524512 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 5017950 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 5443 # Number of incorrect RAS predictions. | 309system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage 310system.cpu.branchPred.usedRAS 5016745 # Number of times the RAS was used to get a target. 311system.cpu.branchPred.RASInCorrect 5399 # Number of incorrect RAS predictions. |
| 255system.cpu.workload.num_syscalls 444 # Number of system calls | 312system.cpu.workload.num_syscalls 444 # Number of system calls |
| 256system.cpu.numCycles 130994109 # number of cpu cycles simulated | 313system.cpu.numCycles 131227460 # number of cpu cycles simulated |
| 257system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 258system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 259system.cpu.fetch.icacheStallCycles 26134025 # Number of cycles fetch is stalled on an Icache miss 260system.cpu.fetch.Insts 182258914 # Number of instructions fetch has processed 261system.cpu.fetch.Branches 33858224 # Number of branches that fetch encountered 262system.cpu.fetch.predictedBranches 24221750 # Number of branches that fetch has predicted taken 263system.cpu.fetch.Cycles 55458228 # Number of cycles fetch has run and was not squashing or blocked 264system.cpu.fetch.SquashCycles 5352681 # Number of cycles fetch has spent squashing 265system.cpu.fetch.BlockedCycles 44757241 # Number of cycles fetch has spent blocked 266system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 267system.cpu.fetch.PendingTrapStallCycles 354 # Number of stall cycles due to pending traps | 316system.cpu.fetch.icacheStallCycles 26135230 # Number of cycles fetch is stalled on an Icache miss 317system.cpu.fetch.Insts 182265293 # Number of instructions fetch has processed 318system.cpu.fetch.Branches 33859770 # Number of branches that fetch encountered 319system.cpu.fetch.predictedBranches 24219454 # Number of branches that fetch has predicted taken 320system.cpu.fetch.Cycles 55459629 # Number of cycles fetch has run and was not squashing or blocked 321system.cpu.fetch.SquashCycles 5354571 # Number of cycles fetch has spent squashing 322system.cpu.fetch.BlockedCycles 44982751 # Number of cycles fetch has spent blocked 323system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 324system.cpu.fetch.PendingTrapStallCycles 314 # Number of stall cycles due to pending traps |
| 268system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR | 325system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR |
| 269system.cpu.fetch.CacheLines 25574362 # Number of cache lines fetched 270system.cpu.fetch.IcacheSquashes 166199 # Number of outstanding Icache misses that were squashed 271system.cpu.fetch.rateDist::samples 130892614 # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::mean 2.454818 # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::stdev 3.314961 # Number of instructions fetched each cycle (Total) | 326system.cpu.fetch.CacheLines 25575393 # Number of cache lines fetched 327system.cpu.fetch.IcacheSquashes 166244 # Number of outstanding Icache misses that were squashed 328system.cpu.fetch.rateDist::samples 131122211 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::mean 2.450609 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::stdev 3.313707 # Number of instructions fetched each cycle (Total) |
| 274system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 331system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 275system.cpu.fetch.rateDist::0 77910684 59.52% 59.52% # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::1 1961091 1.50% 61.02% # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::2 2941416 2.25% 63.27% # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::3 3833946 2.93% 66.20% # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::4 7767539 5.93% 72.13% # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::5 4757616 3.63% 75.77% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::6 2666164 2.04% 77.80% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::7 1316720 1.01% 78.81% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::8 27737438 21.19% 100.00% # Number of instructions fetched each cycle (Total) | 332system.cpu.fetch.rateDist::0 78139546 59.59% 59.59% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::1 1960111 1.49% 61.09% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::2 2942175 2.24% 63.33% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::3 3833696 2.92% 66.26% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::4 7767416 5.92% 72.18% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::5 4757872 3.63% 75.81% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::6 2665225 2.03% 77.84% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::7 1316047 1.00% 78.84% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::8 27740123 21.16% 100.00% # Number of instructions fetched each cycle (Total) |
| 284system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 341system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 287system.cpu.fetch.rateDist::total 130892614 # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.branchRate 0.258471 # Number of branch fetches per cycle 289system.cpu.fetch.rate 1.391352 # Number of inst fetches per cycle 290system.cpu.decode.IdleCycles 36819659 # Number of cycles decode is idle 291system.cpu.decode.BlockedCycles 36980368 # Number of cycles decode is blocked 292system.cpu.decode.RunCycles 43894473 # Number of cycles decode is running 293system.cpu.decode.UnblockCycles 8655405 # Number of cycles decode is unblocking 294system.cpu.decode.SquashCycles 4542709 # Number of cycles decode is squashing 295system.cpu.decode.DecodedInsts 318839804 # Number of instructions handled by decode 296system.cpu.rename.SquashCycles 4542709 # Number of cycles rename is squashing 297system.cpu.rename.IdleCycles 42306626 # Number of cycles rename is idle 298system.cpu.rename.BlockCycles 9548363 # Number of cycles rename is blocking 299system.cpu.rename.serializeStallCycles 7363 # count of cycles rename stalled for serializing inst 300system.cpu.rename.RunCycles 46754553 # Number of cycles rename is running 301system.cpu.rename.UnblockCycles 27733000 # Number of cycles rename is unblocking 302system.cpu.rename.RenamedInsts 314999780 # Number of instructions processed by rename 303system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full 304system.cpu.rename.IQFullEvents 26808 # Number of times rename has blocked due to IQ full 305system.cpu.rename.LSQFullEvents 25879667 # Number of times rename has blocked due to LSQ full 306system.cpu.rename.RenamedOperands 317173158 # Number of destination operands rename has renamed 307system.cpu.rename.RenameLookups 836491506 # Number of register rename lookups that rename has made 308system.cpu.rename.int_rename_lookups 515038229 # Number of integer rename lookups 309system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups | 344system.cpu.fetch.rateDist::total 131122211 # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.branchRate 0.258024 # Number of branch fetches per cycle 346system.cpu.fetch.rate 1.388926 # Number of inst fetches per cycle 347system.cpu.decode.IdleCycles 36831320 # Number of cycles decode is idle 348system.cpu.decode.BlockedCycles 37195756 # Number of cycles decode is blocked 349system.cpu.decode.RunCycles 43906245 # Number of cycles decode is running 350system.cpu.decode.UnblockCycles 8644656 # Number of cycles decode is unblocking 351system.cpu.decode.SquashCycles 4544234 # Number of cycles decode is squashing 352system.cpu.decode.DecodedInsts 318852911 # Number of instructions handled by decode 353system.cpu.rename.SquashCycles 4544234 # Number of cycles rename is squashing 354system.cpu.rename.IdleCycles 42322552 # Number of cycles rename is idle 355system.cpu.rename.BlockCycles 9742718 # Number of cycles rename is blocking 356system.cpu.rename.serializeStallCycles 7418 # count of cycles rename stalled for serializing inst 357system.cpu.rename.RunCycles 46754999 # Number of cycles rename is running 358system.cpu.rename.UnblockCycles 27750290 # Number of cycles rename is unblocking 359system.cpu.rename.RenamedInsts 315016174 # Number of instructions processed by rename 360system.cpu.rename.ROBFullEvents 215 # Number of times rename has blocked due to ROB full 361system.cpu.rename.IQFullEvents 26317 # Number of times rename has blocked due to IQ full 362system.cpu.rename.LSQFullEvents 25895473 # Number of times rename has blocked due to LSQ full 363system.cpu.rename.RenamedOperands 317188133 # Number of destination operands rename has renamed 364system.cpu.rename.RenameLookups 836523485 # Number of register rename lookups that rename has made 365system.cpu.rename.int_rename_lookups 515056961 # Number of integer rename lookups 366system.cpu.rename.fp_rename_lookups 484 # Number of floating rename lookups |
| 310system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed | 367system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed |
| 311system.cpu.rename.UndoneMaps 37960411 # Number of HB maps that are undone due to squashing | 368system.cpu.rename.UndoneMaps 37975386 # Number of HB maps that are undone due to squashing |
| 312system.cpu.rename.serializingInsts 483 # count of serializing insts renamed 313system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed | 369system.cpu.rename.serializingInsts 483 # count of serializing insts renamed 370system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed |
| 314system.cpu.rename.skidInsts 62657657 # count of insts added to the skid buffer 315system.cpu.memDep0.insertedLoads 101560400 # Number of loads inserted to the mem dependence unit. 316system.cpu.memDep0.insertedStores 34776362 # Number of stores inserted to the mem dependence unit. 317system.cpu.memDep0.conflictingLoads 39636404 # Number of conflicting loads. 318system.cpu.memDep0.conflictingStores 5873969 # Number of conflicting stores. 319system.cpu.iq.iqInstsAdded 311477073 # Number of instructions added to the IQ (excludes non-spec) 320system.cpu.iq.iqNonSpecInstsAdded 1619 # Number of non-speculative instructions added to the IQ 321system.cpu.iq.iqInstsIssued 300261813 # Number of instructions issued 322system.cpu.iq.iqSquashedInstsIssued 90477 # Number of squashed instructions issued 323system.cpu.iq.iqSquashedInstsExamined 32704303 # Number of squashed instructions iterated over during squash; mainly for profiling 324system.cpu.iq.iqSquashedOperandsExamined 46143152 # Number of squashed operands that are examined and possibly removed from graph 325system.cpu.iq.iqSquashedNonSpecRemoved 1174 # Number of squashed non-spec instructions that were removed 326system.cpu.iq.issued_per_cycle::samples 130892614 # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::mean 2.293955 # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::stdev 1.698909 # Number of insts issued each cycle | 371system.cpu.rename.skidInsts 62628696 # count of insts added to the skid buffer 372system.cpu.memDep0.insertedLoads 101555761 # Number of loads inserted to the mem dependence unit. 373system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit. 374system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads. 375system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores. 376system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec) 377system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ 378system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued 379system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued 380system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling 381system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph 382system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed 383system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle |
| 329system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 386system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 330system.cpu.iq.issued_per_cycle::0 24143436 18.45% 18.45% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::1 23235636 17.75% 36.20% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::2 25474582 19.46% 55.66% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::3 25828603 19.73% 75.39% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::4 18887958 14.43% 89.82% # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::5 8220714 6.28% 96.10% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::6 3961121 3.03% 99.13% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::7 955436 0.73% 99.86% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::8 185128 0.14% 100.00% # Number of insts issued each cycle | 387system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle |
| 339system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 396system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 342system.cpu.iq.issued_per_cycle::total 130892614 # Number of insts issued each cycle | 399system.cpu.iq.issued_per_cycle::total 131122211 # Number of insts issued each cycle |
| 343system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 400system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 344system.cpu.iq.fu_full::IntAlu 31366 1.52% 1.52% # attempts to use FU when none available 345system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available 346system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available 347system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available 348system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available 349system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available 350system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available 351system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available 352system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available 373system.cpu.iq.fu_full::MemRead 1915737 93.06% 94.58% # attempts to use FU when none available 374system.cpu.iq.fu_full::MemWrite 111488 5.42% 100.00% # attempts to use FU when none available | 401system.cpu.iq.fu_full::IntAlu 31436 1.53% 1.53% # attempts to use FU when none available 402system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available 403system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available 430system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available 431system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available |
| 375system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 376system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 432system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 433system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 377system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued 378system.cpu.iq.FU_type_0::IntAlu 169828970 56.56% 56.57% # Type of FU issued 379system.cpu.iq.FU_type_0::IntMult 11213 0.00% 56.57% # Type of FU issued 380system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.57% # Type of FU issued 381system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 56.57% # Type of FU issued 382system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued 383system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued 384system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued 385system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued 386system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued 407system.cpu.iq.FU_type_0::MemRead 97302750 32.41% 88.98% # Type of FU issued 408system.cpu.iq.FU_type_0::MemWrite 33087237 11.02% 100.00% # Type of FU issued | 434system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued 435system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued 436system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued 437system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued 440system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued 443system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued 464system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued 465system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued |
| 409system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 410system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 466system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 467system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 411system.cpu.iq.FU_type_0::total 300261813 # Type of FU issued 412system.cpu.iq.rate 2.292178 # Inst issue rate 413system.cpu.iq.fu_busy_cnt 2058591 # FU busy when requested 414system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst) 415system.cpu.iq.int_inst_queue_reads 733564971 # Number of integer instruction queue reads 416system.cpu.iq.int_inst_queue_writes 344215080 # Number of integer instruction queue writes 417system.cpu.iq.int_inst_queue_wakeup_accesses 298003281 # Number of integer instruction queue wakeup accesses 418system.cpu.iq.fp_inst_queue_reads 337 # Number of floating instruction queue reads 419system.cpu.iq.fp_inst_queue_writes 435 # Number of floating instruction queue writes 420system.cpu.iq.fp_inst_queue_wakeup_accesses 126 # Number of floating instruction queue wakeup accesses 421system.cpu.iq.int_alu_accesses 302288959 # Number of integer alu accesses 422system.cpu.iq.fp_alu_accesses 169 # Number of floating point alu accesses 423system.cpu.iew.lsq.thread0.forwLoads 54190051 # Number of loads that had data forwarded from stores | 468system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued 469system.cpu.iq.rate 2.288206 # Inst issue rate 470system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested 471system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst) 472system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads 473system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes 474system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses 475system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads 476system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes 477system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses 478system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses 479system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses 480system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores |
| 424system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 481system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 425system.cpu.iew.lsq.thread0.squashedLoads 10781015 # Number of loads squashed 426system.cpu.iew.lsq.thread0.ignoredResponses 32177 # Number of memory responses ignored because the instruction is squashed 427system.cpu.iew.lsq.thread0.memOrderViolation 33336 # Number of memory ordering violations 428system.cpu.iew.lsq.thread0.squashedStores 3336610 # Number of stores squashed | 482system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed 483system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed 484system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations 485system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed |
| 429system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 430system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 486system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 487system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 431system.cpu.iew.lsq.thread0.rescheduledLoads 3220 # Number of loads that were rescheduled 432system.cpu.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked | 488system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled 489system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked |
| 433system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 490system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 434system.cpu.iew.iewSquashCycles 4542709 # Number of cycles IEW is squashing 435system.cpu.iew.iewBlockCycles 2622554 # Number of cycles IEW is blocking 436system.cpu.iew.iewUnblockCycles 162089 # Number of cycles IEW is unblocking 437system.cpu.iew.iewDispatchedInsts 311478692 # Number of instructions dispatched to IQ 438system.cpu.iew.iewDispSquashedInsts 196017 # Number of squashed instructions skipped by dispatch 439system.cpu.iew.iewDispLoadInsts 101560400 # Number of dispatched load instructions 440system.cpu.iew.iewDispStoreInsts 34776362 # Number of dispatched store instructions 441system.cpu.iew.iewDispNonSpecInsts 469 # Number of dispatched non-speculative instructions 442system.cpu.iew.iewIQFullEvents 2626 # Number of times the IQ has become full, causing a stall 443system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall 444system.cpu.iew.memOrderViolationEvents 33336 # Number of memory order violations 445system.cpu.iew.predictedTakenIncorrect 393441 # Number of branches that were predicted taken incorrectly 446system.cpu.iew.predictedNotTakenIncorrect 427689 # Number of branches that were predicted not taken incorrectly 447system.cpu.iew.branchMispredicts 821130 # Number of branch mispredicts detected at execute 448system.cpu.iew.iewExecutedInsts 298856938 # Number of executed instructions 449system.cpu.iew.iewExecLoadInsts 96890588 # Number of load instructions executed 450system.cpu.iew.iewExecSquashedInsts 1404875 # Number of squashed instructions skipped in execute | 491system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing 492system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking 493system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking 494system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ 495system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch 496system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions 497system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions 498system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions 499system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall 500system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall 501system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations 502system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly 503system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly 504system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute 505system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions 506system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed 507system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute |
| 451system.cpu.iew.exec_swp 0 # number of swp insts executed 452system.cpu.iew.exec_nop 0 # number of nop insts executed | 508system.cpu.iew.exec_swp 0 # number of swp insts executed 509system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 453system.cpu.iew.exec_refs 129814899 # number of memory reference insts executed 454system.cpu.iew.exec_branches 30818444 # Number of branches executed 455system.cpu.iew.exec_stores 32924311 # Number of stores executed 456system.cpu.iew.exec_rate 2.281453 # Inst execution rate 457system.cpu.iew.wb_sent 298373185 # cumulative count of insts sent to commit 458system.cpu.iew.wb_count 298003407 # cumulative count of insts written-back 459system.cpu.iew.wb_producers 218253384 # num instructions producing a value 460system.cpu.iew.wb_consumers 296750864 # num instructions consuming a value | 510system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed 511system.cpu.iew.exec_branches 30820824 # Number of branches executed 512system.cpu.iew.exec_stores 32925944 # Number of stores executed 513system.cpu.iew.exec_rate 2.277516 # Inst execution rate 514system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit 515system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back 516system.cpu.iew.wb_producers 218260008 # num instructions producing a value 517system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value |
| 461system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 518system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 462system.cpu.iew.wb_rate 2.274937 # insts written-back per cycle 463system.cpu.iew.wb_fanout 0.735477 # average fanout of values written-back | 519system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle 520system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back |
| 464system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 521system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 465system.cpu.commit.commitSquashedInsts 33298978 # The number of squashed insts skipped by commit | 522system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit |
| 466system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards | 523system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards |
| 467system.cpu.commit.branchMispredicts 774634 # The number of times a branch was mispredicted 468system.cpu.commit.committed_per_cycle::samples 126349905 # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::mean 2.201762 # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::stdev 2.972659 # Number of insts commited each cycle | 524system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted 525system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::mean 2.197795 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::stdev 2.970921 # Number of insts commited each cycle |
| 471system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 528system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 472system.cpu.commit.committed_per_cycle::0 58072656 45.96% 45.96% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::1 19155409 15.16% 61.12% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::2 11632100 9.21% 70.33% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::3 9445412 7.48% 77.80% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::4 1855076 1.47% 79.27% # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::5 2067896 1.64% 80.91% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::6 1301136 1.03% 81.94% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::7 691741 0.55% 82.49% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::8 22128479 17.51% 100.00% # Number of insts commited each cycle | 529system.cpu.commit.committed_per_cycle::0 58251121 46.02% 46.02% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::1 19170530 15.15% 61.17% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::2 11719383 9.26% 70.42% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::3 9409192 7.43% 77.86% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::4 1839491 1.45% 79.31% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::5 2078967 1.64% 80.95% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::6 1287907 1.02% 81.97% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::7 695737 0.55% 82.52% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::8 22125649 17.48% 100.00% # Number of insts commited each cycle |
| 481system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 538system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 484system.cpu.commit.committed_per_cycle::total 126349905 # Number of insts commited each cycle | 541system.cpu.commit.committed_per_cycle::total 126577977 # Number of insts commited each cycle |
| 485system.cpu.commit.committedInsts 157988547 # Number of instructions committed 486system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 487system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 488system.cpu.commit.refs 122219137 # Number of memory references committed 489system.cpu.commit.loads 90779385 # Number of loads committed 490system.cpu.commit.membars 0 # Number of memory barriers committed 491system.cpu.commit.branches 29309705 # Number of branches committed 492system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 493system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 494system.cpu.commit.function_calls 4237596 # Number of function calls committed. | 542system.cpu.commit.committedInsts 157988547 # Number of instructions committed 543system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 544system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 545system.cpu.commit.refs 122219137 # Number of memory references committed 546system.cpu.commit.loads 90779385 # Number of loads committed 547system.cpu.commit.membars 0 # Number of memory barriers committed 548system.cpu.commit.branches 29309705 # Number of branches committed 549system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 550system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 551system.cpu.commit.function_calls 4237596 # Number of function calls committed. |
| 495system.cpu.commit.bw_lim_events 22128479 # number cycles where commit BW limit reached | 552system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached |
| 496system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 553system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 497system.cpu.rob.rob_reads 415712868 # The number of ROB reads 498system.cpu.rob.rob_writes 627529396 # The number of ROB writes 499system.cpu.timesIdled 13705 # Number of times that the entire CPU went into an idle state and unscheduled itself 500system.cpu.idleCycles 101495 # Total number of cycles that the CPU has spent unscheduled due to idling | 554system.cpu.rob.rob_reads 415950983 # The number of ROB reads 555system.cpu.rob.rob_writes 627545403 # The number of ROB writes 556system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself 557system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 501system.cpu.committedInsts 157988547 # Number of Instructions Simulated 502system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 503system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated | 558system.cpu.committedInsts 157988547 # Number of Instructions Simulated 559system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 560system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated |
| 504system.cpu.cpi 0.829137 # CPI: Cycles Per Instruction 505system.cpu.cpi_total 0.829137 # CPI: Total CPI of All Threads 506system.cpu.ipc 1.206074 # IPC: Instructions Per Cycle 507system.cpu.ipc_total 1.206074 # IPC: Total IPC of All Threads 508system.cpu.int_regfile_reads 483722109 # number of integer regfile reads 509system.cpu.int_regfile_writes 234582139 # number of integer regfile writes 510system.cpu.fp_regfile_reads 117 # number of floating regfile reads 511system.cpu.fp_regfile_writes 75 # number of floating regfile writes 512system.cpu.cc_regfile_reads 107053198 # number of cc regfile reads 513system.cpu.cc_regfile_writes 64000024 # number of cc regfile writes 514system.cpu.misc_regfile_reads 191821503 # number of misc regfile reads | 561system.cpu.cpi 0.830614 # CPI: Cycles Per Instruction 562system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads 563system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle 564system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads 565system.cpu.int_regfile_reads 483744134 # number of integer regfile reads 566system.cpu.int_regfile_writes 234595253 # number of integer regfile writes 567system.cpu.fp_regfile_reads 141 # number of floating regfile reads 568system.cpu.fp_regfile_writes 77 # number of floating regfile writes 569system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads 570system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes 571system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads |
| 515system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 572system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 516system.cpu.toL2Bus.throughput 4049501312 # Throughput (bytes/s) 517system.cpu.toL2Bus.trans_dist::ReadReq 1995298 # Transaction distribution 518system.cpu.toL2Bus.trans_dist::ReadResp 1995296 # Transaction distribution 519system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution 520system.cpu.toL2Bus.trans_dist::ReadExReq 82299 # Transaction distribution 521system.cpu.toL2Bus.trans_dist::ReadExResp 82299 # Transaction distribution 522system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2012 # Packet count per connected master and slave (bytes) 523system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219810 # Packet count per connected master and slave (bytes) 524system.cpu.toL2Bus.pkt_count::total 6221822 # Packet count per connected master and slave (bytes) 525system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64384 # Cumulative packet size per connected master and slave (bytes) 526system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265166016 # Cumulative packet size per connected master and slave (bytes) 527system.cpu.toL2Bus.tot_pkt_size::total 265230400 # Cumulative packet size per connected master and slave (bytes) 528system.cpu.toL2Bus.data_through_bus 265230400 # Total data (bytes) | 573system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s) 574system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadResp 1995298 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::Writeback 2066887 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::ReadExReq 82323 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::ReadExResp 82323 # Transaction distribution 579system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2022 # Packet count per connected master and slave (bytes) 580system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6220108 # Packet count per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_count::total 6222130 # Packet count per connected master and slave (bytes) 582system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64704 # Cumulative packet size per connected master and slave (bytes) 583system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265183808 # Cumulative packet size per connected master and slave (bytes) 584system.cpu.toL2Bus.tot_pkt_size::total 265248512 # Cumulative packet size per connected master and slave (bytes) 585system.cpu.toL2Bus.data_through_bus 265248512 # Total data (bytes) |
| 529system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 586system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 530system.cpu.toL2Bus.reqLayer0.occupancy 4138743500 # Layer occupancy (ticks) | 587system.cpu.toL2Bus.reqLayer0.occupancy 4139141500 # Layer occupancy (ticks) |
| 531system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) | 588system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) |
| 532system.cpu.toL2Bus.respLayer0.occupancy 1699750 # Layer occupancy (ticks) | 589system.cpu.toL2Bus.respLayer0.occupancy 1689999 # Layer occupancy (ticks) |
| 533system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 590system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 534system.cpu.toL2Bus.respLayer1.occupancy 3122104250 # Layer occupancy (ticks) | 591system.cpu.toL2Bus.respLayer1.occupancy 3122002000 # Layer occupancy (ticks) |
| 535system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) | 592system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) |
| 536system.cpu.icache.tags.replacements 55 # number of replacements 537system.cpu.icache.tags.tagsinuse 816.683247 # Cycle average of tags in use 538system.cpu.icache.tags.total_refs 25573067 # Total number of references to valid blocks. 539system.cpu.icache.tags.sampled_refs 1006 # Sample count of references to valid blocks. 540system.cpu.icache.tags.avg_refs 25420.543738 # Average number of references to valid blocks. | 593system.cpu.icache.tags.replacements 57 # number of replacements 594system.cpu.icache.tags.tagsinuse 819.642194 # Cycle average of tags in use 595system.cpu.icache.tags.total_refs 25574088 # Total number of references to valid blocks. 596system.cpu.icache.tags.sampled_refs 1011 # Sample count of references to valid blocks. 597system.cpu.icache.tags.avg_refs 25295.833828 # Average number of references to valid blocks. |
| 541system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 598system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 542system.cpu.icache.tags.occ_blocks::cpu.inst 816.683247 # Average occupied blocks per requestor 543system.cpu.icache.tags.occ_percent::cpu.inst 0.398771 # Average percentage of cache occupancy 544system.cpu.icache.tags.occ_percent::total 0.398771 # Average percentage of cache occupancy 545system.cpu.icache.ReadReq_hits::cpu.inst 25573067 # number of ReadReq hits 546system.cpu.icache.ReadReq_hits::total 25573067 # number of ReadReq hits 547system.cpu.icache.demand_hits::cpu.inst 25573067 # number of demand (read+write) hits 548system.cpu.icache.demand_hits::total 25573067 # number of demand (read+write) hits 549system.cpu.icache.overall_hits::cpu.inst 25573067 # number of overall hits 550system.cpu.icache.overall_hits::total 25573067 # number of overall hits 551system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses 552system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses 553system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses 554system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses 555system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses 556system.cpu.icache.overall_misses::total 1295 # number of overall misses 557system.cpu.icache.ReadReq_miss_latency::cpu.inst 85604250 # number of ReadReq miss cycles 558system.cpu.icache.ReadReq_miss_latency::total 85604250 # number of ReadReq miss cycles 559system.cpu.icache.demand_miss_latency::cpu.inst 85604250 # number of demand (read+write) miss cycles 560system.cpu.icache.demand_miss_latency::total 85604250 # number of demand (read+write) miss cycles 561system.cpu.icache.overall_miss_latency::cpu.inst 85604250 # number of overall miss cycles 562system.cpu.icache.overall_miss_latency::total 85604250 # number of overall miss cycles 563system.cpu.icache.ReadReq_accesses::cpu.inst 25574362 # number of ReadReq accesses(hits+misses) 564system.cpu.icache.ReadReq_accesses::total 25574362 # number of ReadReq accesses(hits+misses) 565system.cpu.icache.demand_accesses::cpu.inst 25574362 # number of demand (read+write) accesses 566system.cpu.icache.demand_accesses::total 25574362 # number of demand (read+write) accesses 567system.cpu.icache.overall_accesses::cpu.inst 25574362 # number of overall (read+write) accesses 568system.cpu.icache.overall_accesses::total 25574362 # number of overall (read+write) accesses | 599system.cpu.icache.tags.occ_blocks::cpu.inst 819.642194 # Average occupied blocks per requestor 600system.cpu.icache.tags.occ_percent::cpu.inst 0.400216 # Average percentage of cache occupancy 601system.cpu.icache.tags.occ_percent::total 0.400216 # Average percentage of cache occupancy 602system.cpu.icache.ReadReq_hits::cpu.inst 25574088 # number of ReadReq hits 603system.cpu.icache.ReadReq_hits::total 25574088 # number of ReadReq hits 604system.cpu.icache.demand_hits::cpu.inst 25574088 # number of demand (read+write) hits 605system.cpu.icache.demand_hits::total 25574088 # number of demand (read+write) hits 606system.cpu.icache.overall_hits::cpu.inst 25574088 # number of overall hits 607system.cpu.icache.overall_hits::total 25574088 # number of overall hits 608system.cpu.icache.ReadReq_misses::cpu.inst 1305 # number of ReadReq misses 609system.cpu.icache.ReadReq_misses::total 1305 # number of ReadReq misses 610system.cpu.icache.demand_misses::cpu.inst 1305 # number of demand (read+write) misses 611system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses 612system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses 613system.cpu.icache.overall_misses::total 1305 # number of overall misses 614system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles 615system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles 616system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles 617system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles 618system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles 619system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles 620system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses) 621system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses) 622system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses 623system.cpu.icache.demand_accesses::total 25575393 # number of demand (read+write) accesses 624system.cpu.icache.overall_accesses::cpu.inst 25575393 # number of overall (read+write) accesses 625system.cpu.icache.overall_accesses::total 25575393 # number of overall (read+write) accesses |
| 569system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 570system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 571system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 572system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 573system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 574system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses | 626system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 627system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 628system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 629system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 630system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 631system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses |
| 575system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66103.667954 # average ReadReq miss latency 576system.cpu.icache.ReadReq_avg_miss_latency::total 66103.667954 # average ReadReq miss latency 577system.cpu.icache.demand_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency 578system.cpu.icache.demand_avg_miss_latency::total 66103.667954 # average overall miss latency 579system.cpu.icache.overall_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency 580system.cpu.icache.overall_avg_miss_latency::total 66103.667954 # average overall miss latency 581system.cpu.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked | 632system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency 633system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency 634system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency 635system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency 636system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency 637system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency 638system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked |
| 582system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 583system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 584system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 639system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 640system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 641system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 585system.cpu.icache.avg_blocked_cycles::no_mshrs 37.666667 # average number of cycles each access was blocked | 642system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked |
| 586system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 587system.cpu.icache.fast_writes 0 # number of fast writes performed 588system.cpu.icache.cache_copies 0 # number of cache copies performed | 643system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 644system.cpu.icache.fast_writes 0 # number of fast writes performed 645system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 589system.cpu.icache.ReadReq_mshr_hits::cpu.inst 289 # number of ReadReq MSHR hits 590system.cpu.icache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits 591system.cpu.icache.demand_mshr_hits::cpu.inst 289 # number of demand (read+write) MSHR hits 592system.cpu.icache.demand_mshr_hits::total 289 # number of demand (read+write) MSHR hits 593system.cpu.icache.overall_mshr_hits::cpu.inst 289 # number of overall MSHR hits 594system.cpu.icache.overall_mshr_hits::total 289 # number of overall MSHR hits 595system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1006 # number of ReadReq MSHR misses 596system.cpu.icache.ReadReq_mshr_misses::total 1006 # number of ReadReq MSHR misses 597system.cpu.icache.demand_mshr_misses::cpu.inst 1006 # number of demand (read+write) MSHR misses 598system.cpu.icache.demand_mshr_misses::total 1006 # number of demand (read+write) MSHR misses 599system.cpu.icache.overall_mshr_misses::cpu.inst 1006 # number of overall MSHR misses 600system.cpu.icache.overall_mshr_misses::total 1006 # number of overall MSHR misses 601system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67541250 # number of ReadReq MSHR miss cycles 602system.cpu.icache.ReadReq_mshr_miss_latency::total 67541250 # number of ReadReq MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67541250 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.demand_mshr_miss_latency::total 67541250 # number of demand (read+write) MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67541250 # number of overall MSHR miss cycles 606system.cpu.icache.overall_mshr_miss_latency::total 67541250 # number of overall MSHR miss cycles 607system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses 608system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses 609system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses 610system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses 611system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses 612system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67138.419483 # average ReadReq mshr miss latency 614system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67138.419483 # average ReadReq mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency 616system.cpu.icache.demand_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency 618system.cpu.icache.overall_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency | 646system.cpu.icache.ReadReq_mshr_hits::cpu.inst 294 # number of ReadReq MSHR hits 647system.cpu.icache.ReadReq_mshr_hits::total 294 # number of ReadReq MSHR hits 648system.cpu.icache.demand_mshr_hits::cpu.inst 294 # number of demand (read+write) MSHR hits 649system.cpu.icache.demand_mshr_hits::total 294 # number of demand (read+write) MSHR hits 650system.cpu.icache.overall_mshr_hits::cpu.inst 294 # number of overall MSHR hits 651system.cpu.icache.overall_mshr_hits::total 294 # number of overall MSHR hits 652system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1011 # number of ReadReq MSHR misses 653system.cpu.icache.ReadReq_mshr_misses::total 1011 # number of ReadReq MSHR misses 654system.cpu.icache.demand_mshr_misses::cpu.inst 1011 # number of demand (read+write) MSHR misses 655system.cpu.icache.demand_mshr_misses::total 1011 # number of demand (read+write) MSHR misses 656system.cpu.icache.overall_mshr_misses::cpu.inst 1011 # number of overall MSHR misses 657system.cpu.icache.overall_mshr_misses::total 1011 # number of overall MSHR misses 658system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226001 # number of ReadReq MSHR miss cycles 659system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226001 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.demand_mshr_miss_latency::total 69226001 # number of demand (read+write) MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles 663system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles 664system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 665system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 666system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 667system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 668system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 669system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses 670system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68472.800198 # average ReadReq mshr miss latency 671system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency 673system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency 674system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency 675system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency |
| 619system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 676system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 620system.cpu.l2cache.tags.replacements 461 # number of replacements 621system.cpu.l2cache.tags.tagsinuse 20819.547231 # Cycle average of tags in use 622system.cpu.l2cache.tags.total_refs 4029398 # Total number of references to valid blocks. 623system.cpu.l2cache.tags.sampled_refs 30381 # Sample count of references to valid blocks. 624system.cpu.l2cache.tags.avg_refs 132.628880 # Average number of references to valid blocks. | 677system.cpu.l2cache.tags.replacements 479 # number of replacements 678system.cpu.l2cache.tags.tagsinuse 20806.493932 # Cycle average of tags in use 679system.cpu.l2cache.tags.total_refs 4029616 # Total number of references to valid blocks. 680system.cpu.l2cache.tags.sampled_refs 30401 # Sample count of references to valid blocks. 681system.cpu.l2cache.tags.avg_refs 132.548798 # Average number of references to valid blocks. |
| 625system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 682system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 626system.cpu.l2cache.tags.occ_blocks::writebacks 19905.791561 # Average occupied blocks per requestor 627system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.283783 # Average occupied blocks per requestor 628system.cpu.l2cache.tags.occ_blocks::cpu.data 246.471887 # Average occupied blocks per requestor 629system.cpu.l2cache.tags.occ_percent::writebacks 0.607477 # Average percentage of cache occupancy 630system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020364 # Average percentage of cache occupancy 631system.cpu.l2cache.tags.occ_percent::cpu.data 0.007522 # Average percentage of cache occupancy 632system.cpu.l2cache.tags.occ_percent::total 0.635362 # Average percentage of cache occupancy | 683system.cpu.l2cache.tags.occ_blocks::writebacks 19891.107618 # Average occupied blocks per requestor 684system.cpu.l2cache.tags.occ_blocks::cpu.inst 670.515764 # Average occupied blocks per requestor 685system.cpu.l2cache.tags.occ_blocks::cpu.data 244.870550 # Average occupied blocks per requestor 686system.cpu.l2cache.tags.occ_percent::writebacks 0.607028 # Average percentage of cache occupancy 687system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020463 # Average percentage of cache occupancy 688system.cpu.l2cache.tags.occ_percent::cpu.data 0.007473 # Average percentage of cache occupancy 689system.cpu.l2cache.tags.occ_percent::total 0.634964 # Average percentage of cache occupancy |
| 633system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits | 690system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits |
| 634system.cpu.l2cache.ReadReq_hits::cpu.data 1993882 # number of ReadReq hits 635system.cpu.l2cache.ReadReq_hits::total 1993899 # number of ReadReq hits 636system.cpu.l2cache.Writeback_hits::writebacks 2066630 # number of Writeback hits 637system.cpu.l2cache.Writeback_hits::total 2066630 # number of Writeback hits 638system.cpu.l2cache.ReadExReq_hits::cpu.data 53298 # number of ReadExReq hits 639system.cpu.l2cache.ReadExReq_hits::total 53298 # number of ReadExReq hits | 691system.cpu.l2cache.ReadReq_hits::cpu.data 1993866 # number of ReadReq hits 692system.cpu.l2cache.ReadReq_hits::total 1993883 # number of ReadReq hits 693system.cpu.l2cache.Writeback_hits::writebacks 2066887 # number of Writeback hits 694system.cpu.l2cache.Writeback_hits::total 2066887 # number of Writeback hits 695system.cpu.l2cache.ReadExReq_hits::cpu.data 53320 # number of ReadExReq hits 696system.cpu.l2cache.ReadExReq_hits::total 53320 # number of ReadExReq hits |
| 640system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits | 697system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits |
| 641system.cpu.l2cache.demand_hits::cpu.data 2047180 # number of demand (read+write) hits 642system.cpu.l2cache.demand_hits::total 2047197 # number of demand (read+write) hits | 698system.cpu.l2cache.demand_hits::cpu.data 2047186 # number of demand (read+write) hits 699system.cpu.l2cache.demand_hits::total 2047203 # number of demand (read+write) hits |
| 643system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits | 700system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits |
| 644system.cpu.l2cache.overall_hits::cpu.data 2047180 # number of overall hits 645system.cpu.l2cache.overall_hits::total 2047197 # number of overall hits 646system.cpu.l2cache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses 647system.cpu.l2cache.ReadReq_misses::cpu.data 410 # number of ReadReq misses 648system.cpu.l2cache.ReadReq_misses::total 1399 # number of ReadReq misses 649system.cpu.l2cache.ReadExReq_misses::cpu.data 29001 # number of ReadExReq misses 650system.cpu.l2cache.ReadExReq_misses::total 29001 # number of ReadExReq misses 651system.cpu.l2cache.demand_misses::cpu.inst 989 # number of demand (read+write) misses 652system.cpu.l2cache.demand_misses::cpu.data 29411 # number of demand (read+write) misses 653system.cpu.l2cache.demand_misses::total 30400 # number of demand (read+write) misses 654system.cpu.l2cache.overall_misses::cpu.inst 989 # number of overall misses 655system.cpu.l2cache.overall_misses::cpu.data 29411 # number of overall misses 656system.cpu.l2cache.overall_misses::total 30400 # number of overall misses 657system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 66362250 # number of ReadReq miss cycles 658system.cpu.l2cache.ReadReq_miss_latency::cpu.data 27817000 # number of ReadReq miss cycles 659system.cpu.l2cache.ReadReq_miss_latency::total 94179250 # number of ReadReq miss cycles 660system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1783074500 # number of ReadExReq miss cycles 661system.cpu.l2cache.ReadExReq_miss_latency::total 1783074500 # number of ReadExReq miss cycles 662system.cpu.l2cache.demand_miss_latency::cpu.inst 66362250 # number of demand (read+write) miss cycles 663system.cpu.l2cache.demand_miss_latency::cpu.data 1810891500 # number of demand (read+write) miss cycles 664system.cpu.l2cache.demand_miss_latency::total 1877253750 # number of demand (read+write) miss cycles 665system.cpu.l2cache.overall_miss_latency::cpu.inst 66362250 # number of overall miss cycles 666system.cpu.l2cache.overall_miss_latency::cpu.data 1810891500 # number of overall miss cycles 667system.cpu.l2cache.overall_miss_latency::total 1877253750 # number of overall miss cycles 668system.cpu.l2cache.ReadReq_accesses::cpu.inst 1006 # number of ReadReq accesses(hits+misses) 669system.cpu.l2cache.ReadReq_accesses::cpu.data 1994292 # number of ReadReq accesses(hits+misses) 670system.cpu.l2cache.ReadReq_accesses::total 1995298 # number of ReadReq accesses(hits+misses) 671system.cpu.l2cache.Writeback_accesses::writebacks 2066630 # number of Writeback accesses(hits+misses) 672system.cpu.l2cache.Writeback_accesses::total 2066630 # number of Writeback accesses(hits+misses) 673system.cpu.l2cache.ReadExReq_accesses::cpu.data 82299 # number of ReadExReq accesses(hits+misses) 674system.cpu.l2cache.ReadExReq_accesses::total 82299 # number of ReadExReq accesses(hits+misses) 675system.cpu.l2cache.demand_accesses::cpu.inst 1006 # number of demand (read+write) accesses 676system.cpu.l2cache.demand_accesses::cpu.data 2076591 # number of demand (read+write) accesses 677system.cpu.l2cache.demand_accesses::total 2077597 # number of demand (read+write) accesses 678system.cpu.l2cache.overall_accesses::cpu.inst 1006 # number of overall (read+write) accesses 679system.cpu.l2cache.overall_accesses::cpu.data 2076591 # number of overall (read+write) accesses 680system.cpu.l2cache.overall_accesses::total 2077597 # number of overall (read+write) accesses 681system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983101 # miss rate for ReadReq accesses 682system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000206 # miss rate for ReadReq accesses 683system.cpu.l2cache.ReadReq_miss_rate::total 0.000701 # miss rate for ReadReq accesses 684system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352386 # miss rate for ReadExReq accesses 685system.cpu.l2cache.ReadExReq_miss_rate::total 0.352386 # miss rate for ReadExReq accesses 686system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983101 # miss rate for demand accesses 687system.cpu.l2cache.demand_miss_rate::cpu.data 0.014163 # miss rate for demand accesses 688system.cpu.l2cache.demand_miss_rate::total 0.014632 # miss rate for demand accesses 689system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983101 # miss rate for overall accesses 690system.cpu.l2cache.overall_miss_rate::cpu.data 0.014163 # miss rate for overall accesses 691system.cpu.l2cache.overall_miss_rate::total 0.014632 # miss rate for overall accesses 692system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67100.353893 # average ReadReq miss latency 693system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67846.341463 # average ReadReq miss latency 694system.cpu.l2cache.ReadReq_avg_miss_latency::total 67318.977841 # average ReadReq miss latency 695system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61483.207476 # average ReadExReq miss latency 696system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61483.207476 # average ReadExReq miss latency 697system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67100.353893 # average overall miss latency 698system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61571.911870 # average overall miss latency 699system.cpu.l2cache.demand_avg_miss_latency::total 61751.768092 # average overall miss latency 700system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67100.353893 # average overall miss latency 701system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61571.911870 # average overall miss latency 702system.cpu.l2cache.overall_avg_miss_latency::total 61751.768092 # average overall miss latency | 701system.cpu.l2cache.overall_hits::cpu.data 2047186 # number of overall hits 702system.cpu.l2cache.overall_hits::total 2047203 # number of overall hits 703system.cpu.l2cache.ReadReq_misses::cpu.inst 994 # number of ReadReq misses 704system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses 705system.cpu.l2cache.ReadReq_misses::total 1416 # number of ReadReq misses 706system.cpu.l2cache.ReadExReq_misses::cpu.data 29003 # number of ReadExReq misses 707system.cpu.l2cache.ReadExReq_misses::total 29003 # number of ReadExReq misses 708system.cpu.l2cache.demand_misses::cpu.inst 994 # number of demand (read+write) misses 709system.cpu.l2cache.demand_misses::cpu.data 29425 # number of demand (read+write) misses 710system.cpu.l2cache.demand_misses::total 30419 # number of demand (read+write) misses 711system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses 712system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses 713system.cpu.l2cache.overall_misses::total 30419 # number of overall misses 714system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68040500 # number of ReadReq miss cycles 715system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29989500 # number of ReadReq miss cycles 716system.cpu.l2cache.ReadReq_miss_latency::total 98030000 # number of ReadReq miss cycles 717system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876802500 # number of ReadExReq miss cycles 718system.cpu.l2cache.ReadExReq_miss_latency::total 1876802500 # number of ReadExReq miss cycles 719system.cpu.l2cache.demand_miss_latency::cpu.inst 68040500 # number of demand (read+write) miss cycles 720system.cpu.l2cache.demand_miss_latency::cpu.data 1906792000 # number of demand (read+write) miss cycles 721system.cpu.l2cache.demand_miss_latency::total 1974832500 # number of demand (read+write) miss cycles 722system.cpu.l2cache.overall_miss_latency::cpu.inst 68040500 # number of overall miss cycles 723system.cpu.l2cache.overall_miss_latency::cpu.data 1906792000 # number of overall miss cycles 724system.cpu.l2cache.overall_miss_latency::total 1974832500 # number of overall miss cycles 725system.cpu.l2cache.ReadReq_accesses::cpu.inst 1011 # number of ReadReq accesses(hits+misses) 726system.cpu.l2cache.ReadReq_accesses::cpu.data 1994288 # number of ReadReq accesses(hits+misses) 727system.cpu.l2cache.ReadReq_accesses::total 1995299 # number of ReadReq accesses(hits+misses) 728system.cpu.l2cache.Writeback_accesses::writebacks 2066887 # number of Writeback accesses(hits+misses) 729system.cpu.l2cache.Writeback_accesses::total 2066887 # number of Writeback accesses(hits+misses) 730system.cpu.l2cache.ReadExReq_accesses::cpu.data 82323 # number of ReadExReq accesses(hits+misses) 731system.cpu.l2cache.ReadExReq_accesses::total 82323 # number of ReadExReq accesses(hits+misses) 732system.cpu.l2cache.demand_accesses::cpu.inst 1011 # number of demand (read+write) accesses 733system.cpu.l2cache.demand_accesses::cpu.data 2076611 # number of demand (read+write) accesses 734system.cpu.l2cache.demand_accesses::total 2077622 # number of demand (read+write) accesses 735system.cpu.l2cache.overall_accesses::cpu.inst 1011 # number of overall (read+write) accesses 736system.cpu.l2cache.overall_accesses::cpu.data 2076611 # number of overall (read+write) accesses 737system.cpu.l2cache.overall_accesses::total 2077622 # number of overall (read+write) accesses 738system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983185 # miss rate for ReadReq accesses 739system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000212 # miss rate for ReadReq accesses 740system.cpu.l2cache.ReadReq_miss_rate::total 0.000710 # miss rate for ReadReq accesses 741system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352307 # miss rate for ReadExReq accesses 742system.cpu.l2cache.ReadExReq_miss_rate::total 0.352307 # miss rate for ReadExReq accesses 743system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983185 # miss rate for demand accesses 744system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses 745system.cpu.l2cache.demand_miss_rate::total 0.014641 # miss rate for demand accesses 746system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983185 # miss rate for overall accesses 747system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses 748system.cpu.l2cache.overall_miss_rate::total 0.014641 # miss rate for overall accesses 749system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.207243 # average ReadReq miss latency 750system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71065.165877 # average ReadReq miss latency 751system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.225989 # average ReadReq miss latency 752system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64710.633383 # average ReadExReq miss latency 753system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64710.633383 # average ReadExReq miss latency 754system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency 755system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency 756system.cpu.l2cache.demand_avg_miss_latency::total 64921.019757 # average overall miss latency 757system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency 758system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency 759system.cpu.l2cache.overall_avg_miss_latency::total 64921.019757 # average overall miss latency |
| 703system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 704system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 705system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 706system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 707system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 708system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 709system.cpu.l2cache.fast_writes 0 # number of fast writes performed 710system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 760system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 761system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 763system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 764system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 765system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.cpu.l2cache.fast_writes 0 # number of fast writes performed 767system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 711system.cpu.l2cache.writebacks::writebacks 156 # number of writebacks 712system.cpu.l2cache.writebacks::total 156 # number of writebacks 713system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 989 # number of ReadReq MSHR misses 714system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 410 # number of ReadReq MSHR misses 715system.cpu.l2cache.ReadReq_mshr_misses::total 1399 # number of ReadReq MSHR misses 716system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29001 # number of ReadExReq MSHR misses 717system.cpu.l2cache.ReadExReq_mshr_misses::total 29001 # number of ReadExReq MSHR misses 718system.cpu.l2cache.demand_mshr_misses::cpu.inst 989 # number of demand (read+write) MSHR misses 719system.cpu.l2cache.demand_mshr_misses::cpu.data 29411 # number of demand (read+write) MSHR misses 720system.cpu.l2cache.demand_mshr_misses::total 30400 # number of demand (read+write) MSHR misses 721system.cpu.l2cache.overall_mshr_misses::cpu.inst 989 # number of overall MSHR misses 722system.cpu.l2cache.overall_mshr_misses::cpu.data 29411 # number of overall MSHR misses 723system.cpu.l2cache.overall_mshr_misses::total 30400 # number of overall MSHR misses 724system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53927250 # number of ReadReq MSHR miss cycles 725system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22692500 # number of ReadReq MSHR miss cycles 726system.cpu.l2cache.ReadReq_mshr_miss_latency::total 76619750 # number of ReadReq MSHR miss cycles 727system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1417840500 # number of ReadExReq MSHR miss cycles 728system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1417840500 # number of ReadExReq MSHR miss cycles 729system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53927250 # number of demand (read+write) MSHR miss cycles 730system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1440533000 # number of demand (read+write) MSHR miss cycles 731system.cpu.l2cache.demand_mshr_miss_latency::total 1494460250 # number of demand (read+write) MSHR miss cycles 732system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53927250 # number of overall MSHR miss cycles 733system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1440533000 # number of overall MSHR miss cycles 734system.cpu.l2cache.overall_mshr_miss_latency::total 1494460250 # number of overall MSHR miss cycles 735system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for ReadReq accesses 736system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000206 # mshr miss rate for ReadReq accesses 737system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000701 # mshr miss rate for ReadReq accesses 738system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352386 # mshr miss rate for ReadExReq accesses 739system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352386 # mshr miss rate for ReadExReq accesses 740system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for demand accesses 741system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014163 # mshr miss rate for demand accesses 742system.cpu.l2cache.demand_mshr_miss_rate::total 0.014632 # mshr miss rate for demand accesses 743system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for overall accesses 744system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014163 # mshr miss rate for overall accesses 745system.cpu.l2cache.overall_mshr_miss_rate::total 0.014632 # mshr miss rate for overall accesses 746system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54527.047523 # average ReadReq mshr miss latency 747system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55347.560976 # average ReadReq mshr miss latency 748system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54767.512509 # average ReadReq mshr miss latency 749system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48889.365884 # average ReadExReq mshr miss latency 750system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48889.365884 # average ReadExReq mshr miss latency 751system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency 752system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency 753system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency 754system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency 755system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency 756system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency | 768system.cpu.l2cache.writebacks::writebacks 167 # number of writebacks 769system.cpu.l2cache.writebacks::total 167 # number of writebacks 770system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 994 # number of ReadReq MSHR misses 771system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses 772system.cpu.l2cache.ReadReq_mshr_misses::total 1416 # number of ReadReq MSHR misses 773system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29003 # number of ReadExReq MSHR misses 774system.cpu.l2cache.ReadExReq_mshr_misses::total 29003 # number of ReadExReq MSHR misses 775system.cpu.l2cache.demand_mshr_misses::cpu.inst 994 # number of demand (read+write) MSHR misses 776system.cpu.l2cache.demand_mshr_misses::cpu.data 29425 # number of demand (read+write) MSHR misses 777system.cpu.l2cache.demand_mshr_misses::total 30419 # number of demand (read+write) MSHR misses 778system.cpu.l2cache.overall_mshr_misses::cpu.inst 994 # number of overall MSHR misses 779system.cpu.l2cache.overall_mshr_misses::cpu.data 29425 # number of overall MSHR misses 780system.cpu.l2cache.overall_mshr_misses::total 30419 # number of overall MSHR misses 781system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 55574500 # number of ReadReq MSHR miss cycles 782system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24773500 # number of ReadReq MSHR miss cycles 783system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80348000 # number of ReadReq MSHR miss cycles 784system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1511756500 # number of ReadExReq MSHR miss cycles 785system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1511756500 # number of ReadExReq MSHR miss cycles 786system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55574500 # number of demand (read+write) MSHR miss cycles 787system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1536530000 # number of demand (read+write) MSHR miss cycles 788system.cpu.l2cache.demand_mshr_miss_latency::total 1592104500 # number of demand (read+write) MSHR miss cycles 789system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55574500 # number of overall MSHR miss cycles 790system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1536530000 # number of overall MSHR miss cycles 791system.cpu.l2cache.overall_mshr_miss_latency::total 1592104500 # number of overall MSHR miss cycles 792system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for ReadReq accesses 793system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000212 # mshr miss rate for ReadReq accesses 794system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000710 # mshr miss rate for ReadReq accesses 795system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352307 # mshr miss rate for ReadExReq accesses 796system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352307 # mshr miss rate for ReadExReq accesses 797system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for demand accesses 798system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses 799system.cpu.l2cache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses 800system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983185 # mshr miss rate for overall accesses 801system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses 802system.cpu.l2cache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses 803system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55909.959759 # average ReadReq mshr miss latency 804system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58704.976303 # average ReadReq mshr miss latency 805system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56742.937853 # average ReadReq mshr miss latency 806system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52124.142330 # average ReadExReq mshr miss latency 807system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52124.142330 # average ReadExReq mshr miss latency 808system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency 809system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency 810system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency 811system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency 812system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency 813system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency |
| 757system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 814system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 758system.cpu.dcache.tags.replacements 2072493 # number of replacements 759system.cpu.dcache.tags.tagsinuse 4069.881910 # Cycle average of tags in use 760system.cpu.dcache.tags.total_refs 71371808 # Total number of references to valid blocks. 761system.cpu.dcache.tags.sampled_refs 2076589 # Sample count of references to valid blocks. 762system.cpu.dcache.tags.avg_refs 34.369732 # Average number of references to valid blocks. 763system.cpu.dcache.tags.warmup_cycle 20650704250 # Cycle when the warmup percentage was hit. 764system.cpu.dcache.tags.occ_blocks::cpu.data 4069.881910 # Average occupied blocks per requestor 765system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy 766system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy 767system.cpu.dcache.ReadReq_hits::cpu.data 40030061 # number of ReadReq hits 768system.cpu.dcache.ReadReq_hits::total 40030061 # number of ReadReq hits 769system.cpu.dcache.WriteReq_hits::cpu.data 31341747 # number of WriteReq hits 770system.cpu.dcache.WriteReq_hits::total 31341747 # number of WriteReq hits 771system.cpu.dcache.demand_hits::cpu.data 71371808 # number of demand (read+write) hits 772system.cpu.dcache.demand_hits::total 71371808 # number of demand (read+write) hits 773system.cpu.dcache.overall_hits::cpu.data 71371808 # number of overall hits 774system.cpu.dcache.overall_hits::total 71371808 # number of overall hits 775system.cpu.dcache.ReadReq_misses::cpu.data 2626396 # number of ReadReq misses 776system.cpu.dcache.ReadReq_misses::total 2626396 # number of ReadReq misses 777system.cpu.dcache.WriteReq_misses::cpu.data 98005 # number of WriteReq misses 778system.cpu.dcache.WriteReq_misses::total 98005 # number of WriteReq misses 779system.cpu.dcache.demand_misses::cpu.data 2724401 # number of demand (read+write) misses 780system.cpu.dcache.demand_misses::total 2724401 # number of demand (read+write) misses 781system.cpu.dcache.overall_misses::cpu.data 2724401 # number of overall misses 782system.cpu.dcache.overall_misses::total 2724401 # number of overall misses 783system.cpu.dcache.ReadReq_miss_latency::cpu.data 31387330250 # number of ReadReq miss cycles 784system.cpu.dcache.ReadReq_miss_latency::total 31387330250 # number of ReadReq miss cycles 785system.cpu.dcache.WriteReq_miss_latency::cpu.data 2685755248 # number of WriteReq miss cycles 786system.cpu.dcache.WriteReq_miss_latency::total 2685755248 # number of WriteReq miss cycles 787system.cpu.dcache.demand_miss_latency::cpu.data 34073085498 # number of demand (read+write) miss cycles 788system.cpu.dcache.demand_miss_latency::total 34073085498 # number of demand (read+write) miss cycles 789system.cpu.dcache.overall_miss_latency::cpu.data 34073085498 # number of overall miss cycles 790system.cpu.dcache.overall_miss_latency::total 34073085498 # number of overall miss cycles 791system.cpu.dcache.ReadReq_accesses::cpu.data 42656457 # number of ReadReq accesses(hits+misses) 792system.cpu.dcache.ReadReq_accesses::total 42656457 # number of ReadReq accesses(hits+misses) | 815system.cpu.dcache.tags.replacements 2072514 # number of replacements 816system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use 817system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks. 818system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks. 819system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks. 820system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit. 821system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor 822system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy 823system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy 824system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits 825system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits 826system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits 827system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits 828system.cpu.dcache.demand_hits::cpu.data 71413624 # number of demand (read+write) hits 829system.cpu.dcache.demand_hits::total 71413624 # number of demand (read+write) hits 830system.cpu.dcache.overall_hits::cpu.data 71413624 # number of overall hits 831system.cpu.dcache.overall_hits::total 71413624 # number of overall hits 832system.cpu.dcache.ReadReq_misses::cpu.data 2625746 # number of ReadReq misses 833system.cpu.dcache.ReadReq_misses::total 2625746 # number of ReadReq misses 834system.cpu.dcache.WriteReq_misses::cpu.data 98059 # number of WriteReq misses 835system.cpu.dcache.WriteReq_misses::total 98059 # number of WriteReq misses 836system.cpu.dcache.demand_misses::cpu.data 2723805 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 2723805 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 2723805 # number of overall misses 839system.cpu.dcache.overall_misses::total 2723805 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 31399016250 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 31399016250 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 2779679498 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 2779679498 # number of WriteReq miss cycles 844system.cpu.dcache.demand_miss_latency::cpu.data 34178695748 # number of demand (read+write) miss cycles 845system.cpu.dcache.demand_miss_latency::total 34178695748 # number of demand (read+write) miss cycles 846system.cpu.dcache.overall_miss_latency::cpu.data 34178695748 # number of overall miss cycles 847system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles 848system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses) |
| 793system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 794system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) | 850system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) |
| 795system.cpu.dcache.demand_accesses::cpu.data 74096209 # number of demand (read+write) accesses 796system.cpu.dcache.demand_accesses::total 74096209 # number of demand (read+write) accesses 797system.cpu.dcache.overall_accesses::cpu.data 74096209 # number of overall (read+write) accesses 798system.cpu.dcache.overall_accesses::total 74096209 # number of overall (read+write) accesses 799system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061571 # miss rate for ReadReq accesses 800system.cpu.dcache.ReadReq_miss_rate::total 0.061571 # miss rate for ReadReq accesses 801system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003117 # miss rate for WriteReq accesses 802system.cpu.dcache.WriteReq_miss_rate::total 0.003117 # miss rate for WriteReq accesses 803system.cpu.dcache.demand_miss_rate::cpu.data 0.036768 # miss rate for demand accesses 804system.cpu.dcache.demand_miss_rate::total 0.036768 # miss rate for demand accesses 805system.cpu.dcache.overall_miss_rate::cpu.data 0.036768 # miss rate for overall accesses 806system.cpu.dcache.overall_miss_rate::total 0.036768 # miss rate for overall accesses 807system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11950.722682 # average ReadReq miss latency 808system.cpu.dcache.ReadReq_avg_miss_latency::total 11950.722682 # average ReadReq miss latency 809system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27404.267619 # average WriteReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::total 27404.267619 # average WriteReq miss latency 811system.cpu.dcache.demand_avg_miss_latency::cpu.data 12506.633751 # average overall miss latency 812system.cpu.dcache.demand_avg_miss_latency::total 12506.633751 # average overall miss latency 813system.cpu.dcache.overall_avg_miss_latency::cpu.data 12506.633751 # average overall miss latency 814system.cpu.dcache.overall_avg_miss_latency::total 12506.633751 # average overall miss latency 815system.cpu.dcache.blocked_cycles::no_mshrs 32988 # number of cycles access was blocked | 852system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses 853system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses 854system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses 855system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses 856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses 857system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses 858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses 859system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses 860system.cpu.dcache.demand_miss_rate::cpu.data 0.036740 # miss rate for demand accesses 861system.cpu.dcache.demand_miss_rate::total 0.036740 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.036740 # miss rate for overall accesses 863system.cpu.dcache.overall_miss_rate::total 0.036740 # miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.131613 # average ReadReq miss latency 865system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.131613 # average ReadReq miss latency 866system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28347.010453 # average WriteReq miss latency 867system.cpu.dcache.WriteReq_avg_miss_latency::total 28347.010453 # average WriteReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 12548.143405 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 12548.143405 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 32707 # number of cycles access was blocked |
| 816system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 817system.cpu.dcache.blocked::no_mshrs 9490 # number of cycles access was blocked | 874system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked |
| 818system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 819system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.476080 # average number of cycles each access was blocked | 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.443930 # average number of cycles each access was blocked |
| 820system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 821system.cpu.dcache.fast_writes 0 # number of fast writes performed 822system.cpu.dcache.cache_copies 0 # number of cache copies performed | 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 823system.cpu.dcache.writebacks::writebacks 2066630 # number of writebacks 824system.cpu.dcache.writebacks::total 2066630 # number of writebacks 825system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631996 # number of ReadReq MSHR hits 826system.cpu.dcache.ReadReq_mshr_hits::total 631996 # number of ReadReq MSHR hits 827system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15814 # number of WriteReq MSHR hits 828system.cpu.dcache.WriteReq_mshr_hits::total 15814 # number of WriteReq MSHR hits 829system.cpu.dcache.demand_mshr_hits::cpu.data 647810 # number of demand (read+write) MSHR hits 830system.cpu.dcache.demand_mshr_hits::total 647810 # number of demand (read+write) MSHR hits 831system.cpu.dcache.overall_mshr_hits::cpu.data 647810 # number of overall MSHR hits 832system.cpu.dcache.overall_mshr_hits::total 647810 # number of overall MSHR hits 833system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994400 # number of ReadReq MSHR misses 834system.cpu.dcache.ReadReq_mshr_misses::total 1994400 # number of ReadReq MSHR misses 835system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82191 # number of WriteReq MSHR misses 836system.cpu.dcache.WriteReq_mshr_misses::total 82191 # number of WriteReq MSHR misses 837system.cpu.dcache.demand_mshr_misses::cpu.data 2076591 # number of demand (read+write) MSHR misses 838system.cpu.dcache.demand_mshr_misses::total 2076591 # number of demand (read+write) MSHR misses 839system.cpu.dcache.overall_mshr_misses::cpu.data 2076591 # number of overall MSHR misses 840system.cpu.dcache.overall_mshr_misses::total 2076591 # number of overall MSHR misses 841system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994515250 # number of ReadReq MSHR miss cycles 842system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994515250 # number of ReadReq MSHR miss cycles 843system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397679498 # number of WriteReq MSHR miss cycles 844system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397679498 # number of WriteReq MSHR miss cycles 845system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392194748 # number of demand (read+write) MSHR miss cycles 846system.cpu.dcache.demand_mshr_miss_latency::total 24392194748 # number of demand (read+write) MSHR miss cycles 847system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392194748 # number of overall MSHR miss cycles 848system.cpu.dcache.overall_mshr_miss_latency::total 24392194748 # number of overall MSHR miss cycles 849system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046755 # mshr miss rate for ReadReq accesses 850system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046755 # mshr miss rate for ReadReq accesses 851system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses 852system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses 853system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for demand accesses 854system.cpu.dcache.demand_mshr_miss_rate::total 0.028026 # mshr miss rate for demand accesses 855system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for overall accesses 856system.cpu.dcache.overall_mshr_miss_rate::total 0.028026 # mshr miss rate for overall accesses 857system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.136407 # average ReadReq mshr miss latency 858system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.136407 # average ReadReq mshr miss latency 859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29172.044360 # average WriteReq mshr miss latency 860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29172.044360 # average WriteReq mshr miss latency 861system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency 862system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency 863system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency 864system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency | 880system.cpu.dcache.writebacks::writebacks 2066887 # number of writebacks 881system.cpu.dcache.writebacks::total 2066887 # number of writebacks 882system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631351 # number of ReadReq MSHR hits 883system.cpu.dcache.ReadReq_mshr_hits::total 631351 # number of ReadReq MSHR hits 884system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15843 # number of WriteReq MSHR hits 885system.cpu.dcache.WriteReq_mshr_hits::total 15843 # number of WriteReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 647194 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 647194 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 647194 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 647194 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994395 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 1994395 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82216 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 82216 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 2076611 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 2076611 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 2076611 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 2076611 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996462750 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996462750 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2491650748 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 2491650748 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488113498 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 24488113498 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488113498 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 24488113498 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046710 # mshr miss rate for ReadReq accesses 907system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046710 # mshr miss rate for ReadReq accesses 908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses 909system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses 910system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for demand accesses 911system.cpu.dcache.demand_mshr_miss_rate::total 0.028010 # mshr miss rate for demand accesses 912system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for overall accesses 913system.cpu.dcache.overall_mshr_miss_rate::total 0.028010 # mshr miss rate for overall accesses 914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.140541 # average ReadReq mshr miss latency 915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.140541 # average ReadReq mshr miss latency 916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30306.153887 # average WriteReq mshr miss latency 917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30306.153887 # average WriteReq mshr miss latency 918system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency 919system.cpu.dcache.demand_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency 920system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency 921system.cpu.dcache.overall_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency |
| 865system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 866 867---------- End Simulation Statistics ---------- | 922system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 923 924---------- End Simulation Statistics ---------- |