| stats.txt (9702:094d0280e481) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.064955 # Number of seconds simulated 4sim_ticks 64955437500 # Number of ticks simulated 5final_tick 64955437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.065490 # Number of seconds simulated 4sim_ticks 65489948000 # Number of ticks simulated 5final_tick 65489948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 70718 # Simulator instruction rate (inst/s) 8host_op_rate 124523 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 29075113 # Simulator tick rate (ticks/s) 10host_mem_usage 434544 # Number of bytes of host memory used 11host_seconds 2234.06 # Real time elapsed on the host | 7host_inst_rate 99083 # Simulator instruction rate (inst/s) 8host_op_rate 174470 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41072394 # Simulator tick rate (ticks/s) 10host_mem_usage 386708 # Number of bytes of host memory used 11host_seconds 1594.50 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 64064 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1882496 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1946560 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 64064 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 64064 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 10432 # Number of bytes written to this memory 20system.physmem.bytes_written::total 10432 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1001 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29414 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30415 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 163 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 163 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 986276 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 28981346 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 29967622 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 986276 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 986276 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 160602 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 160602 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 160602 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 986276 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 28981346 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 30128224 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1882624 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 10112 # Number of bytes written to this memory 20system.physmem.bytes_written::total 10112 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29416 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 158 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 158 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 975295 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 28746763 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 29722057 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 975295 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 975295 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 154405 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 154405 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 154405 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 975295 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 28746763 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 29876463 # Total bandwidth to/from this memory (bytes/s) |
| 37system.physmem.readReqs 30415 # Total number of read requests seen | 37system.physmem.readReqs 30415 # Total number of read requests seen |
| 38system.physmem.writeReqs 163 # Total number of write requests seen 39system.physmem.cpureqs 30578 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 1946560 # Total number of bytes read from memory 41system.physmem.bytesWritten 10432 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 1946560 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 40 # Number of read reqs serviced by write Q | 38system.physmem.writeReqs 158 # Total number of write requests seen 39system.physmem.cpureqs 30573 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 1946496 # Total number of bytes read from memory 41system.physmem.bytesWritten 10112 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 10112 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 47 # Number of read reqs serviced by write Q |
| 45system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed | 45system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed |
| 46system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 1903 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 1919 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 1928 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 1935 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 1899 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 1949 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 1933 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 1946 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 1848 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 1890 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 1827 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 7 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 63 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 50 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 11 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 4 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 7 # Track writes on a per bank basis | 46system.physmem.perBankRdReqs::0 1925 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 2026 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 1927 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 1901 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 1864 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 1931 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 1821 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 8 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 7 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 12 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 8 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis |
| 76system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 76system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 80system.physmem.totGap 64955401000 # Total gap between requests | 80system.physmem.totGap 65489931000 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 30415 # Categorize read packet sizes 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 30415 # Categorize read packet sizes 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 94system.physmem.writePktSize::6 163 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 29875 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 392 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see | 94system.physmem.writePktSize::6 158 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 29911 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 366 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 127system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see | 127system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see |
| 129system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see | 129system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see |
| 150system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 150system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 159system.physmem.totQLat 11278750 # Total cycles spent in queuing delays 160system.physmem.totMemAccLat 610070000 # Sum of mem lat for all requests 161system.physmem.totBusLat 151875000 # Total cycles spent in databus access 162system.physmem.totBankLat 446916250 # Total cycles spent in bank access 163system.physmem.avgQLat 371.32 # Average queueing delay per request 164system.physmem.avgBankLat 14713.29 # Average bank access latency per request | 159system.physmem.bytesPerActivate::samples 551 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::mean 3522.090744 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::gmean 829.782913 # Bytes accessed per row activation 162system.physmem.bytesPerActivate::stdev 3844.695710 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::64-65 143 25.95% 25.95% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::128-129 46 8.35% 34.30% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::192-193 23 4.17% 38.48% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::256-257 15 2.72% 41.20% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::320-321 11 2.00% 43.19% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::384-385 10 1.81% 45.01% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::448-449 9 1.63% 46.64% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::512-513 5 0.91% 47.55% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::576-577 5 0.91% 48.46% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::640-641 10 1.81% 50.27% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::704-705 4 0.73% 51.00% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::768-769 6 1.09% 52.09% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::832-833 2 0.36% 52.45% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::896-897 1 0.18% 52.63% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::960-961 3 0.54% 53.18% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1024-1025 1 0.18% 53.36% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.54% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.17% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.54% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.72% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1408-1409 1 0.18% 55.90% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1536-1537 3 0.54% 56.44% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1600-1601 2 0.36% 56.81% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1792-1793 1 0.18% 56.99% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1856-1857 1 0.18% 57.17% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.35% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::2240-2241 2 0.36% 57.71% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::2432-2433 1 0.18% 57.89% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2496-2497 1 0.18% 58.08% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.26% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.62% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2944-2945 1 0.18% 58.80% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::3264-3265 1 0.18% 58.98% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::4032-4033 2 0.36% 59.35% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.53% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::5184-5185 1 0.18% 59.71% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::5312-5313 1 0.18% 59.89% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.07% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.44% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.62% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::8000-8001 1 0.18% 60.80% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::8192-8193 216 39.20% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 551 # Bytes accessed per row activation 206system.physmem.totQLat 7172750 # Total cycles spent in queuing delays 207system.physmem.totMemAccLat 582609000 # Sum of mem lat for all requests 208system.physmem.totBusLat 151840000 # Total cycles spent in databus access 209system.physmem.totBankLat 423596250 # Total cycles spent in bank access 210system.physmem.avgQLat 236.19 # Average queueing delay per request 211system.physmem.avgBankLat 13948.77 # Average bank access latency per request |
| 165system.physmem.avgBusLat 5000.00 # Average bus latency per request | 212system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 166system.physmem.avgMemAccLat 20084.61 # Average memory access latency 167system.physmem.avgRdBW 29.97 # Average achieved read bandwidth in MB/s 168system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s 169system.physmem.avgConsumedRdBW 29.97 # Average consumed read bandwidth in MB/s 170system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s | 213system.physmem.avgMemAccLat 19184.96 # Average memory access latency 214system.physmem.avgRdBW 29.72 # Average achieved read bandwidth in MB/s 215system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s 216system.physmem.avgConsumedRdBW 29.72 # Average consumed read bandwidth in MB/s 217system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s |
| 171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 172system.physmem.busUtil 0.24 # Data bus utilization in percentage | 219system.physmem.busUtil 0.23 # Data bus utilization in percentage |
| 173system.physmem.avgRdQLen 0.01 # Average read queue length over time | 220system.physmem.avgRdQLen 0.01 # Average read queue length over time |
| 174system.physmem.avgWrQLen 9.38 # Average write queue length over time 175system.physmem.readRowHits 29086 # Number of row buffer hits during reads 176system.physmem.writeRowHits 90 # Number of row buffer hits during writes 177system.physmem.readRowHitRate 95.76 # Row buffer hit rate for reads 178system.physmem.writeRowHitRate 55.21 # Row buffer hit rate for writes 179system.physmem.avgGap 2124252.76 # Average gap between requests 180system.cpu.branchPred.lookups 33861369 # Number of BP lookups 181system.cpu.branchPred.condPredicted 33861369 # Number of conditional branches predicted 182system.cpu.branchPred.condIncorrect 775033 # Number of conditional branches incorrect 183system.cpu.branchPred.BTBLookups 19294803 # Number of BTB lookups 184system.cpu.branchPred.BTBHits 19205281 # Number of BTB hits | 221system.physmem.avgWrQLen 0.64 # Average write queue length over time 222system.physmem.readRowHits 29867 # Number of row buffer hits during reads 223system.physmem.writeRowHits 88 # Number of row buffer hits during writes 224system.physmem.readRowHitRate 98.35 # Row buffer hit rate for reads 225system.physmem.writeRowHitRate 55.70 # Row buffer hit rate for writes 226system.physmem.avgGap 2142083.90 # Average gap between requests 227system.membus.throughput 29875486 # Throughput (bytes/s) 228system.membus.trans_dist::ReadReq 1414 # Transaction distribution 229system.membus.trans_dist::ReadResp 1412 # Transaction distribution 230system.membus.trans_dist::Writeback 158 # Transaction distribution 231system.membus.trans_dist::ReadExReq 29001 # Transaction distribution 232system.membus.trans_dist::ReadExResp 29001 # Transaction distribution 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60986 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60986 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::system.physmem.port 60986 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 60986 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956544 # Cumulative packet size per connected master and slave (bytes) 239system.membus.tot_pkt_size::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes) 240system.membus.tot_pkt_size::total 1956544 # Cumulative packet size per connected master and slave (bytes) 241system.membus.data_through_bus 1956544 # Total data (bytes) 242system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 243system.membus.reqLayer0.occupancy 34719000 # Layer occupancy (ticks) 244system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 245system.membus.respLayer1.occupancy 283984750 # Layer occupancy (ticks) 246system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 247system.cpu.branchPred.lookups 33857873 # Number of BP lookups 248system.cpu.branchPred.condPredicted 33857873 # Number of conditional branches predicted 249system.cpu.branchPred.condIncorrect 774323 # Number of conditional branches incorrect 250system.cpu.branchPred.BTBLookups 19304335 # Number of BTB lookups 251system.cpu.branchPred.BTBHits 19204317 # Number of BTB hits |
| 185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 252system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 186system.cpu.branchPred.BTBHitPct 99.536031 # BTB Hit Percentage 187system.cpu.branchPred.usedRAS 5016068 # Number of times the RAS was used to get a target. 188system.cpu.branchPred.RASInCorrect 5449 # Number of incorrect RAS predictions. | 253system.cpu.branchPred.BTBHitPct 99.481888 # BTB Hit Percentage 254system.cpu.branchPred.usedRAS 5017100 # Number of times the RAS was used to get a target. 255system.cpu.branchPred.RASInCorrect 5401 # Number of incorrect RAS predictions. |
| 189system.cpu.workload.num_syscalls 444 # Number of system calls | 256system.cpu.workload.num_syscalls 444 # Number of system calls |
| 190system.cpu.numCycles 129910880 # number of cpu cycles simulated | 257system.cpu.numCycles 130979906 # number of cpu cycles simulated |
| 191system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 192system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 258system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 259system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 193system.cpu.fetch.icacheStallCycles 26135643 # Number of cycles fetch is stalled on an Icache miss 194system.cpu.fetch.Insts 182272269 # Number of instructions fetch has processed 195system.cpu.fetch.Branches 33861369 # Number of branches that fetch encountered 196system.cpu.fetch.predictedBranches 24221349 # Number of branches that fetch has predicted taken 197system.cpu.fetch.Cycles 55463274 # Number of cycles fetch has run and was not squashing or blocked 198system.cpu.fetch.SquashCycles 5355481 # Number of cycles fetch has spent squashing 199system.cpu.fetch.BlockedCycles 43685508 # Number of cycles fetch has spent blocked 200system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 201system.cpu.fetch.PendingTrapStallCycles 275 # Number of stall cycles due to pending traps 202system.cpu.fetch.CacheLines 25577909 # Number of cache lines fetched 203system.cpu.fetch.IcacheSquashes 166501 # Number of outstanding Icache misses that were squashed 204system.cpu.fetch.rateDist::samples 129829944 # Number of instructions fetched each cycle (Total) 205system.cpu.fetch.rateDist::mean 2.475075 # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::stdev 3.321063 # Number of instructions fetched each cycle (Total) | 260system.cpu.fetch.icacheStallCycles 26132901 # Number of cycles fetch is stalled on an Icache miss 261system.cpu.fetch.Insts 182254705 # Number of instructions fetch has processed 262system.cpu.fetch.Branches 33857873 # Number of branches that fetch encountered 263system.cpu.fetch.predictedBranches 24221417 # Number of branches that fetch has predicted taken 264system.cpu.fetch.Cycles 55457387 # Number of cycles fetch has run and was not squashing or blocked 265system.cpu.fetch.SquashCycles 5351238 # Number of cycles fetch has spent squashing 266system.cpu.fetch.BlockedCycles 44744671 # Number of cycles fetch has spent blocked 267system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 268system.cpu.fetch.PendingTrapStallCycles 388 # Number of stall cycles due to pending traps 269system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR 270system.cpu.fetch.CacheLines 25573947 # Number of cache lines fetched 271system.cpu.fetch.IcacheSquashes 166608 # Number of outstanding Icache misses that were squashed 272system.cpu.fetch.rateDist::samples 130876974 # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::mean 2.455077 # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::stdev 3.315032 # Number of instructions fetched each cycle (Total) |
| 207system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 275system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 208system.cpu.fetch.rateDist::0 76844002 59.19% 59.19% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::1 1961117 1.51% 60.70% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::2 2942078 2.27% 62.96% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::3 3835155 2.95% 65.92% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::4 7767567 5.98% 71.90% # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::5 4757667 3.66% 75.57% # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::6 2666355 2.05% 77.62% # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::7 1316617 1.01% 78.63% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::8 27739386 21.37% 100.00% # Number of instructions fetched each cycle (Total) | 276system.cpu.fetch.rateDist::0 77895599 59.52% 59.52% # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::1 1961064 1.50% 61.02% # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::2 2941506 2.25% 63.26% # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::3 3833280 2.93% 66.19% # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::4 7768261 5.94% 72.13% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::5 4757709 3.64% 75.76% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::6 2666396 2.04% 77.80% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::7 1316117 1.01% 78.81% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::8 27737042 21.19% 100.00% # Number of instructions fetched each cycle (Total) |
| 217system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 285system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 220system.cpu.fetch.rateDist::total 129829944 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.branchRate 0.260651 # Number of branch fetches per cycle 222system.cpu.fetch.rate 1.403056 # Number of inst fetches per cycle 223system.cpu.decode.IdleCycles 36820018 # Number of cycles decode is idle 224system.cpu.decode.BlockedCycles 35912600 # Number of cycles decode is blocked 225system.cpu.decode.RunCycles 43886713 # Number of cycles decode is running 226system.cpu.decode.UnblockCycles 8665410 # Number of cycles decode is unblocking 227system.cpu.decode.SquashCycles 4545203 # Number of cycles decode is squashing 228system.cpu.decode.DecodedInsts 318850210 # Number of instructions handled by decode 229system.cpu.rename.SquashCycles 4545203 # Number of cycles rename is squashing 230system.cpu.rename.IdleCycles 42299380 # Number of cycles rename is idle 231system.cpu.rename.BlockCycles 8565943 # Number of cycles rename is blocking 232system.cpu.rename.serializeStallCycles 6540 # count of cycles rename stalled for serializing inst 233system.cpu.rename.RunCycles 46769687 # Number of cycles rename is running 234system.cpu.rename.UnblockCycles 27643191 # Number of cycles rename is unblocking 235system.cpu.rename.RenamedInsts 315014600 # Number of instructions processed by rename 236system.cpu.rename.ROBFullEvents 177 # Number of times rename has blocked due to ROB full 237system.cpu.rename.IQFullEvents 37506 # Number of times rename has blocked due to IQ full 238system.cpu.rename.LSQFullEvents 25780031 # Number of times rename has blocked due to LSQ full 239system.cpu.rename.FullRegisterEvents 461 # Number of times there has been no free registers 240system.cpu.rename.RenamedOperands 317193496 # Number of destination operands rename has renamed 241system.cpu.rename.RenameLookups 836529852 # Number of register rename lookups that rename has made 242system.cpu.rename.int_rename_lookups 836528510 # Number of integer rename lookups 243system.cpu.rename.fp_rename_lookups 1342 # Number of floating rename lookups | 288system.cpu.fetch.rateDist::total 130876974 # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.branchRate 0.258497 # Number of branch fetches per cycle 290system.cpu.fetch.rate 1.391471 # Number of inst fetches per cycle 291system.cpu.decode.IdleCycles 36825046 # Number of cycles decode is idle 292system.cpu.decode.BlockedCycles 36962033 # Number of cycles decode is blocked 293system.cpu.decode.RunCycles 43884335 # Number of cycles decode is running 294system.cpu.decode.UnblockCycles 8664000 # Number of cycles decode is unblocking 295system.cpu.decode.SquashCycles 4541560 # Number of cycles decode is squashing 296system.cpu.decode.DecodedInsts 318828995 # Number of instructions handled by decode 297system.cpu.rename.SquashCycles 4541560 # Number of cycles rename is squashing 298system.cpu.rename.IdleCycles 42312169 # Number of cycles rename is idle 299system.cpu.rename.BlockCycles 9511401 # Number of cycles rename is blocking 300system.cpu.rename.serializeStallCycles 7346 # count of cycles rename stalled for serializing inst 301system.cpu.rename.RunCycles 46756594 # Number of cycles rename is running 302system.cpu.rename.UnblockCycles 27747904 # Number of cycles rename is unblocking 303system.cpu.rename.RenamedInsts 314994654 # Number of instructions processed by rename 304system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full 305system.cpu.rename.IQFullEvents 26642 # Number of times rename has blocked due to IQ full 306system.cpu.rename.LSQFullEvents 25895040 # Number of times rename has blocked due to LSQ full 307system.cpu.rename.FullRegisterEvents 476 # Number of times there has been no free registers 308system.cpu.rename.RenamedOperands 317170346 # Number of destination operands rename has renamed 309system.cpu.rename.RenameLookups 836475154 # Number of register rename lookups that rename has made 310system.cpu.rename.int_rename_lookups 836474392 # Number of integer rename lookups 311system.cpu.rename.fp_rename_lookups 762 # Number of floating rename lookups |
| 244system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed | 312system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed |
| 245system.cpu.rename.UndoneMaps 37980749 # Number of HB maps that are undone due to squashing | 313system.cpu.rename.UndoneMaps 37957599 # Number of HB maps that are undone due to squashing |
| 246system.cpu.rename.serializingInsts 473 # count of serializing insts renamed | 314system.cpu.rename.serializingInsts 473 # count of serializing insts renamed |
| 247system.cpu.rename.tempSerializingInsts 470 # count of temporary serializing insts renamed 248system.cpu.rename.skidInsts 62475342 # count of insts added to the skid buffer 249system.cpu.memDep0.insertedLoads 101554999 # Number of loads inserted to the mem dependence unit. 250system.cpu.memDep0.insertedStores 34779465 # Number of stores inserted to the mem dependence unit. 251system.cpu.memDep0.conflictingLoads 39658435 # Number of conflicting loads. 252system.cpu.memDep0.conflictingStores 5856370 # Number of conflicting stores. 253system.cpu.iq.iqInstsAdded 311474506 # Number of instructions added to the IQ (excludes non-spec) 254system.cpu.iq.iqNonSpecInstsAdded 1648 # Number of non-speculative instructions added to the IQ 255system.cpu.iq.iqInstsIssued 300268759 # Number of instructions issued 256system.cpu.iq.iqSquashedInstsIssued 90582 # Number of squashed instructions issued 257system.cpu.iq.iqSquashedInstsExamined 32704656 # Number of squashed instructions iterated over during squash; mainly for profiling 258system.cpu.iq.iqSquashedOperandsExamined 46105854 # Number of squashed operands that are examined and possibly removed from graph 259system.cpu.iq.iqSquashedNonSpecRemoved 1203 # Number of squashed non-spec instructions that were removed 260system.cpu.iq.issued_per_cycle::samples 129829944 # Number of insts issued each cycle 261system.cpu.iq.issued_per_cycle::mean 2.312785 # Number of insts issued each cycle 262system.cpu.iq.issued_per_cycle::stdev 1.693578 # Number of insts issued each cycle | 315system.cpu.rename.tempSerializingInsts 471 # count of temporary serializing insts renamed 316system.cpu.rename.skidInsts 62618763 # count of insts added to the skid buffer 317system.cpu.memDep0.insertedLoads 101546098 # Number of loads inserted to the mem dependence unit. 318system.cpu.memDep0.insertedStores 34776490 # Number of stores inserted to the mem dependence unit. 319system.cpu.memDep0.conflictingLoads 39628981 # Number of conflicting loads. 320system.cpu.memDep0.conflictingStores 5872628 # Number of conflicting stores. 321system.cpu.iq.iqInstsAdded 311460641 # Number of instructions added to the IQ (excludes non-spec) 322system.cpu.iq.iqNonSpecInstsAdded 1620 # Number of non-speculative instructions added to the IQ 323system.cpu.iq.iqInstsIssued 300263242 # Number of instructions issued 324system.cpu.iq.iqSquashedInstsIssued 89194 # Number of squashed instructions issued 325system.cpu.iq.iqSquashedInstsExamined 32692736 # Number of squashed instructions iterated over during squash; mainly for profiling 326system.cpu.iq.iqSquashedOperandsExamined 46075932 # Number of squashed operands that are examined and possibly removed from graph 327system.cpu.iq.iqSquashedNonSpecRemoved 1175 # Number of squashed non-spec instructions that were removed 328system.cpu.iq.issued_per_cycle::samples 130876974 # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::mean 2.294240 # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::stdev 1.698248 # Number of insts issued each cycle |
| 263system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 331system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 264system.cpu.iq.issued_per_cycle::0 23157142 17.84% 17.84% # Number of insts issued each cycle 265system.cpu.iq.issued_per_cycle::1 23146978 17.83% 35.67% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::2 25463277 19.61% 55.28% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::3 25807307 19.88% 75.16% # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::4 18888431 14.55% 89.70% # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::5 8277018 6.38% 96.08% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::6 3970528 3.06% 99.14% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::7 942780 0.73% 99.86% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::8 176483 0.14% 100.00% # Number of insts issued each cycle | 332system.cpu.iq.issued_per_cycle::0 24131864 18.44% 18.44% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::1 23200747 17.73% 36.17% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::2 25515846 19.50% 55.66% # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::3 25800196 19.71% 75.38% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::4 18908821 14.45% 89.82% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::5 8226578 6.29% 96.11% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::6 3966533 3.03% 99.14% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::7 948269 0.72% 99.86% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::8 178120 0.14% 100.00% # Number of insts issued each cycle |
| 273system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 341system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 276system.cpu.iq.issued_per_cycle::total 129829944 # Number of insts issued each cycle | 344system.cpu.iq.issued_per_cycle::total 130876974 # Number of insts issued each cycle |
| 277system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 345system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 278system.cpu.iq.fu_full::IntAlu 31372 1.52% 1.52% # attempts to use FU when none available | 346system.cpu.iq.fu_full::IntAlu 31350 1.52% 1.52% # attempts to use FU when none available |
| 279system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available 280system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available 281system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available 282system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available 283system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available 284system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available 285system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available 286system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 299system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available | 347system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available 348system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available 349system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available 350system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available 351system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available 352system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available 353system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available 354system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 367system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available |
| 307system.cpu.iq.fu_full::MemRead 1915002 93.02% 94.54% # attempts to use FU when none available 308system.cpu.iq.fu_full::MemWrite 112311 5.46% 100.00% # attempts to use FU when none available | 375system.cpu.iq.fu_full::MemRead 1914118 93.02% 94.55% # attempts to use FU when none available 376system.cpu.iq.fu_full::MemWrite 112203 5.45% 100.00% # attempts to use FU when none available |
| 309system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 310system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 377system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 378system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 311system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued 312system.cpu.iq.FU_type_0::IntAlu 169830588 56.56% 56.57% # Type of FU issued 313system.cpu.iq.FU_type_0::IntMult 11175 0.00% 56.57% # Type of FU issued 314system.cpu.iq.FU_type_0::IntDiv 333 0.00% 56.57% # Type of FU issued 315system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued 316system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued 317system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued 318system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued 319system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued 320system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued 324system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued 325system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued 341system.cpu.iq.FU_type_0::MemRead 97304104 32.41% 88.98% # Type of FU issued 342system.cpu.iq.FU_type_0::MemWrite 33091251 11.02% 100.00% # Type of FU issued | 379system.cpu.iq.FU_type_0::No_OpClass 31269 0.01% 0.01% # Type of FU issued 380system.cpu.iq.FU_type_0::IntAlu 169831463 56.56% 56.57% # Type of FU issued 381system.cpu.iq.FU_type_0::IntMult 11173 0.00% 56.57% # Type of FU issued 382system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued 383system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.58% # Type of FU issued 384system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued 385system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued 386system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued 387system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued 388system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued 409system.cpu.iq.FU_type_0::MemRead 97296683 32.40% 88.98% # Type of FU issued 410system.cpu.iq.FU_type_0::MemWrite 33092294 11.02% 100.00% # Type of FU issued |
| 343system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 344system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 411system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 412system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 345system.cpu.iq.FU_type_0::total 300268759 # Type of FU issued 346system.cpu.iq.rate 2.311344 # Inst issue rate 347system.cpu.iq.fu_busy_cnt 2058685 # FU busy when requested 348system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst) 349system.cpu.iq.int_inst_queue_reads 732516269 # Number of integer instruction queue reads 350system.cpu.iq.int_inst_queue_writes 344212556 # Number of integer instruction queue writes 351system.cpu.iq.int_inst_queue_wakeup_accesses 298017233 # Number of integer instruction queue wakeup accesses 352system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads 353system.cpu.iq.fp_inst_queue_writes 646 # Number of floating instruction queue writes 354system.cpu.iq.fp_inst_queue_wakeup_accesses 145 # Number of floating instruction queue wakeup accesses 355system.cpu.iq.int_alu_accesses 302295951 # Number of integer alu accesses 356system.cpu.iq.fp_alu_accesses 216 # Number of floating point alu accesses 357system.cpu.iew.lsq.thread0.forwLoads 54147980 # Number of loads that had data forwarded from stores | 413system.cpu.iq.FU_type_0::total 300263242 # Type of FU issued 414system.cpu.iq.rate 2.292437 # Inst issue rate 415system.cpu.iq.fu_busy_cnt 2057671 # FU busy when requested 416system.cpu.iq.fu_busy_rate 0.006853 # FU busy rate (busy events/executed inst) 417system.cpu.iq.int_inst_queue_reads 733550061 # Number of integer instruction queue reads 418system.cpu.iq.int_inst_queue_writes 344187115 # Number of integer instruction queue writes 419system.cpu.iq.int_inst_queue_wakeup_accesses 298012847 # Number of integer instruction queue wakeup accesses 420system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads 421system.cpu.iq.fp_inst_queue_writes 328 # Number of floating instruction queue writes 422system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses 423system.cpu.iq.int_alu_accesses 302289511 # Number of integer alu accesses 424system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses 425system.cpu.iew.lsq.thread0.forwLoads 54160833 # Number of loads that had data forwarded from stores |
| 358system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 426system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 359system.cpu.iew.lsq.thread0.squashedLoads 10775614 # Number of loads squashed 360system.cpu.iew.lsq.thread0.ignoredResponses 30228 # Number of memory responses ignored because the instruction is squashed 361system.cpu.iew.lsq.thread0.memOrderViolation 33222 # Number of memory ordering violations 362system.cpu.iew.lsq.thread0.squashedStores 3339713 # Number of stores squashed | 427system.cpu.iew.lsq.thread0.squashedLoads 10766713 # Number of loads squashed 428system.cpu.iew.lsq.thread0.ignoredResponses 30678 # Number of memory responses ignored because the instruction is squashed 429system.cpu.iew.lsq.thread0.memOrderViolation 33261 # Number of memory ordering violations 430system.cpu.iew.lsq.thread0.squashedStores 3336738 # Number of stores squashed |
| 363system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 364system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 431system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 432system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 365system.cpu.iew.lsq.thread0.rescheduledLoads 3234 # Number of loads that were rescheduled 366system.cpu.iew.lsq.thread0.cacheBlocked 8606 # Number of times an access to memory failed due to the cache being blocked | 433system.cpu.iew.lsq.thread0.rescheduledLoads 3210 # Number of loads that were rescheduled 434system.cpu.iew.lsq.thread0.cacheBlocked 8599 # Number of times an access to memory failed due to the cache being blocked |
| 367system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 435system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 368system.cpu.iew.iewSquashCycles 4545203 # Number of cycles IEW is squashing 369system.cpu.iew.iewBlockCycles 1761176 # Number of cycles IEW is blocking 370system.cpu.iew.iewUnblockCycles 160180 # Number of cycles IEW is unblocking 371system.cpu.iew.iewDispatchedInsts 311476154 # Number of instructions dispatched to IQ 372system.cpu.iew.iewDispSquashedInsts 195955 # Number of squashed instructions skipped by dispatch 373system.cpu.iew.iewDispLoadInsts 101554999 # Number of dispatched load instructions 374system.cpu.iew.iewDispStoreInsts 34779465 # Number of dispatched store instructions 375system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions 376system.cpu.iew.iewIQFullEvents 3219 # Number of times the IQ has become full, causing a stall 377system.cpu.iew.iewLSQFullEvents 73682 # Number of times the LSQ has become full, causing a stall 378system.cpu.iew.memOrderViolationEvents 33222 # Number of memory order violations 379system.cpu.iew.predictedTakenIncorrect 393210 # Number of branches that were predicted taken incorrectly 380system.cpu.iew.predictedNotTakenIncorrect 428039 # Number of branches that were predicted not taken incorrectly 381system.cpu.iew.branchMispredicts 821249 # Number of branch mispredicts detected at execute 382system.cpu.iew.iewExecutedInsts 298868187 # Number of executed instructions 383system.cpu.iew.iewExecLoadInsts 96891593 # Number of load instructions executed 384system.cpu.iew.iewExecSquashedInsts 1400572 # Number of squashed instructions skipped in execute | 436system.cpu.iew.iewSquashCycles 4541560 # Number of cycles IEW is squashing 437system.cpu.iew.iewBlockCycles 2575832 # Number of cycles IEW is blocking 438system.cpu.iew.iewUnblockCycles 162156 # Number of cycles IEW is unblocking 439system.cpu.iew.iewDispatchedInsts 311462261 # Number of instructions dispatched to IQ 440system.cpu.iew.iewDispSquashedInsts 197211 # Number of squashed instructions skipped by dispatch 441system.cpu.iew.iewDispLoadInsts 101546098 # Number of dispatched load instructions 442system.cpu.iew.iewDispStoreInsts 34776490 # Number of dispatched store instructions 443system.cpu.iew.iewDispNonSpecInsts 463 # Number of dispatched non-speculative instructions 444system.cpu.iew.iewIQFullEvents 2580 # Number of times the IQ has become full, causing a stall 445system.cpu.iew.iewLSQFullEvents 73528 # Number of times the LSQ has become full, causing a stall 446system.cpu.iew.memOrderViolationEvents 33261 # Number of memory order violations 447system.cpu.iew.predictedTakenIncorrect 393064 # Number of branches that were predicted taken incorrectly 448system.cpu.iew.predictedNotTakenIncorrect 427262 # Number of branches that were predicted not taken incorrectly 449system.cpu.iew.branchMispredicts 820326 # Number of branch mispredicts detected at execute 450system.cpu.iew.iewExecutedInsts 298861022 # Number of executed instructions 451system.cpu.iew.iewExecLoadInsts 96886540 # Number of load instructions executed 452system.cpu.iew.iewExecSquashedInsts 1402220 # Number of squashed instructions skipped in execute |
| 385system.cpu.iew.exec_swp 0 # number of swp insts executed 386system.cpu.iew.exec_nop 0 # number of nop insts executed | 453system.cpu.iew.exec_swp 0 # number of swp insts executed 454system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 387system.cpu.iew.exec_refs 129818447 # number of memory reference insts executed 388system.cpu.iew.exec_branches 30819793 # Number of branches executed 389system.cpu.iew.exec_stores 32926854 # Number of stores executed 390system.cpu.iew.exec_rate 2.300563 # Inst execution rate 391system.cpu.iew.wb_sent 298386144 # cumulative count of insts sent to commit 392system.cpu.iew.wb_count 298017378 # cumulative count of insts written-back 393system.cpu.iew.wb_producers 218312526 # num instructions producing a value 394system.cpu.iew.wb_consumers 296857185 # num instructions consuming a value | 455system.cpu.iew.exec_refs 129814002 # number of memory reference insts executed 456system.cpu.iew.exec_branches 30818579 # Number of branches executed 457system.cpu.iew.exec_stores 32927462 # Number of stores executed 458system.cpu.iew.exec_rate 2.281732 # Inst execution rate 459system.cpu.iew.wb_sent 298381528 # cumulative count of insts sent to commit 460system.cpu.iew.wb_count 298012951 # cumulative count of insts written-back 461system.cpu.iew.wb_producers 218258094 # num instructions producing a value 462system.cpu.iew.wb_consumers 296763752 # num instructions consuming a value |
| 395system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 463system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 396system.cpu.iew.wb_rate 2.294014 # insts written-back per cycle 397system.cpu.iew.wb_fanout 0.735413 # average fanout of values written-back | 464system.cpu.iew.wb_rate 2.275257 # insts written-back per cycle 465system.cpu.iew.wb_fanout 0.735461 # average fanout of values written-back |
| 398system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 466system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 399system.cpu.commit.commitSquashedInsts 33296720 # The number of squashed insts skipped by commit | 467system.cpu.commit.commitSquashedInsts 33282582 # The number of squashed insts skipped by commit |
| 400system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards | 468system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards |
| 401system.cpu.commit.branchMispredicts 775062 # The number of times a branch was mispredicted 402system.cpu.commit.committed_per_cycle::samples 125284741 # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::mean 2.220482 # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::stdev 2.978635 # Number of insts commited each cycle | 469system.cpu.commit.branchMispredicts 774373 # The number of times a branch was mispredicted 470system.cpu.commit.committed_per_cycle::samples 126335414 # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::mean 2.202015 # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::stdev 2.972310 # Number of insts commited each cycle |
| 405system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 473system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 406system.cpu.commit.committed_per_cycle::0 57056182 45.54% 45.54% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::1 19092863 15.24% 60.78% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::2 11627505 9.28% 70.06% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::3 9458661 7.55% 77.61% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::4 1851635 1.48% 79.09% # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::5 2083324 1.66% 80.75% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::6 1287468 1.03% 81.78% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::7 696184 0.56% 82.34% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::8 22130919 17.66% 100.00% # Number of insts commited each cycle | 474system.cpu.commit.committed_per_cycle::0 58023185 45.93% 45.93% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::1 19157211 15.16% 61.09% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::2 11690918 9.25% 70.35% # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::3 9453779 7.48% 77.83% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::4 1822705 1.44% 79.27% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::5 2075367 1.64% 80.91% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::6 1288633 1.02% 81.93% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::7 696301 0.55% 82.49% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::8 22127315 17.51% 100.00% # Number of insts commited each cycle |
| 415system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 483system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 418system.cpu.commit.committed_per_cycle::total 125284741 # Number of insts commited each cycle | 486system.cpu.commit.committed_per_cycle::total 126335414 # Number of insts commited each cycle |
| 419system.cpu.commit.committedInsts 157988547 # Number of instructions committed 420system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 421system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 422system.cpu.commit.refs 122219137 # Number of memory references committed 423system.cpu.commit.loads 90779385 # Number of loads committed 424system.cpu.commit.membars 0 # Number of memory barriers committed 425system.cpu.commit.branches 29309705 # Number of branches committed 426system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 427system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. 428system.cpu.commit.function_calls 4237596 # Number of function calls committed. | 487system.cpu.commit.committedInsts 157988547 # Number of instructions committed 488system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 489system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 490system.cpu.commit.refs 122219137 # Number of memory references committed 491system.cpu.commit.loads 90779385 # Number of loads committed 492system.cpu.commit.membars 0 # Number of memory barriers committed 493system.cpu.commit.branches 29309705 # Number of branches committed 494system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 495system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. 496system.cpu.commit.function_calls 4237596 # Number of function calls committed. |
| 429system.cpu.commit.bw_lim_events 22130919 # number cycles where commit BW limit reached | 497system.cpu.commit.bw_lim_events 22127315 # number cycles where commit BW limit reached |
| 430system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 498system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 431system.cpu.rob.rob_reads 414643006 # The number of ROB reads 432system.cpu.rob.rob_writes 627527392 # The number of ROB writes 433system.cpu.timesIdled 13814 # Number of times that the entire CPU went into an idle state and unscheduled itself 434system.cpu.idleCycles 80936 # Total number of cycles that the CPU has spent unscheduled due to idling | 499system.cpu.rob.rob_reads 415683145 # The number of ROB reads 500system.cpu.rob.rob_writes 627495486 # The number of ROB writes 501system.cpu.timesIdled 13953 # Number of times that the entire CPU went into an idle state and unscheduled itself 502system.cpu.idleCycles 102932 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 435system.cpu.committedInsts 157988547 # Number of Instructions Simulated 436system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 437system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated | 503system.cpu.committedInsts 157988547 # Number of Instructions Simulated 504system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 505system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated |
| 438system.cpu.cpi 0.822280 # CPI: Cycles Per Instruction 439system.cpu.cpi_total 0.822280 # CPI: Total CPI of All Threads 440system.cpu.ipc 1.216130 # IPC: Instructions Per Cycle 441system.cpu.ipc_total 1.216130 # IPC: Total IPC of All Threads 442system.cpu.int_regfile_reads 590791400 # number of integer regfile reads 443system.cpu.int_regfile_writes 298595306 # number of integer regfile writes 444system.cpu.fp_regfile_reads 134 # number of floating regfile reads 445system.cpu.fp_regfile_writes 70 # number of floating regfile writes 446system.cpu.misc_regfile_reads 191828831 # number of misc regfile reads | 506system.cpu.cpi 0.829047 # CPI: Cycles Per Instruction 507system.cpu.cpi_total 0.829047 # CPI: Total CPI of All Threads 508system.cpu.ipc 1.206204 # IPC: Instructions Per Cycle 509system.cpu.ipc_total 1.206204 # IPC: Total IPC of All Threads 510system.cpu.int_regfile_reads 590786274 # number of integer regfile reads 511system.cpu.int_regfile_writes 298589380 # number of integer regfile writes 512system.cpu.fp_regfile_reads 94 # number of floating regfile reads 513system.cpu.fp_regfile_writes 64 # number of floating regfile writes 514system.cpu.misc_regfile_reads 191820132 # number of misc regfile reads |
| 447system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 515system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 448system.cpu.icache.replacements 61 # number of replacements 449system.cpu.icache.tagsinuse 820.655975 # Cycle average of tags in use 450system.cpu.icache.total_refs 25576619 # Total number of references to valid blocks. 451system.cpu.icache.sampled_refs 1018 # Sample count of references to valid blocks. 452system.cpu.icache.avg_refs 25124.380157 # Average number of references to valid blocks. | 516system.cpu.toL2Bus.throughput 4049838977 # Throughput (bytes/s) 517system.cpu.toL2Bus.trans_dist::ReadReq 1995271 # Transaction distribution 518system.cpu.toL2Bus.trans_dist::ReadResp 1995269 # Transaction distribution 519system.cpu.toL2Bus.trans_dist::Writeback 2066544 # Transaction distribution 520system.cpu.toL2Bus.trans_dist::ReadExReq 82308 # Transaction distribution 521system.cpu.toL2Bus.trans_dist::ReadExResp 82308 # Transaction distribution 522system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2026 # Packet count per connected master and slave (bytes) 523system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219674 # Packet count per connected master and slave (bytes) 524system.cpu.toL2Bus.pkt_count 6221700 # Packet count per connected master and slave (bytes) 525system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64832 # Cumulative packet size per connected master and slave (bytes) 526system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265158912 # Cumulative packet size per connected master and slave (bytes) 527system.cpu.toL2Bus.tot_pkt_size 265223744 # Cumulative packet size per connected master and slave (bytes) 528system.cpu.toL2Bus.data_through_bus 265223744 # Total data (bytes) 529system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 530system.cpu.toL2Bus.reqLayer0.occupancy 4138605500 # Layer occupancy (ticks) 531system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) 532system.cpu.toL2Bus.respLayer0.occupancy 1519500 # Layer occupancy (ticks) 533system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 534system.cpu.toL2Bus.respLayer1.occupancy 3114846499 # Layer occupancy (ticks) 535system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) 536system.cpu.icache.replacements 52 # number of replacements 537system.cpu.icache.tagsinuse 824.208577 # Cycle average of tags in use 538system.cpu.icache.total_refs 25572646 # Total number of references to valid blocks. 539system.cpu.icache.sampled_refs 1013 # Sample count of references to valid blocks. 540system.cpu.icache.avg_refs 25244.467917 # Average number of references to valid blocks. |
| 453system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 541system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 454system.cpu.icache.occ_blocks::cpu.inst 820.655975 # Average occupied blocks per requestor 455system.cpu.icache.occ_percent::cpu.inst 0.400711 # Average percentage of cache occupancy 456system.cpu.icache.occ_percent::total 0.400711 # Average percentage of cache occupancy 457system.cpu.icache.ReadReq_hits::cpu.inst 25576619 # number of ReadReq hits 458system.cpu.icache.ReadReq_hits::total 25576619 # number of ReadReq hits 459system.cpu.icache.demand_hits::cpu.inst 25576619 # number of demand (read+write) hits 460system.cpu.icache.demand_hits::total 25576619 # number of demand (read+write) hits 461system.cpu.icache.overall_hits::cpu.inst 25576619 # number of overall hits 462system.cpu.icache.overall_hits::total 25576619 # number of overall hits 463system.cpu.icache.ReadReq_misses::cpu.inst 1290 # number of ReadReq misses 464system.cpu.icache.ReadReq_misses::total 1290 # number of ReadReq misses 465system.cpu.icache.demand_misses::cpu.inst 1290 # number of demand (read+write) misses 466system.cpu.icache.demand_misses::total 1290 # number of demand (read+write) misses 467system.cpu.icache.overall_misses::cpu.inst 1290 # number of overall misses 468system.cpu.icache.overall_misses::total 1290 # number of overall misses 469system.cpu.icache.ReadReq_miss_latency::cpu.inst 64574500 # number of ReadReq miss cycles 470system.cpu.icache.ReadReq_miss_latency::total 64574500 # number of ReadReq miss cycles 471system.cpu.icache.demand_miss_latency::cpu.inst 64574500 # number of demand (read+write) miss cycles 472system.cpu.icache.demand_miss_latency::total 64574500 # number of demand (read+write) miss cycles 473system.cpu.icache.overall_miss_latency::cpu.inst 64574500 # number of overall miss cycles 474system.cpu.icache.overall_miss_latency::total 64574500 # number of overall miss cycles 475system.cpu.icache.ReadReq_accesses::cpu.inst 25577909 # number of ReadReq accesses(hits+misses) 476system.cpu.icache.ReadReq_accesses::total 25577909 # number of ReadReq accesses(hits+misses) 477system.cpu.icache.demand_accesses::cpu.inst 25577909 # number of demand (read+write) accesses 478system.cpu.icache.demand_accesses::total 25577909 # number of demand (read+write) accesses 479system.cpu.icache.overall_accesses::cpu.inst 25577909 # number of overall (read+write) accesses 480system.cpu.icache.overall_accesses::total 25577909 # number of overall (read+write) accesses 481system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses 482system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses 483system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses 484system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses 485system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses 486system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses 487system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50057.751938 # average ReadReq miss latency 488system.cpu.icache.ReadReq_avg_miss_latency::total 50057.751938 # average ReadReq miss latency 489system.cpu.icache.demand_avg_miss_latency::cpu.inst 50057.751938 # average overall miss latency 490system.cpu.icache.demand_avg_miss_latency::total 50057.751938 # average overall miss latency 491system.cpu.icache.overall_avg_miss_latency::cpu.inst 50057.751938 # average overall miss latency 492system.cpu.icache.overall_avg_miss_latency::total 50057.751938 # average overall miss latency 493system.cpu.icache.blocked_cycles::no_mshrs 35 # number of cycles access was blocked | 542system.cpu.icache.occ_blocks::cpu.inst 824.208577 # Average occupied blocks per requestor 543system.cpu.icache.occ_percent::cpu.inst 0.402446 # Average percentage of cache occupancy 544system.cpu.icache.occ_percent::total 0.402446 # Average percentage of cache occupancy 545system.cpu.icache.ReadReq_hits::cpu.inst 25572646 # number of ReadReq hits 546system.cpu.icache.ReadReq_hits::total 25572646 # number of ReadReq hits 547system.cpu.icache.demand_hits::cpu.inst 25572646 # number of demand (read+write) hits 548system.cpu.icache.demand_hits::total 25572646 # number of demand (read+write) hits 549system.cpu.icache.overall_hits::cpu.inst 25572646 # number of overall hits 550system.cpu.icache.overall_hits::total 25572646 # number of overall hits 551system.cpu.icache.ReadReq_misses::cpu.inst 1301 # number of ReadReq misses 552system.cpu.icache.ReadReq_misses::total 1301 # number of ReadReq misses 553system.cpu.icache.demand_misses::cpu.inst 1301 # number of demand (read+write) misses 554system.cpu.icache.demand_misses::total 1301 # number of demand (read+write) misses 555system.cpu.icache.overall_misses::cpu.inst 1301 # number of overall misses 556system.cpu.icache.overall_misses::total 1301 # number of overall misses 557system.cpu.icache.ReadReq_miss_latency::cpu.inst 86424000 # number of ReadReq miss cycles 558system.cpu.icache.ReadReq_miss_latency::total 86424000 # number of ReadReq miss cycles 559system.cpu.icache.demand_miss_latency::cpu.inst 86424000 # number of demand (read+write) miss cycles 560system.cpu.icache.demand_miss_latency::total 86424000 # number of demand (read+write) miss cycles 561system.cpu.icache.overall_miss_latency::cpu.inst 86424000 # number of overall miss cycles 562system.cpu.icache.overall_miss_latency::total 86424000 # number of overall miss cycles 563system.cpu.icache.ReadReq_accesses::cpu.inst 25573947 # number of ReadReq accesses(hits+misses) 564system.cpu.icache.ReadReq_accesses::total 25573947 # number of ReadReq accesses(hits+misses) 565system.cpu.icache.demand_accesses::cpu.inst 25573947 # number of demand (read+write) accesses 566system.cpu.icache.demand_accesses::total 25573947 # number of demand (read+write) accesses 567system.cpu.icache.overall_accesses::cpu.inst 25573947 # number of overall (read+write) accesses 568system.cpu.icache.overall_accesses::total 25573947 # number of overall (read+write) accesses 569system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 570system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 571system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 572system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 573system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 574system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses 575system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66428.900846 # average ReadReq miss latency 576system.cpu.icache.ReadReq_avg_miss_latency::total 66428.900846 # average ReadReq miss latency 577system.cpu.icache.demand_avg_miss_latency::cpu.inst 66428.900846 # average overall miss latency 578system.cpu.icache.demand_avg_miss_latency::total 66428.900846 # average overall miss latency 579system.cpu.icache.overall_avg_miss_latency::cpu.inst 66428.900846 # average overall miss latency 580system.cpu.icache.overall_avg_miss_latency::total 66428.900846 # average overall miss latency 581system.cpu.icache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked |
| 494system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 582system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 495system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked | 583system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked |
| 496system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 584system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 497system.cpu.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked | 585system.cpu.icache.avg_blocked_cycles::no_mshrs 38.333333 # average number of cycles each access was blocked |
| 498system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 499system.cpu.icache.fast_writes 0 # number of fast writes performed 500system.cpu.icache.cache_copies 0 # number of cache copies performed | 586system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 587system.cpu.icache.fast_writes 0 # number of fast writes performed 588system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 501system.cpu.icache.ReadReq_mshr_hits::cpu.inst 272 # number of ReadReq MSHR hits 502system.cpu.icache.ReadReq_mshr_hits::total 272 # number of ReadReq MSHR hits 503system.cpu.icache.demand_mshr_hits::cpu.inst 272 # number of demand (read+write) MSHR hits 504system.cpu.icache.demand_mshr_hits::total 272 # number of demand (read+write) MSHR hits 505system.cpu.icache.overall_mshr_hits::cpu.inst 272 # number of overall MSHR hits 506system.cpu.icache.overall_mshr_hits::total 272 # number of overall MSHR hits 507system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1018 # number of ReadReq MSHR misses 508system.cpu.icache.ReadReq_mshr_misses::total 1018 # number of ReadReq MSHR misses 509system.cpu.icache.demand_mshr_misses::cpu.inst 1018 # number of demand (read+write) MSHR misses 510system.cpu.icache.demand_mshr_misses::total 1018 # number of demand (read+write) MSHR misses 511system.cpu.icache.overall_mshr_misses::cpu.inst 1018 # number of overall MSHR misses 512system.cpu.icache.overall_mshr_misses::total 1018 # number of overall MSHR misses 513system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52495000 # number of ReadReq MSHR miss cycles 514system.cpu.icache.ReadReq_mshr_miss_latency::total 52495000 # number of ReadReq MSHR miss cycles 515system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52495000 # number of demand (read+write) MSHR miss cycles 516system.cpu.icache.demand_mshr_miss_latency::total 52495000 # number of demand (read+write) MSHR miss cycles 517system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52495000 # number of overall MSHR miss cycles 518system.cpu.icache.overall_mshr_miss_latency::total 52495000 # number of overall MSHR miss cycles | 589system.cpu.icache.ReadReq_mshr_hits::cpu.inst 288 # number of ReadReq MSHR hits 590system.cpu.icache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits 591system.cpu.icache.demand_mshr_hits::cpu.inst 288 # number of demand (read+write) MSHR hits 592system.cpu.icache.demand_mshr_hits::total 288 # number of demand (read+write) MSHR hits 593system.cpu.icache.overall_mshr_hits::cpu.inst 288 # number of overall MSHR hits 594system.cpu.icache.overall_mshr_hits::total 288 # number of overall MSHR hits 595system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses 596system.cpu.icache.ReadReq_mshr_misses::total 1013 # number of ReadReq MSHR misses 597system.cpu.icache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses 598system.cpu.icache.demand_mshr_misses::total 1013 # number of demand (read+write) MSHR misses 599system.cpu.icache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses 600system.cpu.icache.overall_mshr_misses::total 1013 # number of overall MSHR misses 601system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68779000 # number of ReadReq MSHR miss cycles 602system.cpu.icache.ReadReq_mshr_miss_latency::total 68779000 # number of ReadReq MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68779000 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.demand_mshr_miss_latency::total 68779000 # number of demand (read+write) MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68779000 # number of overall MSHR miss cycles 606system.cpu.icache.overall_mshr_miss_latency::total 68779000 # number of overall MSHR miss cycles |
| 519system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 520system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 521system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 522system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 523system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 524system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 607system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 608system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 609system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 610system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 611system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 612system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 525system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51566.797642 # average ReadReq mshr miss latency 526system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51566.797642 # average ReadReq mshr miss latency 527system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51566.797642 # average overall mshr miss latency 528system.cpu.icache.demand_avg_mshr_miss_latency::total 51566.797642 # average overall mshr miss latency 529system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51566.797642 # average overall mshr miss latency 530system.cpu.icache.overall_avg_mshr_miss_latency::total 51566.797642 # average overall mshr miss latency | 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67896.347483 # average ReadReq mshr miss latency 614system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67896.347483 # average ReadReq mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67896.347483 # average overall mshr miss latency 616system.cpu.icache.demand_avg_mshr_miss_latency::total 67896.347483 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67896.347483 # average overall mshr miss latency 618system.cpu.icache.overall_avg_mshr_miss_latency::total 67896.347483 # average overall mshr miss latency |
| 531system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 619system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 532system.cpu.l2cache.replacements 476 # number of replacements 533system.cpu.l2cache.tagsinuse 20892.456285 # Cycle average of tags in use 534system.cpu.l2cache.total_refs 4029594 # Total number of references to valid blocks. 535system.cpu.l2cache.sampled_refs 30400 # Sample count of references to valid blocks. 536system.cpu.l2cache.avg_refs 132.552434 # Average number of references to valid blocks. | 620system.cpu.l2cache.replacements 473 # number of replacements 621system.cpu.l2cache.tagsinuse 20826.388210 # Cycle average of tags in use 622system.cpu.l2cache.total_refs 4029249 # Total number of references to valid blocks. 623system.cpu.l2cache.sampled_refs 30396 # Sample count of references to valid blocks. 624system.cpu.l2cache.avg_refs 132.558527 # Average number of references to valid blocks. |
| 537system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 625system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 538system.cpu.l2cache.occ_blocks::writebacks 19980.495233 # Average occupied blocks per requestor 539system.cpu.l2cache.occ_blocks::cpu.inst 670.175654 # Average occupied blocks per requestor 540system.cpu.l2cache.occ_blocks::cpu.data 241.785398 # Average occupied blocks per requestor 541system.cpu.l2cache.occ_percent::writebacks 0.609756 # Average percentage of cache occupancy | 626system.cpu.l2cache.occ_blocks::writebacks 19907.583487 # Average occupied blocks per requestor 627system.cpu.l2cache.occ_blocks::cpu.inst 670.159667 # Average occupied blocks per requestor 628system.cpu.l2cache.occ_blocks::cpu.data 248.645055 # Average occupied blocks per requestor 629system.cpu.l2cache.occ_percent::writebacks 0.607531 # Average percentage of cache occupancy |
| 542system.cpu.l2cache.occ_percent::cpu.inst 0.020452 # Average percentage of cache occupancy | 630system.cpu.l2cache.occ_percent::cpu.inst 0.020452 # Average percentage of cache occupancy |
| 543system.cpu.l2cache.occ_percent::cpu.data 0.007379 # Average percentage of cache occupancy 544system.cpu.l2cache.occ_percent::total 0.637587 # Average percentage of cache occupancy 545system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 546system.cpu.l2cache.ReadReq_hits::cpu.data 1993856 # number of ReadReq hits 547system.cpu.l2cache.ReadReq_hits::total 1993873 # number of ReadReq hits 548system.cpu.l2cache.Writeback_hits::writebacks 2066867 # number of Writeback hits 549system.cpu.l2cache.Writeback_hits::total 2066867 # number of Writeback hits 550system.cpu.l2cache.ReadExReq_hits::cpu.data 53312 # number of ReadExReq hits 551system.cpu.l2cache.ReadExReq_hits::total 53312 # number of ReadExReq hits 552system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 553system.cpu.l2cache.demand_hits::cpu.data 2047168 # number of demand (read+write) hits 554system.cpu.l2cache.demand_hits::total 2047185 # number of demand (read+write) hits 555system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 556system.cpu.l2cache.overall_hits::cpu.data 2047168 # number of overall hits 557system.cpu.l2cache.overall_hits::total 2047185 # number of overall hits 558system.cpu.l2cache.ReadReq_misses::cpu.inst 1001 # number of ReadReq misses 559system.cpu.l2cache.ReadReq_misses::cpu.data 414 # number of ReadReq misses 560system.cpu.l2cache.ReadReq_misses::total 1415 # number of ReadReq misses 561system.cpu.l2cache.ReadExReq_misses::cpu.data 29000 # number of ReadExReq misses 562system.cpu.l2cache.ReadExReq_misses::total 29000 # number of ReadExReq misses 563system.cpu.l2cache.demand_misses::cpu.inst 1001 # number of demand (read+write) misses 564system.cpu.l2cache.demand_misses::cpu.data 29414 # number of demand (read+write) misses | 631system.cpu.l2cache.occ_percent::cpu.data 0.007588 # Average percentage of cache occupancy 632system.cpu.l2cache.occ_percent::total 0.635571 # Average percentage of cache occupancy 633system.cpu.l2cache.ReadReq_hits::cpu.inst 15 # number of ReadReq hits 634system.cpu.l2cache.ReadReq_hits::cpu.data 1993842 # number of ReadReq hits 635system.cpu.l2cache.ReadReq_hits::total 1993857 # number of ReadReq hits 636system.cpu.l2cache.Writeback_hits::writebacks 2066544 # number of Writeback hits 637system.cpu.l2cache.Writeback_hits::total 2066544 # number of Writeback hits 638system.cpu.l2cache.ReadExReq_hits::cpu.data 53307 # number of ReadExReq hits 639system.cpu.l2cache.ReadExReq_hits::total 53307 # number of ReadExReq hits 640system.cpu.l2cache.demand_hits::cpu.inst 15 # number of demand (read+write) hits 641system.cpu.l2cache.demand_hits::cpu.data 2047149 # number of demand (read+write) hits 642system.cpu.l2cache.demand_hits::total 2047164 # number of demand (read+write) hits 643system.cpu.l2cache.overall_hits::cpu.inst 15 # number of overall hits 644system.cpu.l2cache.overall_hits::cpu.data 2047149 # number of overall hits 645system.cpu.l2cache.overall_hits::total 2047164 # number of overall hits 646system.cpu.l2cache.ReadReq_misses::cpu.inst 998 # number of ReadReq misses 647system.cpu.l2cache.ReadReq_misses::cpu.data 416 # number of ReadReq misses 648system.cpu.l2cache.ReadReq_misses::total 1414 # number of ReadReq misses 649system.cpu.l2cache.ReadExReq_misses::cpu.data 29001 # number of ReadExReq misses 650system.cpu.l2cache.ReadExReq_misses::total 29001 # number of ReadExReq misses 651system.cpu.l2cache.demand_misses::cpu.inst 998 # number of demand (read+write) misses 652system.cpu.l2cache.demand_misses::cpu.data 29417 # number of demand (read+write) misses |
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| 566system.cpu.l2cache.overall_misses::cpu.inst 1001 # number of overall misses 567system.cpu.l2cache.overall_misses::cpu.data 29414 # number of overall misses | 654system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses 655system.cpu.l2cache.overall_misses::cpu.data 29417 # number of overall misses |
| 568system.cpu.l2cache.overall_misses::total 30415 # number of overall misses | 656system.cpu.l2cache.overall_misses::total 30415 # number of overall misses |
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number of overall miss cycles 580system.cpu.l2cache.ReadReq_accesses::cpu.inst 1018 # number of ReadReq accesses(hits+misses) 581system.cpu.l2cache.ReadReq_accesses::cpu.data 1994270 # number of ReadReq accesses(hits+misses) 582system.cpu.l2cache.ReadReq_accesses::total 1995288 # number of ReadReq accesses(hits+misses) 583system.cpu.l2cache.Writeback_accesses::writebacks 2066867 # number of Writeback accesses(hits+misses) 584system.cpu.l2cache.Writeback_accesses::total 2066867 # number of Writeback accesses(hits+misses) 585system.cpu.l2cache.ReadExReq_accesses::cpu.data 82312 # number of ReadExReq accesses(hits+misses) 586system.cpu.l2cache.ReadExReq_accesses::total 82312 # number of ReadExReq accesses(hits+misses) 587system.cpu.l2cache.demand_accesses::cpu.inst 1018 # number of demand (read+write) accesses 588system.cpu.l2cache.demand_accesses::cpu.data 2076582 # number of demand (read+write) accesses 589system.cpu.l2cache.demand_accesses::total 2077600 # number of demand (read+write) accesses 590system.cpu.l2cache.overall_accesses::cpu.inst 1018 # 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number of demand (read+write) miss cycles 664system.cpu.l2cache.demand_miss_latency::total 1871302500 # number of demand (read+write) miss cycles 665system.cpu.l2cache.overall_miss_latency::cpu.inst 67606500 # number of overall miss cycles 666system.cpu.l2cache.overall_miss_latency::cpu.data 1803696000 # number of overall miss cycles 667system.cpu.l2cache.overall_miss_latency::total 1871302500 # number of overall miss cycles 668system.cpu.l2cache.ReadReq_accesses::cpu.inst 1013 # number of ReadReq accesses(hits+misses) 669system.cpu.l2cache.ReadReq_accesses::cpu.data 1994258 # number of ReadReq accesses(hits+misses) 670system.cpu.l2cache.ReadReq_accesses::total 1995271 # number of ReadReq accesses(hits+misses) 671system.cpu.l2cache.Writeback_accesses::writebacks 2066544 # number of Writeback accesses(hits+misses) 672system.cpu.l2cache.Writeback_accesses::total 2066544 # number of Writeback accesses(hits+misses) 673system.cpu.l2cache.ReadExReq_accesses::cpu.data 82308 # number of ReadExReq accesses(hits+misses) 674system.cpu.l2cache.ReadExReq_accesses::total 82308 # number of ReadExReq accesses(hits+misses) 675system.cpu.l2cache.demand_accesses::cpu.inst 1013 # number of demand (read+write) accesses 676system.cpu.l2cache.demand_accesses::cpu.data 2076566 # number of demand (read+write) accesses 677system.cpu.l2cache.demand_accesses::total 2077579 # number of demand (read+write) accesses 678system.cpu.l2cache.overall_accesses::cpu.inst 1013 # number of overall (read+write) accesses 679system.cpu.l2cache.overall_accesses::cpu.data 2076566 # number of overall (read+write) accesses 680system.cpu.l2cache.overall_accesses::total 2077579 # number of overall (read+write) accesses 681system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985192 # miss rate for ReadReq accesses 682system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000209 # miss rate for ReadReq accesses |
| 595system.cpu.l2cache.ReadReq_miss_rate::total 0.000709 # miss rate for ReadReq accesses | 683system.cpu.l2cache.ReadReq_miss_rate::total 0.000709 # miss rate for ReadReq accesses |
| 596system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352318 # miss rate for ReadExReq accesses 597system.cpu.l2cache.ReadExReq_miss_rate::total 0.352318 # miss rate for ReadExReq accesses 598system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983301 # miss rate for demand accesses 599system.cpu.l2cache.demand_miss_rate::cpu.data 0.014165 # miss rate for demand accesses 600system.cpu.l2cache.demand_miss_rate::total 0.014639 # miss rate for demand accesses 601system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983301 # miss rate for overall accesses 602system.cpu.l2cache.overall_miss_rate::cpu.data 0.014165 # miss rate for overall accesses 603system.cpu.l2cache.overall_miss_rate::total 0.014639 # miss rate for overall accesses 604system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51247.752248 # average ReadReq miss latency 605system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51452.898551 # average ReadReq miss latency 606system.cpu.l2cache.ReadReq_avg_miss_latency::total 51307.773852 # average ReadReq miss latency 607system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42013.706897 # average ReadExReq miss latency 608system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42013.706897 # average ReadExReq miss latency 609system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51247.752248 # average overall miss latency 610system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42146.562861 # average overall miss latency 611system.cpu.l2cache.demand_avg_miss_latency::total 42446.095676 # average overall miss latency 612system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51247.752248 # average overall miss latency 613system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42146.562861 # average overall miss latency 614system.cpu.l2cache.overall_avg_miss_latency::total 42446.095676 # average overall miss latency | 684system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352347 # miss rate for ReadExReq accesses 685system.cpu.l2cache.ReadExReq_miss_rate::total 0.352347 # miss rate for ReadExReq accesses 686system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985192 # miss rate for demand accesses 687system.cpu.l2cache.demand_miss_rate::cpu.data 0.014166 # miss rate for demand accesses 688system.cpu.l2cache.demand_miss_rate::total 0.014640 # miss rate for demand accesses 689system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985192 # miss rate for overall accesses 690system.cpu.l2cache.overall_miss_rate::cpu.data 0.014166 # miss rate for overall accesses 691system.cpu.l2cache.overall_miss_rate::total 0.014640 # miss rate for overall accesses 692system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67741.983968 # average ReadReq miss latency 693system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68390.625000 # average ReadReq miss latency 694system.cpu.l2cache.ReadReq_avg_miss_latency::total 67932.814710 # average ReadReq miss latency 695system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61213.251267 # average ReadExReq miss latency 696system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61213.251267 # average ReadExReq miss latency 697system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67741.983968 # average overall miss latency 698system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61314.749975 # average overall miss latency 699system.cpu.l2cache.demand_avg_miss_latency::total 61525.645241 # average overall miss latency 700system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67741.983968 # average overall miss latency 701system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61314.749975 # average overall miss latency 702system.cpu.l2cache.overall_avg_miss_latency::total 61525.645241 # average overall miss latency |
| 615system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 616system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 617system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 618system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 619system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 620system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 621system.cpu.l2cache.fast_writes 0 # number of fast writes performed 622system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 703system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 704system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 705system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 706system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 707system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 708system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 709system.cpu.l2cache.fast_writes 0 # number of fast writes performed 710system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
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| 632system.cpu.l2cache.demand_mshr_misses::total 30415 # number of demand (read+write) MSHR misses | 720system.cpu.l2cache.demand_mshr_misses::total 30415 # number of demand (read+write) MSHR misses |
| 633system.cpu.l2cache.overall_mshr_misses::cpu.inst 1001 # number of overall MSHR misses 634system.cpu.l2cache.overall_mshr_misses::cpu.data 29414 # number of overall MSHR misses | 721system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses 722system.cpu.l2cache.overall_mshr_misses::cpu.data 29417 # number of overall MSHR misses |
| 635system.cpu.l2cache.overall_mshr_misses::total 30415 # number of overall MSHR misses | 723system.cpu.l2cache.overall_mshr_misses::total 30415 # number of overall MSHR misses |
| 636system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38886556 # number of ReadReq MSHR miss cycles 637system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16149852 # number of ReadReq MSHR miss cycles 638system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55036408 # number of ReadReq MSHR miss cycles 639system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 860635717 # number of ReadExReq MSHR miss cycles 640system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 860635717 # number of ReadExReq MSHR miss cycles 641system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38886556 # number of demand (read+write) MSHR miss cycles 642system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 876785569 # number of demand (read+write) MSHR miss cycles 643system.cpu.l2cache.demand_mshr_miss_latency::total 915672125 # number of demand (read+write) MSHR miss cycles 644system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38886556 # number of overall MSHR miss cycles 645system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 876785569 # number of overall MSHR miss cycles 646system.cpu.l2cache.overall_mshr_miss_latency::total 915672125 # number of overall MSHR miss cycles 647system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for ReadReq accesses 648system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000208 # mshr miss rate for ReadReq accesses | 724system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 55248500 # number of ReadReq MSHR miss cycles 725system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23325000 # number of ReadReq MSHR miss cycles 726system.cpu.l2cache.ReadReq_mshr_miss_latency::total 78573500 # number of ReadReq MSHR miss cycles 727system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1417505250 # number of ReadExReq MSHR miss cycles 728system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1417505250 # number of ReadExReq MSHR miss cycles 729system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55248500 # number of demand (read+write) MSHR miss cycles 730system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1440830250 # number of demand (read+write) MSHR miss cycles 731system.cpu.l2cache.demand_mshr_miss_latency::total 1496078750 # number of demand (read+write) MSHR miss cycles 732system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55248500 # number of overall MSHR miss cycles 733system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1440830250 # number of overall MSHR miss cycles 734system.cpu.l2cache.overall_mshr_miss_latency::total 1496078750 # number of overall MSHR miss cycles 735system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985192 # mshr miss rate for ReadReq accesses 736system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000209 # mshr miss rate for ReadReq accesses |
| 649system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadReq accesses | 737system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadReq accesses |
| 650system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352318 # mshr miss rate for ReadExReq accesses 651system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352318 # mshr miss rate for ReadExReq accesses 652system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for demand accesses 653system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014165 # mshr miss rate for demand accesses 654system.cpu.l2cache.demand_mshr_miss_rate::total 0.014639 # mshr miss rate for demand accesses 655system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for overall accesses 656system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014165 # mshr miss rate for overall accesses 657system.cpu.l2cache.overall_mshr_miss_rate::total 0.014639 # mshr miss rate for overall accesses 658system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38847.708292 # average ReadReq mshr miss latency 659system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39009.304348 # average ReadReq mshr miss latency 660system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38894.987986 # average ReadReq mshr miss latency 661system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29677.093690 # average ReadExReq mshr miss latency 662system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29677.093690 # average ReadExReq mshr miss latency 663system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38847.708292 # average overall mshr miss latency 664system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29808.443904 # average overall mshr miss latency 665system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30105.938682 # average overall mshr miss latency 666system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38847.708292 # average overall mshr miss latency 667system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29808.443904 # average overall mshr miss latency 668system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30105.938682 # average overall mshr miss latency | 738system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352347 # mshr miss rate for ReadExReq accesses 739system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352347 # mshr miss rate for ReadExReq accesses 740system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985192 # mshr miss rate for demand accesses 741system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014166 # mshr miss rate for demand accesses 742system.cpu.l2cache.demand_mshr_miss_rate::total 0.014640 # mshr miss rate for demand accesses 743system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985192 # mshr miss rate for overall accesses 744system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014166 # mshr miss rate for overall accesses 745system.cpu.l2cache.overall_mshr_miss_rate::total 0.014640 # mshr miss rate for overall accesses 746system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55359.218437 # average ReadReq mshr miss latency 747system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56069.711538 # average ReadReq mshr miss latency 748system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55568.246110 # average ReadReq mshr miss latency 749system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48877.805938 # average ReadExReq mshr miss latency 750system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48877.805938 # average ReadExReq mshr miss latency 751system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55359.218437 # average overall mshr miss latency 752system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48979.510147 # average overall mshr miss latency 753system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49188.845964 # average overall mshr miss latency 754system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55359.218437 # average overall mshr miss latency 755system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48979.510147 # average overall mshr miss latency 756system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49188.845964 # average overall mshr miss latency |
| 669system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 757system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 670system.cpu.dcache.replacements 2072485 # number of replacements 671system.cpu.dcache.tagsinuse 4072.522671 # Cycle average of tags in use 672system.cpu.dcache.total_refs 71414123 # Total number of references to valid blocks. 673system.cpu.dcache.sampled_refs 2076581 # Sample count of references to valid blocks. 674system.cpu.dcache.avg_refs 34.390242 # Average number of references to valid blocks. 675system.cpu.dcache.warmup_cycle 20537505000 # Cycle when the warmup percentage was hit. 676system.cpu.dcache.occ_blocks::cpu.data 4072.522671 # Average occupied blocks per requestor 677system.cpu.dcache.occ_percent::cpu.data 0.994268 # Average percentage of cache occupancy 678system.cpu.dcache.occ_percent::total 0.994268 # Average percentage of cache occupancy 679system.cpu.dcache.ReadReq_hits::cpu.data 40072419 # number of ReadReq hits 680system.cpu.dcache.ReadReq_hits::total 40072419 # number of ReadReq hits 681system.cpu.dcache.WriteReq_hits::cpu.data 31341704 # number of WriteReq hits 682system.cpu.dcache.WriteReq_hits::total 31341704 # number of WriteReq hits 683system.cpu.dcache.demand_hits::cpu.data 71414123 # number of demand (read+write) hits 684system.cpu.dcache.demand_hits::total 71414123 # number of demand (read+write) hits 685system.cpu.dcache.overall_hits::cpu.data 71414123 # number of overall hits 686system.cpu.dcache.overall_hits::total 71414123 # number of overall hits 687system.cpu.dcache.ReadReq_misses::cpu.data 2626925 # number of ReadReq misses 688system.cpu.dcache.ReadReq_misses::total 2626925 # number of ReadReq misses 689system.cpu.dcache.WriteReq_misses::cpu.data 98048 # number of WriteReq misses 690system.cpu.dcache.WriteReq_misses::total 98048 # number of WriteReq misses 691system.cpu.dcache.demand_misses::cpu.data 2724973 # number of demand (read+write) misses 692system.cpu.dcache.demand_misses::total 2724973 # number of demand (read+write) misses 693system.cpu.dcache.overall_misses::cpu.data 2724973 # number of overall misses 694system.cpu.dcache.overall_misses::total 2724973 # number of overall misses 695system.cpu.dcache.ReadReq_miss_latency::cpu.data 31341587500 # number of ReadReq miss cycles 696system.cpu.dcache.ReadReq_miss_latency::total 31341587500 # number of ReadReq miss cycles 697system.cpu.dcache.WriteReq_miss_latency::cpu.data 2106729496 # number of WriteReq miss cycles 698system.cpu.dcache.WriteReq_miss_latency::total 2106729496 # number of WriteReq miss cycles 699system.cpu.dcache.demand_miss_latency::cpu.data 33448316996 # number of demand (read+write) miss cycles 700system.cpu.dcache.demand_miss_latency::total 33448316996 # number of demand (read+write) miss cycles 701system.cpu.dcache.overall_miss_latency::cpu.data 33448316996 # number of overall miss cycles 702system.cpu.dcache.overall_miss_latency::total 33448316996 # number of overall miss cycles 703system.cpu.dcache.ReadReq_accesses::cpu.data 42699344 # number of ReadReq accesses(hits+misses) 704system.cpu.dcache.ReadReq_accesses::total 42699344 # number of ReadReq accesses(hits+misses) | 758system.cpu.dcache.replacements 2072468 # number of replacements 759system.cpu.dcache.tagsinuse 4069.997432 # Cycle average of tags in use 760system.cpu.dcache.total_refs 71397556 # Total number of references to valid blocks. 761system.cpu.dcache.sampled_refs 2076564 # Sample count of references to valid blocks. 762system.cpu.dcache.avg_refs 34.382545 # Average number of references to valid blocks. 763system.cpu.dcache.warmup_cycle 20655836000 # Cycle when the warmup percentage was hit. 764system.cpu.dcache.occ_blocks::cpu.data 4069.997432 # Average occupied blocks per requestor 765system.cpu.dcache.occ_percent::cpu.data 0.993652 # Average percentage of cache occupancy 766system.cpu.dcache.occ_percent::total 0.993652 # Average percentage of cache occupancy 767system.cpu.dcache.ReadReq_hits::cpu.data 40055849 # number of ReadReq hits 768system.cpu.dcache.ReadReq_hits::total 40055849 # number of ReadReq hits 769system.cpu.dcache.WriteReq_hits::cpu.data 31341707 # number of WriteReq hits 770system.cpu.dcache.WriteReq_hits::total 31341707 # number of WriteReq hits 771system.cpu.dcache.demand_hits::cpu.data 71397556 # number of demand (read+write) hits 772system.cpu.dcache.demand_hits::total 71397556 # number of demand (read+write) hits 773system.cpu.dcache.overall_hits::cpu.data 71397556 # number of overall hits 774system.cpu.dcache.overall_hits::total 71397556 # number of overall hits 775system.cpu.dcache.ReadReq_misses::cpu.data 2625767 # number of ReadReq misses 776system.cpu.dcache.ReadReq_misses::total 2625767 # number of ReadReq misses 777system.cpu.dcache.WriteReq_misses::cpu.data 98045 # number of WriteReq misses 778system.cpu.dcache.WriteReq_misses::total 98045 # number of WriteReq misses 779system.cpu.dcache.demand_misses::cpu.data 2723812 # number of demand (read+write) misses 780system.cpu.dcache.demand_misses::total 2723812 # number of demand (read+write) misses 781system.cpu.dcache.overall_misses::cpu.data 2723812 # number of overall misses 782system.cpu.dcache.overall_misses::total 2723812 # number of overall misses 783system.cpu.dcache.ReadReq_miss_latency::cpu.data 31384094500 # number of ReadReq miss cycles 784system.cpu.dcache.ReadReq_miss_latency::total 31384094500 # number of ReadReq miss cycles 785system.cpu.dcache.WriteReq_miss_latency::cpu.data 2663792498 # number of WriteReq miss cycles 786system.cpu.dcache.WriteReq_miss_latency::total 2663792498 # number of WriteReq miss cycles 787system.cpu.dcache.demand_miss_latency::cpu.data 34047886998 # number of demand (read+write) miss cycles 788system.cpu.dcache.demand_miss_latency::total 34047886998 # number of demand (read+write) miss cycles 789system.cpu.dcache.overall_miss_latency::cpu.data 34047886998 # number of overall miss cycles 790system.cpu.dcache.overall_miss_latency::total 34047886998 # number of overall miss cycles 791system.cpu.dcache.ReadReq_accesses::cpu.data 42681616 # number of ReadReq accesses(hits+misses) 792system.cpu.dcache.ReadReq_accesses::total 42681616 # number of ReadReq accesses(hits+misses) |
| 705system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 706system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) | 793system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 794system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) |
| 707system.cpu.dcache.demand_accesses::cpu.data 74139096 # number of demand (read+write) accesses 708system.cpu.dcache.demand_accesses::total 74139096 # number of demand (read+write) accesses 709system.cpu.dcache.overall_accesses::cpu.data 74139096 # number of overall (read+write) accesses 710system.cpu.dcache.overall_accesses::total 74139096 # number of overall (read+write) accesses 711system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061521 # miss rate for ReadReq accesses 712system.cpu.dcache.ReadReq_miss_rate::total 0.061521 # miss rate for ReadReq accesses | 795system.cpu.dcache.demand_accesses::cpu.data 74121368 # number of demand (read+write) accesses 796system.cpu.dcache.demand_accesses::total 74121368 # number of demand (read+write) accesses 797system.cpu.dcache.overall_accesses::cpu.data 74121368 # number of overall (read+write) accesses 798system.cpu.dcache.overall_accesses::total 74121368 # number of overall (read+write) accesses 799system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061520 # miss rate for ReadReq accesses 800system.cpu.dcache.ReadReq_miss_rate::total 0.061520 # miss rate for ReadReq accesses |
| 713system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses 714system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses | 801system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses 802system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses |
| 715system.cpu.dcache.demand_miss_rate::cpu.data 0.036755 # miss rate for demand accesses 716system.cpu.dcache.demand_miss_rate::total 0.036755 # miss rate for demand accesses 717system.cpu.dcache.overall_miss_rate::cpu.data 0.036755 # miss rate for overall accesses 718system.cpu.dcache.overall_miss_rate::total 0.036755 # miss rate for overall accesses 719system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.903052 # average ReadReq miss latency 720system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.903052 # average ReadReq miss latency 721system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21486.715649 # average WriteReq miss latency 722system.cpu.dcache.WriteReq_avg_miss_latency::total 21486.715649 # average WriteReq miss latency 723system.cpu.dcache.demand_avg_miss_latency::cpu.data 12274.733363 # average overall miss latency 724system.cpu.dcache.demand_avg_miss_latency::total 12274.733363 # average overall miss latency 725system.cpu.dcache.overall_avg_miss_latency::cpu.data 12274.733363 # average overall miss latency 726system.cpu.dcache.overall_avg_miss_latency::total 12274.733363 # average overall miss latency 727system.cpu.dcache.blocked_cycles::no_mshrs 32679 # number of cycles access was blocked | 803system.cpu.dcache.demand_miss_rate::cpu.data 0.036748 # miss rate for demand accesses 804system.cpu.dcache.demand_miss_rate::total 0.036748 # miss rate for demand accesses 805system.cpu.dcache.overall_miss_rate::cpu.data 0.036748 # miss rate for overall accesses 806system.cpu.dcache.overall_miss_rate::total 0.036748 # miss rate for overall accesses 807system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11952.353160 # average ReadReq miss latency 808system.cpu.dcache.ReadReq_avg_miss_latency::total 11952.353160 # average ReadReq miss latency 809system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.080504 # average WriteReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.080504 # average WriteReq miss latency 811system.cpu.dcache.demand_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency 812system.cpu.dcache.demand_avg_miss_latency::total 12500.087010 # average overall miss latency 813system.cpu.dcache.overall_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency 814system.cpu.dcache.overall_avg_miss_latency::total 12500.087010 # average overall miss latency 815system.cpu.dcache.blocked_cycles::no_mshrs 32905 # number of cycles access was blocked |
| 728system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 816system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 729system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked | 817system.cpu.dcache.blocked::no_mshrs 9507 # number of cycles access was blocked |
| 730system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 818system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 731system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.440981 # average number of cycles each access was blocked | 819system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.461134 # average number of cycles each access was blocked |
| 732system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 733system.cpu.dcache.fast_writes 0 # number of fast writes performed 734system.cpu.dcache.cache_copies 0 # number of cache copies performed | 820system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 821system.cpu.dcache.fast_writes 0 # number of fast writes performed 822system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 735system.cpu.dcache.writebacks::writebacks 2066867 # number of writebacks 736system.cpu.dcache.writebacks::total 2066867 # number of writebacks 737system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632543 # number of ReadReq MSHR hits 738system.cpu.dcache.ReadReq_mshr_hits::total 632543 # number of ReadReq MSHR hits 739system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15848 # number of WriteReq MSHR hits 740system.cpu.dcache.WriteReq_mshr_hits::total 15848 # number of WriteReq MSHR hits 741system.cpu.dcache.demand_mshr_hits::cpu.data 648391 # number of demand (read+write) MSHR hits 742system.cpu.dcache.demand_mshr_hits::total 648391 # number of demand (read+write) MSHR hits 743system.cpu.dcache.overall_mshr_hits::cpu.data 648391 # number of overall MSHR hits 744system.cpu.dcache.overall_mshr_hits::total 648391 # number of overall MSHR hits 745system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994382 # number of ReadReq MSHR misses 746system.cpu.dcache.ReadReq_mshr_misses::total 1994382 # number of ReadReq MSHR misses 747system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82200 # number of WriteReq MSHR misses 748system.cpu.dcache.WriteReq_mshr_misses::total 82200 # number of WriteReq MSHR misses 749system.cpu.dcache.demand_mshr_misses::cpu.data 2076582 # number of demand (read+write) MSHR misses 750system.cpu.dcache.demand_mshr_misses::total 2076582 # number of demand (read+write) MSHR misses 751system.cpu.dcache.overall_mshr_misses::cpu.data 2076582 # number of overall MSHR misses 752system.cpu.dcache.overall_mshr_misses::total 2076582 # number of overall MSHR misses 753system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987816500 # number of ReadReq MSHR miss cycles 754system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987816500 # number of ReadReq MSHR miss cycles 755system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833120496 # number of WriteReq MSHR miss cycles 756system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833120496 # number of WriteReq MSHR miss cycles 757system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23820936996 # number of demand (read+write) MSHR miss cycles 758system.cpu.dcache.demand_mshr_miss_latency::total 23820936996 # number of demand (read+write) MSHR miss cycles 759system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23820936996 # number of overall MSHR miss cycles 760system.cpu.dcache.overall_mshr_miss_latency::total 23820936996 # number of overall MSHR miss cycles 761system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046708 # mshr miss rate for ReadReq accesses 762system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046708 # mshr miss rate for ReadReq accesses 763system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses 764system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses 765system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028009 # mshr miss rate for demand accesses 766system.cpu.dcache.demand_mshr_miss_rate::total 0.028009 # mshr miss rate for demand accesses 767system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028009 # mshr miss rate for overall accesses 768system.cpu.dcache.overall_mshr_miss_rate::total 0.028009 # mshr miss rate for overall accesses 769system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.877130 # average ReadReq mshr miss latency 770system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.877130 # average ReadReq mshr miss latency 771system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22300.735961 # average WriteReq mshr miss latency 772system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22300.735961 # average WriteReq mshr miss latency 773system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.223865 # average overall mshr miss latency 774system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.223865 # average overall mshr miss latency 775system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.223865 # average overall mshr miss latency 776system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.223865 # average overall mshr miss latency | 823system.cpu.dcache.writebacks::writebacks 2066544 # number of writebacks 824system.cpu.dcache.writebacks::total 2066544 # number of writebacks 825system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631390 # number of ReadReq MSHR hits 826system.cpu.dcache.ReadReq_mshr_hits::total 631390 # number of ReadReq MSHR hits 827system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15856 # number of WriteReq MSHR hits 828system.cpu.dcache.WriteReq_mshr_hits::total 15856 # number of WriteReq MSHR hits 829system.cpu.dcache.demand_mshr_hits::cpu.data 647246 # number of demand (read+write) MSHR hits 830system.cpu.dcache.demand_mshr_hits::total 647246 # number of demand (read+write) MSHR hits 831system.cpu.dcache.overall_mshr_hits::cpu.data 647246 # number of overall MSHR hits 832system.cpu.dcache.overall_mshr_hits::total 647246 # number of overall MSHR hits 833system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994377 # number of ReadReq MSHR misses 834system.cpu.dcache.ReadReq_mshr_misses::total 1994377 # number of ReadReq MSHR misses 835system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82189 # number of WriteReq MSHR misses 836system.cpu.dcache.WriteReq_mshr_misses::total 82189 # number of WriteReq MSHR misses 837system.cpu.dcache.demand_mshr_misses::cpu.data 2076566 # number of demand (read+write) MSHR misses 838system.cpu.dcache.demand_mshr_misses::total 2076566 # number of demand (read+write) MSHR misses 839system.cpu.dcache.overall_mshr_misses::cpu.data 2076566 # number of overall MSHR misses 840system.cpu.dcache.overall_mshr_misses::total 2076566 # number of overall MSHR misses 841system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994900501 # number of ReadReq MSHR miss cycles 842system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994900501 # number of ReadReq MSHR miss cycles 843system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2389827998 # number of WriteReq MSHR miss cycles 844system.cpu.dcache.WriteReq_mshr_miss_latency::total 2389827998 # number of WriteReq MSHR miss cycles 845system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24384728499 # number of demand (read+write) MSHR miss cycles 846system.cpu.dcache.demand_mshr_miss_latency::total 24384728499 # number of demand (read+write) MSHR miss cycles 847system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24384728499 # number of overall MSHR miss cycles 848system.cpu.dcache.overall_mshr_miss_latency::total 24384728499 # number of overall MSHR miss cycles 849system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046727 # mshr miss rate for ReadReq accesses 850system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046727 # mshr miss rate for ReadReq accesses 851system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses 852system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses 853system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for demand accesses 854system.cpu.dcache.demand_mshr_miss_rate::total 0.028016 # mshr miss rate for demand accesses 855system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for overall accesses 856system.cpu.dcache.overall_mshr_miss_rate::total 0.028016 # mshr miss rate for overall accesses 857system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.456757 # average ReadReq mshr miss latency 858system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.456757 # average ReadReq mshr miss latency 859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29077.224422 # average WriteReq mshr miss latency 860system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29077.224422 # average WriteReq mshr miss latency 861system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency 862system.cpu.dcache.demand_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency 863system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency 864system.cpu.dcache.overall_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency |
| 777system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 778 779---------- End Simulation Statistics ---------- | 865system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 866 867---------- End Simulation Statistics ---------- |