| stats.txt (9490:e6a09d97bdc9) | stats.txt (9568:cd1351d4d850) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.066005 # Number of seconds simulated 4sim_ticks 66004575000 # Number of ticks simulated 5final_tick 66004575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.066022 # Number of seconds simulated 4sim_ticks 66021796500 # Number of ticks simulated 5final_tick 66021796500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 124260 # Simulator instruction rate (inst/s) 8host_op_rate 218802 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 51913433 # Simulator tick rate (ticks/s) 10host_mem_usage 384868 # Number of bytes of host memory used 11host_seconds 1271.44 # Real time elapsed on the host | 7host_inst_rate 92381 # Simulator instruction rate (inst/s) 8host_op_rate 162668 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38604948 # Simulator tick rate (ticks/s) 10host_mem_usage 384888 # Number of bytes of host memory used 11host_seconds 1710.19 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192463 # Number of ops (including micro ops) simulated | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192463 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1882560 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1947648 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 10816 # Number of bytes written to this memory 20system.physmem.bytes_written::total 10816 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29415 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30432 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 169 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 169 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 986113 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 28521659 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 29507773 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 986113 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 986113 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 163867 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 163867 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 163867 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 986113 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 28521659 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 29671640 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 30434 # Total number of read requests seen 38system.physmem.writeReqs 169 # Total number of write requests seen 39system.physmem.cpureqs 30604 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 1947648 # Total number of bytes read from memory 41system.physmem.bytesWritten 10816 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 1947648 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 10816 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q | 14system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1881664 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 9856 # Number of bytes written to this memory 20system.physmem.bytes_written::total 9856 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29401 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 154 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 154 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 981979 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 28500648 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 29482627 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 981979 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 981979 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 149284 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 149284 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 149284 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 981979 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 28500648 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 29631911 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 30416 # Total number of read requests seen 38system.physmem.writeReqs 154 # Total number of write requests seen 39system.physmem.cpureqs 30571 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 1946496 # Total number of bytes read from memory 41system.physmem.bytesWritten 9856 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 9856 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 46 # Number of read reqs serviced by write Q |
| 45system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis | 45system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis |
| 47system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 1972 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 1959 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 1883 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis | 47system.physmem.perBankRdReqs::1 1906 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 1973 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 1961 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 1879 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 1864 # Track reads on a per bank basis |
| 52system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis | 52system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis |
| 54system.physmem.perBankRdReqs::8 1932 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 1937 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 1891 # Track reads on a per bank basis | 54system.physmem.perBankRdReqs::8 1931 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 1939 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 1872 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 1873 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 1845 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 1890 # Track reads on a per bank basis |
| 60system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis | 60system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis |
| 61system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis | 61system.physmem.perBankRdReqs::15 1799 # Track reads on a per bank basis |
| 62system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis | 62system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis |
| 63system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis | 63system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis |
| 64system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis | 64system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis |
| 65system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis | 65system.physmem.perBankWrReqs::3 39 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 7 # Track writes on a per bank basis |
| 67system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis | 67system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis |
| 71system.physmem.perBankWrReqs::9 1 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 5 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 9 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 9 # Track writes on a per bank basis | 71system.physmem.perBankWrReqs::9 8 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 5 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 3 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 13 # Track writes on a per bank basis |
| 76system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 76system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 80system.physmem.totGap 66004558000 # Total gap between requests | 80system.physmem.totGap 66021783500 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 87system.physmem.readPktSize::6 30434 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 169 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 1 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 29835 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 405 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see | 87system.physmem.readPktSize::6 30416 # Categorize read packet sizes 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes 94system.physmem.writePktSize::6 154 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 29836 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 402 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see |
| 112system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 99system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see | 127system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see |
| 149system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see | 135system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see |
| 157system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::16 6 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see |
| 164system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 150system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 12335337 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 610214087 # Sum of mem lat for all requests 176system.physmem.totBusLat 151870000 # Total cycles spent in databus access 177system.physmem.totBankLat 446008750 # Total cycles spent in bank access 178system.physmem.avgQLat 406.11 # Average queueing delay per request 179system.physmem.avgBankLat 14683.90 # Average bank access latency per request | 159system.physmem.totQLat 12785750 # Total cycles spent in queuing delays 160system.physmem.totMemAccLat 610218250 # Sum of mem lat for all requests 161system.physmem.totBusLat 151850000 # Total cycles spent in databus access 162system.physmem.totBankLat 445582500 # Total cycles spent in bank access 163system.physmem.avgQLat 421.00 # Average queueing delay per request 164system.physmem.avgBankLat 14671.80 # Average bank access latency per request |
| 180system.physmem.avgBusLat 5000.00 # Average bus latency per request | 165system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 181system.physmem.avgMemAccLat 20090.01 # Average memory access latency 182system.physmem.avgRdBW 29.51 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 29.51 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s | 166system.physmem.avgMemAccLat 20092.80 # Average memory access latency 167system.physmem.avgRdBW 29.48 # Average achieved read bandwidth in MB/s 168system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s 169system.physmem.avgConsumedRdBW 29.48 # Average consumed read bandwidth in MB/s 170system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s |
| 186system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.23 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.01 # Average read queue length over time | 171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 172system.physmem.busUtil 0.23 # Data bus utilization in percentage 173system.physmem.avgRdQLen 0.01 # Average read queue length over time |
| 189system.physmem.avgWrQLen 1.18 # Average write queue length over time 190system.physmem.readRowHits 29113 # Number of row buffer hits during reads 191system.physmem.writeRowHits 87 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 95.85 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 51.48 # Row buffer hit rate for writes 194system.physmem.avgGap 2156800.25 # Average gap between requests 195system.cpu.branchPred.lookups 34551755 # Number of BP lookups 196system.cpu.branchPred.condPredicted 34551755 # Number of conditional branches predicted 197system.cpu.branchPred.condIncorrect 910403 # Number of conditional branches incorrect 198system.cpu.branchPred.BTBLookups 24766802 # Number of BTB lookups 199system.cpu.branchPred.BTBHits 24665055 # Number of BTB hits | 174system.physmem.avgWrQLen 1.30 # Average write queue length over time 175system.physmem.readRowHits 29116 # Number of row buffer hits during reads 176system.physmem.writeRowHits 69 # Number of row buffer hits during writes 177system.physmem.readRowHitRate 95.87 # Row buffer hit rate for reads 178system.physmem.writeRowHitRate 44.81 # Row buffer hit rate for writes 179system.physmem.avgGap 2159691.97 # Average gap between requests 180system.cpu.branchPred.lookups 34555739 # Number of BP lookups 181system.cpu.branchPred.condPredicted 34555739 # Number of conditional branches predicted 182system.cpu.branchPred.condIncorrect 911751 # Number of conditional branches incorrect 183system.cpu.branchPred.BTBLookups 24769004 # Number of BTB lookups 184system.cpu.branchPred.BTBHits 24665056 # Number of BTB hits |
| 200system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 201system.cpu.branchPred.BTBHitPct 99.589180 # BTB Hit Percentage | 186system.cpu.branchPred.BTBHitPct 99.580330 # BTB Hit Percentage |
| 202system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 203system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 204system.cpu.workload.num_syscalls 444 # Number of system calls | 187system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 188system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 189system.cpu.workload.num_syscalls 444 # Number of system calls |
| 205system.cpu.numCycles 132009151 # number of cpu cycles simulated | 190system.cpu.numCycles 132043594 # number of cpu cycles simulated |
| 206system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 207system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 191system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 192system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 208system.cpu.fetch.icacheStallCycles 26590977 # Number of cycles fetch is stalled on an Icache miss 209system.cpu.fetch.Insts 185543024 # Number of instructions fetch has processed 210system.cpu.fetch.Branches 34551755 # Number of branches that fetch encountered 211system.cpu.fetch.predictedBranches 24665055 # Number of branches that fetch has predicted taken 212system.cpu.fetch.Cycles 56499392 # Number of cycles fetch has run and was not squashing or blocked 213system.cpu.fetch.SquashCycles 6118358 # Number of cycles fetch has spent squashing 214system.cpu.fetch.BlockedCycles 43667810 # Number of cycles fetch has spent blocked 215system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 216system.cpu.fetch.PendingTrapStallCycles 138 # Number of stall cycles due to pending traps 217system.cpu.fetch.CacheLines 25944504 # Number of cache lines fetched 218system.cpu.fetch.IcacheSquashes 189453 # Number of outstanding Icache misses that were squashed 219system.cpu.fetch.rateDist::samples 131930197 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::mean 2.484743 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::stdev 3.326414 # Number of instructions fetched each cycle (Total) | 193system.cpu.fetch.icacheStallCycles 26598616 # Number of cycles fetch is stalled on an Icache miss 194system.cpu.fetch.Insts 185589305 # Number of instructions fetch has processed 195system.cpu.fetch.Branches 34555739 # Number of branches that fetch encountered 196system.cpu.fetch.predictedBranches 24665056 # Number of branches that fetch has predicted taken 197system.cpu.fetch.Cycles 56508781 # Number of cycles fetch has run and was not squashing or blocked 198system.cpu.fetch.SquashCycles 6124933 # Number of cycles fetch has spent squashing 199system.cpu.fetch.BlockedCycles 43680261 # Number of cycles fetch has spent blocked 200system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 201system.cpu.fetch.PendingTrapStallCycles 134 # Number of stall cycles due to pending traps 202system.cpu.fetch.CacheLines 25951098 # Number of cache lines fetched 203system.cpu.fetch.IcacheSquashes 190273 # Number of outstanding Icache misses that were squashed 204system.cpu.fetch.rateDist::samples 131964855 # Number of instructions fetched each cycle (Total) 205system.cpu.fetch.rateDist::mean 2.484572 # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::stdev 3.326415 # Number of instructions fetched each cycle (Total) |
| 222system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 207system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 223system.cpu.fetch.rateDist::0 77978275 59.11% 59.11% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::1 1995894 1.51% 60.62% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::2 2955143 2.24% 62.86% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::3 3921314 2.97% 65.83% # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::4 7795304 5.91% 71.74% # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::5 4757842 3.61% 75.35% # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.rateDist::6 2730359 2.07% 77.42% # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.rateDist::7 1578596 1.20% 78.61% # Number of instructions fetched each cycle (Total) 231system.cpu.fetch.rateDist::8 28217470 21.39% 100.00% # Number of instructions fetched each cycle (Total) | 208system.cpu.fetch.rateDist::0 78003722 59.11% 59.11% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::1 1996961 1.51% 60.62% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::2 2955104 2.24% 62.86% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::3 3922098 2.97% 65.83% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::4 7793741 5.91% 71.74% # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::5 4759235 3.61% 75.35% # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::6 2730671 2.07% 77.42% # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::7 1579089 1.20% 78.61% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::8 28224234 21.39% 100.00% # Number of instructions fetched each cycle (Total) |
| 232system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 233system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 217system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 235system.cpu.fetch.rateDist::total 131930197 # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.branchRate 0.261738 # Number of branch fetches per cycle 237system.cpu.fetch.rate 1.405532 # Number of inst fetches per cycle 238system.cpu.decode.IdleCycles 37427999 # Number of cycles decode is idle 239system.cpu.decode.BlockedCycles 35920173 # Number of cycles decode is blocked 240system.cpu.decode.RunCycles 44744893 # Number of cycles decode is running 241system.cpu.decode.UnblockCycles 8665277 # Number of cycles decode is unblocking 242system.cpu.decode.SquashCycles 5171855 # Number of cycles decode is squashing 243system.cpu.decode.DecodedInsts 324565548 # Number of instructions handled by decode 244system.cpu.rename.SquashCycles 5171855 # Number of cycles rename is squashing 245system.cpu.rename.IdleCycles 42969195 # Number of cycles rename is idle 246system.cpu.rename.BlockCycles 8593654 # Number of cycles rename is blocking 247system.cpu.rename.serializeStallCycles 9092 # count of cycles rename stalled for serializing inst 248system.cpu.rename.RunCycles 47590664 # Number of cycles rename is running 249system.cpu.rename.UnblockCycles 27595737 # Number of cycles rename is unblocking 250system.cpu.rename.RenamedInsts 320190802 # Number of instructions processed by rename 251system.cpu.rename.ROBFullEvents 211 # Number of times rename has blocked due to ROB full 252system.cpu.rename.IQFullEvents 56984 # Number of times rename has blocked due to IQ full 253system.cpu.rename.LSQFullEvents 25724332 # Number of times rename has blocked due to LSQ full 254system.cpu.rename.FullRegisterEvents 365 # Number of times there has been no free registers 255system.cpu.rename.RenamedOperands 322194206 # Number of destination operands rename has renamed 256system.cpu.rename.RenameLookups 849198017 # Number of register rename lookups that rename has made 257system.cpu.rename.int_rename_lookups 849196232 # Number of integer rename lookups 258system.cpu.rename.fp_rename_lookups 1785 # Number of floating rename lookups | 220system.cpu.fetch.rateDist::total 131964855 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.branchRate 0.261699 # Number of branch fetches per cycle 222system.cpu.fetch.rate 1.405515 # Number of inst fetches per cycle 223system.cpu.decode.IdleCycles 37438024 # Number of cycles decode is idle 224system.cpu.decode.BlockedCycles 35931161 # Number of cycles decode is blocked 225system.cpu.decode.RunCycles 44761152 # Number of cycles decode is running 226system.cpu.decode.UnblockCycles 8657481 # Number of cycles decode is unblocking 227system.cpu.decode.SquashCycles 5177037 # Number of cycles decode is squashing 228system.cpu.decode.DecodedInsts 324625052 # Number of instructions handled by decode 229system.cpu.rename.SquashCycles 5177037 # Number of cycles rename is squashing 230system.cpu.rename.IdleCycles 42998776 # Number of cycles rename is idle 231system.cpu.rename.BlockCycles 8560534 # Number of cycles rename is blocking 232system.cpu.rename.serializeStallCycles 9611 # count of cycles rename stalled for serializing inst 233system.cpu.rename.RunCycles 47593573 # Number of cycles rename is running 234system.cpu.rename.UnblockCycles 27625324 # Number of cycles rename is unblocking 235system.cpu.rename.RenamedInsts 320243292 # Number of instructions processed by rename 236system.cpu.rename.ROBFullEvents 235 # Number of times rename has blocked due to ROB full 237system.cpu.rename.IQFullEvents 57194 # Number of times rename has blocked due to IQ full 238system.cpu.rename.LSQFullEvents 25761475 # Number of times rename has blocked due to LSQ full 239system.cpu.rename.FullRegisterEvents 370 # Number of times there has been no free registers 240system.cpu.rename.RenamedOperands 322250586 # Number of destination operands rename has renamed 241system.cpu.rename.RenameLookups 849328812 # Number of register rename lookups that rename has made 242system.cpu.rename.int_rename_lookups 849326947 # Number of integer rename lookups 243system.cpu.rename.fp_rename_lookups 1865 # Number of floating rename lookups |
| 259system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed | 244system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed |
| 260system.cpu.rename.UndoneMaps 42981461 # Number of HB maps that are undone due to squashing | 245system.cpu.rename.UndoneMaps 43037841 # Number of HB maps that are undone due to squashing |
| 261system.cpu.rename.serializingInsts 469 # count of serializing insts renamed 262system.cpu.rename.tempSerializingInsts 463 # count of temporary serializing insts renamed | 246system.cpu.rename.serializingInsts 469 # count of serializing insts renamed 247system.cpu.rename.tempSerializingInsts 463 # count of temporary serializing insts renamed |
| 263system.cpu.rename.skidInsts 62356862 # count of insts added to the skid buffer 264system.cpu.memDep0.insertedLoads 102568377 # Number of loads inserted to the mem dependence unit. 265system.cpu.memDep0.insertedStores 35231338 # Number of stores inserted to the mem dependence unit. 266system.cpu.memDep0.conflictingLoads 39589479 # Number of conflicting loads. 267system.cpu.memDep0.conflictingStores 6005074 # Number of conflicting stores. 268system.cpu.iq.iqInstsAdded 315870239 # Number of instructions added to the IQ (excludes non-spec) 269system.cpu.iq.iqNonSpecInstsAdded 1674 # Number of non-speculative instructions added to the IQ 270system.cpu.iq.iqInstsIssued 302163622 # Number of instructions issued 271system.cpu.iq.iqSquashedInstsIssued 115310 # Number of squashed instructions issued 272system.cpu.iq.iqSquashedInstsExamined 37046058 # Number of squashed instructions iterated over during squash; mainly for profiling 273system.cpu.iq.iqSquashedOperandsExamined 54286160 # Number of squashed operands that are examined and possibly removed from graph 274system.cpu.iq.iqSquashedNonSpecRemoved 1229 # Number of squashed non-spec instructions that were removed 275system.cpu.iq.issued_per_cycle::samples 131930197 # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::mean 2.290329 # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::stdev 1.700150 # Number of insts issued each cycle | 248system.cpu.rename.skidInsts 62395647 # count of insts added to the skid buffer 249system.cpu.memDep0.insertedLoads 102574673 # Number of loads inserted to the mem dependence unit. 250system.cpu.memDep0.insertedStores 35240496 # Number of stores inserted to the mem dependence unit. 251system.cpu.memDep0.conflictingLoads 39587079 # Number of conflicting loads. 252system.cpu.memDep0.conflictingStores 6070451 # Number of conflicting stores. 253system.cpu.iq.iqInstsAdded 315904307 # Number of instructions added to the IQ (excludes non-spec) 254system.cpu.iq.iqNonSpecInstsAdded 1659 # Number of non-speculative instructions added to the IQ 255system.cpu.iq.iqInstsIssued 302190238 # Number of instructions issued 256system.cpu.iq.iqSquashedInstsIssued 114769 # Number of squashed instructions issued 257system.cpu.iq.iqSquashedInstsExamined 37077809 # Number of squashed instructions iterated over during squash; mainly for profiling 258system.cpu.iq.iqSquashedOperandsExamined 54333314 # Number of squashed operands that are examined and possibly removed from graph 259system.cpu.iq.iqSquashedNonSpecRemoved 1214 # Number of squashed non-spec instructions that were removed 260system.cpu.iq.issued_per_cycle::samples 131964855 # Number of insts issued each cycle 261system.cpu.iq.issued_per_cycle::mean 2.289930 # Number of insts issued each cycle 262system.cpu.iq.issued_per_cycle::stdev 1.700500 # Number of insts issued each cycle |
| 278system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 263system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 279system.cpu.iq.issued_per_cycle::0 24515615 18.58% 18.58% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::1 23292289 17.66% 36.24% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::2 25896464 19.63% 55.87% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::3 25797972 19.55% 75.42% # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::4 18916380 14.34% 89.76% # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::5 8292938 6.29% 96.04% # Number of insts issued each cycle 285system.cpu.iq.issued_per_cycle::6 4139203 3.14% 99.18% # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::7 915627 0.69% 99.88% # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::8 163709 0.12% 100.00% # Number of insts issued each cycle | 264system.cpu.iq.issued_per_cycle::0 24574614 18.62% 18.62% # Number of insts issued each cycle 265system.cpu.iq.issued_per_cycle::1 23238985 17.61% 36.23% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::2 25913680 19.64% 55.87% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::3 25803819 19.55% 75.42% # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::4 18917522 14.34% 89.76% # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::5 8297062 6.29% 96.05% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::6 4140134 3.14% 99.18% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::7 916078 0.69% 99.88% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::8 162961 0.12% 100.00% # Number of insts issued each cycle |
| 288system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 289system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 290system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 273system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 291system.cpu.iq.issued_per_cycle::total 131930197 # Number of insts issued each cycle | 276system.cpu.iq.issued_per_cycle::total 131964855 # Number of insts issued each cycle |
| 292system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 277system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 293system.cpu.iq.fu_full::IntAlu 38493 1.98% 1.98% # attempts to use FU when none available 294system.cpu.iq.fu_full::IntMult 0 0.00% 1.98% # attempts to use FU when none available 295system.cpu.iq.fu_full::IntDiv 0 0.00% 1.98% # attempts to use FU when none available 296system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available 297system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available 298system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available 299system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available 300system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available 301system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available 321system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available 322system.cpu.iq.fu_full::MemRead 1820587 93.51% 95.49% # attempts to use FU when none available 323system.cpu.iq.fu_full::MemWrite 87813 4.51% 100.00% # attempts to use FU when none available | 278system.cpu.iq.fu_full::IntAlu 38351 1.96% 1.96% # attempts to use FU when none available 279system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available 280system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available 281system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available 282system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available 283system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available 284system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available 285system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available 286system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available 287system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available 288system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available 307system.cpu.iq.fu_full::MemRead 1834339 93.53% 95.49% # attempts to use FU when none available 308system.cpu.iq.fu_full::MemWrite 88449 4.51% 100.00% # attempts to use FU when none available |
| 324system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 325system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 326system.cpu.iq.FU_type_0::No_OpClass 31282 0.01% 0.01% # Type of FU issued | 309system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 310system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 311system.cpu.iq.FU_type_0::No_OpClass 31282 0.01% 0.01% # Type of FU issued |
| 327system.cpu.iq.FU_type_0::IntAlu 171146899 56.64% 56.65% # Type of FU issued | 312system.cpu.iq.FU_type_0::IntAlu 171161474 56.64% 56.65% # Type of FU issued |
| 328system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued 329system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued | 313system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued 314system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued |
| 330system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued | 315system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.65% # Type of FU issued |
| 331system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued 332system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued 333system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued 334system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.65% # Type of FU issued 335system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.65% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.65% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.65% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.65% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 348system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.65% # Type of FU issued 349system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.65% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.65% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.65% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Type of FU issued 353system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued 354system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued 355system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued | 316system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued 317system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued 318system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued 319system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.65% # Type of FU issued 320system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.65% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.65% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.65% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.65% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 333system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.65% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.65% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.65% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.65% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued |
| 356system.cpu.iq.FU_type_0::MemRead 97755630 32.35% 89.00% # Type of FU issued 357system.cpu.iq.FU_type_0::MemWrite 33229776 11.00% 100.00% # Type of FU issued | 341system.cpu.iq.FU_type_0::MemRead 97761295 32.35% 89.00% # Type of FU issued 342system.cpu.iq.FU_type_0::MemWrite 33236158 11.00% 100.00% # Type of FU issued |
| 358system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 359system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 343system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 344system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 360system.cpu.iq.FU_type_0::total 302163622 # Type of FU issued 361system.cpu.iq.rate 2.288960 # Inst issue rate 362system.cpu.iq.fu_busy_cnt 1946893 # FU busy when requested 363system.cpu.iq.fu_busy_rate 0.006443 # FU busy rate (busy events/executed inst) 364system.cpu.iq.int_inst_queue_reads 738319072 # Number of integer instruction queue reads 365system.cpu.iq.int_inst_queue_writes 352950108 # Number of integer instruction queue writes 366system.cpu.iq.int_inst_queue_wakeup_accesses 299522625 # Number of integer instruction queue wakeup accesses 367system.cpu.iq.fp_inst_queue_reads 572 # Number of floating instruction queue reads 368system.cpu.iq.fp_inst_queue_writes 867 # Number of floating instruction queue writes 369system.cpu.iq.fp_inst_queue_wakeup_accesses 162 # Number of floating instruction queue wakeup accesses 370system.cpu.iq.int_alu_accesses 304078975 # Number of integer alu accesses 371system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses 372system.cpu.iew.lsq.thread0.forwLoads 53992768 # Number of loads that had data forwarded from stores | 345system.cpu.iq.FU_type_0::total 302190238 # Type of FU issued 346system.cpu.iq.rate 2.288564 # Inst issue rate 347system.cpu.iq.fu_busy_cnt 1961139 # FU busy when requested 348system.cpu.iq.fu_busy_rate 0.006490 # FU busy rate (busy events/executed inst) 349system.cpu.iq.int_inst_queue_reads 738420696 # Number of integer instruction queue reads 350system.cpu.iq.int_inst_queue_writes 353016005 # Number of integer instruction queue writes 351system.cpu.iq.int_inst_queue_wakeup_accesses 299545946 # Number of integer instruction queue wakeup accesses 352system.cpu.iq.fp_inst_queue_reads 543 # Number of floating instruction queue reads 353system.cpu.iq.fp_inst_queue_writes 861 # Number of floating instruction queue writes 354system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses 355system.cpu.iq.int_alu_accesses 304119846 # Number of integer alu accesses 356system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses 357system.cpu.iew.lsq.thread0.forwLoads 53994204 # Number of loads that had data forwarded from stores |
| 373system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 358system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 374system.cpu.iew.lsq.thread0.squashedLoads 11788993 # Number of loads squashed 375system.cpu.iew.lsq.thread0.ignoredResponses 26852 # Number of memory responses ignored because the instruction is squashed 376system.cpu.iew.lsq.thread0.memOrderViolation 33996 # Number of memory ordering violations 377system.cpu.iew.lsq.thread0.squashedStores 3791586 # Number of stores squashed | 359system.cpu.iew.lsq.thread0.squashedLoads 11795289 # Number of loads squashed 360system.cpu.iew.lsq.thread0.ignoredResponses 26124 # Number of memory responses ignored because the instruction is squashed 361system.cpu.iew.lsq.thread0.memOrderViolation 34117 # Number of memory ordering violations 362system.cpu.iew.lsq.thread0.squashedStores 3800744 # Number of stores squashed |
| 378system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 379system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 363system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 364system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 380system.cpu.iew.lsq.thread0.rescheduledLoads 3239 # Number of loads that were rescheduled 381system.cpu.iew.lsq.thread0.cacheBlocked 8506 # Number of times an access to memory failed due to the cache being blocked | 365system.cpu.iew.lsq.thread0.rescheduledLoads 3243 # Number of loads that were rescheduled 366system.cpu.iew.lsq.thread0.cacheBlocked 8488 # Number of times an access to memory failed due to the cache being blocked |
| 382system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 367system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 383system.cpu.iew.iewSquashCycles 5171855 # Number of cycles IEW is squashing 384system.cpu.iew.iewBlockCycles 1763635 # Number of cycles IEW is blocking 385system.cpu.iew.iewUnblockCycles 159728 # Number of cycles IEW is unblocking 386system.cpu.iew.iewDispatchedInsts 315871913 # Number of instructions dispatched to IQ 387system.cpu.iew.iewDispSquashedInsts 195728 # Number of squashed instructions skipped by dispatch 388system.cpu.iew.iewDispLoadInsts 102568377 # Number of dispatched load instructions 389system.cpu.iew.iewDispStoreInsts 35231338 # Number of dispatched store instructions | 368system.cpu.iew.iewSquashCycles 5177037 # Number of cycles IEW is squashing 369system.cpu.iew.iewBlockCycles 1758271 # Number of cycles IEW is blocking 370system.cpu.iew.iewUnblockCycles 159446 # Number of cycles IEW is unblocking 371system.cpu.iew.iewDispatchedInsts 315905966 # Number of instructions dispatched to IQ 372system.cpu.iew.iewDispSquashedInsts 197291 # Number of squashed instructions skipped by dispatch 373system.cpu.iew.iewDispLoadInsts 102574673 # Number of dispatched load instructions 374system.cpu.iew.iewDispStoreInsts 35240496 # Number of dispatched store instructions |
| 390system.cpu.iew.iewDispNonSpecInsts 464 # Number of dispatched non-speculative instructions | 375system.cpu.iew.iewDispNonSpecInsts 464 # Number of dispatched non-speculative instructions |
| 391system.cpu.iew.iewIQFullEvents 3188 # Number of times the IQ has become full, causing a stall 392system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall 393system.cpu.iew.memOrderViolationEvents 33996 # Number of memory order violations 394system.cpu.iew.predictedTakenIncorrect 522451 # Number of branches that were predicted taken incorrectly 395system.cpu.iew.predictedNotTakenIncorrect 444817 # Number of branches that were predicted not taken incorrectly 396system.cpu.iew.branchMispredicts 967268 # Number of branch mispredicts detected at execute 397system.cpu.iew.iewExecutedInsts 300543939 # Number of executed instructions 398system.cpu.iew.iewExecLoadInsts 97286160 # Number of load instructions executed 399system.cpu.iew.iewExecSquashedInsts 1619683 # Number of squashed instructions skipped in execute | 376system.cpu.iew.iewIQFullEvents 3186 # Number of times the IQ has become full, causing a stall 377system.cpu.iew.iewLSQFullEvents 73305 # Number of times the LSQ has become full, causing a stall 378system.cpu.iew.memOrderViolationEvents 34117 # Number of memory order violations 379system.cpu.iew.predictedTakenIncorrect 522582 # Number of branches that were predicted taken incorrectly 380system.cpu.iew.predictedNotTakenIncorrect 446237 # Number of branches that were predicted not taken incorrectly 381system.cpu.iew.branchMispredicts 968819 # Number of branch mispredicts detected at execute 382system.cpu.iew.iewExecutedInsts 300569422 # Number of executed instructions 383system.cpu.iew.iewExecLoadInsts 97293064 # Number of load instructions executed 384system.cpu.iew.iewExecSquashedInsts 1620816 # Number of squashed instructions skipped in execute |
| 400system.cpu.iew.exec_swp 0 # number of swp insts executed 401system.cpu.iew.exec_nop 0 # number of nop insts executed | 385system.cpu.iew.exec_swp 0 # number of swp insts executed 386system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 402system.cpu.iew.exec_refs 130298049 # number of memory reference insts executed 403system.cpu.iew.exec_branches 30887567 # Number of branches executed 404system.cpu.iew.exec_stores 33011889 # Number of stores executed 405system.cpu.iew.exec_rate 2.276690 # Inst execution rate 406system.cpu.iew.wb_sent 299950982 # cumulative count of insts sent to commit 407system.cpu.iew.wb_count 299522787 # cumulative count of insts written-back 408system.cpu.iew.wb_producers 219513248 # num instructions producing a value 409system.cpu.iew.wb_consumers 298024509 # num instructions consuming a value | 387system.cpu.iew.exec_refs 130310023 # number of memory reference insts executed 388system.cpu.iew.exec_branches 30888402 # Number of branches executed 389system.cpu.iew.exec_stores 33016959 # Number of stores executed 390system.cpu.iew.exec_rate 2.276289 # Inst execution rate 391system.cpu.iew.wb_sent 299975987 # cumulative count of insts sent to commit 392system.cpu.iew.wb_count 299546100 # cumulative count of insts written-back 393system.cpu.iew.wb_producers 219510783 # num instructions producing a value 394system.cpu.iew.wb_consumers 298009836 # num instructions consuming a value |
| 410system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 395system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 411system.cpu.iew.wb_rate 2.268955 # insts written-back per cycle 412system.cpu.iew.wb_fanout 0.736561 # average fanout of values written-back | 396system.cpu.iew.wb_rate 2.268539 # insts written-back per cycle 397system.cpu.iew.wb_fanout 0.736589 # average fanout of values written-back |
| 413system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 398system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 414system.cpu.commit.commitSquashedInsts 37692291 # The number of squashed insts skipped by commit | 399system.cpu.commit.commitSquashedInsts 37726716 # The number of squashed insts skipped by commit |
| 415system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards | 400system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards |
| 416system.cpu.commit.branchMispredicts 910422 # The number of times a branch was mispredicted 417system.cpu.commit.committed_per_cycle::samples 126758342 # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::mean 2.194668 # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::stdev 2.965617 # Number of insts commited each cycle | 401system.cpu.commit.branchMispredicts 911770 # The number of times a branch was mispredicted 402system.cpu.commit.committed_per_cycle::samples 126787818 # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::mean 2.194158 # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::stdev 2.965410 # Number of insts commited each cycle |
| 420system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 405system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 421system.cpu.commit.committed_per_cycle::0 58200495 45.91% 45.91% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::1 19281721 15.21% 61.13% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::2 11800672 9.31% 70.44% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::3 9590531 7.57% 78.00% # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::4 1751465 1.38% 79.38% # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::5 2073903 1.64% 81.02% # Number of insts commited each cycle 427system.cpu.commit.committed_per_cycle::6 1296843 1.02% 82.04% # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::7 720324 0.57% 82.61% # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::8 22042388 17.39% 100.00% # Number of insts commited each cycle | 406system.cpu.commit.committed_per_cycle::0 58221604 45.92% 45.92% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::1 19287083 15.21% 61.13% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::2 11808302 9.31% 70.45% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::3 9592177 7.57% 78.01% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::4 1746716 1.38% 79.39% # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::5 2074829 1.64% 81.03% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::6 1294024 1.02% 82.05% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::7 717572 0.57% 82.61% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::8 22045511 17.39% 100.00% # Number of insts commited each cycle |
| 430system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 431system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 432system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 415system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 433system.cpu.commit.committed_per_cycle::total 126758342 # Number of insts commited each cycle | 418system.cpu.commit.committed_per_cycle::total 126787818 # Number of insts commited each cycle |
| 434system.cpu.commit.committedInsts 157988547 # Number of instructions committed 435system.cpu.commit.committedOps 278192463 # Number of ops (including micro ops) committed 436system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 437system.cpu.commit.refs 122219136 # Number of memory references committed 438system.cpu.commit.loads 90779384 # Number of loads committed 439system.cpu.commit.membars 0 # Number of memory barriers committed 440system.cpu.commit.branches 29309705 # Number of branches committed 441system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 442system.cpu.commit.int_insts 278186172 # Number of committed integer instructions. 443system.cpu.commit.function_calls 0 # Number of function calls committed. | 419system.cpu.commit.committedInsts 157988547 # Number of instructions committed 420system.cpu.commit.committedOps 278192463 # Number of ops (including micro ops) committed 421system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 422system.cpu.commit.refs 122219136 # Number of memory references committed 423system.cpu.commit.loads 90779384 # Number of loads committed 424system.cpu.commit.membars 0 # Number of memory barriers committed 425system.cpu.commit.branches 29309705 # Number of branches committed 426system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 427system.cpu.commit.int_insts 278186172 # Number of committed integer instructions. 428system.cpu.commit.function_calls 0 # Number of function calls committed. |
| 444system.cpu.commit.bw_lim_events 22042388 # number cycles where commit BW limit reached | 429system.cpu.commit.bw_lim_events 22045511 # number cycles where commit BW limit reached |
| 445system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 430system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 446system.cpu.rob.rob_reads 420600708 # The number of ROB reads 447system.cpu.rob.rob_writes 636946432 # The number of ROB writes 448system.cpu.timesIdled 13762 # Number of times that the entire CPU went into an idle state and unscheduled itself 449system.cpu.idleCycles 78954 # Total number of cycles that the CPU has spent unscheduled due to idling | 431system.cpu.rob.rob_reads 420661486 # The number of ROB reads 432system.cpu.rob.rob_writes 637020452 # The number of ROB writes 433system.cpu.timesIdled 13945 # Number of times that the entire CPU went into an idle state and unscheduled itself 434system.cpu.idleCycles 78739 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 450system.cpu.committedInsts 157988547 # Number of Instructions Simulated 451system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated 452system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated | 435system.cpu.committedInsts 157988547 # Number of Instructions Simulated 436system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated 437system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated |
| 453system.cpu.cpi 0.835562 # CPI: Cycles Per Instruction 454system.cpu.cpi_total 0.835562 # CPI: Total CPI of All Threads 455system.cpu.ipc 1.196800 # IPC: Instructions Per Cycle 456system.cpu.ipc_total 1.196800 # IPC: Total IPC of All Threads 457system.cpu.int_regfile_reads 592847791 # number of integer regfile reads 458system.cpu.int_regfile_writes 300194164 # number of integer regfile writes 459system.cpu.fp_regfile_reads 150 # number of floating regfile reads 460system.cpu.fp_regfile_writes 76 # number of floating regfile writes 461system.cpu.misc_regfile_reads 192689354 # number of misc regfile reads 462system.cpu.icache.replacements 61 # number of replacements 463system.cpu.icache.tagsinuse 835.847711 # Cycle average of tags in use 464system.cpu.icache.total_refs 25943160 # Total number of references to valid blocks. 465system.cpu.icache.sampled_refs 1033 # Sample count of references to valid blocks. 466system.cpu.icache.avg_refs 25114.385286 # Average number of references to valid blocks. | 438system.cpu.cpi 0.835780 # CPI: Cycles Per Instruction 439system.cpu.cpi_total 0.835780 # CPI: Total CPI of All Threads 440system.cpu.ipc 1.196488 # IPC: Instructions Per Cycle 441system.cpu.ipc_total 1.196488 # IPC: Total IPC of All Threads 442system.cpu.int_regfile_reads 592874208 # number of integer regfile reads 443system.cpu.int_regfile_writes 300213863 # number of integer regfile writes 444system.cpu.fp_regfile_reads 139 # number of floating regfile reads 445system.cpu.fp_regfile_writes 70 # number of floating regfile writes 446system.cpu.misc_regfile_reads 192707426 # number of misc regfile reads 447system.cpu.icache.replacements 62 # number of replacements 448system.cpu.icache.tagsinuse 835.762840 # Cycle average of tags in use 449system.cpu.icache.total_refs 25949757 # Total number of references to valid blocks. 450system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks. 451system.cpu.icache.avg_refs 25218.422741 # Average number of references to valid blocks. |
| 467system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 452system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 468system.cpu.icache.occ_blocks::cpu.inst 835.847711 # Average occupied blocks per requestor 469system.cpu.icache.occ_percent::cpu.inst 0.408129 # Average percentage of cache occupancy 470system.cpu.icache.occ_percent::total 0.408129 # Average percentage of cache occupancy 471system.cpu.icache.ReadReq_hits::cpu.inst 25943160 # number of ReadReq hits 472system.cpu.icache.ReadReq_hits::total 25943160 # number of ReadReq hits 473system.cpu.icache.demand_hits::cpu.inst 25943160 # number of demand (read+write) hits 474system.cpu.icache.demand_hits::total 25943160 # number of demand (read+write) hits 475system.cpu.icache.overall_hits::cpu.inst 25943160 # number of overall hits 476system.cpu.icache.overall_hits::total 25943160 # number of overall hits 477system.cpu.icache.ReadReq_misses::cpu.inst 1344 # number of ReadReq misses 478system.cpu.icache.ReadReq_misses::total 1344 # number of ReadReq misses 479system.cpu.icache.demand_misses::cpu.inst 1344 # number of demand (read+write) misses 480system.cpu.icache.demand_misses::total 1344 # number of demand (read+write) misses 481system.cpu.icache.overall_misses::cpu.inst 1344 # number of overall misses 482system.cpu.icache.overall_misses::total 1344 # number of overall misses 483system.cpu.icache.ReadReq_miss_latency::cpu.inst 65684000 # number of ReadReq miss cycles 484system.cpu.icache.ReadReq_miss_latency::total 65684000 # number of ReadReq miss cycles 485system.cpu.icache.demand_miss_latency::cpu.inst 65684000 # number of demand (read+write) miss cycles 486system.cpu.icache.demand_miss_latency::total 65684000 # number of demand (read+write) miss cycles 487system.cpu.icache.overall_miss_latency::cpu.inst 65684000 # number of overall miss cycles 488system.cpu.icache.overall_miss_latency::total 65684000 # number of overall miss cycles 489system.cpu.icache.ReadReq_accesses::cpu.inst 25944504 # number of ReadReq accesses(hits+misses) 490system.cpu.icache.ReadReq_accesses::total 25944504 # number of ReadReq accesses(hits+misses) 491system.cpu.icache.demand_accesses::cpu.inst 25944504 # number of demand (read+write) accesses 492system.cpu.icache.demand_accesses::total 25944504 # number of demand (read+write) accesses 493system.cpu.icache.overall_accesses::cpu.inst 25944504 # number of overall (read+write) accesses 494system.cpu.icache.overall_accesses::total 25944504 # number of overall (read+write) accesses | 453system.cpu.icache.occ_blocks::cpu.inst 835.762840 # Average occupied blocks per requestor 454system.cpu.icache.occ_percent::cpu.inst 0.408087 # Average percentage of cache occupancy 455system.cpu.icache.occ_percent::total 0.408087 # Average percentage of cache occupancy 456system.cpu.icache.ReadReq_hits::cpu.inst 25949757 # number of ReadReq hits 457system.cpu.icache.ReadReq_hits::total 25949757 # number of ReadReq hits 458system.cpu.icache.demand_hits::cpu.inst 25949757 # number of demand (read+write) hits 459system.cpu.icache.demand_hits::total 25949757 # number of demand (read+write) hits 460system.cpu.icache.overall_hits::cpu.inst 25949757 # number of overall hits 461system.cpu.icache.overall_hits::total 25949757 # number of overall hits 462system.cpu.icache.ReadReq_misses::cpu.inst 1341 # number of ReadReq misses 463system.cpu.icache.ReadReq_misses::total 1341 # number of ReadReq misses 464system.cpu.icache.demand_misses::cpu.inst 1341 # number of demand (read+write) misses 465system.cpu.icache.demand_misses::total 1341 # number of demand (read+write) misses 466system.cpu.icache.overall_misses::cpu.inst 1341 # number of overall misses 467system.cpu.icache.overall_misses::total 1341 # number of overall misses 468system.cpu.icache.ReadReq_miss_latency::cpu.inst 65663000 # number of ReadReq miss cycles 469system.cpu.icache.ReadReq_miss_latency::total 65663000 # number of ReadReq miss cycles 470system.cpu.icache.demand_miss_latency::cpu.inst 65663000 # number of demand (read+write) miss cycles 471system.cpu.icache.demand_miss_latency::total 65663000 # number of demand (read+write) miss cycles 472system.cpu.icache.overall_miss_latency::cpu.inst 65663000 # number of overall miss cycles 473system.cpu.icache.overall_miss_latency::total 65663000 # number of overall miss cycles 474system.cpu.icache.ReadReq_accesses::cpu.inst 25951098 # number of ReadReq accesses(hits+misses) 475system.cpu.icache.ReadReq_accesses::total 25951098 # number of ReadReq accesses(hits+misses) 476system.cpu.icache.demand_accesses::cpu.inst 25951098 # number of demand (read+write) accesses 477system.cpu.icache.demand_accesses::total 25951098 # number of demand (read+write) accesses 478system.cpu.icache.overall_accesses::cpu.inst 25951098 # number of overall (read+write) accesses 479system.cpu.icache.overall_accesses::total 25951098 # number of overall (read+write) accesses |
| 495system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses 496system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses 497system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses 498system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses 499system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses 500system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses | 480system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses 481system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses 482system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses 483system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses 484system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses 485system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses |
| 501system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48872.023810 # average ReadReq miss latency 502system.cpu.icache.ReadReq_avg_miss_latency::total 48872.023810 # average ReadReq miss latency 503system.cpu.icache.demand_avg_miss_latency::cpu.inst 48872.023810 # average overall miss latency 504system.cpu.icache.demand_avg_miss_latency::total 48872.023810 # average overall miss latency 505system.cpu.icache.overall_avg_miss_latency::cpu.inst 48872.023810 # average overall miss latency 506system.cpu.icache.overall_avg_miss_latency::total 48872.023810 # average overall miss latency | 486system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48965.697241 # average ReadReq miss latency 487system.cpu.icache.ReadReq_avg_miss_latency::total 48965.697241 # average ReadReq miss latency 488system.cpu.icache.demand_avg_miss_latency::cpu.inst 48965.697241 # average overall miss latency 489system.cpu.icache.demand_avg_miss_latency::total 48965.697241 # average overall miss latency 490system.cpu.icache.overall_avg_miss_latency::cpu.inst 48965.697241 # average overall miss latency 491system.cpu.icache.overall_avg_miss_latency::total 48965.697241 # average overall miss latency |
| 507system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked 508system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 509system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 510system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 511system.cpu.icache.avg_blocked_cycles::no_mshrs 26.600000 # average number of cycles each access was blocked 512system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 513system.cpu.icache.fast_writes 0 # number of fast writes performed 514system.cpu.icache.cache_copies 0 # number of cache copies performed | 492system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked 493system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 494system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 495system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 496system.cpu.icache.avg_blocked_cycles::no_mshrs 26.600000 # average number of cycles each access was blocked 497system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 498system.cpu.icache.fast_writes 0 # number of fast writes performed 499system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 515system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits 516system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits 517system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits 518system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits 519system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits 520system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits 521system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1034 # number of ReadReq MSHR misses 522system.cpu.icache.ReadReq_mshr_misses::total 1034 # number of ReadReq MSHR misses 523system.cpu.icache.demand_mshr_misses::cpu.inst 1034 # number of demand (read+write) MSHR misses 524system.cpu.icache.demand_mshr_misses::total 1034 # number of demand (read+write) MSHR misses 525system.cpu.icache.overall_mshr_misses::cpu.inst 1034 # number of overall MSHR misses 526system.cpu.icache.overall_mshr_misses::total 1034 # number of overall MSHR misses 527system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51833500 # number of ReadReq MSHR miss cycles 528system.cpu.icache.ReadReq_mshr_miss_latency::total 51833500 # number of ReadReq MSHR miss cycles 529system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51833500 # number of demand (read+write) MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::total 51833500 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51833500 # number of overall MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::total 51833500 # number of overall MSHR miss cycles | 500system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits 501system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits 502system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits 503system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits 504system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits 505system.cpu.icache.overall_mshr_hits::total 311 # number of overall MSHR hits 506system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses 507system.cpu.icache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses 508system.cpu.icache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses 509system.cpu.icache.demand_mshr_misses::total 1030 # number of demand (read+write) MSHR misses 510system.cpu.icache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses 511system.cpu.icache.overall_mshr_misses::total 1030 # number of overall MSHR misses 512system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51831000 # number of ReadReq MSHR miss cycles 513system.cpu.icache.ReadReq_mshr_miss_latency::total 51831000 # number of ReadReq MSHR miss cycles 514system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51831000 # number of demand (read+write) MSHR miss cycles 515system.cpu.icache.demand_mshr_miss_latency::total 51831000 # number of demand (read+write) MSHR miss cycles 516system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51831000 # number of overall MSHR miss cycles 517system.cpu.icache.overall_mshr_miss_latency::total 51831000 # number of overall MSHR miss cycles |
| 533system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 534system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 535system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 536system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 537system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 538system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 518system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 519system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 520system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 521system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 522system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 523system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 539system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50129.110251 # average ReadReq mshr miss latency 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50129.110251 # average ReadReq mshr miss latency 541system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50129.110251 # average overall mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::total 50129.110251 # average overall mshr miss latency 543system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50129.110251 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::total 50129.110251 # average overall mshr miss latency | 524system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50321.359223 # average ReadReq mshr miss latency 525system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50321.359223 # average ReadReq mshr miss latency 526system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50321.359223 # average overall mshr miss latency 527system.cpu.icache.demand_avg_mshr_miss_latency::total 50321.359223 # average overall mshr miss latency 528system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50321.359223 # average overall mshr miss latency 529system.cpu.icache.overall_avg_mshr_miss_latency::total 50321.359223 # average overall mshr miss latency |
| 545system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 530system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 546system.cpu.l2cache.replacements 480 # number of replacements 547system.cpu.l2cache.tagsinuse 20802.892196 # Cycle average of tags in use 548system.cpu.l2cache.total_refs 4028440 # Total number of references to valid blocks. 549system.cpu.l2cache.sampled_refs 30411 # Sample count of references to valid blocks. 550system.cpu.l2cache.avg_refs 132.466542 # Average number of references to valid blocks. | 531system.cpu.l2cache.replacements 462 # number of replacements 532system.cpu.l2cache.tagsinuse 20805.290602 # Cycle average of tags in use 533system.cpu.l2cache.total_refs 4028325 # Total number of references to valid blocks. 534system.cpu.l2cache.sampled_refs 30393 # Sample count of references to valid blocks. 535system.cpu.l2cache.avg_refs 132.541210 # Average number of references to valid blocks. |
| 551system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 536system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 552system.cpu.l2cache.occ_blocks::writebacks 19867.143947 # Average occupied blocks per requestor 553system.cpu.l2cache.occ_blocks::cpu.inst 689.298857 # Average occupied blocks per requestor 554system.cpu.l2cache.occ_blocks::cpu.data 246.449393 # Average occupied blocks per requestor 555system.cpu.l2cache.occ_percent::writebacks 0.606297 # Average percentage of cache occupancy 556system.cpu.l2cache.occ_percent::cpu.inst 0.021036 # Average percentage of cache occupancy 557system.cpu.l2cache.occ_percent::cpu.data 0.007521 # Average percentage of cache occupancy 558system.cpu.l2cache.occ_percent::total 0.634854 # Average percentage of cache occupancy | 537system.cpu.l2cache.occ_blocks::writebacks 19869.756423 # Average occupied blocks per requestor 538system.cpu.l2cache.occ_blocks::cpu.inst 689.265972 # Average occupied blocks per requestor 539system.cpu.l2cache.occ_blocks::cpu.data 246.268207 # Average occupied blocks per requestor 540system.cpu.l2cache.occ_percent::writebacks 0.606377 # Average percentage of cache occupancy 541system.cpu.l2cache.occ_percent::cpu.inst 0.021035 # Average percentage of cache occupancy 542system.cpu.l2cache.occ_percent::cpu.data 0.007516 # Average percentage of cache occupancy 543system.cpu.l2cache.occ_percent::total 0.634927 # Average percentage of cache occupancy |
| 559system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits | 544system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits |
| 560system.cpu.l2cache.ReadReq_hits::cpu.data 1993529 # number of ReadReq hits 561system.cpu.l2cache.ReadReq_hits::total 1993545 # number of ReadReq hits 562system.cpu.l2cache.Writeback_hits::writebacks 2066104 # number of Writeback hits 563system.cpu.l2cache.Writeback_hits::total 2066104 # number of Writeback hits 564system.cpu.l2cache.ReadExReq_hits::cpu.data 53248 # number of ReadExReq hits 565system.cpu.l2cache.ReadExReq_hits::total 53248 # number of ReadExReq hits | 545system.cpu.l2cache.ReadReq_hits::cpu.data 1993469 # number of ReadReq hits 546system.cpu.l2cache.ReadReq_hits::total 1993485 # number of ReadReq hits 547system.cpu.l2cache.Writeback_hits::writebacks 2066038 # number of Writeback hits 548system.cpu.l2cache.Writeback_hits::total 2066038 # number of Writeback hits 549system.cpu.l2cache.ReadExReq_hits::cpu.data 53254 # number of ReadExReq hits 550system.cpu.l2cache.ReadExReq_hits::total 53254 # number of ReadExReq hits |
| 566system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits | 551system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits |
| 567system.cpu.l2cache.demand_hits::cpu.data 2046777 # number of demand (read+write) hits 568system.cpu.l2cache.demand_hits::total 2046793 # number of demand (read+write) hits | 552system.cpu.l2cache.demand_hits::cpu.data 2046723 # number of demand (read+write) hits 553system.cpu.l2cache.demand_hits::total 2046739 # number of demand (read+write) hits |
| 569system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits | 554system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits |
| 570system.cpu.l2cache.overall_hits::cpu.data 2046777 # number of overall hits 571system.cpu.l2cache.overall_hits::total 2046793 # number of overall hits 572system.cpu.l2cache.ReadReq_misses::cpu.inst 1017 # number of ReadReq misses 573system.cpu.l2cache.ReadReq_misses::cpu.data 417 # number of ReadReq misses 574system.cpu.l2cache.ReadReq_misses::total 1434 # number of ReadReq misses | 555system.cpu.l2cache.overall_hits::cpu.data 2046723 # number of overall hits 556system.cpu.l2cache.overall_hits::total 2046739 # number of overall hits 557system.cpu.l2cache.ReadReq_misses::cpu.inst 1013 # number of ReadReq misses 558system.cpu.l2cache.ReadReq_misses::cpu.data 404 # number of ReadReq misses 559system.cpu.l2cache.ReadReq_misses::total 1417 # number of ReadReq misses |
| 575system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 576system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses | 560system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 561system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses |
| 577system.cpu.l2cache.ReadExReq_misses::cpu.data 29000 # number of ReadExReq misses 578system.cpu.l2cache.ReadExReq_misses::total 29000 # number of ReadExReq misses 579system.cpu.l2cache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses 580system.cpu.l2cache.demand_misses::cpu.data 29417 # number of demand (read+write) misses 581system.cpu.l2cache.demand_misses::total 30434 # number of demand (read+write) misses 582system.cpu.l2cache.overall_misses::cpu.inst 1017 # number of overall misses 583system.cpu.l2cache.overall_misses::cpu.data 29417 # number of overall misses 584system.cpu.l2cache.overall_misses::total 30434 # number of overall misses 585system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50633000 # number of ReadReq miss cycles 586system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21040000 # number of ReadReq miss cycles 587system.cpu.l2cache.ReadReq_miss_latency::total 71673000 # number of ReadReq miss cycles 588system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1219810500 # number of ReadExReq miss cycles 589system.cpu.l2cache.ReadExReq_miss_latency::total 1219810500 # number of ReadExReq miss cycles 590system.cpu.l2cache.demand_miss_latency::cpu.inst 50633000 # number of demand (read+write) miss cycles 591system.cpu.l2cache.demand_miss_latency::cpu.data 1240850500 # number of demand (read+write) miss cycles 592system.cpu.l2cache.demand_miss_latency::total 1291483500 # number of demand (read+write) miss cycles 593system.cpu.l2cache.overall_miss_latency::cpu.inst 50633000 # number of overall miss cycles 594system.cpu.l2cache.overall_miss_latency::cpu.data 1240850500 # number of overall miss cycles 595system.cpu.l2cache.overall_miss_latency::total 1291483500 # number of overall miss cycles 596system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033 # number of ReadReq accesses(hits+misses) 597system.cpu.l2cache.ReadReq_accesses::cpu.data 1993946 # number of ReadReq accesses(hits+misses) 598system.cpu.l2cache.ReadReq_accesses::total 1994979 # number of ReadReq accesses(hits+misses) 599system.cpu.l2cache.Writeback_accesses::writebacks 2066104 # number of Writeback accesses(hits+misses) 600system.cpu.l2cache.Writeback_accesses::total 2066104 # number of Writeback accesses(hits+misses) | 562system.cpu.l2cache.ReadExReq_misses::cpu.data 28999 # number of ReadExReq misses 563system.cpu.l2cache.ReadExReq_misses::total 28999 # number of ReadExReq misses 564system.cpu.l2cache.demand_misses::cpu.inst 1013 # number of demand (read+write) misses 565system.cpu.l2cache.demand_misses::cpu.data 29403 # number of demand (read+write) misses 566system.cpu.l2cache.demand_misses::total 30416 # number of demand (read+write) misses 567system.cpu.l2cache.overall_misses::cpu.inst 1013 # number of overall misses 568system.cpu.l2cache.overall_misses::cpu.data 29403 # number of overall misses 569system.cpu.l2cache.overall_misses::total 30416 # number of overall misses 570system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50632500 # number of ReadReq miss cycles 571system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20596000 # number of ReadReq miss cycles 572system.cpu.l2cache.ReadReq_miss_latency::total 71228500 # number of ReadReq miss cycles 573system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1219887500 # number of ReadExReq miss cycles 574system.cpu.l2cache.ReadExReq_miss_latency::total 1219887500 # number of ReadExReq miss cycles 575system.cpu.l2cache.demand_miss_latency::cpu.inst 50632500 # number of demand (read+write) miss cycles 576system.cpu.l2cache.demand_miss_latency::cpu.data 1240483500 # number of demand (read+write) miss cycles 577system.cpu.l2cache.demand_miss_latency::total 1291116000 # number of demand (read+write) miss cycles 578system.cpu.l2cache.overall_miss_latency::cpu.inst 50632500 # number of overall miss cycles 579system.cpu.l2cache.overall_miss_latency::cpu.data 1240483500 # number of overall miss cycles 580system.cpu.l2cache.overall_miss_latency::total 1291116000 # number of overall miss cycles 581system.cpu.l2cache.ReadReq_accesses::cpu.inst 1029 # number of ReadReq accesses(hits+misses) 582system.cpu.l2cache.ReadReq_accesses::cpu.data 1993873 # number of ReadReq accesses(hits+misses) 583system.cpu.l2cache.ReadReq_accesses::total 1994902 # number of ReadReq accesses(hits+misses) 584system.cpu.l2cache.Writeback_accesses::writebacks 2066038 # number of Writeback accesses(hits+misses) 585system.cpu.l2cache.Writeback_accesses::total 2066038 # number of Writeback accesses(hits+misses) |
| 601system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 602system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) | 586system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 587system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) |
| 603system.cpu.l2cache.ReadExReq_accesses::cpu.data 82248 # number of ReadExReq accesses(hits+misses) 604system.cpu.l2cache.ReadExReq_accesses::total 82248 # number of ReadExReq accesses(hits+misses) 605system.cpu.l2cache.demand_accesses::cpu.inst 1033 # number of demand (read+write) accesses 606system.cpu.l2cache.demand_accesses::cpu.data 2076194 # number of demand (read+write) accesses 607system.cpu.l2cache.demand_accesses::total 2077227 # number of demand (read+write) accesses 608system.cpu.l2cache.overall_accesses::cpu.inst 1033 # number of overall (read+write) accesses 609system.cpu.l2cache.overall_accesses::cpu.data 2076194 # number of overall (read+write) accesses 610system.cpu.l2cache.overall_accesses::total 2077227 # number of overall (read+write) accesses 611system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984511 # miss rate for ReadReq accesses 612system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000209 # miss rate for ReadReq accesses 613system.cpu.l2cache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses | 588system.cpu.l2cache.ReadExReq_accesses::cpu.data 82253 # number of ReadExReq accesses(hits+misses) 589system.cpu.l2cache.ReadExReq_accesses::total 82253 # number of ReadExReq accesses(hits+misses) 590system.cpu.l2cache.demand_accesses::cpu.inst 1029 # number of demand (read+write) accesses 591system.cpu.l2cache.demand_accesses::cpu.data 2076126 # number of demand (read+write) accesses 592system.cpu.l2cache.demand_accesses::total 2077155 # number of demand (read+write) accesses 593system.cpu.l2cache.overall_accesses::cpu.inst 1029 # number of overall (read+write) accesses 594system.cpu.l2cache.overall_accesses::cpu.data 2076126 # number of overall (read+write) accesses 595system.cpu.l2cache.overall_accesses::total 2077155 # number of overall (read+write) accesses 596system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984451 # miss rate for ReadReq accesses 597system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000203 # miss rate for ReadReq accesses 598system.cpu.l2cache.ReadReq_miss_rate::total 0.000710 # miss rate for ReadReq accesses |
| 614system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 615system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 599system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 600system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 616system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352592 # miss rate for ReadExReq accesses 617system.cpu.l2cache.ReadExReq_miss_rate::total 0.352592 # miss rate for ReadExReq accesses 618system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984511 # miss rate for demand accesses 619system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses 620system.cpu.l2cache.demand_miss_rate::total 0.014651 # miss rate for demand accesses 621system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984511 # miss rate for overall accesses 622system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses 623system.cpu.l2cache.overall_miss_rate::total 0.014651 # miss rate for overall accesses 624system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49786.627335 # average ReadReq miss latency 625system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50455.635492 # average ReadReq miss latency 626system.cpu.l2cache.ReadReq_avg_miss_latency::total 49981.171548 # average ReadReq miss latency 627system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42062.431034 # average ReadExReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42062.431034 # average ReadExReq miss latency 629system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency 630system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency 631system.cpu.l2cache.demand_avg_miss_latency::total 42435.549057 # average overall miss latency 632system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency 633system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::total 42435.549057 # average overall miss latency | 601system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352559 # miss rate for ReadExReq accesses 602system.cpu.l2cache.ReadExReq_miss_rate::total 0.352559 # miss rate for ReadExReq accesses 603system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984451 # miss rate for demand accesses 604system.cpu.l2cache.demand_miss_rate::cpu.data 0.014162 # miss rate for demand accesses 605system.cpu.l2cache.demand_miss_rate::total 0.014643 # miss rate for demand accesses 606system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984451 # miss rate for overall accesses 607system.cpu.l2cache.overall_miss_rate::cpu.data 0.014162 # miss rate for overall accesses 608system.cpu.l2cache.overall_miss_rate::total 0.014643 # miss rate for overall accesses 609system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49982.724580 # average ReadReq miss latency 610system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50980.198020 # average ReadReq miss latency 611system.cpu.l2cache.ReadReq_avg_miss_latency::total 50267.113620 # average ReadReq miss latency 612system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42066.536777 # average ReadExReq miss latency 613system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42066.536777 # average ReadExReq miss latency 614system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49982.724580 # average overall miss latency 615system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42189.011325 # average overall miss latency 616system.cpu.l2cache.demand_avg_miss_latency::total 42448.579695 # average overall miss latency 617system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49982.724580 # average overall miss latency 618system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42189.011325 # average overall miss latency 619system.cpu.l2cache.overall_avg_miss_latency::total 42448.579695 # average overall miss latency |
| 635system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 636system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 639system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 640system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 641system.cpu.l2cache.fast_writes 0 # number of fast writes performed 642system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 620system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 621system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 622system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 623system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 624system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 625system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 626system.cpu.l2cache.fast_writes 0 # number of fast writes performed 627system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 643system.cpu.l2cache.writebacks::writebacks 169 # number of writebacks 644system.cpu.l2cache.writebacks::total 169 # number of writebacks 645system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1017 # number of ReadReq MSHR misses 646system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses 647system.cpu.l2cache.ReadReq_mshr_misses::total 1434 # number of ReadReq MSHR misses | 628system.cpu.l2cache.writebacks::writebacks 154 # number of writebacks 629system.cpu.l2cache.writebacks::total 154 # number of writebacks 630system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses 631system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 404 # number of ReadReq MSHR misses 632system.cpu.l2cache.ReadReq_mshr_misses::total 1417 # number of ReadReq MSHR misses |
| 648system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 649system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses | 633system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 634system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses |
| 650system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29000 # number of ReadExReq MSHR misses 651system.cpu.l2cache.ReadExReq_mshr_misses::total 29000 # number of ReadExReq MSHR misses 652system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses 653system.cpu.l2cache.demand_mshr_misses::cpu.data 29417 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.demand_mshr_misses::total 30434 # number of demand (read+write) MSHR misses 655system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses 656system.cpu.l2cache.overall_mshr_misses::cpu.data 29417 # number of overall MSHR misses 657system.cpu.l2cache.overall_mshr_misses::total 30434 # number of overall MSHR misses 658system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38011868 # number of ReadReq MSHR miss cycles 659system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15869892 # number of ReadReq MSHR miss cycles 660system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53881760 # number of ReadReq MSHR miss cycles | 635system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28999 # number of ReadExReq MSHR misses 636system.cpu.l2cache.ReadExReq_mshr_misses::total 28999 # number of ReadExReq MSHR misses 637system.cpu.l2cache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses 638system.cpu.l2cache.demand_mshr_misses::cpu.data 29403 # number of demand (read+write) MSHR misses 639system.cpu.l2cache.demand_mshr_misses::total 30416 # number of demand (read+write) MSHR misses 640system.cpu.l2cache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses 641system.cpu.l2cache.overall_mshr_misses::cpu.data 29403 # number of overall MSHR misses 642system.cpu.l2cache.overall_mshr_misses::total 30416 # number of overall MSHR misses 643system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38064309 # number of ReadReq MSHR miss cycles 644system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15602084 # number of ReadReq MSHR miss cycles 645system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53666393 # number of ReadReq MSHR miss cycles |
| 661system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles 662system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles | 646system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles 647system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles |
| 663system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862092136 # number of ReadExReq MSHR miss cycles 664system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862092136 # number of ReadExReq MSHR miss cycles 665system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38011868 # number of demand (read+write) MSHR miss cycles 666system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 877962028 # number of demand (read+write) MSHR miss cycles 667system.cpu.l2cache.demand_mshr_miss_latency::total 915973896 # number of demand (read+write) MSHR miss cycles 668system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38011868 # number of overall MSHR miss cycles 669system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 877962028 # number of overall MSHR miss cycles 670system.cpu.l2cache.overall_mshr_miss_latency::total 915973896 # number of overall MSHR miss cycles 671system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for ReadReq accesses 672system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000209 # mshr miss rate for ReadReq accesses 673system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses | 648system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862137460 # number of ReadExReq MSHR miss cycles 649system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862137460 # number of ReadExReq MSHR miss cycles 650system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38064309 # number of demand (read+write) MSHR miss cycles 651system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 877739544 # number of demand (read+write) MSHR miss cycles 652system.cpu.l2cache.demand_mshr_miss_latency::total 915803853 # number of demand (read+write) MSHR miss cycles 653system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38064309 # number of overall MSHR miss cycles 654system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 877739544 # number of overall MSHR miss cycles 655system.cpu.l2cache.overall_mshr_miss_latency::total 915803853 # number of overall MSHR miss cycles 656system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for ReadReq accesses 657system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000203 # mshr miss rate for ReadReq accesses 658system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000710 # mshr miss rate for ReadReq accesses |
| 674system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 675system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 659system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 660system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 676system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352592 # mshr miss rate for ReadExReq accesses 677system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352592 # mshr miss rate for ReadExReq accesses 678system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for demand accesses 679system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses 680system.cpu.l2cache.demand_mshr_miss_rate::total 0.014651 # mshr miss rate for demand accesses 681system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for overall accesses 682system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses 683system.cpu.l2cache.overall_mshr_miss_rate::total 0.014651 # mshr miss rate for overall accesses 684system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37376.468043 # average ReadReq mshr miss latency 685system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38057.294964 # average ReadReq mshr miss latency 686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37574.449093 # average ReadReq mshr miss latency | 661system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352559 # mshr miss rate for ReadExReq accesses 662system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352559 # mshr miss rate for ReadExReq accesses 663system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for demand accesses 664system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014162 # mshr miss rate for demand accesses 665system.cpu.l2cache.demand_mshr_miss_rate::total 0.014643 # mshr miss rate for demand accesses 666system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for overall accesses 667system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014162 # mshr miss rate for overall accesses 668system.cpu.l2cache.overall_mshr_miss_rate::total 0.014643 # mshr miss rate for overall accesses 669system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37575.823297 # average ReadReq mshr miss latency 670system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38619.019802 # average ReadReq mshr miss latency 671system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37873.248412 # average ReadReq mshr miss latency |
| 687system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 688system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency | 672system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 673system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency |
| 689system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29727.315034 # average ReadExReq mshr miss latency 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29727.315034 # average ReadExReq mshr miss latency 691system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency | 674system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29729.903100 # average ReadExReq mshr miss latency 675system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29729.903100 # average ReadExReq mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37575.823297 # average overall mshr miss latency 677system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29852.040404 # average overall mshr miss latency 678system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30109.279754 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37575.823297 # average overall mshr miss latency 680system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29852.040404 # average overall mshr miss latency 681system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30109.279754 # average overall mshr miss latency |
| 697system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 682system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 698system.cpu.dcache.replacements 2072095 # number of replacements 699system.cpu.dcache.tagsinuse 4072.471954 # Cycle average of tags in use 700system.cpu.dcache.total_refs 71964033 # Total number of references to valid blocks. 701system.cpu.dcache.sampled_refs 2076191 # Sample count of references to valid blocks. 702system.cpu.dcache.avg_refs 34.661567 # Average number of references to valid blocks. | 683system.cpu.dcache.replacements 2072027 # number of replacements 684system.cpu.dcache.tagsinuse 4072.478091 # Cycle average of tags in use 685system.cpu.dcache.total_refs 71969321 # Total number of references to valid blocks. 686system.cpu.dcache.sampled_refs 2076123 # Sample count of references to valid blocks. 687system.cpu.dcache.avg_refs 34.665249 # Average number of references to valid blocks. |
| 703system.cpu.dcache.warmup_cycle 21154875000 # Cycle when the warmup percentage was hit. | 688system.cpu.dcache.warmup_cycle 21154875000 # Cycle when the warmup percentage was hit. |
| 704system.cpu.dcache.occ_blocks::cpu.data 4072.471954 # Average occupied blocks per requestor 705system.cpu.dcache.occ_percent::cpu.data 0.994256 # Average percentage of cache occupancy 706system.cpu.dcache.occ_percent::total 0.994256 # Average percentage of cache occupancy 707system.cpu.dcache.ReadReq_hits::cpu.data 40622570 # number of ReadReq hits 708system.cpu.dcache.ReadReq_hits::total 40622570 # number of ReadReq hits 709system.cpu.dcache.WriteReq_hits::cpu.data 31341456 # number of WriteReq hits 710system.cpu.dcache.WriteReq_hits::total 31341456 # number of WriteReq hits 711system.cpu.dcache.demand_hits::cpu.data 71964026 # number of demand (read+write) hits 712system.cpu.dcache.demand_hits::total 71964026 # number of demand (read+write) hits 713system.cpu.dcache.overall_hits::cpu.data 71964026 # number of overall hits 714system.cpu.dcache.overall_hits::total 71964026 # number of overall hits 715system.cpu.dcache.ReadReq_misses::cpu.data 2625435 # number of ReadReq misses 716system.cpu.dcache.ReadReq_misses::total 2625435 # number of ReadReq misses 717system.cpu.dcache.WriteReq_misses::cpu.data 98296 # number of WriteReq misses 718system.cpu.dcache.WriteReq_misses::total 98296 # number of WriteReq misses 719system.cpu.dcache.demand_misses::cpu.data 2723731 # number of demand (read+write) misses 720system.cpu.dcache.demand_misses::total 2723731 # number of demand (read+write) misses 721system.cpu.dcache.overall_misses::cpu.data 2723731 # number of overall misses 722system.cpu.dcache.overall_misses::total 2723731 # number of overall misses 723system.cpu.dcache.ReadReq_miss_latency::cpu.data 31317831000 # number of ReadReq miss cycles 724system.cpu.dcache.ReadReq_miss_latency::total 31317831000 # number of ReadReq miss cycles 725system.cpu.dcache.WriteReq_miss_latency::cpu.data 2109058498 # number of WriteReq miss cycles 726system.cpu.dcache.WriteReq_miss_latency::total 2109058498 # number of WriteReq miss cycles 727system.cpu.dcache.demand_miss_latency::cpu.data 33426889498 # number of demand (read+write) miss cycles 728system.cpu.dcache.demand_miss_latency::total 33426889498 # number of demand (read+write) miss cycles 729system.cpu.dcache.overall_miss_latency::cpu.data 33426889498 # number of overall miss cycles 730system.cpu.dcache.overall_miss_latency::total 33426889498 # number of overall miss cycles 731system.cpu.dcache.ReadReq_accesses::cpu.data 43248005 # number of ReadReq accesses(hits+misses) 732system.cpu.dcache.ReadReq_accesses::total 43248005 # number of ReadReq accesses(hits+misses) | 689system.cpu.dcache.occ_blocks::cpu.data 4072.478091 # Average occupied blocks per requestor 690system.cpu.dcache.occ_percent::cpu.data 0.994257 # Average percentage of cache occupancy 691system.cpu.dcache.occ_percent::total 0.994257 # Average percentage of cache occupancy 692system.cpu.dcache.ReadReq_hits::cpu.data 40627855 # number of ReadReq hits 693system.cpu.dcache.ReadReq_hits::total 40627855 # number of ReadReq hits 694system.cpu.dcache.WriteReq_hits::cpu.data 31341459 # number of WriteReq hits 695system.cpu.dcache.WriteReq_hits::total 31341459 # number of WriteReq hits 696system.cpu.dcache.demand_hits::cpu.data 71969314 # number of demand (read+write) hits 697system.cpu.dcache.demand_hits::total 71969314 # number of demand (read+write) hits 698system.cpu.dcache.overall_hits::cpu.data 71969314 # number of overall hits 699system.cpu.dcache.overall_hits::total 71969314 # number of overall hits 700system.cpu.dcache.ReadReq_misses::cpu.data 2625363 # number of ReadReq misses 701system.cpu.dcache.ReadReq_misses::total 2625363 # number of ReadReq misses 702system.cpu.dcache.WriteReq_misses::cpu.data 98293 # number of WriteReq misses 703system.cpu.dcache.WriteReq_misses::total 98293 # number of WriteReq misses 704system.cpu.dcache.demand_misses::cpu.data 2723656 # number of demand (read+write) misses 705system.cpu.dcache.demand_misses::total 2723656 # number of demand (read+write) misses 706system.cpu.dcache.overall_misses::cpu.data 2723656 # number of overall misses 707system.cpu.dcache.overall_misses::total 2723656 # number of overall misses 708system.cpu.dcache.ReadReq_miss_latency::cpu.data 31317935000 # number of ReadReq miss cycles 709system.cpu.dcache.ReadReq_miss_latency::total 31317935000 # number of ReadReq miss cycles 710system.cpu.dcache.WriteReq_miss_latency::cpu.data 2109133999 # number of WriteReq miss cycles 711system.cpu.dcache.WriteReq_miss_latency::total 2109133999 # number of WriteReq miss cycles 712system.cpu.dcache.demand_miss_latency::cpu.data 33427068999 # number of demand (read+write) miss cycles 713system.cpu.dcache.demand_miss_latency::total 33427068999 # number of demand (read+write) miss cycles 714system.cpu.dcache.overall_miss_latency::cpu.data 33427068999 # number of overall miss cycles 715system.cpu.dcache.overall_miss_latency::total 33427068999 # number of overall miss cycles 716system.cpu.dcache.ReadReq_accesses::cpu.data 43253218 # number of ReadReq accesses(hits+misses) 717system.cpu.dcache.ReadReq_accesses::total 43253218 # number of ReadReq accesses(hits+misses) |
| 733system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 734system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) | 718system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 719system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) |
| 735system.cpu.dcache.demand_accesses::cpu.data 74687757 # number of demand (read+write) accesses 736system.cpu.dcache.demand_accesses::total 74687757 # number of demand (read+write) accesses 737system.cpu.dcache.overall_accesses::cpu.data 74687757 # number of overall (read+write) accesses 738system.cpu.dcache.overall_accesses::total 74687757 # number of overall (read+write) accesses 739system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060706 # miss rate for ReadReq accesses 740system.cpu.dcache.ReadReq_miss_rate::total 0.060706 # miss rate for ReadReq accesses | 720system.cpu.dcache.demand_accesses::cpu.data 74692970 # number of demand (read+write) accesses 721system.cpu.dcache.demand_accesses::total 74692970 # number of demand (read+write) accesses 722system.cpu.dcache.overall_accesses::cpu.data 74692970 # number of overall (read+write) accesses 723system.cpu.dcache.overall_accesses::total 74692970 # number of overall (read+write) accesses 724system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060698 # miss rate for ReadReq accesses 725system.cpu.dcache.ReadReq_miss_rate::total 0.060698 # miss rate for ReadReq accesses |
| 741system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses 742system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses | 726system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses 727system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses |
| 743system.cpu.dcache.demand_miss_rate::cpu.data 0.036468 # miss rate for demand accesses 744system.cpu.dcache.demand_miss_rate::total 0.036468 # miss rate for demand accesses 745system.cpu.dcache.overall_miss_rate::cpu.data 0.036468 # miss rate for overall accesses 746system.cpu.dcache.overall_miss_rate::total 0.036468 # miss rate for overall accesses 747system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.625542 # average ReadReq miss latency 748system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.625542 # average ReadReq miss latency 749system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21456.198604 # average WriteReq miss latency 750system.cpu.dcache.WriteReq_avg_miss_latency::total 21456.198604 # average WriteReq miss latency 751system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency 752system.cpu.dcache.demand_avg_miss_latency::total 12272.463580 # average overall miss latency 753system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency 754system.cpu.dcache.overall_avg_miss_latency::total 12272.463580 # average overall miss latency 755system.cpu.dcache.blocked_cycles::no_mshrs 32211 # number of cycles access was blocked | 728system.cpu.dcache.demand_miss_rate::cpu.data 0.036465 # miss rate for demand accesses 729system.cpu.dcache.demand_miss_rate::total 0.036465 # miss rate for demand accesses 730system.cpu.dcache.overall_miss_rate::cpu.data 0.036465 # miss rate for overall accesses 731system.cpu.dcache.overall_miss_rate::total 0.036465 # miss rate for overall accesses 732system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.992296 # average ReadReq miss latency 733system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.992296 # average ReadReq miss latency 734system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21457.621591 # average WriteReq miss latency 735system.cpu.dcache.WriteReq_avg_miss_latency::total 21457.621591 # average WriteReq miss latency 736system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.867425 # average overall miss latency 737system.cpu.dcache.demand_avg_miss_latency::total 12272.867425 # average overall miss latency 738system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.867425 # average overall miss latency 739system.cpu.dcache.overall_avg_miss_latency::total 12272.867425 # average overall miss latency 740system.cpu.dcache.blocked_cycles::no_mshrs 31969 # number of cycles access was blocked |
| 756system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 741system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 757system.cpu.dcache.blocked::no_mshrs 9475 # number of cycles access was blocked | 742system.cpu.dcache.blocked::no_mshrs 9433 # number of cycles access was blocked |
| 758system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 743system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 759system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.399578 # average number of cycles each access was blocked | 744system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.389060 # average number of cycles each access was blocked |
| 760system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 761system.cpu.dcache.fast_writes 0 # number of fast writes performed 762system.cpu.dcache.cache_copies 0 # number of cache copies performed | 745system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 746system.cpu.dcache.fast_writes 0 # number of fast writes performed 747system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 763system.cpu.dcache.writebacks::writebacks 2066104 # number of writebacks 764system.cpu.dcache.writebacks::total 2066104 # number of writebacks 765system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631384 # number of ReadReq MSHR hits 766system.cpu.dcache.ReadReq_mshr_hits::total 631384 # number of ReadReq MSHR hits 767system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits 768system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits 769system.cpu.dcache.demand_mshr_hits::cpu.data 647536 # number of demand (read+write) MSHR hits 770system.cpu.dcache.demand_mshr_hits::total 647536 # number of demand (read+write) MSHR hits 771system.cpu.dcache.overall_mshr_hits::cpu.data 647536 # number of overall MSHR hits 772system.cpu.dcache.overall_mshr_hits::total 647536 # number of overall MSHR hits 773system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994051 # number of ReadReq MSHR misses 774system.cpu.dcache.ReadReq_mshr_misses::total 1994051 # number of ReadReq MSHR misses 775system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82144 # number of WriteReq MSHR misses 776system.cpu.dcache.WriteReq_mshr_misses::total 82144 # number of WriteReq MSHR misses 777system.cpu.dcache.demand_mshr_misses::cpu.data 2076195 # number of demand (read+write) MSHR misses 778system.cpu.dcache.demand_mshr_misses::total 2076195 # number of demand (read+write) MSHR misses 779system.cpu.dcache.overall_mshr_misses::cpu.data 2076195 # number of overall MSHR misses 780system.cpu.dcache.overall_mshr_misses::total 2076195 # number of overall MSHR misses 781system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987856500 # number of ReadReq MSHR miss cycles 782system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987856500 # number of ReadReq MSHR miss cycles 783system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833812998 # number of WriteReq MSHR miss cycles 784system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833812998 # number of WriteReq MSHR miss cycles 785system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23821669498 # number of demand (read+write) MSHR miss cycles 786system.cpu.dcache.demand_mshr_miss_latency::total 23821669498 # number of demand (read+write) MSHR miss cycles 787system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23821669498 # number of overall MSHR miss cycles 788system.cpu.dcache.overall_mshr_miss_latency::total 23821669498 # number of overall MSHR miss cycles 789system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046107 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046107 # mshr miss rate for ReadReq accesses | 748system.cpu.dcache.writebacks::writebacks 2066038 # number of writebacks 749system.cpu.dcache.writebacks::total 2066038 # number of writebacks 750system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631383 # number of ReadReq MSHR hits 751system.cpu.dcache.ReadReq_mshr_hits::total 631383 # number of ReadReq MSHR hits 752system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16146 # number of WriteReq MSHR hits 753system.cpu.dcache.WriteReq_mshr_hits::total 16146 # number of WriteReq MSHR hits 754system.cpu.dcache.demand_mshr_hits::cpu.data 647529 # number of demand (read+write) MSHR hits 755system.cpu.dcache.demand_mshr_hits::total 647529 # number of demand (read+write) MSHR hits 756system.cpu.dcache.overall_mshr_hits::cpu.data 647529 # number of overall MSHR hits 757system.cpu.dcache.overall_mshr_hits::total 647529 # number of overall MSHR hits 758system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1993980 # number of ReadReq MSHR misses 759system.cpu.dcache.ReadReq_mshr_misses::total 1993980 # number of ReadReq MSHR misses 760system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82147 # number of WriteReq MSHR misses 761system.cpu.dcache.WriteReq_mshr_misses::total 82147 # number of WriteReq MSHR misses 762system.cpu.dcache.demand_mshr_misses::cpu.data 2076127 # number of demand (read+write) MSHR misses 763system.cpu.dcache.demand_mshr_misses::total 2076127 # number of demand (read+write) MSHR misses 764system.cpu.dcache.overall_mshr_misses::cpu.data 2076127 # number of overall MSHR misses 765system.cpu.dcache.overall_mshr_misses::total 2076127 # number of overall MSHR misses 766system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982224500 # number of ReadReq MSHR miss cycles 767system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982224500 # number of ReadReq MSHR miss cycles 768system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833925499 # number of WriteReq MSHR miss cycles 769system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833925499 # number of WriteReq MSHR miss cycles 770system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816149999 # number of demand (read+write) MSHR miss cycles 771system.cpu.dcache.demand_mshr_miss_latency::total 23816149999 # number of demand (read+write) MSHR miss cycles 772system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23816149999 # number of overall MSHR miss cycles 773system.cpu.dcache.overall_mshr_miss_latency::total 23816149999 # number of overall MSHR miss cycles 774system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046100 # mshr miss rate for ReadReq accesses 775system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046100 # mshr miss rate for ReadReq accesses |
| 791system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses | 776system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses 777system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses |
| 793system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for demand accesses 794system.cpu.dcache.demand_mshr_miss_rate::total 0.027798 # mshr miss rate for demand accesses 795system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for overall accesses 796system.cpu.dcache.overall_mshr_miss_rate::total 0.027798 # mshr miss rate for overall accesses 797system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.727250 # average ReadReq mshr miss latency 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.727250 # average ReadReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.369376 # average WriteReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.369376 # average WriteReq mshr miss latency 801system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency 802system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency 803system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency 804system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency | 778system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for demand accesses 779system.cpu.dcache.demand_mshr_miss_rate::total 0.027795 # mshr miss rate for demand accesses 780system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for overall accesses 781system.cpu.dcache.overall_mshr_miss_rate::total 0.027795 # mshr miss rate for overall accesses 782system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.295379 # average ReadReq mshr miss latency 783system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.295379 # average ReadReq mshr miss latency 784system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.923600 # average WriteReq mshr miss latency 785system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.923600 # average WriteReq mshr miss latency 786system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.432142 # average overall mshr miss latency 787system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.432142 # average overall mshr miss latency 788system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.432142 # average overall mshr miss latency 789system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.432142 # average overall mshr miss latency |
| 805system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 806 807---------- End Simulation Statistics ---------- | 790system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 791 792---------- End Simulation Statistics ---------- |