| stats.txt (9481:b0fa6b872f40) | stats.txt (9490:e6a09d97bdc9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.065983 # Number of seconds simulated 4sim_ticks 65982862500 # Number of ticks simulated 5final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.066005 # Number of seconds simulated 4sim_ticks 66004575000 # Number of ticks simulated 5final_tick 66004575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 72483 # Simulator instruction rate (inst/s) 8host_op_rate 127630 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 30271870 # Simulator tick rate (ticks/s) 10host_mem_usage 430980 # Number of bytes of host memory used 11host_seconds 2179.68 # Real time elapsed on the host | 7host_inst_rate 124260 # Simulator instruction rate (inst/s) 8host_op_rate 218802 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 51913433 # Simulator tick rate (ticks/s) 10host_mem_usage 384868 # Number of bytes of host memory used 11host_seconds 1271.44 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192463 # Number of ops (including micro ops) simulated | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192463 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1948288 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 11136 # Number of bytes written to this memory 20system.physmem.bytes_written::total 11136 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30442 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 174 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 174 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 988378 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 28538804 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 29527182 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 988378 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 988378 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 168771 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 168771 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 168771 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 988378 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 28538804 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 29695953 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 30444 # Total number of read requests seen 38system.physmem.writeReqs 174 # Total number of write requests seen 39system.physmem.cpureqs 30619 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 1948288 # Total number of bytes read from memory 41system.physmem.bytesWritten 11136 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 1948288 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 11136 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q | 14system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1882560 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1947648 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 10816 # Number of bytes written to this memory 20system.physmem.bytes_written::total 10816 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29415 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30432 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 169 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 169 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 986113 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 28521659 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 29507773 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 986113 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 986113 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 163867 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 163867 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 163867 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 986113 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 28521659 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 29671640 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 30434 # Total number of read requests seen 38system.physmem.writeReqs 169 # Total number of write requests seen 39system.physmem.cpureqs 30604 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 1947648 # Total number of bytes read from memory 41system.physmem.bytesWritten 10816 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 1947648 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 10816 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q |
| 45system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed | 45system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed |
| 46system.physmem.perBankRdReqs::0 1914 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 2031 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 1924 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 1999 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 1964 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 1870 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 1866 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 1859 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 1923 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 1903 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 1827 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 1881 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 1910 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 1876 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 1869 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 1770 # Track reads on a per bank basis | 46system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 1972 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 1959 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 1883 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 1932 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 1937 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 1891 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis |
| 62system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis | 62system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis |
| 63system.physmem.perBankWrReqs::1 93 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 6 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 5 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 11 # Track writes on a per bank basis | 63system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis |
| 67system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis | 67system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis |
| 68system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 7 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 14 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 14 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 11 # Track writes on a per bank basis | 68system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 1 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 5 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 9 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 9 # Track writes on a per bank basis |
| 76system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 76system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 80system.physmem.totGap 65982843000 # Total gap between requests | 80system.physmem.totGap 66004558000 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 87system.physmem.readPktSize::6 30444 # Categorize read packet sizes | 87system.physmem.readPktSize::6 30434 # Categorize read packet sizes |
| 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes | 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes |
| 96system.physmem.writePktSize::6 174 # categorize write packet sizes | 96system.physmem.writePktSize::6 169 # categorize write packet sizes |
| 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 1 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 1 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 108system.physmem.rdQLenPdf::0 29860 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 399 # What read queue length does an incoming req see | 108system.physmem.rdQLenPdf::0 29835 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 405 # What read queue length does an incoming req see |
| 110system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see | 110system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see |
| 111system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see | 111system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see |
| 113system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 20 unchanged lines hidden (view full) --- 141system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see | 113system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 20 unchanged lines hidden (view full) --- 141system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see |
| 149system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see | 149system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see --- 4 unchanged lines hidden (view full) --- 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 154system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see --- 4 unchanged lines hidden (view full) --- 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 174system.physmem.totQLat 10445857 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 571603857 # Sum of mem lat for all requests 176system.physmem.totBusLat 121544000 # Total cycles spent in databus access 177system.physmem.totBankLat 439614000 # Total cycles spent in bank access 178system.physmem.avgQLat 343.77 # Average queueing delay per request 179system.physmem.avgBankLat 14467.65 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 18811.42 # Average memory access latency 182system.physmem.avgRdBW 29.53 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 29.53 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 0.17 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.19 # Data bus utilization in percentage | 174system.physmem.totQLat 12335337 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 610214087 # Sum of mem lat for all requests 176system.physmem.totBusLat 151870000 # Total cycles spent in databus access 177system.physmem.totBankLat 446008750 # Total cycles spent in bank access 178system.physmem.avgQLat 406.11 # Average queueing delay per request 179system.physmem.avgBankLat 14683.90 # Average bank access latency per request 180system.physmem.avgBusLat 5000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 20090.01 # Average memory access latency 182system.physmem.avgRdBW 29.51 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 29.51 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.23 # Data bus utilization in percentage |
| 188system.physmem.avgRdQLen 0.01 # Average read queue length over time | 188system.physmem.avgRdQLen 0.01 # Average read queue length over time |
| 189system.physmem.avgWrQLen 11.24 # Average write queue length over time 190system.physmem.readRowHits 29640 # Number of row buffer hits during reads 191system.physmem.writeRowHits 45 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes 194system.physmem.avgGap 2155034.39 # Average gap between requests 195system.cpu.branchPred.lookups 34537566 # Number of BP lookups 196system.cpu.branchPred.condPredicted 34537566 # Number of conditional branches predicted 197system.cpu.branchPred.condIncorrect 909846 # Number of conditional branches incorrect 198system.cpu.branchPred.BTBLookups 24744786 # Number of BTB lookups 199system.cpu.branchPred.BTBHits 24642661 # Number of BTB hits | 189system.physmem.avgWrQLen 1.18 # Average write queue length over time 190system.physmem.readRowHits 29113 # Number of row buffer hits during reads 191system.physmem.writeRowHits 87 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 95.85 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 51.48 # Row buffer hit rate for writes 194system.physmem.avgGap 2156800.25 # Average gap between requests 195system.cpu.branchPred.lookups 34551755 # Number of BP lookups 196system.cpu.branchPred.condPredicted 34551755 # Number of conditional branches predicted 197system.cpu.branchPred.condIncorrect 910403 # Number of conditional branches incorrect 198system.cpu.branchPred.BTBLookups 24766802 # Number of BTB lookups 199system.cpu.branchPred.BTBHits 24665055 # Number of BTB hits |
| 200system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 200system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 201system.cpu.branchPred.BTBHitPct 99.587287 # BTB Hit Percentage | 201system.cpu.branchPred.BTBHitPct 99.589180 # BTB Hit Percentage |
| 202system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 203system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 204system.cpu.workload.num_syscalls 444 # Number of system calls | 202system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 203system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 204system.cpu.workload.num_syscalls 444 # Number of system calls |
| 205system.cpu.numCycles 131965726 # number of cpu cycles simulated | 205system.cpu.numCycles 132009151 # number of cpu cycles simulated |
| 206system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 207system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 206system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 207system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 208system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss 209system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed 210system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered 211system.cpu.fetch.predictedBranches 24642661 # Number of branches that fetch has predicted taken 212system.cpu.fetch.Cycles 56492855 # Number of cycles fetch has run and was not squashing or blocked 213system.cpu.fetch.SquashCycles 6109576 # Number of cycles fetch has spent squashing 214system.cpu.fetch.BlockedCycles 43628030 # Number of cycles fetch has spent blocked 215system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 216system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps 217system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR 218system.cpu.fetch.CacheLines 25952051 # Number of cache lines fetched 219system.cpu.fetch.IcacheSquashes 188971 # Number of outstanding Icache misses that were squashed 220system.cpu.fetch.rateDist::samples 131886743 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::mean 2.485312 # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::stdev 3.326723 # Number of instructions fetched each cycle (Total) | 208system.cpu.fetch.icacheStallCycles 26590977 # Number of cycles fetch is stalled on an Icache miss 209system.cpu.fetch.Insts 185543024 # Number of instructions fetch has processed 210system.cpu.fetch.Branches 34551755 # Number of branches that fetch encountered 211system.cpu.fetch.predictedBranches 24665055 # Number of branches that fetch has predicted taken 212system.cpu.fetch.Cycles 56499392 # Number of cycles fetch has run and was not squashing or blocked 213system.cpu.fetch.SquashCycles 6118358 # Number of cycles fetch has spent squashing 214system.cpu.fetch.BlockedCycles 43667810 # Number of cycles fetch has spent blocked 215system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 216system.cpu.fetch.PendingTrapStallCycles 138 # Number of stall cycles due to pending traps 217system.cpu.fetch.CacheLines 25944504 # Number of cache lines fetched 218system.cpu.fetch.IcacheSquashes 189453 # Number of outstanding Icache misses that were squashed 219system.cpu.fetch.rateDist::samples 131930197 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::mean 2.484743 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::stdev 3.326414 # Number of instructions fetched each cycle (Total) |
| 223system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 222system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 224system.cpu.fetch.rateDist::0 77942049 59.10% 59.10% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::1 1996023 1.51% 60.61% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::2 2954192 2.24% 62.85% # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::3 3924230 2.98% 65.83% # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::4 7791327 5.91% 71.73% # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.rateDist::5 4757391 3.61% 75.34% # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.rateDist::6 2730462 2.07% 77.41% # Number of instructions fetched each cycle (Total) 231system.cpu.fetch.rateDist::7 1561040 1.18% 78.60% # Number of instructions fetched each cycle (Total) 232system.cpu.fetch.rateDist::8 28230029 21.40% 100.00% # Number of instructions fetched each cycle (Total) | 223system.cpu.fetch.rateDist::0 77978275 59.11% 59.11% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::1 1995894 1.51% 60.62% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::2 2955143 2.24% 62.86% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::3 3921314 2.97% 65.83% # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::4 7795304 5.91% 71.74% # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::5 4757842 3.61% 75.35% # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.rateDist::6 2730359 2.07% 77.42% # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.rateDist::7 1578596 1.20% 78.61% # Number of instructions fetched each cycle (Total) 231system.cpu.fetch.rateDist::8 28217470 21.39% 100.00% # Number of instructions fetched each cycle (Total) |
| 233system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 235system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 232system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 233system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 236system.cpu.fetch.rateDist::total 131886743 # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.branchRate 0.261716 # Number of branch fetches per cycle 238system.cpu.fetch.rate 1.406198 # Number of inst fetches per cycle 239system.cpu.decode.IdleCycles 37433496 # Number of cycles decode is idle 240system.cpu.decode.BlockedCycles 35884188 # Number of cycles decode is blocked 241system.cpu.decode.RunCycles 44759605 # Number of cycles decode is running 242system.cpu.decode.UnblockCycles 8645670 # Number of cycles decode is unblocking 243system.cpu.decode.SquashCycles 5163784 # Number of cycles decode is squashing 244system.cpu.decode.DecodedInsts 324546222 # Number of instructions handled by decode 245system.cpu.rename.SquashCycles 5163784 # Number of cycles rename is squashing 246system.cpu.rename.IdleCycles 42999384 # Number of cycles rename is idle 247system.cpu.rename.BlockCycles 8526748 # Number of cycles rename is blocking 248system.cpu.rename.serializeStallCycles 9161 # count of cycles rename stalled for serializing inst 249system.cpu.rename.RunCycles 47575820 # Number of cycles rename is running 250system.cpu.rename.UnblockCycles 27611846 # Number of cycles rename is unblocking 251system.cpu.rename.RenamedInsts 320149985 # Number of instructions processed by rename 252system.cpu.rename.ROBFullEvents 225 # Number of times rename has blocked due to ROB full 253system.cpu.rename.IQFullEvents 53569 # Number of times rename has blocked due to IQ full 254system.cpu.rename.LSQFullEvents 25749083 # Number of times rename has blocked due to LSQ full 255system.cpu.rename.FullRegisterEvents 361 # Number of times there has been no free registers 256system.cpu.rename.RenamedOperands 322162823 # Number of destination operands rename has renamed 257system.cpu.rename.RenameLookups 849088667 # Number of register rename lookups that rename has made 258system.cpu.rename.int_rename_lookups 849086832 # Number of integer rename lookups 259system.cpu.rename.fp_rename_lookups 1835 # Number of floating rename lookups | 235system.cpu.fetch.rateDist::total 131930197 # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.branchRate 0.261738 # Number of branch fetches per cycle 237system.cpu.fetch.rate 1.405532 # Number of inst fetches per cycle 238system.cpu.decode.IdleCycles 37427999 # Number of cycles decode is idle 239system.cpu.decode.BlockedCycles 35920173 # Number of cycles decode is blocked 240system.cpu.decode.RunCycles 44744893 # Number of cycles decode is running 241system.cpu.decode.UnblockCycles 8665277 # Number of cycles decode is unblocking 242system.cpu.decode.SquashCycles 5171855 # Number of cycles decode is squashing 243system.cpu.decode.DecodedInsts 324565548 # Number of instructions handled by decode 244system.cpu.rename.SquashCycles 5171855 # Number of cycles rename is squashing 245system.cpu.rename.IdleCycles 42969195 # Number of cycles rename is idle 246system.cpu.rename.BlockCycles 8593654 # Number of cycles rename is blocking 247system.cpu.rename.serializeStallCycles 9092 # count of cycles rename stalled for serializing inst 248system.cpu.rename.RunCycles 47590664 # Number of cycles rename is running 249system.cpu.rename.UnblockCycles 27595737 # Number of cycles rename is unblocking 250system.cpu.rename.RenamedInsts 320190802 # Number of instructions processed by rename 251system.cpu.rename.ROBFullEvents 211 # Number of times rename has blocked due to ROB full 252system.cpu.rename.IQFullEvents 56984 # Number of times rename has blocked due to IQ full 253system.cpu.rename.LSQFullEvents 25724332 # Number of times rename has blocked due to LSQ full 254system.cpu.rename.FullRegisterEvents 365 # Number of times there has been no free registers 255system.cpu.rename.RenamedOperands 322194206 # Number of destination operands rename has renamed 256system.cpu.rename.RenameLookups 849198017 # Number of register rename lookups that rename has made 257system.cpu.rename.int_rename_lookups 849196232 # Number of integer rename lookups 258system.cpu.rename.fp_rename_lookups 1785 # Number of floating rename lookups |
| 260system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed | 259system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed |
| 261system.cpu.rename.UndoneMaps 42950078 # Number of HB maps that are undone due to squashing 262system.cpu.rename.serializingInsts 468 # count of serializing insts renamed 263system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed 264system.cpu.rename.skidInsts 62353215 # count of insts added to the skid buffer 265system.cpu.memDep0.insertedLoads 102529083 # Number of loads inserted to the mem dependence unit. 266system.cpu.memDep0.insertedStores 35255084 # Number of stores inserted to the mem dependence unit. 267system.cpu.memDep0.conflictingLoads 39579305 # Number of conflicting loads. 268system.cpu.memDep0.conflictingStores 5971941 # Number of conflicting stores. 269system.cpu.iq.iqInstsAdded 315806334 # Number of instructions added to the IQ (excludes non-spec) 270system.cpu.iq.iqNonSpecInstsAdded 1679 # Number of non-speculative instructions added to the IQ 271system.cpu.iq.iqInstsIssued 302165189 # Number of instructions issued 272system.cpu.iq.iqSquashedInstsIssued 115128 # Number of squashed instructions issued 273system.cpu.iq.iqSquashedInstsExamined 36987116 # Number of squashed instructions iterated over during squash; mainly for profiling 274system.cpu.iq.iqSquashedOperandsExamined 54145851 # Number of squashed operands that are examined and possibly removed from graph 275system.cpu.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed 276system.cpu.iq.issued_per_cycle::samples 131886743 # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::mean 2.291096 # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::stdev 1.700528 # Number of insts issued each cycle | 260system.cpu.rename.UndoneMaps 42981461 # Number of HB maps that are undone due to squashing 261system.cpu.rename.serializingInsts 469 # count of serializing insts renamed 262system.cpu.rename.tempSerializingInsts 463 # count of temporary serializing insts renamed 263system.cpu.rename.skidInsts 62356862 # count of insts added to the skid buffer 264system.cpu.memDep0.insertedLoads 102568377 # Number of loads inserted to the mem dependence unit. 265system.cpu.memDep0.insertedStores 35231338 # Number of stores inserted to the mem dependence unit. 266system.cpu.memDep0.conflictingLoads 39589479 # Number of conflicting loads. 267system.cpu.memDep0.conflictingStores 6005074 # Number of conflicting stores. 268system.cpu.iq.iqInstsAdded 315870239 # Number of instructions added to the IQ (excludes non-spec) 269system.cpu.iq.iqNonSpecInstsAdded 1674 # Number of non-speculative instructions added to the IQ 270system.cpu.iq.iqInstsIssued 302163622 # Number of instructions issued 271system.cpu.iq.iqSquashedInstsIssued 115310 # Number of squashed instructions issued 272system.cpu.iq.iqSquashedInstsExamined 37046058 # Number of squashed instructions iterated over during squash; mainly for profiling 273system.cpu.iq.iqSquashedOperandsExamined 54286160 # Number of squashed operands that are examined and possibly removed from graph 274system.cpu.iq.iqSquashedNonSpecRemoved 1229 # Number of squashed non-spec instructions that were removed 275system.cpu.iq.issued_per_cycle::samples 131930197 # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::mean 2.290329 # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::stdev 1.700150 # Number of insts issued each cycle |
| 279system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 278system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 280system.cpu.iq.issued_per_cycle::0 24537309 18.60% 18.60% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::1 23216690 17.60% 36.21% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::2 25879367 19.62% 55.83% # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::3 25801755 19.56% 75.39% # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::4 18920728 14.35% 89.74% # Number of insts issued each cycle 285system.cpu.iq.issued_per_cycle::5 8321327 6.31% 96.05% # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::6 4137839 3.14% 99.19% # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::7 905905 0.69% 99.87% # Number of insts issued each cycle 288system.cpu.iq.issued_per_cycle::8 165823 0.13% 100.00% # Number of insts issued each cycle | 279system.cpu.iq.issued_per_cycle::0 24515615 18.58% 18.58% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::1 23292289 17.66% 36.24% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::2 25896464 19.63% 55.87% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::3 25797972 19.55% 75.42% # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::4 18916380 14.34% 89.76% # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::5 8292938 6.29% 96.04% # Number of insts issued each cycle 285system.cpu.iq.issued_per_cycle::6 4139203 3.14% 99.18% # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::7 915627 0.69% 99.88% # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::8 163709 0.12% 100.00% # Number of insts issued each cycle |
| 289system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 290system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 291system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 288system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 289system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 290system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 292system.cpu.iq.issued_per_cycle::total 131886743 # Number of insts issued each cycle | 291system.cpu.iq.issued_per_cycle::total 131930197 # Number of insts issued each cycle |
| 293system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 292system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 294system.cpu.iq.fu_full::IntAlu 38358 1.96% 1.96% # attempts to use FU when none available 295system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available 296system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available 297system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available 298system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available 299system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available 300system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available 301system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available 302system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available 321system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available 322system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available 323system.cpu.iq.fu_full::MemRead 1830721 93.50% 95.46% # attempts to use FU when none available 324system.cpu.iq.fu_full::MemWrite 88976 4.54% 100.00% # attempts to use FU when none available | 293system.cpu.iq.fu_full::IntAlu 38493 1.98% 1.98% # attempts to use FU when none available 294system.cpu.iq.fu_full::IntMult 0 0.00% 1.98% # attempts to use FU when none available 295system.cpu.iq.fu_full::IntDiv 0 0.00% 1.98% # attempts to use FU when none available 296system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available 297system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available 298system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available 299system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available 300system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available 301system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available 321system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available 322system.cpu.iq.fu_full::MemRead 1820587 93.51% 95.49% # attempts to use FU when none available 323system.cpu.iq.fu_full::MemWrite 87813 4.51% 100.00% # attempts to use FU when none available |
| 325system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 326system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 324system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 325system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 327system.cpu.iq.FU_type_0::No_OpClass 31295 0.01% 0.01% # Type of FU issued 328system.cpu.iq.FU_type_0::IntAlu 171151869 56.64% 56.65% # Type of FU issued | 326system.cpu.iq.FU_type_0::No_OpClass 31282 0.01% 0.01% # Type of FU issued 327system.cpu.iq.FU_type_0::IntAlu 171146899 56.64% 56.65% # Type of FU issued |
| 329system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued 330system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued 331system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued 332system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued 333system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued 334system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued 335system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.65% # Type of FU issued 336system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.65% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 349system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.65% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.65% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.65% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.65% # Type of FU issued 353system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Type of FU issued 354system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued 355system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued 356system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued | 328system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued 329system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued 330system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued 331system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.65% # Type of FU issued 332system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.65% # Type of FU issued 333system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.65% # Type of FU issued 334system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.65% # Type of FU issued 335system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.65% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 348system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.65% # Type of FU issued 349system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.65% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.65% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.65% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Type of FU issued 353system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued 354system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued 355system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued |
| 357system.cpu.iq.FU_type_0::MemRead 97747173 32.35% 89.00% # Type of FU issued 358system.cpu.iq.FU_type_0::MemWrite 33234817 11.00% 100.00% # Type of FU issued | 356system.cpu.iq.FU_type_0::MemRead 97755630 32.35% 89.00% # Type of FU issued 357system.cpu.iq.FU_type_0::MemWrite 33229776 11.00% 100.00% # Type of FU issued |
| 359system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 360system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 358system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 359system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 361system.cpu.iq.FU_type_0::total 302165189 # Type of FU issued 362system.cpu.iq.rate 2.289725 # Inst issue rate 363system.cpu.iq.fu_busy_cnt 1958055 # FU busy when requested 364system.cpu.iq.fu_busy_rate 0.006480 # FU busy rate (busy events/executed inst) 365system.cpu.iq.int_inst_queue_reads 738289800 # Number of integer instruction queue reads 366system.cpu.iq.int_inst_queue_writes 352827074 # Number of integer instruction queue writes 367system.cpu.iq.int_inst_queue_wakeup_accesses 299525455 # Number of integer instruction queue wakeup accesses 368system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads 369system.cpu.iq.fp_inst_queue_writes 863 # Number of floating instruction queue writes 370system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses 371system.cpu.iq.int_alu_accesses 304091716 # Number of integer alu accesses 372system.cpu.iq.fp_alu_accesses 233 # Number of floating point alu accesses 373system.cpu.iew.lsq.thread0.forwLoads 54002404 # Number of loads that had data forwarded from stores | 360system.cpu.iq.FU_type_0::total 302163622 # Type of FU issued 361system.cpu.iq.rate 2.288960 # Inst issue rate 362system.cpu.iq.fu_busy_cnt 1946893 # FU busy when requested 363system.cpu.iq.fu_busy_rate 0.006443 # FU busy rate (busy events/executed inst) 364system.cpu.iq.int_inst_queue_reads 738319072 # Number of integer instruction queue reads 365system.cpu.iq.int_inst_queue_writes 352950108 # Number of integer instruction queue writes 366system.cpu.iq.int_inst_queue_wakeup_accesses 299522625 # Number of integer instruction queue wakeup accesses 367system.cpu.iq.fp_inst_queue_reads 572 # Number of floating instruction queue reads 368system.cpu.iq.fp_inst_queue_writes 867 # Number of floating instruction queue writes 369system.cpu.iq.fp_inst_queue_wakeup_accesses 162 # Number of floating instruction queue wakeup accesses 370system.cpu.iq.int_alu_accesses 304078975 # Number of integer alu accesses 371system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses 372system.cpu.iew.lsq.thread0.forwLoads 53992768 # Number of loads that had data forwarded from stores |
| 374system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 373system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 375system.cpu.iew.lsq.thread0.squashedLoads 11749699 # Number of loads squashed 376system.cpu.iew.lsq.thread0.ignoredResponses 26201 # Number of memory responses ignored because the instruction is squashed 377system.cpu.iew.lsq.thread0.memOrderViolation 33919 # Number of memory ordering violations 378system.cpu.iew.lsq.thread0.squashedStores 3815332 # Number of stores squashed | 374system.cpu.iew.lsq.thread0.squashedLoads 11788993 # Number of loads squashed 375system.cpu.iew.lsq.thread0.ignoredResponses 26852 # Number of memory responses ignored because the instruction is squashed 376system.cpu.iew.lsq.thread0.memOrderViolation 33996 # Number of memory ordering violations 377system.cpu.iew.lsq.thread0.squashedStores 3791586 # Number of stores squashed |
| 379system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 380system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 378system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 379system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 381system.cpu.iew.lsq.thread0.rescheduledLoads 3226 # Number of loads that were rescheduled 382system.cpu.iew.lsq.thread0.cacheBlocked 8521 # Number of times an access to memory failed due to the cache being blocked | 380system.cpu.iew.lsq.thread0.rescheduledLoads 3239 # Number of loads that were rescheduled 381system.cpu.iew.lsq.thread0.cacheBlocked 8506 # Number of times an access to memory failed due to the cache being blocked |
| 383system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 382system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 384system.cpu.iew.iewSquashCycles 5163784 # Number of cycles IEW is squashing 385system.cpu.iew.iewBlockCycles 1727826 # Number of cycles IEW is blocking 386system.cpu.iew.iewUnblockCycles 159628 # Number of cycles IEW is unblocking 387system.cpu.iew.iewDispatchedInsts 315808013 # Number of instructions dispatched to IQ 388system.cpu.iew.iewDispSquashedInsts 197001 # Number of squashed instructions skipped by dispatch 389system.cpu.iew.iewDispLoadInsts 102529083 # Number of dispatched load instructions 390system.cpu.iew.iewDispStoreInsts 35255084 # Number of dispatched store instructions | 383system.cpu.iew.iewSquashCycles 5171855 # Number of cycles IEW is squashing 384system.cpu.iew.iewBlockCycles 1763635 # Number of cycles IEW is blocking 385system.cpu.iew.iewUnblockCycles 159728 # Number of cycles IEW is unblocking 386system.cpu.iew.iewDispatchedInsts 315871913 # Number of instructions dispatched to IQ 387system.cpu.iew.iewDispSquashedInsts 195728 # Number of squashed instructions skipped by dispatch 388system.cpu.iew.iewDispLoadInsts 102568377 # Number of dispatched load instructions 389system.cpu.iew.iewDispStoreInsts 35231338 # Number of dispatched store instructions |
| 391system.cpu.iew.iewDispNonSpecInsts 464 # Number of dispatched non-speculative instructions | 390system.cpu.iew.iewDispNonSpecInsts 464 # Number of dispatched non-speculative instructions |
| 392system.cpu.iew.iewIQFullEvents 3215 # Number of times the IQ has become full, causing a stall 393system.cpu.iew.iewLSQFullEvents 73485 # Number of times the LSQ has become full, causing a stall 394system.cpu.iew.memOrderViolationEvents 33919 # Number of memory order violations 395system.cpu.iew.predictedTakenIncorrect 521490 # Number of branches that were predicted taken incorrectly 396system.cpu.iew.predictedNotTakenIncorrect 445155 # Number of branches that were predicted not taken incorrectly 397system.cpu.iew.branchMispredicts 966645 # Number of branch mispredicts detected at execute 398system.cpu.iew.iewExecutedInsts 300546126 # Number of executed instructions 399system.cpu.iew.iewExecLoadInsts 97278076 # Number of load instructions executed 400system.cpu.iew.iewExecSquashedInsts 1619063 # Number of squashed instructions skipped in execute | 391system.cpu.iew.iewIQFullEvents 3188 # Number of times the IQ has become full, causing a stall 392system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall 393system.cpu.iew.memOrderViolationEvents 33996 # Number of memory order violations 394system.cpu.iew.predictedTakenIncorrect 522451 # Number of branches that were predicted taken incorrectly 395system.cpu.iew.predictedNotTakenIncorrect 444817 # Number of branches that were predicted not taken incorrectly 396system.cpu.iew.branchMispredicts 967268 # Number of branch mispredicts detected at execute 397system.cpu.iew.iewExecutedInsts 300543939 # Number of executed instructions 398system.cpu.iew.iewExecLoadInsts 97286160 # Number of load instructions executed 399system.cpu.iew.iewExecSquashedInsts 1619683 # Number of squashed instructions skipped in execute |
| 401system.cpu.iew.exec_swp 0 # number of swp insts executed 402system.cpu.iew.exec_nop 0 # number of nop insts executed | 400system.cpu.iew.exec_swp 0 # number of swp insts executed 401system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 403system.cpu.iew.exec_refs 130293374 # number of memory reference insts executed 404system.cpu.iew.exec_branches 30888175 # Number of branches executed 405system.cpu.iew.exec_stores 33015298 # Number of stores executed 406system.cpu.iew.exec_rate 2.277456 # Inst execution rate 407system.cpu.iew.wb_sent 299954363 # cumulative count of insts sent to commit 408system.cpu.iew.wb_count 299525609 # cumulative count of insts written-back 409system.cpu.iew.wb_producers 219474385 # num instructions producing a value 410system.cpu.iew.wb_consumers 297941322 # num instructions consuming a value | 402system.cpu.iew.exec_refs 130298049 # number of memory reference insts executed 403system.cpu.iew.exec_branches 30887567 # Number of branches executed 404system.cpu.iew.exec_stores 33011889 # Number of stores executed 405system.cpu.iew.exec_rate 2.276690 # Inst execution rate 406system.cpu.iew.wb_sent 299950982 # cumulative count of insts sent to commit 407system.cpu.iew.wb_count 299522787 # cumulative count of insts written-back 408system.cpu.iew.wb_producers 219513248 # num instructions producing a value 409system.cpu.iew.wb_consumers 298024509 # num instructions consuming a value |
| 411system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 410system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 412system.cpu.iew.wb_rate 2.269723 # insts written-back per cycle 413system.cpu.iew.wb_fanout 0.736636 # average fanout of values written-back | 411system.cpu.iew.wb_rate 2.268955 # insts written-back per cycle 412system.cpu.iew.wb_fanout 0.736561 # average fanout of values written-back |
| 414system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 413system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 415system.cpu.commit.commitSquashedInsts 37628513 # The number of squashed insts skipped by commit | 414system.cpu.commit.commitSquashedInsts 37692291 # The number of squashed insts skipped by commit |
| 416system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards | 415system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards |
| 417system.cpu.commit.branchMispredicts 909867 # The number of times a branch was mispredicted 418system.cpu.commit.committed_per_cycle::samples 126722959 # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::mean 2.195281 # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::stdev 2.965844 # Number of insts commited each cycle | 416system.cpu.commit.branchMispredicts 910422 # The number of times a branch was mispredicted 417system.cpu.commit.committed_per_cycle::samples 126758342 # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::mean 2.194668 # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::stdev 2.965617 # Number of insts commited each cycle |
| 421system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 420system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 422system.cpu.commit.committed_per_cycle::0 58163271 45.90% 45.90% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::1 19278050 15.21% 61.11% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::2 11813019 9.32% 70.43% # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::3 9592484 7.57% 78.00% # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::4 1741744 1.37% 79.38% # Number of insts commited each cycle 427system.cpu.commit.committed_per_cycle::5 2072615 1.64% 81.01% # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::6 1297671 1.02% 82.04% # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::7 717994 0.57% 82.60% # Number of insts commited each cycle 430system.cpu.commit.committed_per_cycle::8 22046111 17.40% 100.00% # Number of insts commited each cycle | 421system.cpu.commit.committed_per_cycle::0 58200495 45.91% 45.91% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::1 19281721 15.21% 61.13% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::2 11800672 9.31% 70.44% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::3 9590531 7.57% 78.00% # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::4 1751465 1.38% 79.38% # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::5 2073903 1.64% 81.02% # Number of insts commited each cycle 427system.cpu.commit.committed_per_cycle::6 1296843 1.02% 82.04% # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::7 720324 0.57% 82.61% # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::8 22042388 17.39% 100.00% # Number of insts commited each cycle |
| 431system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 432system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 433system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 430system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 431system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 432system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 434system.cpu.commit.committed_per_cycle::total 126722959 # Number of insts commited each cycle | 433system.cpu.commit.committed_per_cycle::total 126758342 # Number of insts commited each cycle |
| 435system.cpu.commit.committedInsts 157988547 # Number of instructions committed 436system.cpu.commit.committedOps 278192463 # Number of ops (including micro ops) committed 437system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 438system.cpu.commit.refs 122219136 # Number of memory references committed 439system.cpu.commit.loads 90779384 # Number of loads committed 440system.cpu.commit.membars 0 # Number of memory barriers committed 441system.cpu.commit.branches 29309705 # Number of branches committed 442system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 443system.cpu.commit.int_insts 278186172 # Number of committed integer instructions. 444system.cpu.commit.function_calls 0 # Number of function calls committed. | 434system.cpu.commit.committedInsts 157988547 # Number of instructions committed 435system.cpu.commit.committedOps 278192463 # Number of ops (including micro ops) committed 436system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 437system.cpu.commit.refs 122219136 # Number of memory references committed 438system.cpu.commit.loads 90779384 # Number of loads committed 439system.cpu.commit.membars 0 # Number of memory barriers committed 440system.cpu.commit.branches 29309705 # Number of branches committed 441system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 442system.cpu.commit.int_insts 278186172 # Number of committed integer instructions. 443system.cpu.commit.function_calls 0 # Number of function calls committed. |
| 445system.cpu.commit.bw_lim_events 22046111 # number cycles where commit BW limit reached | 444system.cpu.commit.bw_lim_events 22042388 # number cycles where commit BW limit reached |
| 446system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 445system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 447system.cpu.rob.rob_reads 420497824 # The number of ROB reads 448system.cpu.rob.rob_writes 636810847 # The number of ROB writes 449system.cpu.timesIdled 13700 # Number of times that the entire CPU went into an idle state and unscheduled itself 450system.cpu.idleCycles 78983 # Total number of cycles that the CPU has spent unscheduled due to idling | 446system.cpu.rob.rob_reads 420600708 # The number of ROB reads 447system.cpu.rob.rob_writes 636946432 # The number of ROB writes 448system.cpu.timesIdled 13762 # Number of times that the entire CPU went into an idle state and unscheduled itself 449system.cpu.idleCycles 78954 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 451system.cpu.committedInsts 157988547 # Number of Instructions Simulated 452system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated 453system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated | 450system.cpu.committedInsts 157988547 # Number of Instructions Simulated 451system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated 452system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated |
| 454system.cpu.cpi 0.835287 # CPI: Cycles Per Instruction 455system.cpu.cpi_total 0.835287 # CPI: Total CPI of All Threads 456system.cpu.ipc 1.197194 # IPC: Instructions Per Cycle 457system.cpu.ipc_total 1.197194 # IPC: Total IPC of All Threads 458system.cpu.int_regfile_reads 592820364 # number of integer regfile reads 459system.cpu.int_regfile_writes 300190131 # number of integer regfile writes 460system.cpu.fp_regfile_reads 138 # number of floating regfile reads 461system.cpu.fp_regfile_writes 78 # number of floating regfile writes 462system.cpu.misc_regfile_reads 192690356 # number of misc regfile reads 463system.cpu.icache.replacements 68 # number of replacements 464system.cpu.icache.tagsinuse 836.141368 # Cycle average of tags in use 465system.cpu.icache.total_refs 25950700 # Total number of references to valid blocks. 466system.cpu.icache.sampled_refs 1039 # Sample count of references to valid blocks. 467system.cpu.icache.avg_refs 24976.612127 # Average number of references to valid blocks. | 453system.cpu.cpi 0.835562 # CPI: Cycles Per Instruction 454system.cpu.cpi_total 0.835562 # CPI: Total CPI of All Threads 455system.cpu.ipc 1.196800 # IPC: Instructions Per Cycle 456system.cpu.ipc_total 1.196800 # IPC: Total IPC of All Threads 457system.cpu.int_regfile_reads 592847791 # number of integer regfile reads 458system.cpu.int_regfile_writes 300194164 # number of integer regfile writes 459system.cpu.fp_regfile_reads 150 # number of floating regfile reads 460system.cpu.fp_regfile_writes 76 # number of floating regfile writes 461system.cpu.misc_regfile_reads 192689354 # number of misc regfile reads 462system.cpu.icache.replacements 61 # number of replacements 463system.cpu.icache.tagsinuse 835.847711 # Cycle average of tags in use 464system.cpu.icache.total_refs 25943160 # Total number of references to valid blocks. 465system.cpu.icache.sampled_refs 1033 # Sample count of references to valid blocks. 466system.cpu.icache.avg_refs 25114.385286 # Average number of references to valid blocks. |
| 468system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 467system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 469system.cpu.icache.occ_blocks::cpu.inst 836.141368 # Average occupied blocks per requestor 470system.cpu.icache.occ_percent::cpu.inst 0.408272 # Average percentage of cache occupancy 471system.cpu.icache.occ_percent::total 0.408272 # Average percentage of cache occupancy 472system.cpu.icache.ReadReq_hits::cpu.inst 25950700 # number of ReadReq hits 473system.cpu.icache.ReadReq_hits::total 25950700 # number of ReadReq hits 474system.cpu.icache.demand_hits::cpu.inst 25950700 # number of demand (read+write) hits 475system.cpu.icache.demand_hits::total 25950700 # number of demand (read+write) hits 476system.cpu.icache.overall_hits::cpu.inst 25950700 # number of overall hits 477system.cpu.icache.overall_hits::total 25950700 # number of overall hits 478system.cpu.icache.ReadReq_misses::cpu.inst 1351 # number of ReadReq misses 479system.cpu.icache.ReadReq_misses::total 1351 # number of ReadReq misses 480system.cpu.icache.demand_misses::cpu.inst 1351 # number of demand (read+write) misses 481system.cpu.icache.demand_misses::total 1351 # number of demand (read+write) misses 482system.cpu.icache.overall_misses::cpu.inst 1351 # number of overall misses 483system.cpu.icache.overall_misses::total 1351 # number of overall misses 484system.cpu.icache.ReadReq_miss_latency::cpu.inst 65349000 # number of ReadReq miss cycles 485system.cpu.icache.ReadReq_miss_latency::total 65349000 # number of ReadReq miss cycles 486system.cpu.icache.demand_miss_latency::cpu.inst 65349000 # number of demand (read+write) miss cycles 487system.cpu.icache.demand_miss_latency::total 65349000 # number of demand (read+write) miss cycles 488system.cpu.icache.overall_miss_latency::cpu.inst 65349000 # number of overall miss cycles 489system.cpu.icache.overall_miss_latency::total 65349000 # number of overall miss cycles 490system.cpu.icache.ReadReq_accesses::cpu.inst 25952051 # number of ReadReq accesses(hits+misses) 491system.cpu.icache.ReadReq_accesses::total 25952051 # number of ReadReq accesses(hits+misses) 492system.cpu.icache.demand_accesses::cpu.inst 25952051 # number of demand (read+write) accesses 493system.cpu.icache.demand_accesses::total 25952051 # number of demand (read+write) accesses 494system.cpu.icache.overall_accesses::cpu.inst 25952051 # number of overall (read+write) accesses 495system.cpu.icache.overall_accesses::total 25952051 # number of overall (read+write) accesses | 468system.cpu.icache.occ_blocks::cpu.inst 835.847711 # Average occupied blocks per requestor 469system.cpu.icache.occ_percent::cpu.inst 0.408129 # Average percentage of cache occupancy 470system.cpu.icache.occ_percent::total 0.408129 # Average percentage of cache occupancy 471system.cpu.icache.ReadReq_hits::cpu.inst 25943160 # number of ReadReq hits 472system.cpu.icache.ReadReq_hits::total 25943160 # number of ReadReq hits 473system.cpu.icache.demand_hits::cpu.inst 25943160 # number of demand (read+write) hits 474system.cpu.icache.demand_hits::total 25943160 # number of demand (read+write) hits 475system.cpu.icache.overall_hits::cpu.inst 25943160 # number of overall hits 476system.cpu.icache.overall_hits::total 25943160 # number of overall hits 477system.cpu.icache.ReadReq_misses::cpu.inst 1344 # number of ReadReq misses 478system.cpu.icache.ReadReq_misses::total 1344 # number of ReadReq misses 479system.cpu.icache.demand_misses::cpu.inst 1344 # number of demand (read+write) misses 480system.cpu.icache.demand_misses::total 1344 # number of demand (read+write) misses 481system.cpu.icache.overall_misses::cpu.inst 1344 # number of overall misses 482system.cpu.icache.overall_misses::total 1344 # number of overall misses 483system.cpu.icache.ReadReq_miss_latency::cpu.inst 65684000 # number of ReadReq miss cycles 484system.cpu.icache.ReadReq_miss_latency::total 65684000 # number of ReadReq miss cycles 485system.cpu.icache.demand_miss_latency::cpu.inst 65684000 # number of demand (read+write) miss cycles 486system.cpu.icache.demand_miss_latency::total 65684000 # number of demand (read+write) miss cycles 487system.cpu.icache.overall_miss_latency::cpu.inst 65684000 # number of overall miss cycles 488system.cpu.icache.overall_miss_latency::total 65684000 # number of overall miss cycles 489system.cpu.icache.ReadReq_accesses::cpu.inst 25944504 # number of ReadReq accesses(hits+misses) 490system.cpu.icache.ReadReq_accesses::total 25944504 # number of ReadReq accesses(hits+misses) 491system.cpu.icache.demand_accesses::cpu.inst 25944504 # number of demand (read+write) accesses 492system.cpu.icache.demand_accesses::total 25944504 # number of demand (read+write) accesses 493system.cpu.icache.overall_accesses::cpu.inst 25944504 # number of overall (read+write) accesses 494system.cpu.icache.overall_accesses::total 25944504 # number of overall (read+write) accesses |
| 496system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses 497system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses 498system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses 499system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses 500system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses 501system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses | 495system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses 496system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses 497system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses 498system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses 499system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses 500system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses |
| 502system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48370.836417 # average ReadReq miss latency 503system.cpu.icache.ReadReq_avg_miss_latency::total 48370.836417 # average ReadReq miss latency 504system.cpu.icache.demand_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency 505system.cpu.icache.demand_avg_miss_latency::total 48370.836417 # average overall miss latency 506system.cpu.icache.overall_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency 507system.cpu.icache.overall_avg_miss_latency::total 48370.836417 # average overall miss latency 508system.cpu.icache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked | 501system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48872.023810 # average ReadReq miss latency 502system.cpu.icache.ReadReq_avg_miss_latency::total 48872.023810 # average ReadReq miss latency 503system.cpu.icache.demand_avg_miss_latency::cpu.inst 48872.023810 # average overall miss latency 504system.cpu.icache.demand_avg_miss_latency::total 48872.023810 # average overall miss latency 505system.cpu.icache.overall_avg_miss_latency::cpu.inst 48872.023810 # average overall miss latency 506system.cpu.icache.overall_avg_miss_latency::total 48872.023810 # average overall miss latency 507system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked |
| 509system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 510system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 511system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 508system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 509system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 510system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 512system.cpu.icache.avg_blocked_cycles::no_mshrs 48.600000 # average number of cycles each access was blocked | 511system.cpu.icache.avg_blocked_cycles::no_mshrs 26.600000 # average number of cycles each access was blocked |
| 513system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 514system.cpu.icache.fast_writes 0 # number of fast writes performed 515system.cpu.icache.cache_copies 0 # number of cache copies performed | 512system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 513system.cpu.icache.fast_writes 0 # number of fast writes performed 514system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 516system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits 517system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits 518system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits 519system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits 520system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits 521system.cpu.icache.overall_mshr_hits::total 311 # number of overall MSHR hits 522system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1040 # number of ReadReq MSHR misses 523system.cpu.icache.ReadReq_mshr_misses::total 1040 # number of ReadReq MSHR misses 524system.cpu.icache.demand_mshr_misses::cpu.inst 1040 # number of demand (read+write) MSHR misses 525system.cpu.icache.demand_mshr_misses::total 1040 # number of demand (read+write) MSHR misses 526system.cpu.icache.overall_mshr_misses::cpu.inst 1040 # number of overall MSHR misses 527system.cpu.icache.overall_mshr_misses::total 1040 # number of overall MSHR misses 528system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52081000 # number of ReadReq MSHR miss cycles 529system.cpu.icache.ReadReq_mshr_miss_latency::total 52081000 # number of ReadReq MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52081000 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.demand_mshr_miss_latency::total 52081000 # number of demand (read+write) MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52081000 # number of overall MSHR miss cycles 533system.cpu.icache.overall_mshr_miss_latency::total 52081000 # number of overall MSHR miss cycles | 515system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits 516system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits 517system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits 518system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits 519system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits 520system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits 521system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1034 # number of ReadReq MSHR misses 522system.cpu.icache.ReadReq_mshr_misses::total 1034 # number of ReadReq MSHR misses 523system.cpu.icache.demand_mshr_misses::cpu.inst 1034 # number of demand (read+write) MSHR misses 524system.cpu.icache.demand_mshr_misses::total 1034 # number of demand (read+write) MSHR misses 525system.cpu.icache.overall_mshr_misses::cpu.inst 1034 # number of overall MSHR misses 526system.cpu.icache.overall_mshr_misses::total 1034 # number of overall MSHR misses 527system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51833500 # number of ReadReq MSHR miss cycles 528system.cpu.icache.ReadReq_mshr_miss_latency::total 51833500 # number of ReadReq MSHR miss cycles 529system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51833500 # number of demand (read+write) MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::total 51833500 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51833500 # number of overall MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::total 51833500 # number of overall MSHR miss cycles |
| 534system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 535system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 536system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 537system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 538system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 539system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 533system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 534system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 535system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 536system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 537system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 538system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50077.884615 # average ReadReq mshr miss latency 541system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50077.884615 # average ReadReq mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency 543system.cpu.icache.demand_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency 545system.cpu.icache.overall_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency | 539system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50129.110251 # average ReadReq mshr miss latency 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50129.110251 # average ReadReq mshr miss latency 541system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50129.110251 # average overall mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::total 50129.110251 # average overall mshr miss latency 543system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50129.110251 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::total 50129.110251 # average overall mshr miss latency |
| 546system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 545system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 547system.cpu.l2cache.replacements 488 # number of replacements 548system.cpu.l2cache.tagsinuse 20806.359941 # Cycle average of tags in use 549system.cpu.l2cache.total_refs 4028768 # Total number of references to valid blocks. 550system.cpu.l2cache.sampled_refs 30421 # Sample count of references to valid blocks. 551system.cpu.l2cache.avg_refs 132.433779 # Average number of references to valid blocks. | 546system.cpu.l2cache.replacements 480 # number of replacements 547system.cpu.l2cache.tagsinuse 20802.892196 # Cycle average of tags in use 548system.cpu.l2cache.total_refs 4028440 # Total number of references to valid blocks. 549system.cpu.l2cache.sampled_refs 30411 # Sample count of references to valid blocks. 550system.cpu.l2cache.avg_refs 132.466542 # Average number of references to valid blocks. |
| 552system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 551system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 553system.cpu.l2cache.occ_blocks::writebacks 19869.947946 # Average occupied blocks per requestor 554system.cpu.l2cache.occ_blocks::cpu.inst 692.491887 # Average occupied blocks per requestor 555system.cpu.l2cache.occ_blocks::cpu.data 243.920108 # Average occupied blocks per requestor 556system.cpu.l2cache.occ_percent::writebacks 0.606383 # Average percentage of cache occupancy 557system.cpu.l2cache.occ_percent::cpu.inst 0.021133 # Average percentage of cache occupancy 558system.cpu.l2cache.occ_percent::cpu.data 0.007444 # Average percentage of cache occupancy 559system.cpu.l2cache.occ_percent::total 0.634960 # Average percentage of cache occupancy 560system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 561system.cpu.l2cache.ReadReq_hits::cpu.data 1993518 # number of ReadReq hits 562system.cpu.l2cache.ReadReq_hits::total 1993538 # number of ReadReq hits 563system.cpu.l2cache.Writeback_hits::writebacks 2066432 # number of Writeback hits 564system.cpu.l2cache.Writeback_hits::total 2066432 # number of Writeback hits 565system.cpu.l2cache.ReadExReq_hits::cpu.data 53227 # number of ReadExReq hits 566system.cpu.l2cache.ReadExReq_hits::total 53227 # number of ReadExReq hits 567system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 568system.cpu.l2cache.demand_hits::cpu.data 2046745 # number of demand (read+write) hits 569system.cpu.l2cache.demand_hits::total 2046765 # number of demand (read+write) hits 570system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 571system.cpu.l2cache.overall_hits::cpu.data 2046745 # number of overall hits 572system.cpu.l2cache.overall_hits::total 2046765 # number of overall hits 573system.cpu.l2cache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses 574system.cpu.l2cache.ReadReq_misses::cpu.data 424 # number of ReadReq misses 575system.cpu.l2cache.ReadReq_misses::total 1443 # number of ReadReq misses | 552system.cpu.l2cache.occ_blocks::writebacks 19867.143947 # Average occupied blocks per requestor 553system.cpu.l2cache.occ_blocks::cpu.inst 689.298857 # Average occupied blocks per requestor 554system.cpu.l2cache.occ_blocks::cpu.data 246.449393 # Average occupied blocks per requestor 555system.cpu.l2cache.occ_percent::writebacks 0.606297 # Average percentage of cache occupancy 556system.cpu.l2cache.occ_percent::cpu.inst 0.021036 # Average percentage of cache occupancy 557system.cpu.l2cache.occ_percent::cpu.data 0.007521 # Average percentage of cache occupancy 558system.cpu.l2cache.occ_percent::total 0.634854 # Average percentage of cache occupancy 559system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 560system.cpu.l2cache.ReadReq_hits::cpu.data 1993529 # number of ReadReq hits 561system.cpu.l2cache.ReadReq_hits::total 1993545 # number of ReadReq hits 562system.cpu.l2cache.Writeback_hits::writebacks 2066104 # number of Writeback hits 563system.cpu.l2cache.Writeback_hits::total 2066104 # number of Writeback hits 564system.cpu.l2cache.ReadExReq_hits::cpu.data 53248 # number of ReadExReq hits 565system.cpu.l2cache.ReadExReq_hits::total 53248 # number of ReadExReq hits 566system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 567system.cpu.l2cache.demand_hits::cpu.data 2046777 # number of demand (read+write) hits 568system.cpu.l2cache.demand_hits::total 2046793 # number of demand (read+write) hits 569system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 570system.cpu.l2cache.overall_hits::cpu.data 2046777 # number of overall hits 571system.cpu.l2cache.overall_hits::total 2046793 # number of overall hits 572system.cpu.l2cache.ReadReq_misses::cpu.inst 1017 # number of ReadReq misses 573system.cpu.l2cache.ReadReq_misses::cpu.data 417 # number of ReadReq misses 574system.cpu.l2cache.ReadReq_misses::total 1434 # number of ReadReq misses |
| 576system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 577system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses | 575system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 576system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses |
| 578system.cpu.l2cache.ReadExReq_misses::cpu.data 29001 # number of ReadExReq misses 579system.cpu.l2cache.ReadExReq_misses::total 29001 # number of ReadExReq misses 580system.cpu.l2cache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses 581system.cpu.l2cache.demand_misses::cpu.data 29425 # number of demand (read+write) misses 582system.cpu.l2cache.demand_misses::total 30444 # number of demand (read+write) misses 583system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses 584system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses 585system.cpu.l2cache.overall_misses::total 30444 # number of overall misses 586system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50833500 # number of ReadReq miss cycles 587system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21223000 # number of ReadReq miss cycles 588system.cpu.l2cache.ReadReq_miss_latency::total 72056500 # number of ReadReq miss cycles 589system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199120000 # number of ReadExReq miss cycles 590system.cpu.l2cache.ReadExReq_miss_latency::total 1199120000 # number of ReadExReq miss cycles 591system.cpu.l2cache.demand_miss_latency::cpu.inst 50833500 # number of demand (read+write) miss cycles 592system.cpu.l2cache.demand_miss_latency::cpu.data 1220343000 # number of demand (read+write) miss cycles 593system.cpu.l2cache.demand_miss_latency::total 1271176500 # number of demand (read+write) miss cycles 594system.cpu.l2cache.overall_miss_latency::cpu.inst 50833500 # number of overall miss cycles 595system.cpu.l2cache.overall_miss_latency::cpu.data 1220343000 # number of overall miss cycles 596system.cpu.l2cache.overall_miss_latency::total 1271176500 # number of overall miss cycles 597system.cpu.l2cache.ReadReq_accesses::cpu.inst 1039 # number of ReadReq accesses(hits+misses) 598system.cpu.l2cache.ReadReq_accesses::cpu.data 1993942 # number of ReadReq accesses(hits+misses) 599system.cpu.l2cache.ReadReq_accesses::total 1994981 # number of ReadReq accesses(hits+misses) 600system.cpu.l2cache.Writeback_accesses::writebacks 2066432 # number of Writeback accesses(hits+misses) 601system.cpu.l2cache.Writeback_accesses::total 2066432 # number of Writeback accesses(hits+misses) | 577system.cpu.l2cache.ReadExReq_misses::cpu.data 29000 # number of ReadExReq misses 578system.cpu.l2cache.ReadExReq_misses::total 29000 # number of ReadExReq misses 579system.cpu.l2cache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses 580system.cpu.l2cache.demand_misses::cpu.data 29417 # number of demand (read+write) misses 581system.cpu.l2cache.demand_misses::total 30434 # number of demand (read+write) misses 582system.cpu.l2cache.overall_misses::cpu.inst 1017 # number of overall misses 583system.cpu.l2cache.overall_misses::cpu.data 29417 # number of overall misses 584system.cpu.l2cache.overall_misses::total 30434 # number of overall misses 585system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50633000 # number of ReadReq miss cycles 586system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21040000 # number of ReadReq miss cycles 587system.cpu.l2cache.ReadReq_miss_latency::total 71673000 # number of ReadReq miss cycles 588system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1219810500 # number of ReadExReq miss cycles 589system.cpu.l2cache.ReadExReq_miss_latency::total 1219810500 # number of ReadExReq miss cycles 590system.cpu.l2cache.demand_miss_latency::cpu.inst 50633000 # number of demand (read+write) miss cycles 591system.cpu.l2cache.demand_miss_latency::cpu.data 1240850500 # number of demand (read+write) miss cycles 592system.cpu.l2cache.demand_miss_latency::total 1291483500 # number of demand (read+write) miss cycles 593system.cpu.l2cache.overall_miss_latency::cpu.inst 50633000 # number of overall miss cycles 594system.cpu.l2cache.overall_miss_latency::cpu.data 1240850500 # number of overall miss cycles 595system.cpu.l2cache.overall_miss_latency::total 1291483500 # number of overall miss cycles 596system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033 # number of ReadReq accesses(hits+misses) 597system.cpu.l2cache.ReadReq_accesses::cpu.data 1993946 # number of ReadReq accesses(hits+misses) 598system.cpu.l2cache.ReadReq_accesses::total 1994979 # number of ReadReq accesses(hits+misses) 599system.cpu.l2cache.Writeback_accesses::writebacks 2066104 # number of Writeback accesses(hits+misses) 600system.cpu.l2cache.Writeback_accesses::total 2066104 # number of Writeback accesses(hits+misses) |
| 602system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 603system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) | 601system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 602system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) |
| 604system.cpu.l2cache.ReadExReq_accesses::cpu.data 82228 # number of ReadExReq accesses(hits+misses) 605system.cpu.l2cache.ReadExReq_accesses::total 82228 # number of ReadExReq accesses(hits+misses) 606system.cpu.l2cache.demand_accesses::cpu.inst 1039 # number of demand (read+write) accesses 607system.cpu.l2cache.demand_accesses::cpu.data 2076170 # number of demand (read+write) accesses 608system.cpu.l2cache.demand_accesses::total 2077209 # number of demand (read+write) accesses 609system.cpu.l2cache.overall_accesses::cpu.inst 1039 # number of overall (read+write) accesses 610system.cpu.l2cache.overall_accesses::cpu.data 2076170 # number of overall (read+write) accesses 611system.cpu.l2cache.overall_accesses::total 2077209 # number of overall (read+write) accesses 612system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.980751 # miss rate for ReadReq accesses 613system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000213 # miss rate for ReadReq accesses 614system.cpu.l2cache.ReadReq_miss_rate::total 0.000723 # miss rate for ReadReq accesses | 603system.cpu.l2cache.ReadExReq_accesses::cpu.data 82248 # number of ReadExReq accesses(hits+misses) 604system.cpu.l2cache.ReadExReq_accesses::total 82248 # number of ReadExReq accesses(hits+misses) 605system.cpu.l2cache.demand_accesses::cpu.inst 1033 # number of demand (read+write) accesses 606system.cpu.l2cache.demand_accesses::cpu.data 2076194 # number of demand (read+write) accesses 607system.cpu.l2cache.demand_accesses::total 2077227 # number of demand (read+write) accesses 608system.cpu.l2cache.overall_accesses::cpu.inst 1033 # number of overall (read+write) accesses 609system.cpu.l2cache.overall_accesses::cpu.data 2076194 # number of overall (read+write) accesses 610system.cpu.l2cache.overall_accesses::total 2077227 # number of overall (read+write) accesses 611system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984511 # miss rate for ReadReq accesses 612system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000209 # miss rate for ReadReq accesses 613system.cpu.l2cache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses |
| 615system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 616system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 614system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 615system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 617system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352690 # miss rate for ReadExReq accesses 618system.cpu.l2cache.ReadExReq_miss_rate::total 0.352690 # miss rate for ReadExReq accesses 619system.cpu.l2cache.demand_miss_rate::cpu.inst 0.980751 # miss rate for demand accesses 620system.cpu.l2cache.demand_miss_rate::cpu.data 0.014173 # miss rate for demand accesses 621system.cpu.l2cache.demand_miss_rate::total 0.014656 # miss rate for demand accesses 622system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980751 # miss rate for overall accesses 623system.cpu.l2cache.overall_miss_rate::cpu.data 0.014173 # miss rate for overall accesses 624system.cpu.l2cache.overall_miss_rate::total 0.014656 # miss rate for overall accesses 625system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49885.672228 # average ReadReq miss latency 626system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50054.245283 # average ReadReq miss latency 627system.cpu.l2cache.ReadReq_avg_miss_latency::total 49935.204435 # average ReadReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41347.539740 # average ReadExReq miss latency 629system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41347.539740 # average ReadExReq miss latency 630system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency 631system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency 632system.cpu.l2cache.demand_avg_miss_latency::total 41754.582184 # average overall miss latency 633system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency 635system.cpu.l2cache.overall_avg_miss_latency::total 41754.582184 # average overall miss latency | 616system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352592 # miss rate for ReadExReq accesses 617system.cpu.l2cache.ReadExReq_miss_rate::total 0.352592 # miss rate for ReadExReq accesses 618system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984511 # miss rate for demand accesses 619system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses 620system.cpu.l2cache.demand_miss_rate::total 0.014651 # miss rate for demand accesses 621system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984511 # miss rate for overall accesses 622system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses 623system.cpu.l2cache.overall_miss_rate::total 0.014651 # miss rate for overall accesses 624system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49786.627335 # average ReadReq miss latency 625system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50455.635492 # average ReadReq miss latency 626system.cpu.l2cache.ReadReq_avg_miss_latency::total 49981.171548 # average ReadReq miss latency 627system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42062.431034 # average ReadExReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42062.431034 # average ReadExReq miss latency 629system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency 630system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency 631system.cpu.l2cache.demand_avg_miss_latency::total 42435.549057 # average overall miss latency 632system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency 633system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::total 42435.549057 # average overall miss latency |
| 636system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 641system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.l2cache.fast_writes 0 # number of fast writes performed 643system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 635system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 636system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 639system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 640system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 641system.cpu.l2cache.fast_writes 0 # number of fast writes performed 642system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 644system.cpu.l2cache.writebacks::writebacks 174 # number of writebacks 645system.cpu.l2cache.writebacks::total 174 # number of writebacks 646system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses 647system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 424 # number of ReadReq MSHR misses 648system.cpu.l2cache.ReadReq_mshr_misses::total 1443 # number of ReadReq MSHR misses | 643system.cpu.l2cache.writebacks::writebacks 169 # number of writebacks 644system.cpu.l2cache.writebacks::total 169 # number of writebacks 645system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1017 # number of ReadReq MSHR misses 646system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses 647system.cpu.l2cache.ReadReq_mshr_misses::total 1434 # number of ReadReq MSHR misses |
| 649system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 650system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses | 648system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 649system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses |
| 651system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29001 # number of ReadExReq MSHR misses 652system.cpu.l2cache.ReadExReq_mshr_misses::total 29001 # number of ReadExReq MSHR misses 653system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.demand_mshr_misses::cpu.data 29425 # number of demand (read+write) MSHR misses 655system.cpu.l2cache.demand_mshr_misses::total 30444 # number of demand (read+write) MSHR misses 656system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses 657system.cpu.l2cache.overall_mshr_misses::cpu.data 29425 # number of overall MSHR misses 658system.cpu.l2cache.overall_mshr_misses::total 30444 # number of overall MSHR misses 659system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38000083 # number of ReadReq MSHR miss cycles 660system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880649 # number of ReadReq MSHR miss cycles 661system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53880732 # number of ReadReq MSHR miss cycles | 650system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29000 # number of ReadExReq MSHR misses 651system.cpu.l2cache.ReadExReq_mshr_misses::total 29000 # number of ReadExReq MSHR misses 652system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses 653system.cpu.l2cache.demand_mshr_misses::cpu.data 29417 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.demand_mshr_misses::total 30434 # number of demand (read+write) MSHR misses 655system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses 656system.cpu.l2cache.overall_mshr_misses::cpu.data 29417 # number of overall MSHR misses 657system.cpu.l2cache.overall_mshr_misses::total 30434 # number of overall MSHR misses 658system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38011868 # number of ReadReq MSHR miss cycles 659system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15869892 # number of ReadReq MSHR miss cycles 660system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53881760 # number of ReadReq MSHR miss cycles |
| 662system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles 663system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles | 661system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles 662system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles |
| 664system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824195395 # number of ReadExReq MSHR miss cycles 665system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824195395 # number of ReadExReq MSHR miss cycles 666system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38000083 # number of demand (read+write) MSHR miss cycles 667system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840076044 # number of demand (read+write) MSHR miss cycles 668system.cpu.l2cache.demand_mshr_miss_latency::total 878076127 # number of demand (read+write) MSHR miss cycles 669system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38000083 # number of overall MSHR miss cycles 670system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840076044 # number of overall MSHR miss cycles 671system.cpu.l2cache.overall_mshr_miss_latency::total 878076127 # number of overall MSHR miss cycles 672system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for ReadReq accesses 673system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadReq accesses 674system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000723 # mshr miss rate for ReadReq accesses | 663system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862092136 # number of ReadExReq MSHR miss cycles 664system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862092136 # number of ReadExReq MSHR miss cycles 665system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38011868 # number of demand (read+write) MSHR miss cycles 666system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 877962028 # number of demand (read+write) MSHR miss cycles 667system.cpu.l2cache.demand_mshr_miss_latency::total 915973896 # number of demand (read+write) MSHR miss cycles 668system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38011868 # number of overall MSHR miss cycles 669system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 877962028 # number of overall MSHR miss cycles 670system.cpu.l2cache.overall_mshr_miss_latency::total 915973896 # number of overall MSHR miss cycles 671system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for ReadReq accesses 672system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000209 # mshr miss rate for ReadReq accesses 673system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses |
| 675system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 676system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 674system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 675system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 677system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352690 # mshr miss rate for ReadExReq accesses 678system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352690 # mshr miss rate for ReadExReq accesses 679system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for demand accesses 680system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for demand accesses 681system.cpu.l2cache.demand_mshr_miss_rate::total 0.014656 # mshr miss rate for demand accesses 682system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for overall accesses 683system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for overall accesses 684system.cpu.l2cache.overall_mshr_miss_rate::total 0.014656 # mshr miss rate for overall accesses 685system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.543670 # average ReadReq mshr miss latency 686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37454.360849 # average ReadReq mshr miss latency 687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37339.384615 # average ReadReq mshr miss latency | 676system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352592 # mshr miss rate for ReadExReq accesses 677system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352592 # mshr miss rate for ReadExReq accesses 678system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for demand accesses 679system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses 680system.cpu.l2cache.demand_mshr_miss_rate::total 0.014651 # mshr miss rate for demand accesses 681system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for overall accesses 682system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses 683system.cpu.l2cache.overall_mshr_miss_rate::total 0.014651 # mshr miss rate for overall accesses 684system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37376.468043 # average ReadReq mshr miss latency 685system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38057.294964 # average ReadReq mshr miss latency 686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37574.449093 # average ReadReq mshr miss latency |
| 688system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 689system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency | 687system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 688system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency |
| 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28419.550878 # average ReadExReq mshr miss latency 691system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28419.550878 # average ReadExReq mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency 694system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency 697system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency | 689system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29727.315034 # average ReadExReq mshr miss latency 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29727.315034 # average ReadExReq mshr miss latency 691system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency |
| 698system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 697system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 699system.cpu.dcache.replacements 2072071 # number of replacements 700system.cpu.dcache.tagsinuse 4072.565350 # Cycle average of tags in use 701system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks. 702system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks. 703system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks. 704system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit. 705system.cpu.dcache.occ_blocks::cpu.data 4072.565350 # Average occupied blocks per requestor 706system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy 707system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy 708system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits 709system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits 710system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits 711system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits 712system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits 713system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits 714system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits 715system.cpu.dcache.overall_hits::total 71946748 # number of overall hits 716system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses 717system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses 718system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses 719system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses 720system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses 721system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses 722system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses 723system.cpu.dcache.overall_misses::total 2723462 # number of overall misses 724system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321024000 # number of ReadReq miss cycles 725system.cpu.dcache.ReadReq_miss_latency::total 31321024000 # number of ReadReq miss cycles 726system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles 727system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles 728system.cpu.dcache.demand_miss_latency::cpu.data 33409132498 # number of demand (read+write) miss cycles 729system.cpu.dcache.demand_miss_latency::total 33409132498 # number of demand (read+write) miss cycles 730system.cpu.dcache.overall_miss_latency::cpu.data 33409132498 # number of overall miss cycles 731system.cpu.dcache.overall_miss_latency::total 33409132498 # number of overall miss cycles 732system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses) 733system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses) | 698system.cpu.dcache.replacements 2072095 # number of replacements 699system.cpu.dcache.tagsinuse 4072.471954 # Cycle average of tags in use 700system.cpu.dcache.total_refs 71964033 # Total number of references to valid blocks. 701system.cpu.dcache.sampled_refs 2076191 # Sample count of references to valid blocks. 702system.cpu.dcache.avg_refs 34.661567 # Average number of references to valid blocks. 703system.cpu.dcache.warmup_cycle 21154875000 # Cycle when the warmup percentage was hit. 704system.cpu.dcache.occ_blocks::cpu.data 4072.471954 # Average occupied blocks per requestor 705system.cpu.dcache.occ_percent::cpu.data 0.994256 # Average percentage of cache occupancy 706system.cpu.dcache.occ_percent::total 0.994256 # Average percentage of cache occupancy 707system.cpu.dcache.ReadReq_hits::cpu.data 40622570 # number of ReadReq hits 708system.cpu.dcache.ReadReq_hits::total 40622570 # number of ReadReq hits 709system.cpu.dcache.WriteReq_hits::cpu.data 31341456 # number of WriteReq hits 710system.cpu.dcache.WriteReq_hits::total 31341456 # number of WriteReq hits 711system.cpu.dcache.demand_hits::cpu.data 71964026 # number of demand (read+write) hits 712system.cpu.dcache.demand_hits::total 71964026 # number of demand (read+write) hits 713system.cpu.dcache.overall_hits::cpu.data 71964026 # number of overall hits 714system.cpu.dcache.overall_hits::total 71964026 # number of overall hits 715system.cpu.dcache.ReadReq_misses::cpu.data 2625435 # number of ReadReq misses 716system.cpu.dcache.ReadReq_misses::total 2625435 # number of ReadReq misses 717system.cpu.dcache.WriteReq_misses::cpu.data 98296 # number of WriteReq misses 718system.cpu.dcache.WriteReq_misses::total 98296 # number of WriteReq misses 719system.cpu.dcache.demand_misses::cpu.data 2723731 # number of demand (read+write) misses 720system.cpu.dcache.demand_misses::total 2723731 # number of demand (read+write) misses 721system.cpu.dcache.overall_misses::cpu.data 2723731 # number of overall misses 722system.cpu.dcache.overall_misses::total 2723731 # number of overall misses 723system.cpu.dcache.ReadReq_miss_latency::cpu.data 31317831000 # number of ReadReq miss cycles 724system.cpu.dcache.ReadReq_miss_latency::total 31317831000 # number of ReadReq miss cycles 725system.cpu.dcache.WriteReq_miss_latency::cpu.data 2109058498 # number of WriteReq miss cycles 726system.cpu.dcache.WriteReq_miss_latency::total 2109058498 # number of WriteReq miss cycles 727system.cpu.dcache.demand_miss_latency::cpu.data 33426889498 # number of demand (read+write) miss cycles 728system.cpu.dcache.demand_miss_latency::total 33426889498 # number of demand (read+write) miss cycles 729system.cpu.dcache.overall_miss_latency::cpu.data 33426889498 # number of overall miss cycles 730system.cpu.dcache.overall_miss_latency::total 33426889498 # number of overall miss cycles 731system.cpu.dcache.ReadReq_accesses::cpu.data 43248005 # number of ReadReq accesses(hits+misses) 732system.cpu.dcache.ReadReq_accesses::total 43248005 # number of ReadReq accesses(hits+misses) |
| 734system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 735system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) | 733system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 734system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) |
| 736system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses 737system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses 738system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses 739system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses 740system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses 741system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses | 735system.cpu.dcache.demand_accesses::cpu.data 74687757 # number of demand (read+write) accesses 736system.cpu.dcache.demand_accesses::total 74687757 # number of demand (read+write) accesses 737system.cpu.dcache.overall_accesses::cpu.data 74687757 # number of overall (read+write) accesses 738system.cpu.dcache.overall_accesses::total 74687757 # number of overall (read+write) accesses 739system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060706 # miss rate for ReadReq accesses 740system.cpu.dcache.ReadReq_miss_rate::total 0.060706 # miss rate for ReadReq accesses |
| 742system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses 743system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses | 741system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses 742system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses |
| 744system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses 745system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses 746system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses 747system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses 748system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.973272 # average ReadReq miss latency 749system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.973272 # average ReadReq miss latency 750system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency 751system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency 752system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency 753system.cpu.dcache.demand_avg_miss_latency::total 12267.155737 # average overall miss latency 754system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency 755system.cpu.dcache.overall_avg_miss_latency::total 12267.155737 # average overall miss latency 756system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked | 743system.cpu.dcache.demand_miss_rate::cpu.data 0.036468 # miss rate for demand accesses 744system.cpu.dcache.demand_miss_rate::total 0.036468 # miss rate for demand accesses 745system.cpu.dcache.overall_miss_rate::cpu.data 0.036468 # miss rate for overall accesses 746system.cpu.dcache.overall_miss_rate::total 0.036468 # miss rate for overall accesses 747system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.625542 # average ReadReq miss latency 748system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.625542 # average ReadReq miss latency 749system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21456.198604 # average WriteReq miss latency 750system.cpu.dcache.WriteReq_avg_miss_latency::total 21456.198604 # average WriteReq miss latency 751system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency 752system.cpu.dcache.demand_avg_miss_latency::total 12272.463580 # average overall miss latency 753system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency 754system.cpu.dcache.overall_avg_miss_latency::total 12272.463580 # average overall miss latency 755system.cpu.dcache.blocked_cycles::no_mshrs 32211 # number of cycles access was blocked |
| 757system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 756system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 758system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked | 757system.cpu.dcache.blocked::no_mshrs 9475 # number of cycles access was blocked |
| 759system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 758system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 760system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked | 759system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.399578 # average number of cycles each access was blocked |
| 761system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 762system.cpu.dcache.fast_writes 0 # number of fast writes performed 763system.cpu.dcache.cache_copies 0 # number of cache copies performed | 760system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 761system.cpu.dcache.fast_writes 0 # number of fast writes performed 762system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 764system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks 765system.cpu.dcache.writebacks::total 2066432 # number of writebacks 766system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits 767system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits | 763system.cpu.dcache.writebacks::writebacks 2066104 # number of writebacks 764system.cpu.dcache.writebacks::total 2066104 # number of writebacks 765system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631384 # number of ReadReq MSHR hits 766system.cpu.dcache.ReadReq_mshr_hits::total 631384 # number of ReadReq MSHR hits |
| 768system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits 769system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits | 767system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits 768system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits |
| 770system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits 771system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits 772system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits 773system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits 774system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses 775system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses 776system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses 777system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses 778system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses 779system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses 780system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses 781system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses 782system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983434000 # number of ReadReq MSHR miss cycles 783system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983434000 # number of ReadReq MSHR miss cycles 784system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles 785system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles 786system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285998 # number of demand (read+write) MSHR miss cycles 787system.cpu.dcache.demand_mshr_miss_latency::total 23796285998 # number of demand (read+write) MSHR miss cycles 788system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285998 # number of overall MSHR miss cycles 789system.cpu.dcache.overall_mshr_miss_latency::total 23796285998 # number of overall MSHR miss cycles 790system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses 791system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses 792system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses 793system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses 794system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses 795system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses 796system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses 797system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531518 # average ReadReq mshr miss latency 799system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531518 # average ReadReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency 801system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency 802system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency 803system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency 804system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency 805system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency | 769system.cpu.dcache.demand_mshr_hits::cpu.data 647536 # number of demand (read+write) MSHR hits 770system.cpu.dcache.demand_mshr_hits::total 647536 # number of demand (read+write) MSHR hits 771system.cpu.dcache.overall_mshr_hits::cpu.data 647536 # number of overall MSHR hits 772system.cpu.dcache.overall_mshr_hits::total 647536 # number of overall MSHR hits 773system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994051 # number of ReadReq MSHR misses 774system.cpu.dcache.ReadReq_mshr_misses::total 1994051 # number of ReadReq MSHR misses 775system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82144 # number of WriteReq MSHR misses 776system.cpu.dcache.WriteReq_mshr_misses::total 82144 # number of WriteReq MSHR misses 777system.cpu.dcache.demand_mshr_misses::cpu.data 2076195 # number of demand (read+write) MSHR misses 778system.cpu.dcache.demand_mshr_misses::total 2076195 # number of demand (read+write) MSHR misses 779system.cpu.dcache.overall_mshr_misses::cpu.data 2076195 # number of overall MSHR misses 780system.cpu.dcache.overall_mshr_misses::total 2076195 # number of overall MSHR misses 781system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987856500 # number of ReadReq MSHR miss cycles 782system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987856500 # number of ReadReq MSHR miss cycles 783system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833812998 # number of WriteReq MSHR miss cycles 784system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833812998 # number of WriteReq MSHR miss cycles 785system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23821669498 # number of demand (read+write) MSHR miss cycles 786system.cpu.dcache.demand_mshr_miss_latency::total 23821669498 # number of demand (read+write) MSHR miss cycles 787system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23821669498 # number of overall MSHR miss cycles 788system.cpu.dcache.overall_mshr_miss_latency::total 23821669498 # number of overall MSHR miss cycles 789system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046107 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046107 # mshr miss rate for ReadReq accesses 791system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses 793system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for demand accesses 794system.cpu.dcache.demand_mshr_miss_rate::total 0.027798 # mshr miss rate for demand accesses 795system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for overall accesses 796system.cpu.dcache.overall_mshr_miss_rate::total 0.027798 # mshr miss rate for overall accesses 797system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.727250 # average ReadReq mshr miss latency 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.727250 # average ReadReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.369376 # average WriteReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.369376 # average WriteReq mshr miss latency 801system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency 802system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency 803system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency 804system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency |
| 806system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 807 808---------- End Simulation Statistics ---------- | 805system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 806 807---------- End Simulation Statistics ---------- |