| stats.txt (9373:26ba525347fe) | stats.txt (9449:56610ab73040) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.065983 # Number of seconds simulated 4sim_ticks 65982862500 # Number of ticks simulated 5final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.065983 # Number of seconds simulated 4sim_ticks 65982862500 # Number of ticks simulated 5final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 71115 # Simulator instruction rate (inst/s) 8host_op_rate 125222 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 29700736 # Simulator tick rate (ticks/s) 10host_mem_usage 413360 # Number of bytes of host memory used 11host_seconds 2221.59 # Real time elapsed on the host | 7host_inst_rate 39069 # Simulator instruction rate (inst/s) 8host_op_rate 68794 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16316772 # Simulator tick rate (ticks/s) 10host_mem_usage 376348 # Number of bytes of host memory used 11host_seconds 4043.87 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192463 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1948288 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 11136 # Number of bytes written to this memory --- 52 unchanged lines hidden (view full) --- 72system.physmem.perBankWrReqs::10 14 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 11 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192463 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1948288 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 11136 # Number of bytes written to this memory --- 52 unchanged lines hidden (view full) --- 72system.physmem.perBankWrReqs::10 14 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 11 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 80system.physmem.totGap 65982842000 # Total gap between requests | 80system.physmem.totGap 65982843000 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 30444 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 77 unchanged lines hidden (view full) --- 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 30444 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 77 unchanged lines hidden (view full) --- 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 174system.physmem.totQLat 10444357 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 571602357 # Sum of mem lat for all requests | 174system.physmem.totQLat 10445857 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 571603857 # Sum of mem lat for all requests |
| 176system.physmem.totBusLat 121544000 # Total cycles spent in databus access 177system.physmem.totBankLat 439614000 # Total cycles spent in bank access | 176system.physmem.totBusLat 121544000 # Total cycles spent in databus access 177system.physmem.totBankLat 439614000 # Total cycles spent in bank access |
| 178system.physmem.avgQLat 343.72 # Average queueing delay per request | 178system.physmem.avgQLat 343.77 # Average queueing delay per request |
| 179system.physmem.avgBankLat 14467.65 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request | 179system.physmem.avgBankLat 14467.65 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 181system.physmem.avgMemAccLat 18811.37 # Average memory access latency | 181system.physmem.avgMemAccLat 18811.42 # Average memory access latency |
| 182system.physmem.avgRdBW 29.53 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 29.53 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 0.17 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.19 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.01 # Average read queue length over time 189system.physmem.avgWrQLen 11.24 # Average write queue length over time 190system.physmem.readRowHits 29640 # Number of row buffer hits during reads 191system.physmem.writeRowHits 45 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes | 182system.physmem.avgRdBW 29.53 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 29.53 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 0.17 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.19 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.01 # Average read queue length over time 189system.physmem.avgWrQLen 11.24 # Average write queue length over time 190system.physmem.readRowHits 29640 # Number of row buffer hits during reads 191system.physmem.writeRowHits 45 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes |
| 194system.physmem.avgGap 2155034.36 # Average gap between requests | 194system.physmem.avgGap 2155034.39 # Average gap between requests |
| 195system.cpu.workload.num_syscalls 444 # Number of system calls 196system.cpu.numCycles 131965726 # number of cpu cycles simulated 197system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 198system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 199system.cpu.BPredUnit.lookups 34537566 # Number of BP lookups 200system.cpu.BPredUnit.condPredicted 34537566 # Number of conditional branches predicted 201system.cpu.BPredUnit.condIncorrect 909846 # Number of conditional branches incorrect 202system.cpu.BPredUnit.BTBLookups 24744786 # Number of BTB lookups 203system.cpu.BPredUnit.BTBHits 24642661 # Number of BTB hits 204system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 205system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 206system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. | 195system.cpu.workload.num_syscalls 444 # Number of system calls 196system.cpu.numCycles 131965726 # number of cpu cycles simulated 197system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 198system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 199system.cpu.BPredUnit.lookups 34537566 # Number of BP lookups 200system.cpu.BPredUnit.condPredicted 34537566 # Number of conditional branches predicted 201system.cpu.BPredUnit.condIncorrect 909846 # Number of conditional branches incorrect 202system.cpu.BPredUnit.BTBLookups 24744786 # Number of BTB lookups 203system.cpu.BPredUnit.BTBHits 24642661 # Number of BTB hits 204system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 205system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 206system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 207system.cpu.fetch.icacheStallCycles 26601820 # Number of cycles fetch is stalled on an Icache miss | 207system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss |
| 208system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed 209system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered 210system.cpu.fetch.predictedBranches 24642661 # Number of branches that fetch has predicted taken 211system.cpu.fetch.Cycles 56492855 # Number of cycles fetch has run and was not squashing or blocked 212system.cpu.fetch.SquashCycles 6109576 # Number of cycles fetch has spent squashing 213system.cpu.fetch.BlockedCycles 43628030 # Number of cycles fetch has spent blocked | 208system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed 209system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered 210system.cpu.fetch.predictedBranches 24642661 # Number of branches that fetch has predicted taken 211system.cpu.fetch.Cycles 56492855 # Number of cycles fetch has run and was not squashing or blocked 212system.cpu.fetch.SquashCycles 6109576 # Number of cycles fetch has spent squashing 213system.cpu.fetch.BlockedCycles 43628030 # Number of cycles fetch has spent blocked |
| 214system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 214system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 215system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps 216system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR | 215system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps 216system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR |
| 217system.cpu.fetch.CacheLines 25952050 # Number of cache lines fetched 218system.cpu.fetch.IcacheSquashes 188970 # Number of outstanding Icache misses that were squashed | 217system.cpu.fetch.CacheLines 25952051 # Number of cache lines fetched 218system.cpu.fetch.IcacheSquashes 188971 # Number of outstanding Icache misses that were squashed |
| 219system.cpu.fetch.rateDist::samples 131886743 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::mean 2.485312 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::stdev 3.326723 # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::0 77942049 59.10% 59.10% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::1 1996023 1.51% 60.61% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::2 2954192 2.24% 62.85% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::3 3924230 2.98% 65.83% # Number of instructions fetched each cycle (Total) --- 228 unchanged lines hidden (view full) --- 455system.cpu.ipc 1.197194 # IPC: Instructions Per Cycle 456system.cpu.ipc_total 1.197194 # IPC: Total IPC of All Threads 457system.cpu.int_regfile_reads 592820364 # number of integer regfile reads 458system.cpu.int_regfile_writes 300190131 # number of integer regfile writes 459system.cpu.fp_regfile_reads 138 # number of floating regfile reads 460system.cpu.fp_regfile_writes 78 # number of floating regfile writes 461system.cpu.misc_regfile_reads 192690356 # number of misc regfile reads 462system.cpu.icache.replacements 68 # number of replacements | 219system.cpu.fetch.rateDist::samples 131886743 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::mean 2.485312 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::stdev 3.326723 # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::0 77942049 59.10% 59.10% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::1 1996023 1.51% 60.61% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::2 2954192 2.24% 62.85% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::3 3924230 2.98% 65.83% # Number of instructions fetched each cycle (Total) --- 228 unchanged lines hidden (view full) --- 455system.cpu.ipc 1.197194 # IPC: Instructions Per Cycle 456system.cpu.ipc_total 1.197194 # IPC: Total IPC of All Threads 457system.cpu.int_regfile_reads 592820364 # number of integer regfile reads 458system.cpu.int_regfile_writes 300190131 # number of integer regfile writes 459system.cpu.fp_regfile_reads 138 # number of floating regfile reads 460system.cpu.fp_regfile_writes 78 # number of floating regfile writes 461system.cpu.misc_regfile_reads 192690356 # number of misc regfile reads 462system.cpu.icache.replacements 68 # number of replacements |
| 463system.cpu.icache.tagsinuse 836.141366 # Cycle average of tags in use | 463system.cpu.icache.tagsinuse 836.141368 # Cycle average of tags in use |
| 464system.cpu.icache.total_refs 25950700 # Total number of references to valid blocks. 465system.cpu.icache.sampled_refs 1039 # Sample count of references to valid blocks. 466system.cpu.icache.avg_refs 24976.612127 # Average number of references to valid blocks. 467system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 464system.cpu.icache.total_refs 25950700 # Total number of references to valid blocks. 465system.cpu.icache.sampled_refs 1039 # Sample count of references to valid blocks. 466system.cpu.icache.avg_refs 24976.612127 # Average number of references to valid blocks. 467system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 468system.cpu.icache.occ_blocks::cpu.inst 836.141366 # Average occupied blocks per requestor | 468system.cpu.icache.occ_blocks::cpu.inst 836.141368 # Average occupied blocks per requestor |
| 469system.cpu.icache.occ_percent::cpu.inst 0.408272 # Average percentage of cache occupancy 470system.cpu.icache.occ_percent::total 0.408272 # Average percentage of cache occupancy 471system.cpu.icache.ReadReq_hits::cpu.inst 25950700 # number of ReadReq hits 472system.cpu.icache.ReadReq_hits::total 25950700 # number of ReadReq hits 473system.cpu.icache.demand_hits::cpu.inst 25950700 # number of demand (read+write) hits 474system.cpu.icache.demand_hits::total 25950700 # number of demand (read+write) hits 475system.cpu.icache.overall_hits::cpu.inst 25950700 # number of overall hits 476system.cpu.icache.overall_hits::total 25950700 # number of overall hits | 469system.cpu.icache.occ_percent::cpu.inst 0.408272 # Average percentage of cache occupancy 470system.cpu.icache.occ_percent::total 0.408272 # Average percentage of cache occupancy 471system.cpu.icache.ReadReq_hits::cpu.inst 25950700 # number of ReadReq hits 472system.cpu.icache.ReadReq_hits::total 25950700 # number of ReadReq hits 473system.cpu.icache.demand_hits::cpu.inst 25950700 # number of demand (read+write) hits 474system.cpu.icache.demand_hits::total 25950700 # number of demand (read+write) hits 475system.cpu.icache.overall_hits::cpu.inst 25950700 # number of overall hits 476system.cpu.icache.overall_hits::total 25950700 # number of overall hits |
| 477system.cpu.icache.ReadReq_misses::cpu.inst 1350 # number of ReadReq misses 478system.cpu.icache.ReadReq_misses::total 1350 # number of ReadReq misses 479system.cpu.icache.demand_misses::cpu.inst 1350 # number of demand (read+write) misses 480system.cpu.icache.demand_misses::total 1350 # number of demand (read+write) misses 481system.cpu.icache.overall_misses::cpu.inst 1350 # number of overall misses 482system.cpu.icache.overall_misses::total 1350 # number of overall misses 483system.cpu.icache.ReadReq_miss_latency::cpu.inst 65277000 # number of ReadReq miss cycles 484system.cpu.icache.ReadReq_miss_latency::total 65277000 # number of ReadReq miss cycles 485system.cpu.icache.demand_miss_latency::cpu.inst 65277000 # number of demand (read+write) miss cycles 486system.cpu.icache.demand_miss_latency::total 65277000 # number of demand (read+write) miss cycles 487system.cpu.icache.overall_miss_latency::cpu.inst 65277000 # number of overall miss cycles 488system.cpu.icache.overall_miss_latency::total 65277000 # number of overall miss cycles 489system.cpu.icache.ReadReq_accesses::cpu.inst 25952050 # number of ReadReq accesses(hits+misses) 490system.cpu.icache.ReadReq_accesses::total 25952050 # number of ReadReq accesses(hits+misses) 491system.cpu.icache.demand_accesses::cpu.inst 25952050 # number of demand (read+write) accesses 492system.cpu.icache.demand_accesses::total 25952050 # number of demand (read+write) accesses 493system.cpu.icache.overall_accesses::cpu.inst 25952050 # number of overall (read+write) accesses 494system.cpu.icache.overall_accesses::total 25952050 # number of overall (read+write) accesses | 477system.cpu.icache.ReadReq_misses::cpu.inst 1351 # number of ReadReq misses 478system.cpu.icache.ReadReq_misses::total 1351 # number of ReadReq misses 479system.cpu.icache.demand_misses::cpu.inst 1351 # number of demand (read+write) misses 480system.cpu.icache.demand_misses::total 1351 # number of demand (read+write) misses 481system.cpu.icache.overall_misses::cpu.inst 1351 # number of overall misses 482system.cpu.icache.overall_misses::total 1351 # number of overall misses 483system.cpu.icache.ReadReq_miss_latency::cpu.inst 65349000 # number of ReadReq miss cycles 484system.cpu.icache.ReadReq_miss_latency::total 65349000 # number of ReadReq miss cycles 485system.cpu.icache.demand_miss_latency::cpu.inst 65349000 # number of demand (read+write) miss cycles 486system.cpu.icache.demand_miss_latency::total 65349000 # number of demand (read+write) miss cycles 487system.cpu.icache.overall_miss_latency::cpu.inst 65349000 # number of overall miss cycles 488system.cpu.icache.overall_miss_latency::total 65349000 # number of overall miss cycles 489system.cpu.icache.ReadReq_accesses::cpu.inst 25952051 # number of ReadReq accesses(hits+misses) 490system.cpu.icache.ReadReq_accesses::total 25952051 # number of ReadReq accesses(hits+misses) 491system.cpu.icache.demand_accesses::cpu.inst 25952051 # number of demand (read+write) accesses 492system.cpu.icache.demand_accesses::total 25952051 # number of demand (read+write) accesses 493system.cpu.icache.overall_accesses::cpu.inst 25952051 # number of overall (read+write) accesses 494system.cpu.icache.overall_accesses::total 25952051 # number of overall (read+write) accesses |
| 495system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses 496system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses 497system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses 498system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses 499system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses 500system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses | 495system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses 496system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses 497system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses 498system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses 499system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses 500system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses |
| 501system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48353.333333 # average ReadReq miss latency 502system.cpu.icache.ReadReq_avg_miss_latency::total 48353.333333 # average ReadReq miss latency 503system.cpu.icache.demand_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency 504system.cpu.icache.demand_avg_miss_latency::total 48353.333333 # average overall miss latency 505system.cpu.icache.overall_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency 506system.cpu.icache.overall_avg_miss_latency::total 48353.333333 # average overall miss latency | 501system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48370.836417 # average ReadReq miss latency 502system.cpu.icache.ReadReq_avg_miss_latency::total 48370.836417 # average ReadReq miss latency 503system.cpu.icache.demand_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency 504system.cpu.icache.demand_avg_miss_latency::total 48370.836417 # average overall miss latency 505system.cpu.icache.overall_avg_miss_latency::cpu.inst 48370.836417 # average overall miss latency 506system.cpu.icache.overall_avg_miss_latency::total 48370.836417 # average overall miss latency |
| 507system.cpu.icache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked 508system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 509system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 510system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 511system.cpu.icache.avg_blocked_cycles::no_mshrs 48.600000 # average number of cycles each access was blocked 512system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 513system.cpu.icache.fast_writes 0 # number of fast writes performed 514system.cpu.icache.cache_copies 0 # number of cache copies performed | 507system.cpu.icache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked 508system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 509system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 510system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 511system.cpu.icache.avg_blocked_cycles::no_mshrs 48.600000 # average number of cycles each access was blocked 512system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 513system.cpu.icache.fast_writes 0 # number of fast writes performed 514system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 515system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits 516system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits 517system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits 518system.cpu.icache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits 519system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits 520system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits | 515system.cpu.icache.ReadReq_mshr_hits::cpu.inst 311 # number of ReadReq MSHR hits 516system.cpu.icache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits 517system.cpu.icache.demand_mshr_hits::cpu.inst 311 # number of demand (read+write) MSHR hits 518system.cpu.icache.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits 519system.cpu.icache.overall_mshr_hits::cpu.inst 311 # number of overall MSHR hits 520system.cpu.icache.overall_mshr_hits::total 311 # number of overall MSHR hits |
| 521system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1040 # number of ReadReq MSHR misses 522system.cpu.icache.ReadReq_mshr_misses::total 1040 # number of ReadReq MSHR misses 523system.cpu.icache.demand_mshr_misses::cpu.inst 1040 # number of demand (read+write) MSHR misses 524system.cpu.icache.demand_mshr_misses::total 1040 # number of demand (read+write) MSHR misses 525system.cpu.icache.overall_mshr_misses::cpu.inst 1040 # number of overall MSHR misses 526system.cpu.icache.overall_mshr_misses::total 1040 # number of overall MSHR misses | 521system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1040 # number of ReadReq MSHR misses 522system.cpu.icache.ReadReq_mshr_misses::total 1040 # number of ReadReq MSHR misses 523system.cpu.icache.demand_mshr_misses::cpu.inst 1040 # number of demand (read+write) MSHR misses 524system.cpu.icache.demand_mshr_misses::total 1040 # number of demand (read+write) MSHR misses 525system.cpu.icache.overall_mshr_misses::cpu.inst 1040 # number of overall MSHR misses 526system.cpu.icache.overall_mshr_misses::total 1040 # number of overall MSHR misses |
| 527system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52080000 # number of ReadReq MSHR miss cycles 528system.cpu.icache.ReadReq_mshr_miss_latency::total 52080000 # number of ReadReq MSHR miss cycles 529system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52080000 # number of demand (read+write) MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::total 52080000 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52080000 # number of overall MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::total 52080000 # number of overall MSHR miss cycles | 527system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52081000 # number of ReadReq MSHR miss cycles 528system.cpu.icache.ReadReq_mshr_miss_latency::total 52081000 # number of ReadReq MSHR miss cycles 529system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52081000 # number of demand (read+write) MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::total 52081000 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52081000 # number of overall MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::total 52081000 # number of overall MSHR miss cycles |
| 533system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 534system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 535system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 536system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 537system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 538system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 533system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 534system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 535system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 536system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 537system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 538system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 539system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50076.923077 # average ReadReq mshr miss latency 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50076.923077 # average ReadReq mshr miss latency 541system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency 543system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency | 539system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50077.884615 # average ReadReq mshr miss latency 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50077.884615 # average ReadReq mshr miss latency 541system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency 543system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50077.884615 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::total 50077.884615 # average overall mshr miss latency |
| 545system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 545system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 546system.cpu.dcache.replacements 2072071 # number of replacements 547system.cpu.dcache.tagsinuse 4072.565348 # Cycle average of tags in use 548system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks. 549system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks. 550system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks. 551system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit. 552system.cpu.dcache.occ_blocks::cpu.data 4072.565348 # Average occupied blocks per requestor 553system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy 554system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy 555system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits 556system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits 557system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits 558system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits 559system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits 560system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits 561system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits 562system.cpu.dcache.overall_hits::total 71946748 # number of overall hits 563system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses 564system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses 565system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses 566system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses 567system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses 568system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses 569system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses 570system.cpu.dcache.overall_misses::total 2723462 # number of overall misses 571system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321017500 # number of ReadReq miss cycles 572system.cpu.dcache.ReadReq_miss_latency::total 31321017500 # number of ReadReq miss cycles 573system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles 574system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles 575system.cpu.dcache.demand_miss_latency::cpu.data 33409125998 # number of demand (read+write) miss cycles 576system.cpu.dcache.demand_miss_latency::total 33409125998 # number of demand (read+write) miss cycles 577system.cpu.dcache.overall_miss_latency::cpu.data 33409125998 # number of overall miss cycles 578system.cpu.dcache.overall_miss_latency::total 33409125998 # number of overall miss cycles 579system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses) 580system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses) 581system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 582system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 583system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses 584system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses 585system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses 586system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses 587system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses 588system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses 589system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses 590system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses 591system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses 592system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses 593system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses 594system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses 595system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.970796 # average ReadReq miss latency 596system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.970796 # average ReadReq miss latency 597system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency 598system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency 599system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.153350 # average overall miss latency 600system.cpu.dcache.demand_avg_miss_latency::total 12267.153350 # average overall miss latency 601system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.153350 # average overall miss latency 602system.cpu.dcache.overall_avg_miss_latency::total 12267.153350 # average overall miss latency 603system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked 604system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 605system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked 606system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 607system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked 608system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 609system.cpu.dcache.fast_writes 0 # number of fast writes performed 610system.cpu.dcache.cache_copies 0 # number of cache copies performed 611system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks 612system.cpu.dcache.writebacks::total 2066432 # number of writebacks 613system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits 614system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits 615system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits 616system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits 617system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits 618system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits 619system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits 620system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits 621system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses 622system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses 623system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses 624system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses 625system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses 626system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses 627system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses 628system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses 629system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983433500 # number of ReadReq MSHR miss cycles 630system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983433500 # number of ReadReq MSHR miss cycles 631system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles 632system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles 633system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285498 # number of demand (read+write) MSHR miss cycles 634system.cpu.dcache.demand_mshr_miss_latency::total 23796285498 # number of demand (read+write) MSHR miss cycles 635system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285498 # number of overall MSHR miss cycles 636system.cpu.dcache.overall_mshr_miss_latency::total 23796285498 # number of overall MSHR miss cycles 637system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses 638system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses 639system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses 640system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses 641system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses 642system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses 643system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses 644system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses 645system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531267 # average ReadReq mshr miss latency 646system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531267 # average ReadReq mshr miss latency 647system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency 648system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency 649system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621176 # average overall mshr miss latency 650system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621176 # average overall mshr miss latency 651system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621176 # average overall mshr miss latency 652system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621176 # average overall mshr miss latency 653system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 654system.cpu.l2cache.replacements 488 # number of replacements | 546system.cpu.l2cache.replacements 488 # number of replacements |
| 655system.cpu.l2cache.tagsinuse 20806.359939 # Cycle average of tags in use | 547system.cpu.l2cache.tagsinuse 20806.359941 # Cycle average of tags in use |
| 656system.cpu.l2cache.total_refs 4028768 # Total number of references to valid blocks. 657system.cpu.l2cache.sampled_refs 30421 # Sample count of references to valid blocks. 658system.cpu.l2cache.avg_refs 132.433779 # Average number of references to valid blocks. 659system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 660system.cpu.l2cache.occ_blocks::writebacks 19869.947946 # Average occupied blocks per requestor | 548system.cpu.l2cache.total_refs 4028768 # Total number of references to valid blocks. 549system.cpu.l2cache.sampled_refs 30421 # Sample count of references to valid blocks. 550system.cpu.l2cache.avg_refs 132.433779 # Average number of references to valid blocks. 551system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 552system.cpu.l2cache.occ_blocks::writebacks 19869.947946 # Average occupied blocks per requestor |
| 661system.cpu.l2cache.occ_blocks::cpu.inst 692.491885 # Average occupied blocks per requestor | 553system.cpu.l2cache.occ_blocks::cpu.inst 692.491887 # Average occupied blocks per requestor |
| 662system.cpu.l2cache.occ_blocks::cpu.data 243.920108 # Average occupied blocks per requestor 663system.cpu.l2cache.occ_percent::writebacks 0.606383 # Average percentage of cache occupancy 664system.cpu.l2cache.occ_percent::cpu.inst 0.021133 # Average percentage of cache occupancy 665system.cpu.l2cache.occ_percent::cpu.data 0.007444 # Average percentage of cache occupancy 666system.cpu.l2cache.occ_percent::total 0.634960 # Average percentage of cache occupancy 667system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 668system.cpu.l2cache.ReadReq_hits::cpu.data 1993518 # number of ReadReq hits 669system.cpu.l2cache.ReadReq_hits::total 1993538 # number of ReadReq hits --- 15 unchanged lines hidden (view full) --- 685system.cpu.l2cache.ReadExReq_misses::cpu.data 29001 # number of ReadExReq misses 686system.cpu.l2cache.ReadExReq_misses::total 29001 # number of ReadExReq misses 687system.cpu.l2cache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses 688system.cpu.l2cache.demand_misses::cpu.data 29425 # number of demand (read+write) misses 689system.cpu.l2cache.demand_misses::total 30444 # number of demand (read+write) misses 690system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses 691system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses 692system.cpu.l2cache.overall_misses::total 30444 # number of overall misses | 554system.cpu.l2cache.occ_blocks::cpu.data 243.920108 # Average occupied blocks per requestor 555system.cpu.l2cache.occ_percent::writebacks 0.606383 # Average percentage of cache occupancy 556system.cpu.l2cache.occ_percent::cpu.inst 0.021133 # Average percentage of cache occupancy 557system.cpu.l2cache.occ_percent::cpu.data 0.007444 # Average percentage of cache occupancy 558system.cpu.l2cache.occ_percent::total 0.634960 # Average percentage of cache occupancy 559system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 560system.cpu.l2cache.ReadReq_hits::cpu.data 1993518 # number of ReadReq hits 561system.cpu.l2cache.ReadReq_hits::total 1993538 # number of ReadReq hits --- 15 unchanged lines hidden (view full) --- 577system.cpu.l2cache.ReadExReq_misses::cpu.data 29001 # number of ReadExReq misses 578system.cpu.l2cache.ReadExReq_misses::total 29001 # number of ReadExReq misses 579system.cpu.l2cache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses 580system.cpu.l2cache.demand_misses::cpu.data 29425 # number of demand (read+write) misses 581system.cpu.l2cache.demand_misses::total 30444 # number of demand (read+write) misses 582system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses 583system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses 584system.cpu.l2cache.overall_misses::total 30444 # number of overall misses |
| 693system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50832500 # number of ReadReq miss cycles 694system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21222500 # number of ReadReq miss cycles 695system.cpu.l2cache.ReadReq_miss_latency::total 72055000 # number of ReadReq miss cycles | 585system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50833500 # number of ReadReq miss cycles 586system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21223000 # number of ReadReq miss cycles 587system.cpu.l2cache.ReadReq_miss_latency::total 72056500 # number of ReadReq miss cycles |
| 696system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199120000 # number of ReadExReq miss cycles 697system.cpu.l2cache.ReadExReq_miss_latency::total 1199120000 # number of ReadExReq miss cycles | 588system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199120000 # number of ReadExReq miss cycles 589system.cpu.l2cache.ReadExReq_miss_latency::total 1199120000 # number of ReadExReq miss cycles |
| 698system.cpu.l2cache.demand_miss_latency::cpu.inst 50832500 # number of demand (read+write) miss cycles 699system.cpu.l2cache.demand_miss_latency::cpu.data 1220342500 # number of demand (read+write) miss cycles 700system.cpu.l2cache.demand_miss_latency::total 1271175000 # number of demand (read+write) miss cycles 701system.cpu.l2cache.overall_miss_latency::cpu.inst 50832500 # number of overall miss cycles 702system.cpu.l2cache.overall_miss_latency::cpu.data 1220342500 # number of overall miss cycles 703system.cpu.l2cache.overall_miss_latency::total 1271175000 # number of overall miss cycles | 590system.cpu.l2cache.demand_miss_latency::cpu.inst 50833500 # number of demand (read+write) miss cycles 591system.cpu.l2cache.demand_miss_latency::cpu.data 1220343000 # number of demand (read+write) miss cycles 592system.cpu.l2cache.demand_miss_latency::total 1271176500 # number of demand (read+write) miss cycles 593system.cpu.l2cache.overall_miss_latency::cpu.inst 50833500 # number of overall miss cycles 594system.cpu.l2cache.overall_miss_latency::cpu.data 1220343000 # number of overall miss cycles 595system.cpu.l2cache.overall_miss_latency::total 1271176500 # number of overall miss cycles |
| 704system.cpu.l2cache.ReadReq_accesses::cpu.inst 1039 # number of ReadReq accesses(hits+misses) 705system.cpu.l2cache.ReadReq_accesses::cpu.data 1993942 # number of ReadReq accesses(hits+misses) 706system.cpu.l2cache.ReadReq_accesses::total 1994981 # number of ReadReq accesses(hits+misses) 707system.cpu.l2cache.Writeback_accesses::writebacks 2066432 # number of Writeback accesses(hits+misses) 708system.cpu.l2cache.Writeback_accesses::total 2066432 # number of Writeback accesses(hits+misses) 709system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 710system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) 711system.cpu.l2cache.ReadExReq_accesses::cpu.data 82228 # number of ReadExReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 724system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352690 # miss rate for ReadExReq accesses 725system.cpu.l2cache.ReadExReq_miss_rate::total 0.352690 # miss rate for ReadExReq accesses 726system.cpu.l2cache.demand_miss_rate::cpu.inst 0.980751 # miss rate for demand accesses 727system.cpu.l2cache.demand_miss_rate::cpu.data 0.014173 # miss rate for demand accesses 728system.cpu.l2cache.demand_miss_rate::total 0.014656 # miss rate for demand accesses 729system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980751 # miss rate for overall accesses 730system.cpu.l2cache.overall_miss_rate::cpu.data 0.014173 # miss rate for overall accesses 731system.cpu.l2cache.overall_miss_rate::total 0.014656 # miss rate for overall accesses | 596system.cpu.l2cache.ReadReq_accesses::cpu.inst 1039 # number of ReadReq accesses(hits+misses) 597system.cpu.l2cache.ReadReq_accesses::cpu.data 1993942 # number of ReadReq accesses(hits+misses) 598system.cpu.l2cache.ReadReq_accesses::total 1994981 # number of ReadReq accesses(hits+misses) 599system.cpu.l2cache.Writeback_accesses::writebacks 2066432 # number of Writeback accesses(hits+misses) 600system.cpu.l2cache.Writeback_accesses::total 2066432 # number of Writeback accesses(hits+misses) 601system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 602system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) 603system.cpu.l2cache.ReadExReq_accesses::cpu.data 82228 # number of ReadExReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 616system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352690 # miss rate for ReadExReq accesses 617system.cpu.l2cache.ReadExReq_miss_rate::total 0.352690 # miss rate for ReadExReq accesses 618system.cpu.l2cache.demand_miss_rate::cpu.inst 0.980751 # miss rate for demand accesses 619system.cpu.l2cache.demand_miss_rate::cpu.data 0.014173 # miss rate for demand accesses 620system.cpu.l2cache.demand_miss_rate::total 0.014656 # miss rate for demand accesses 621system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980751 # miss rate for overall accesses 622system.cpu.l2cache.overall_miss_rate::cpu.data 0.014173 # miss rate for overall accesses 623system.cpu.l2cache.overall_miss_rate::total 0.014656 # miss rate for overall accesses |
| 732system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49884.690873 # average ReadReq miss latency 733system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50053.066038 # average ReadReq miss latency 734system.cpu.l2cache.ReadReq_avg_miss_latency::total 49934.164934 # average ReadReq miss latency | 624system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49885.672228 # average ReadReq miss latency 625system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50054.245283 # average ReadReq miss latency 626system.cpu.l2cache.ReadReq_avg_miss_latency::total 49935.204435 # average ReadReq miss latency |
| 735system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41347.539740 # average ReadExReq miss latency 736system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41347.539740 # average ReadExReq miss latency | 627system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41347.539740 # average ReadExReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41347.539740 # average ReadExReq miss latency |
| 737system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency 738system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency 739system.cpu.l2cache.demand_avg_miss_latency::total 41754.532913 # average overall miss latency 740system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency 741system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency 742system.cpu.l2cache.overall_avg_miss_latency::total 41754.532913 # average overall miss latency | 629system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency 630system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency 631system.cpu.l2cache.demand_avg_miss_latency::total 41754.582184 # average overall miss latency 632system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49885.672228 # average overall miss latency 633system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.999150 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::total 41754.582184 # average overall miss latency |
| 743system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 744system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 745system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 746system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 747system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 748system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 749system.cpu.l2cache.fast_writes 0 # number of fast writes performed 750system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 758system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29001 # number of ReadExReq MSHR misses 759system.cpu.l2cache.ReadExReq_mshr_misses::total 29001 # number of ReadExReq MSHR misses 760system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses 761system.cpu.l2cache.demand_mshr_misses::cpu.data 29425 # number of demand (read+write) MSHR misses 762system.cpu.l2cache.demand_mshr_misses::total 30444 # number of demand (read+write) MSHR misses 763system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses 764system.cpu.l2cache.overall_mshr_misses::cpu.data 29425 # number of overall MSHR misses 765system.cpu.l2cache.overall_mshr_misses::total 30444 # number of overall MSHR misses | 635system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 636system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 639system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 640system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 641system.cpu.l2cache.fast_writes 0 # number of fast writes performed 642system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 650system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29001 # number of ReadExReq MSHR misses 651system.cpu.l2cache.ReadExReq_mshr_misses::total 29001 # number of ReadExReq MSHR misses 652system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses 653system.cpu.l2cache.demand_mshr_misses::cpu.data 29425 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.demand_mshr_misses::total 30444 # number of demand (read+write) MSHR misses 655system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses 656system.cpu.l2cache.overall_mshr_misses::cpu.data 29425 # number of overall MSHR misses 657system.cpu.l2cache.overall_mshr_misses::total 30444 # number of overall MSHR misses |
| 766system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 37999583 # number of ReadReq MSHR miss cycles 767system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880149 # number of ReadReq MSHR miss cycles 768system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53879732 # number of ReadReq MSHR miss cycles | 658system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38000083 # number of ReadReq MSHR miss cycles 659system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880649 # number of ReadReq MSHR miss cycles 660system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53880732 # number of ReadReq MSHR miss cycles |
| 769system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles 770system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles 771system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824195395 # number of ReadExReq MSHR miss cycles 772system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824195395 # number of ReadExReq MSHR miss cycles | 661system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles 662system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles 663system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824195395 # number of ReadExReq MSHR miss cycles 664system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824195395 # number of ReadExReq MSHR miss cycles |
| 773system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37999583 # number of demand (read+write) MSHR miss cycles 774system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840075544 # number of demand (read+write) MSHR miss cycles 775system.cpu.l2cache.demand_mshr_miss_latency::total 878075127 # number of demand (read+write) MSHR miss cycles 776system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37999583 # number of overall MSHR miss cycles 777system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840075544 # number of overall MSHR miss cycles 778system.cpu.l2cache.overall_mshr_miss_latency::total 878075127 # number of overall MSHR miss cycles | 665system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38000083 # number of demand (read+write) MSHR miss cycles 666system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840076044 # number of demand (read+write) MSHR miss cycles 667system.cpu.l2cache.demand_mshr_miss_latency::total 878076127 # number of demand (read+write) MSHR miss cycles 668system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38000083 # number of overall MSHR miss cycles 669system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840076044 # number of overall MSHR miss cycles 670system.cpu.l2cache.overall_mshr_miss_latency::total 878076127 # number of overall MSHR miss cycles |
| 779system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for ReadReq accesses 780system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadReq accesses 781system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000723 # mshr miss rate for ReadReq accesses 782system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 783system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 784system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352690 # mshr miss rate for ReadExReq accesses 785system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352690 # mshr miss rate for ReadExReq accesses 786system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for demand accesses 787system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for demand accesses 788system.cpu.l2cache.demand_mshr_miss_rate::total 0.014656 # mshr miss rate for demand accesses 789system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for overall accesses 790system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for overall accesses 791system.cpu.l2cache.overall_mshr_miss_rate::total 0.014656 # mshr miss rate for overall accesses | 671system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for ReadReq accesses 672system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadReq accesses 673system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000723 # mshr miss rate for ReadReq accesses 674system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 675system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 676system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352690 # mshr miss rate for ReadExReq accesses 677system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352690 # mshr miss rate for ReadExReq accesses 678system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for demand accesses 679system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for demand accesses 680system.cpu.l2cache.demand_mshr_miss_rate::total 0.014656 # mshr miss rate for demand accesses 681system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for overall accesses 682system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for overall accesses 683system.cpu.l2cache.overall_mshr_miss_rate::total 0.014656 # mshr miss rate for overall accesses |
| 792system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.052993 # average ReadReq mshr miss latency 793system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37453.181604 # average ReadReq mshr miss latency 794system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37338.691615 # average ReadReq mshr miss latency | 684system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.543670 # average ReadReq mshr miss latency 685system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37454.360849 # average ReadReq mshr miss latency 686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37339.384615 # average ReadReq mshr miss latency |
| 795system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 796system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 797system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28419.550878 # average ReadExReq mshr miss latency 798system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28419.550878 # average ReadExReq mshr miss latency | 687system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 688system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 689system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28419.550878 # average ReadExReq mshr miss latency 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28419.550878 # average ReadExReq mshr miss latency |
| 799system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency 800system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency 801system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency 802system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency 803system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency 804system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency | 691system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency |
| 805system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 697system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 698system.cpu.dcache.replacements 2072071 # number of replacements 699system.cpu.dcache.tagsinuse 4072.565350 # Cycle average of tags in use 700system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks. 701system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks. 702system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks. 703system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit. 704system.cpu.dcache.occ_blocks::cpu.data 4072.565350 # Average occupied blocks per requestor 705system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy 706system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy 707system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits 708system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits 709system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits 710system.cpu.dcache.WriteReq_hits::total 31341476 # number of WriteReq hits 711system.cpu.dcache.demand_hits::cpu.data 71946748 # number of demand (read+write) hits 712system.cpu.dcache.demand_hits::total 71946748 # number of demand (read+write) hits 713system.cpu.dcache.overall_hits::cpu.data 71946748 # number of overall hits 714system.cpu.dcache.overall_hits::total 71946748 # number of overall hits 715system.cpu.dcache.ReadReq_misses::cpu.data 2625186 # number of ReadReq misses 716system.cpu.dcache.ReadReq_misses::total 2625186 # number of ReadReq misses 717system.cpu.dcache.WriteReq_misses::cpu.data 98276 # number of WriteReq misses 718system.cpu.dcache.WriteReq_misses::total 98276 # number of WriteReq misses 719system.cpu.dcache.demand_misses::cpu.data 2723462 # number of demand (read+write) misses 720system.cpu.dcache.demand_misses::total 2723462 # number of demand (read+write) misses 721system.cpu.dcache.overall_misses::cpu.data 2723462 # number of overall misses 722system.cpu.dcache.overall_misses::total 2723462 # number of overall misses 723system.cpu.dcache.ReadReq_miss_latency::cpu.data 31321024000 # number of ReadReq miss cycles 724system.cpu.dcache.ReadReq_miss_latency::total 31321024000 # number of ReadReq miss cycles 725system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088108498 # number of WriteReq miss cycles 726system.cpu.dcache.WriteReq_miss_latency::total 2088108498 # number of WriteReq miss cycles 727system.cpu.dcache.demand_miss_latency::cpu.data 33409132498 # number of demand (read+write) miss cycles 728system.cpu.dcache.demand_miss_latency::total 33409132498 # number of demand (read+write) miss cycles 729system.cpu.dcache.overall_miss_latency::cpu.data 33409132498 # number of overall miss cycles 730system.cpu.dcache.overall_miss_latency::total 33409132498 # number of overall miss cycles 731system.cpu.dcache.ReadReq_accesses::cpu.data 43230458 # number of ReadReq accesses(hits+misses) 732system.cpu.dcache.ReadReq_accesses::total 43230458 # number of ReadReq accesses(hits+misses) 733system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 734system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 735system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses 736system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses 737system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses 738system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses 739system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses 740system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses 741system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses 742system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses 743system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses 744system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses 745system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses 746system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses 747system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.973272 # average ReadReq miss latency 748system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.973272 # average ReadReq miss latency 749system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency 750system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency 751system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency 752system.cpu.dcache.demand_avg_miss_latency::total 12267.155737 # average overall miss latency 753system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency 754system.cpu.dcache.overall_avg_miss_latency::total 12267.155737 # average overall miss latency 755system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked 756system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 757system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked 758system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 759system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked 760system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 761system.cpu.dcache.fast_writes 0 # number of fast writes performed 762system.cpu.dcache.cache_copies 0 # number of cache copies performed 763system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks 764system.cpu.dcache.writebacks::total 2066432 # number of writebacks 765system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits 766system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits 767system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits 768system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits 769system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits 770system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits 771system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits 772system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits 773system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses 774system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses 775system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses 776system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses 777system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses 778system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses 779system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses 780system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses 781system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983434000 # number of ReadReq MSHR miss cycles 782system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983434000 # number of ReadReq MSHR miss cycles 783system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles 784system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles 785system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285998 # number of demand (read+write) MSHR miss cycles 786system.cpu.dcache.demand_mshr_miss_latency::total 23796285998 # number of demand (read+write) MSHR miss cycles 787system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285998 # number of overall MSHR miss cycles 788system.cpu.dcache.overall_mshr_miss_latency::total 23796285998 # number of overall MSHR miss cycles 789system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses 791system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses 793system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses 794system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses 795system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses 796system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses 797system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531518 # average ReadReq mshr miss latency 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531518 # average ReadReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency 801system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency 802system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency 803system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency 804system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency 805system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 806 807---------- End Simulation Statistics ---------- | 806 807---------- End Simulation Statistics ---------- |