| stats.txt (9285:9901180cd573) | stats.txt (9312:e05e1b69ebf2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.061487 # Number of seconds simulated 4sim_ticks 61487437500 # Number of ticks simulated 5final_tick 61487437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.061268 # Number of seconds simulated 4sim_ticks 61267871000 # Number of ticks simulated 5final_tick 61267871000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 86290 # Simulator instruction rate (inst/s) 8host_op_rate 151942 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33582980 # Simulator tick rate (ticks/s) 10host_mem_usage 365956 # Number of bytes of host memory used 11host_seconds 1830.91 # Real time elapsed on the host | 7host_inst_rate 120787 # Simulator instruction rate (inst/s) 8host_op_rate 212686 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 46841085 # Simulator tick rate (ticks/s) 10host_mem_usage 363680 # Number of bytes of host memory used 11host_seconds 1307.99 # Real time elapsed on the host |
| 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192462 # Number of ops (including micro ops) simulated | 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192462 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1893056 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1961408 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 20288 # Number of bytes written to this memory 20system.physmem.bytes_written::total 20288 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29579 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30647 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 317 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 317 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1111642 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 30787687 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 31899329 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1111642 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1111642 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 329954 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 329954 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 329954 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1111642 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 30787687 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 32229283 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1893248 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1962048 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 20608 # Number of bytes written to this memory 20system.physmem.bytes_written::total 20608 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29582 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30657 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 322 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 322 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1122938 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 30901155 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 32024093 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1122938 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1122938 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 336359 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 336359 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 336359 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1122938 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 30901155 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 32360452 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 30662 # Total number of read requests seen 38system.physmem.writeReqs 322 # Total number of write requests seen 39system.physmem.cpureqs 30989 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 1962048 # Total number of bytes read from memory 41system.physmem.bytesWritten 20608 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 1962048 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 20608 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 28 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 1936 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 1969 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 2038 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 2024 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 1986 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 1872 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 1877 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 1862 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 1926 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 1900 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 1830 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 1883 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 1923 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 1961 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 1876 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 1771 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 18 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 14 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 124 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 18 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 19 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 2 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 4 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 18 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 11 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 8 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 12 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 55 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 3 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 61267857000 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 30662 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 322 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 5 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 29991 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 477 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 129 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 13 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 14 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 14 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 14 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 14 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 14 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 14 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 14 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 14 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 14 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 14 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 14 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 14 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 14 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 14 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 14 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 14 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 14 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 14 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 14166089 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 582752089 # Sum of mem lat for all requests 176system.physmem.totBusLat 122532000 # Total cycles spent in databus access 177system.physmem.totBankLat 446054000 # Total cycles spent in bank access 178system.physmem.avgQLat 462.43 # Average queueing delay per request 179system.physmem.avgBankLat 14560.75 # Average bank access latency per request 180system.physmem.avgBusLat 3999.87 # Average bus latency per request 181system.physmem.avgMemAccLat 19023.05 # Average memory access latency 182system.physmem.avgRdBW 32.02 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 0.34 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 32.02 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 0.34 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.20 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.01 # Average read queue length over time 189system.physmem.avgWrQLen 4.97 # Average write queue length over time 190system.physmem.readRowHits 29782 # Number of row buffer hits during reads 191system.physmem.writeRowHits 175 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 97.22 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 54.35 # Row buffer hit rate for writes 194system.physmem.avgGap 1977403.08 # Average gap between requests |
| 37system.cpu.workload.num_syscalls 444 # Number of system calls | 195system.cpu.workload.num_syscalls 444 # Number of system calls |
| 38system.cpu.numCycles 122974876 # number of cpu cycles simulated | 196system.cpu.numCycles 122535743 # number of cpu cycles simulated |
| 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 197system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 198system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 41system.cpu.BPredUnit.lookups 35563581 # Number of BP lookups 42system.cpu.BPredUnit.condPredicted 35563581 # Number of conditional branches predicted 43system.cpu.BPredUnit.condIncorrect 1083908 # Number of conditional branches incorrect 44system.cpu.BPredUnit.BTBLookups 25421016 # Number of BTB lookups 45system.cpu.BPredUnit.BTBHits 25287599 # Number of BTB hits | 199system.cpu.BPredUnit.lookups 35570832 # Number of BP lookups 200system.cpu.BPredUnit.condPredicted 35570832 # Number of conditional branches predicted 201system.cpu.BPredUnit.condIncorrect 1084026 # Number of conditional branches incorrect 202system.cpu.BPredUnit.BTBLookups 25425275 # Number of BTB lookups 203system.cpu.BPredUnit.BTBHits 25293552 # Number of BTB hits |
| 46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. | 204system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 205system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 206system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 49system.cpu.fetch.icacheStallCycles 27814300 # Number of cycles fetch is stalled on an Icache miss 50system.cpu.fetch.Insts 193613700 # Number of instructions fetch has processed 51system.cpu.fetch.Branches 35563581 # Number of branches that fetch encountered 52system.cpu.fetch.predictedBranches 25287599 # Number of branches that fetch has predicted taken 53system.cpu.fetch.Cycles 58598336 # Number of cycles fetch has run and was not squashing or blocked 54system.cpu.fetch.SquashCycles 7345607 # Number of cycles fetch has spent squashing 55system.cpu.fetch.BlockedCycles 30298263 # Number of cycles fetch has spent blocked 56system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 57system.cpu.fetch.PendingTrapStallCycles 223 # Number of stall cycles due to pending traps 58system.cpu.fetch.CacheLines 27172491 # Number of cache lines fetched 59system.cpu.fetch.IcacheSquashes 322176 # Number of outstanding Icache misses that were squashed 60system.cpu.fetch.rateDist::samples 122946211 # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::mean 2.768410 # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::stdev 3.402032 # Number of instructions fetched each cycle (Total) | 207system.cpu.fetch.icacheStallCycles 27817646 # Number of cycles fetch is stalled on an Icache miss 208system.cpu.fetch.Insts 193664357 # Number of instructions fetch has processed 209system.cpu.fetch.Branches 35570832 # Number of branches that fetch encountered 210system.cpu.fetch.predictedBranches 25293552 # Number of branches that fetch has predicted taken 211system.cpu.fetch.Cycles 58615511 # Number of cycles fetch has run and was not squashing or blocked 212system.cpu.fetch.SquashCycles 7353362 # Number of cycles fetch has spent squashing 213system.cpu.fetch.BlockedCycles 29831602 # Number of cycles fetch has spent blocked 214system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 215system.cpu.fetch.PendingTrapStallCycles 154 # Number of stall cycles due to pending traps 216system.cpu.fetch.CacheLines 27179590 # Number of cache lines fetched 217system.cpu.fetch.IcacheSquashes 325172 # Number of outstanding Icache misses that were squashed 218system.cpu.fetch.rateDist::samples 122507486 # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::mean 2.779073 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::stdev 3.404197 # Number of instructions fetched each cycle (Total) |
| 63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 221system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 64system.cpu.fetch.rateDist::0 67085101 54.56% 54.56% # Number of instructions fetched each cycle (Total) 65system.cpu.fetch.rateDist::1 2067083 1.68% 56.25% # Number of instructions fetched each cycle (Total) 66system.cpu.fetch.rateDist::2 2985500 2.43% 58.67% # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::3 3997651 3.25% 61.93% # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::4 7978379 6.49% 68.42% # Number of instructions fetched each cycle (Total) 69system.cpu.fetch.rateDist::5 5028202 4.09% 72.50% # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.rateDist::6 2861375 2.33% 74.83% # Number of instructions fetched each cycle (Total) 71system.cpu.fetch.rateDist::7 1431598 1.16% 76.00% # Number of instructions fetched each cycle (Total) 72system.cpu.fetch.rateDist::8 29511322 24.00% 100.00% # Number of instructions fetched each cycle (Total) | 222system.cpu.fetch.rateDist::0 66630267 54.39% 54.39% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::1 2068884 1.69% 56.08% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::2 2984971 2.44% 58.51% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::3 3999258 3.26% 61.78% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::4 7980935 6.51% 68.29% # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::5 5030075 4.11% 72.40% # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::6 2863623 2.34% 74.74% # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.rateDist::7 1430988 1.17% 75.90% # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.rateDist::8 29518485 24.10% 100.00% # Number of instructions fetched each cycle (Total) |
| 73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 231system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 232system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 233system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 76system.cpu.fetch.rateDist::total 122946211 # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.branchRate 0.289194 # Number of branch fetches per cycle 78system.cpu.fetch.rate 1.574417 # Number of inst fetches per cycle 79system.cpu.decode.IdleCycles 38912587 # Number of cycles decode is idle 80system.cpu.decode.BlockedCycles 22600530 # Number of cycles decode is blocked 81system.cpu.decode.RunCycles 48050125 # Number of cycles decode is running 82system.cpu.decode.UnblockCycles 7147919 # Number of cycles decode is unblocking 83system.cpu.decode.SquashCycles 6235050 # Number of cycles decode is squashing 84system.cpu.decode.DecodedInsts 336030812 # Number of instructions handled by decode 85system.cpu.rename.SquashCycles 6235050 # Number of cycles rename is squashing 86system.cpu.rename.IdleCycles 43304200 # Number of cycles rename is idle 87system.cpu.rename.BlockCycles 3170225 # Number of cycles rename is blocking 88system.cpu.rename.serializeStallCycles 8978 # count of cycles rename stalled for serializing inst 89system.cpu.rename.RunCycles 50645325 # Number of cycles rename is running 90system.cpu.rename.UnblockCycles 19582433 # Number of cycles rename is unblocking 91system.cpu.rename.RenamedInsts 332156996 # Number of instructions processed by rename 92system.cpu.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full 93system.cpu.rename.IQFullEvents 3311 # Number of times rename has blocked due to IQ full 94system.cpu.rename.LSQFullEvents 17907327 # Number of times rename has blocked due to LSQ full 95system.cpu.rename.FullRegisterEvents 182 # Number of times there has been no free registers 96system.cpu.rename.RenamedOperands 334503257 # Number of destination operands rename has renamed 97system.cpu.rename.RenameLookups 881229115 # Number of register rename lookups that rename has made 98system.cpu.rename.int_rename_lookups 881227036 # Number of integer rename lookups 99system.cpu.rename.fp_rename_lookups 2079 # Number of floating rename lookups | 234system.cpu.fetch.rateDist::total 122507486 # Number of instructions fetched each cycle (Total) 235system.cpu.fetch.branchRate 0.290289 # Number of branch fetches per cycle 236system.cpu.fetch.rate 1.580472 # Number of inst fetches per cycle 237system.cpu.decode.IdleCycles 38875412 # Number of cycles decode is idle 238system.cpu.decode.BlockedCycles 22176556 # Number of cycles decode is blocked 239system.cpu.decode.RunCycles 48070998 # Number of cycles decode is running 240system.cpu.decode.UnblockCycles 7141971 # Number of cycles decode is unblocking 241system.cpu.decode.SquashCycles 6242549 # Number of cycles decode is squashing 242system.cpu.decode.DecodedInsts 336118074 # Number of instructions handled by decode 243system.cpu.rename.SquashCycles 6242549 # Number of cycles rename is squashing 244system.cpu.rename.IdleCycles 43268905 # Number of cycles rename is idle 245system.cpu.rename.BlockCycles 2886935 # Number of cycles rename is blocking 246system.cpu.rename.serializeStallCycles 6989 # count of cycles rename stalled for serializing inst 247system.cpu.rename.RunCycles 50676752 # Number of cycles rename is running 248system.cpu.rename.UnblockCycles 19425356 # Number of cycles rename is unblocking 249system.cpu.rename.RenamedInsts 332235244 # Number of instructions processed by rename 250system.cpu.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full 251system.cpu.rename.IQFullEvents 9392 # Number of times rename has blocked due to IQ full 252system.cpu.rename.LSQFullEvents 17753597 # Number of times rename has blocked due to LSQ full 253system.cpu.rename.FullRegisterEvents 139 # Number of times there has been no free registers 254system.cpu.rename.RenamedOperands 334580463 # Number of destination operands rename has renamed 255system.cpu.rename.RenameLookups 881428154 # Number of register rename lookups that rename has made 256system.cpu.rename.int_rename_lookups 881426042 # Number of integer rename lookups 257system.cpu.rename.fp_rename_lookups 2112 # Number of floating rename lookups |
| 100system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed | 258system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed |
| 101system.cpu.rename.UndoneMaps 55290513 # Number of HB maps that are undone due to squashing 102system.cpu.rename.serializingInsts 484 # count of serializing insts renamed 103system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed 104system.cpu.rename.skidInsts 44388140 # count of insts added to the skid buffer 105system.cpu.memDep0.insertedLoads 104937995 # Number of loads inserted to the mem dependence unit. 106system.cpu.memDep0.insertedStores 36474446 # Number of stores inserted to the mem dependence unit. 107system.cpu.memDep0.conflictingLoads 41500364 # Number of conflicting loads. 108system.cpu.memDep0.conflictingStores 5836392 # Number of conflicting stores. 109system.cpu.iq.iqInstsAdded 323873529 # Number of instructions added to the IQ (excludes non-spec) 110system.cpu.iq.iqNonSpecInstsAdded 1758 # Number of non-speculative instructions added to the IQ 111system.cpu.iq.iqInstsIssued 307729409 # Number of instructions issued 112system.cpu.iq.iqSquashedInstsIssued 216713 # Number of squashed instructions issued 113system.cpu.iq.iqSquashedInstsExamined 45479887 # Number of squashed instructions iterated over during squash; mainly for profiling 114system.cpu.iq.iqSquashedOperandsExamined 66424397 # Number of squashed operands that are examined and possibly removed from graph 115system.cpu.iq.iqSquashedNonSpecRemoved 1312 # Number of squashed non-spec instructions that were removed 116system.cpu.iq.issued_per_cycle::samples 122946211 # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::mean 2.502960 # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::stdev 1.799833 # Number of insts issued each cycle | 259system.cpu.rename.UndoneMaps 55367719 # Number of HB maps that are undone due to squashing 260system.cpu.rename.serializingInsts 486 # count of serializing insts renamed 261system.cpu.rename.tempSerializingInsts 482 # count of temporary serializing insts renamed 262system.cpu.rename.skidInsts 44129062 # count of insts added to the skid buffer 263system.cpu.memDep0.insertedLoads 104954101 # Number of loads inserted to the mem dependence unit. 264system.cpu.memDep0.insertedStores 36485312 # Number of stores inserted to the mem dependence unit. 265system.cpu.memDep0.conflictingLoads 41562946 # Number of conflicting loads. 266system.cpu.memDep0.conflictingStores 5830806 # Number of conflicting stores. 267system.cpu.iq.iqInstsAdded 323945312 # Number of instructions added to the IQ (excludes non-spec) 268system.cpu.iq.iqNonSpecInstsAdded 1773 # Number of non-speculative instructions added to the IQ 269system.cpu.iq.iqInstsIssued 307769548 # Number of instructions issued 270system.cpu.iq.iqSquashedInstsIssued 217281 # Number of squashed instructions issued 271system.cpu.iq.iqSquashedInstsExamined 45552285 # Number of squashed instructions iterated over during squash; mainly for profiling 272system.cpu.iq.iqSquashedOperandsExamined 66549913 # Number of squashed operands that are examined and possibly removed from graph 273system.cpu.iq.iqSquashedNonSpecRemoved 1327 # Number of squashed non-spec instructions that were removed 274system.cpu.iq.issued_per_cycle::samples 122507486 # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::mean 2.512251 # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::stdev 1.799024 # Number of insts issued each cycle |
| 119system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 277system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 120system.cpu.iq.issued_per_cycle::0 21631935 17.59% 17.59% # Number of insts issued each cycle 121system.cpu.iq.issued_per_cycle::1 17051158 13.87% 31.46% # Number of insts issued each cycle 122system.cpu.iq.issued_per_cycle::2 24526773 19.95% 51.41% # Number of insts issued each cycle 123system.cpu.iq.issued_per_cycle::3 23966381 19.49% 70.91% # Number of insts issued each cycle 124system.cpu.iq.issued_per_cycle::4 19143829 15.57% 86.48% # Number of insts issued each cycle 125system.cpu.iq.issued_per_cycle::5 9189049 7.47% 93.95% # Number of insts issued each cycle 126system.cpu.iq.issued_per_cycle::6 5012385 4.08% 98.03% # Number of insts issued each cycle 127system.cpu.iq.issued_per_cycle::7 2266917 1.84% 99.87% # Number of insts issued each cycle 128system.cpu.iq.issued_per_cycle::8 157784 0.13% 100.00% # Number of insts issued each cycle | 278system.cpu.iq.issued_per_cycle::0 21268867 17.36% 17.36% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::1 16938160 13.83% 31.19% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::2 24590210 20.07% 51.26% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::3 23966706 19.56% 70.82% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::4 19077143 15.57% 86.40% # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::5 9190745 7.50% 93.90% # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::6 4997191 4.08% 97.98% # Number of insts issued each cycle 285system.cpu.iq.issued_per_cycle::7 2322305 1.90% 99.87% # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::8 156159 0.13% 100.00% # Number of insts issued each cycle |
| 129system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 130system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 131system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 287system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 288system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 289system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 132system.cpu.iq.issued_per_cycle::total 122946211 # Number of insts issued each cycle | 290system.cpu.iq.issued_per_cycle::total 122507486 # Number of insts issued each cycle |
| 133system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 291system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 134system.cpu.iq.fu_full::IntAlu 50945 1.97% 1.97% # attempts to use FU when none available 135system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available 136system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available 137system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available 138system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available 139system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available 140system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available 141system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available 142system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available 155system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available 156system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available 157system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available 158system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available 159system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available 163system.cpu.iq.fu_full::MemRead 1871750 72.23% 74.20% # attempts to use FU when none available 164system.cpu.iq.fu_full::MemWrite 668572 25.80% 100.00% # attempts to use FU when none available | 292system.cpu.iq.fu_full::IntAlu 51278 1.98% 1.98% # attempts to use FU when none available 293system.cpu.iq.fu_full::IntMult 0 0.00% 1.98% # attempts to use FU when none available 294system.cpu.iq.fu_full::IntDiv 0 0.00% 1.98% # attempts to use FU when none available 295system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available 296system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available 297system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available 298system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available 299system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available 300system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available 321system.cpu.iq.fu_full::MemRead 1865528 72.01% 73.99% # attempts to use FU when none available 322system.cpu.iq.fu_full::MemWrite 673849 26.01% 100.00% # attempts to use FU when none available |
| 165system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 166system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 323system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 324system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 167system.cpu.iq.FU_type_0::No_OpClass 33168 0.01% 0.01% # Type of FU issued 168system.cpu.iq.FU_type_0::IntAlu 174887442 56.83% 56.84% # Type of FU issued | 325system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued 326system.cpu.iq.FU_type_0::IntAlu 174913911 56.83% 56.84% # Type of FU issued |
| 169system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued 170system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued | 327system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued 328system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued |
| 171system.cpu.iq.FU_type_0::FloatAdd 52 0.00% 56.84% # Type of FU issued | 329system.cpu.iq.FU_type_0::FloatAdd 42 0.00% 56.84% # Type of FU issued |
| 172system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued 173system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued 174system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued 175system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.84% # Type of FU issued 176system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.84% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.84% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.84% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.84% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 189system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.84% # Type of FU issued 190system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.84% # Type of FU issued 191system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.84% # Type of FU issued 192system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.84% # Type of FU issued 193system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued | 330system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued 331system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued 332system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued 333system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.84% # Type of FU issued 334system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.84% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.84% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.84% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.84% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 347system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.84% # Type of FU issued 348system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.84% # Type of FU issued 349system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.84% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.84% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued 353system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued 354system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued |
| 197system.cpu.iq.FU_type_0::MemRead 98817076 32.11% 88.95% # Type of FU issued 198system.cpu.iq.FU_type_0::MemWrite 33991671 11.05% 100.00% # Type of FU issued | 355system.cpu.iq.FU_type_0::MemRead 98825778 32.11% 88.95% # Type of FU issued 356system.cpu.iq.FU_type_0::MemWrite 33996476 11.05% 100.00% # Type of FU issued |
| 199system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 200system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 357system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 358system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 201system.cpu.iq.FU_type_0::total 307729409 # Type of FU issued 202system.cpu.iq.rate 2.502376 # Inst issue rate 203system.cpu.iq.fu_busy_cnt 2591267 # FU busy when requested 204system.cpu.iq.fu_busy_rate 0.008421 # FU busy rate (busy events/executed inst) 205system.cpu.iq.int_inst_queue_reads 741212334 # Number of integer instruction queue reads 206system.cpu.iq.int_inst_queue_writes 369384855 # Number of integer instruction queue writes 207system.cpu.iq.int_inst_queue_wakeup_accesses 304533759 # Number of integer instruction queue wakeup accesses 208system.cpu.iq.fp_inst_queue_reads 675 # Number of floating instruction queue reads 209system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes 210system.cpu.iq.fp_inst_queue_wakeup_accesses 209 # Number of floating instruction queue wakeup accesses 211system.cpu.iq.int_alu_accesses 310287186 # Number of integer alu accesses 212system.cpu.iq.fp_alu_accesses 322 # Number of floating point alu accesses 213system.cpu.iew.lsq.thread0.forwLoads 52324197 # Number of loads that had data forwarded from stores | 359system.cpu.iq.FU_type_0::total 307769548 # Type of FU issued 360system.cpu.iq.rate 2.511672 # Inst issue rate 361system.cpu.iq.fu_busy_cnt 2590655 # FU busy when requested 362system.cpu.iq.fu_busy_rate 0.008418 # FU busy rate (busy events/executed inst) 363system.cpu.iq.int_inst_queue_reads 740853926 # Number of integer instruction queue reads 364system.cpu.iq.int_inst_queue_writes 369529188 # Number of integer instruction queue writes 365system.cpu.iq.int_inst_queue_wakeup_accesses 304569650 # Number of integer instruction queue wakeup accesses 366system.cpu.iq.fp_inst_queue_reads 592 # Number of floating instruction queue reads 367system.cpu.iq.fp_inst_queue_writes 1017 # Number of floating instruction queue writes 368system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses 369system.cpu.iq.int_alu_accesses 310326577 # Number of integer alu accesses 370system.cpu.iq.fp_alu_accesses 285 # Number of floating point alu accesses 371system.cpu.iew.lsq.thread0.forwLoads 52294659 # Number of loads that had data forwarded from stores |
| 214system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 372system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 215system.cpu.iew.lsq.thread0.squashedLoads 14158611 # Number of loads squashed 216system.cpu.iew.lsq.thread0.ignoredResponses 53020 # Number of memory responses ignored because the instruction is squashed 217system.cpu.iew.lsq.thread0.memOrderViolation 31592 # Number of memory ordering violations 218system.cpu.iew.lsq.thread0.squashedStores 5034695 # Number of stores squashed | 373system.cpu.iew.lsq.thread0.squashedLoads 14174717 # Number of loads squashed 374system.cpu.iew.lsq.thread0.ignoredResponses 50650 # Number of memory responses ignored because the instruction is squashed 375system.cpu.iew.lsq.thread0.memOrderViolation 31690 # Number of memory ordering violations 376system.cpu.iew.lsq.thread0.squashedStores 5045561 # Number of stores squashed |
| 219system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 220system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 377system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 378system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 221system.cpu.iew.lsq.thread0.rescheduledLoads 3174 # Number of loads that were rescheduled 222system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked | 379system.cpu.iew.lsq.thread0.rescheduledLoads 3163 # Number of loads that were rescheduled 380system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked |
| 223system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 381system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 224system.cpu.iew.iewSquashCycles 6235050 # Number of cycles IEW is squashing 225system.cpu.iew.iewBlockCycles 247932 # Number of cycles IEW is blocking 226system.cpu.iew.iewUnblockCycles 19449 # Number of cycles IEW is unblocking 227system.cpu.iew.iewDispatchedInsts 323875287 # Number of instructions dispatched to IQ 228system.cpu.iew.iewDispSquashedInsts 344865 # Number of squashed instructions skipped by dispatch 229system.cpu.iew.iewDispLoadInsts 104937995 # Number of dispatched load instructions 230system.cpu.iew.iewDispStoreInsts 36474446 # Number of dispatched store instructions 231system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions 232system.cpu.iew.iewIQFullEvents 247 # Number of times the IQ has become full, causing a stall 233system.cpu.iew.iewLSQFullEvents 894 # Number of times the LSQ has become full, causing a stall 234system.cpu.iew.memOrderViolationEvents 31592 # Number of memory order violations 235system.cpu.iew.predictedTakenIncorrect 595265 # Number of branches that were predicted taken incorrectly 236system.cpu.iew.predictedNotTakenIncorrect 583416 # Number of branches that were predicted not taken incorrectly 237system.cpu.iew.branchMispredicts 1178681 # Number of branch mispredicts detected at execute 238system.cpu.iew.iewExecutedInsts 305536893 # Number of executed instructions 239system.cpu.iew.iewExecLoadInsts 98199399 # Number of load instructions executed 240system.cpu.iew.iewExecSquashedInsts 2192516 # Number of squashed instructions skipped in execute | 382system.cpu.iew.iewSquashCycles 6242549 # Number of cycles IEW is squashing 383system.cpu.iew.iewBlockCycles 128946 # Number of cycles IEW is blocking 384system.cpu.iew.iewUnblockCycles 5786 # Number of cycles IEW is unblocking 385system.cpu.iew.iewDispatchedInsts 323947085 # Number of instructions dispatched to IQ 386system.cpu.iew.iewDispSquashedInsts 341652 # Number of squashed instructions skipped by dispatch 387system.cpu.iew.iewDispLoadInsts 104954101 # Number of dispatched load instructions 388system.cpu.iew.iewDispStoreInsts 36485312 # Number of dispatched store instructions 389system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions 390system.cpu.iew.iewIQFullEvents 376 # Number of times the IQ has become full, causing a stall 391system.cpu.iew.iewLSQFullEvents 886 # Number of times the LSQ has become full, causing a stall 392system.cpu.iew.memOrderViolationEvents 31690 # Number of memory order violations 393system.cpu.iew.predictedTakenIncorrect 595739 # Number of branches that were predicted taken incorrectly 394system.cpu.iew.predictedNotTakenIncorrect 583103 # Number of branches that were predicted not taken incorrectly 395system.cpu.iew.branchMispredicts 1178842 # Number of branch mispredicts detected at execute 396system.cpu.iew.iewExecutedInsts 305571382 # Number of executed instructions 397system.cpu.iew.iewExecLoadInsts 98206856 # Number of load instructions executed 398system.cpu.iew.iewExecSquashedInsts 2198166 # Number of squashed instructions skipped in execute |
| 241system.cpu.iew.exec_swp 0 # number of swp insts executed 242system.cpu.iew.exec_nop 0 # number of nop insts executed | 399system.cpu.iew.exec_swp 0 # number of swp insts executed 400system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 243system.cpu.iew.exec_refs 131640830 # number of memory reference insts executed 244system.cpu.iew.exec_branches 31219911 # Number of branches executed 245system.cpu.iew.exec_stores 33441431 # Number of stores executed 246system.cpu.iew.exec_rate 2.484547 # Inst execution rate 247system.cpu.iew.wb_sent 304949933 # cumulative count of insts sent to commit 248system.cpu.iew.wb_count 304533968 # cumulative count of insts written-back 249system.cpu.iew.wb_producers 225863686 # num instructions producing a value 250system.cpu.iew.wb_consumers 311805704 # num instructions consuming a value | 401system.cpu.iew.exec_refs 131649773 # number of memory reference insts executed 402system.cpu.iew.exec_branches 31223750 # Number of branches executed 403system.cpu.iew.exec_stores 33442917 # Number of stores executed 404system.cpu.iew.exec_rate 2.493733 # Inst execution rate 405system.cpu.iew.wb_sent 304986534 # cumulative count of insts sent to commit 406system.cpu.iew.wb_count 304569837 # cumulative count of insts written-back 407system.cpu.iew.wb_producers 226002140 # num instructions producing a value 408system.cpu.iew.wb_consumers 312068538 # num instructions consuming a value |
| 251system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 409system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 252system.cpu.iew.wb_rate 2.476392 # insts written-back per cycle 253system.cpu.iew.wb_fanout 0.724373 # average fanout of values written-back | 410system.cpu.iew.wb_rate 2.485559 # insts written-back per cycle 411system.cpu.iew.wb_fanout 0.724207 # average fanout of values written-back |
| 254system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 412system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 255system.cpu.commit.commitSquashedInsts 45684582 # The number of squashed insts skipped by commit | 413system.cpu.commit.commitSquashedInsts 45756293 # The number of squashed insts skipped by commit |
| 256system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards | 414system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards |
| 257system.cpu.commit.branchMispredicts 1083935 # The number of times a branch was mispredicted 258system.cpu.commit.committed_per_cycle::samples 116711161 # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::mean 2.383598 # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::stdev 2.781080 # Number of insts commited each cycle | 415system.cpu.commit.branchMispredicts 1084042 # The number of times a branch was mispredicted 416system.cpu.commit.committed_per_cycle::samples 116264937 # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::mean 2.392746 # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::stdev 2.783730 # Number of insts commited each cycle |
| 261system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 419system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 262system.cpu.commit.committed_per_cycle::0 38716768 33.17% 33.17% # Number of insts commited each cycle 263system.cpu.commit.committed_per_cycle::1 22386952 19.18% 52.35% # Number of insts commited each cycle 264system.cpu.commit.committed_per_cycle::2 17053265 14.61% 66.97% # Number of insts commited each cycle 265system.cpu.commit.committed_per_cycle::3 13105313 11.23% 78.20% # Number of insts commited each cycle 266system.cpu.commit.committed_per_cycle::4 2048873 1.76% 79.95% # Number of insts commited each cycle 267system.cpu.commit.committed_per_cycle::5 3220721 2.76% 82.71% # Number of insts commited each cycle 268system.cpu.commit.committed_per_cycle::6 1361336 1.17% 83.88% # Number of insts commited each cycle 269system.cpu.commit.committed_per_cycle::7 627536 0.54% 84.41% # Number of insts commited each cycle 270system.cpu.commit.committed_per_cycle::8 18190397 15.59% 100.00% # Number of insts commited each cycle | 420system.cpu.commit.committed_per_cycle::0 38380575 33.01% 33.01% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::1 22255868 19.14% 52.15% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::2 17068651 14.68% 66.83% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::3 13099730 11.27% 78.10% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::4 2025175 1.74% 79.84% # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::5 3235783 2.78% 82.63% # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::6 1359435 1.17% 83.80% # Number of insts commited each cycle 427system.cpu.commit.committed_per_cycle::7 653883 0.56% 84.36% # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::8 18185837 15.64% 100.00% # Number of insts commited each cycle |
| 271system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 272system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 273system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 429system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 430system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 431system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 274system.cpu.commit.committed_per_cycle::total 116711161 # Number of insts commited each cycle | 432system.cpu.commit.committed_per_cycle::total 116264937 # Number of insts commited each cycle |
| 275system.cpu.commit.committedInsts 157988547 # Number of instructions committed 276system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed 277system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 278system.cpu.commit.refs 122219135 # Number of memory references committed 279system.cpu.commit.loads 90779384 # Number of loads committed 280system.cpu.commit.membars 0 # Number of memory barriers committed 281system.cpu.commit.branches 29309705 # Number of branches committed 282system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 283system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. 284system.cpu.commit.function_calls 0 # Number of function calls committed. | 433system.cpu.commit.committedInsts 157988547 # Number of instructions committed 434system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed 435system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 436system.cpu.commit.refs 122219135 # Number of memory references committed 437system.cpu.commit.loads 90779384 # Number of loads committed 438system.cpu.commit.membars 0 # Number of memory barriers committed 439system.cpu.commit.branches 29309705 # Number of branches committed 440system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 441system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. 442system.cpu.commit.function_calls 0 # Number of function calls committed. |
| 285system.cpu.commit.bw_lim_events 18190397 # number cycles where commit BW limit reached | 443system.cpu.commit.bw_lim_events 18185837 # number cycles where commit BW limit reached |
| 286system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 444system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 287system.cpu.rob.rob_reads 422397808 # The number of ROB reads 288system.cpu.rob.rob_writes 653994696 # The number of ROB writes 289system.cpu.timesIdled 646 # Number of times that the entire CPU went into an idle state and unscheduled itself 290system.cpu.idleCycles 28665 # Total number of cycles that the CPU has spent unscheduled due to idling | 445system.cpu.rob.rob_reads 422027855 # The number of ROB reads 446system.cpu.rob.rob_writes 654145762 # The number of ROB writes 447system.cpu.timesIdled 622 # Number of times that the entire CPU went into an idle state and unscheduled itself 448system.cpu.idleCycles 28257 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 291system.cpu.committedInsts 157988547 # Number of Instructions Simulated 292system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated 293system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated | 449system.cpu.committedInsts 157988547 # Number of Instructions Simulated 450system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated 451system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated |
| 294system.cpu.cpi 0.778378 # CPI: Cycles Per Instruction 295system.cpu.cpi_total 0.778378 # CPI: Total CPI of All Threads 296system.cpu.ipc 1.284722 # IPC: Instructions Per Cycle 297system.cpu.ipc_total 1.284722 # IPC: Total IPC of All Threads 298system.cpu.int_regfile_reads 598611638 # number of integer regfile reads 299system.cpu.int_regfile_writes 305159096 # number of integer regfile writes 300system.cpu.fp_regfile_reads 198 # number of floating regfile reads 301system.cpu.fp_regfile_writes 109 # number of floating regfile writes 302system.cpu.misc_regfile_reads 195504004 # number of misc regfile reads 303system.cpu.icache.replacements 86 # number of replacements 304system.cpu.icache.tagsinuse 846.025687 # Cycle average of tags in use 305system.cpu.icache.total_refs 27171094 # Total number of references to valid blocks. 306system.cpu.icache.sampled_refs 1075 # Sample count of references to valid blocks. 307system.cpu.icache.avg_refs 25275.436279 # Average number of references to valid blocks. | 452system.cpu.cpi 0.775599 # CPI: Cycles Per Instruction 453system.cpu.cpi_total 0.775599 # CPI: Total CPI of All Threads 454system.cpu.ipc 1.289326 # IPC: Instructions Per Cycle 455system.cpu.ipc_total 1.289326 # IPC: Total IPC of All Threads 456system.cpu.int_regfile_reads 598644238 # number of integer regfile reads 457system.cpu.int_regfile_writes 305189502 # number of integer regfile writes 458system.cpu.fp_regfile_reads 171 # number of floating regfile reads 459system.cpu.fp_regfile_writes 94 # number of floating regfile writes 460system.cpu.misc_regfile_reads 195525442 # number of misc regfile reads 461system.cpu.icache.replacements 87 # number of replacements 462system.cpu.icache.tagsinuse 849.665087 # Cycle average of tags in use 463system.cpu.icache.total_refs 27178218 # Total number of references to valid blocks. 464system.cpu.icache.sampled_refs 1083 # Sample count of references to valid blocks. 465system.cpu.icache.avg_refs 25095.307479 # Average number of references to valid blocks. |
| 308system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 466system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 309system.cpu.icache.occ_blocks::cpu.inst 846.025687 # Average occupied blocks per requestor 310system.cpu.icache.occ_percent::cpu.inst 0.413098 # Average percentage of cache occupancy 311system.cpu.icache.occ_percent::total 0.413098 # Average percentage of cache occupancy 312system.cpu.icache.ReadReq_hits::cpu.inst 27171094 # number of ReadReq hits 313system.cpu.icache.ReadReq_hits::total 27171094 # number of ReadReq hits 314system.cpu.icache.demand_hits::cpu.inst 27171094 # number of demand (read+write) hits 315system.cpu.icache.demand_hits::total 27171094 # number of demand (read+write) hits 316system.cpu.icache.overall_hits::cpu.inst 27171094 # number of overall hits 317system.cpu.icache.overall_hits::total 27171094 # number of overall hits 318system.cpu.icache.ReadReq_misses::cpu.inst 1397 # number of ReadReq misses 319system.cpu.icache.ReadReq_misses::total 1397 # number of ReadReq misses 320system.cpu.icache.demand_misses::cpu.inst 1397 # number of demand (read+write) misses 321system.cpu.icache.demand_misses::total 1397 # number of demand (read+write) misses 322system.cpu.icache.overall_misses::cpu.inst 1397 # number of overall misses 323system.cpu.icache.overall_misses::total 1397 # number of overall misses 324system.cpu.icache.ReadReq_miss_latency::cpu.inst 49824500 # number of ReadReq miss cycles 325system.cpu.icache.ReadReq_miss_latency::total 49824500 # number of ReadReq miss cycles 326system.cpu.icache.demand_miss_latency::cpu.inst 49824500 # number of demand (read+write) miss cycles 327system.cpu.icache.demand_miss_latency::total 49824500 # number of demand (read+write) miss cycles 328system.cpu.icache.overall_miss_latency::cpu.inst 49824500 # number of overall miss cycles 329system.cpu.icache.overall_miss_latency::total 49824500 # number of overall miss cycles 330system.cpu.icache.ReadReq_accesses::cpu.inst 27172491 # number of ReadReq accesses(hits+misses) 331system.cpu.icache.ReadReq_accesses::total 27172491 # number of ReadReq accesses(hits+misses) 332system.cpu.icache.demand_accesses::cpu.inst 27172491 # number of demand (read+write) accesses 333system.cpu.icache.demand_accesses::total 27172491 # number of demand (read+write) accesses 334system.cpu.icache.overall_accesses::cpu.inst 27172491 # number of overall (read+write) accesses 335system.cpu.icache.overall_accesses::total 27172491 # number of overall (read+write) accesses 336system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses 337system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 338system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses 339system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses 340system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses 341system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses 342system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35665.354331 # average ReadReq miss latency 343system.cpu.icache.ReadReq_avg_miss_latency::total 35665.354331 # average ReadReq miss latency 344system.cpu.icache.demand_avg_miss_latency::cpu.inst 35665.354331 # average overall miss latency 345system.cpu.icache.demand_avg_miss_latency::total 35665.354331 # average overall miss latency 346system.cpu.icache.overall_avg_miss_latency::cpu.inst 35665.354331 # average overall miss latency 347system.cpu.icache.overall_avg_miss_latency::total 35665.354331 # average overall miss latency | 467system.cpu.icache.occ_blocks::cpu.inst 849.665087 # Average occupied blocks per requestor 468system.cpu.icache.occ_percent::cpu.inst 0.414876 # Average percentage of cache occupancy 469system.cpu.icache.occ_percent::total 0.414876 # Average percentage of cache occupancy 470system.cpu.icache.ReadReq_hits::cpu.inst 27178218 # number of ReadReq hits 471system.cpu.icache.ReadReq_hits::total 27178218 # number of ReadReq hits 472system.cpu.icache.demand_hits::cpu.inst 27178218 # number of demand (read+write) hits 473system.cpu.icache.demand_hits::total 27178218 # number of demand (read+write) hits 474system.cpu.icache.overall_hits::cpu.inst 27178218 # number of overall hits 475system.cpu.icache.overall_hits::total 27178218 # number of overall hits 476system.cpu.icache.ReadReq_misses::cpu.inst 1372 # number of ReadReq misses 477system.cpu.icache.ReadReq_misses::total 1372 # number of ReadReq misses 478system.cpu.icache.demand_misses::cpu.inst 1372 # number of demand (read+write) misses 479system.cpu.icache.demand_misses::total 1372 # number of demand (read+write) misses 480system.cpu.icache.overall_misses::cpu.inst 1372 # number of overall misses 481system.cpu.icache.overall_misses::total 1372 # number of overall misses 482system.cpu.icache.ReadReq_miss_latency::cpu.inst 45099500 # number of ReadReq miss cycles 483system.cpu.icache.ReadReq_miss_latency::total 45099500 # number of ReadReq miss cycles 484system.cpu.icache.demand_miss_latency::cpu.inst 45099500 # number of demand (read+write) miss cycles 485system.cpu.icache.demand_miss_latency::total 45099500 # number of demand (read+write) miss cycles 486system.cpu.icache.overall_miss_latency::cpu.inst 45099500 # number of overall miss cycles 487system.cpu.icache.overall_miss_latency::total 45099500 # number of overall miss cycles 488system.cpu.icache.ReadReq_accesses::cpu.inst 27179590 # number of ReadReq accesses(hits+misses) 489system.cpu.icache.ReadReq_accesses::total 27179590 # number of ReadReq accesses(hits+misses) 490system.cpu.icache.demand_accesses::cpu.inst 27179590 # number of demand (read+write) accesses 491system.cpu.icache.demand_accesses::total 27179590 # number of demand (read+write) accesses 492system.cpu.icache.overall_accesses::cpu.inst 27179590 # number of overall (read+write) accesses 493system.cpu.icache.overall_accesses::total 27179590 # number of overall (read+write) accesses 494system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses 495system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses 496system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses 497system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses 498system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses 499system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses 500system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32871.355685 # average ReadReq miss latency 501system.cpu.icache.ReadReq_avg_miss_latency::total 32871.355685 # average ReadReq miss latency 502system.cpu.icache.demand_avg_miss_latency::cpu.inst 32871.355685 # average overall miss latency 503system.cpu.icache.demand_avg_miss_latency::total 32871.355685 # average overall miss latency 504system.cpu.icache.overall_avg_miss_latency::cpu.inst 32871.355685 # average overall miss latency 505system.cpu.icache.overall_avg_miss_latency::total 32871.355685 # average overall miss latency |
| 348system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu.icache.fast_writes 0 # number of fast writes performed 355system.cpu.icache.cache_copies 0 # number of cache copies performed | 506system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 507system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 508system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 509system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 510system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 511system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 512system.cpu.icache.fast_writes 0 # number of fast writes performed 513system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 356system.cpu.icache.ReadReq_mshr_hits::cpu.inst 320 # number of ReadReq MSHR hits 357system.cpu.icache.ReadReq_mshr_hits::total 320 # number of ReadReq MSHR hits 358system.cpu.icache.demand_mshr_hits::cpu.inst 320 # number of demand (read+write) MSHR hits 359system.cpu.icache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits 360system.cpu.icache.overall_mshr_hits::cpu.inst 320 # number of overall MSHR hits 361system.cpu.icache.overall_mshr_hits::total 320 # number of overall MSHR hits 362system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses 363system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses 364system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses 365system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses 366system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses 367system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses 368system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39164500 # number of ReadReq MSHR miss cycles 369system.cpu.icache.ReadReq_mshr_miss_latency::total 39164500 # number of ReadReq MSHR miss cycles 370system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39164500 # number of demand (read+write) MSHR miss cycles 371system.cpu.icache.demand_mshr_miss_latency::total 39164500 # number of demand (read+write) MSHR miss cycles 372system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39164500 # number of overall MSHR miss cycles 373system.cpu.icache.overall_mshr_miss_latency::total 39164500 # number of overall MSHR miss cycles | 514system.cpu.icache.ReadReq_mshr_hits::cpu.inst 283 # number of ReadReq MSHR hits 515system.cpu.icache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits 516system.cpu.icache.demand_mshr_hits::cpu.inst 283 # number of demand (read+write) MSHR hits 517system.cpu.icache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits 518system.cpu.icache.overall_mshr_hits::cpu.inst 283 # number of overall MSHR hits 519system.cpu.icache.overall_mshr_hits::total 283 # number of overall MSHR hits 520system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1089 # number of ReadReq MSHR misses 521system.cpu.icache.ReadReq_mshr_misses::total 1089 # number of ReadReq MSHR misses 522system.cpu.icache.demand_mshr_misses::cpu.inst 1089 # number of demand (read+write) MSHR misses 523system.cpu.icache.demand_mshr_misses::total 1089 # number of demand (read+write) MSHR misses 524system.cpu.icache.overall_mshr_misses::cpu.inst 1089 # number of overall MSHR misses 525system.cpu.icache.overall_mshr_misses::total 1089 # number of overall MSHR misses 526system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36146000 # number of ReadReq MSHR miss cycles 527system.cpu.icache.ReadReq_mshr_miss_latency::total 36146000 # number of ReadReq MSHR miss cycles 528system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36146000 # number of demand (read+write) MSHR miss cycles 529system.cpu.icache.demand_mshr_miss_latency::total 36146000 # number of demand (read+write) MSHR miss cycles 530system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36146000 # number of overall MSHR miss cycles 531system.cpu.icache.overall_mshr_miss_latency::total 36146000 # number of overall MSHR miss cycles |
| 374system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 375system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 376system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 377system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 378system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 379system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses | 532system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 533system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses 534system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 535system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses 536system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 537system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses |
| 380system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36364.438254 # average ReadReq mshr miss latency 381system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36364.438254 # average ReadReq mshr miss latency 382system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36364.438254 # average overall mshr miss latency 383system.cpu.icache.demand_avg_mshr_miss_latency::total 36364.438254 # average overall mshr miss latency 384system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36364.438254 # average overall mshr miss latency 385system.cpu.icache.overall_avg_mshr_miss_latency::total 36364.438254 # average overall mshr miss latency | 538system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33191.919192 # average ReadReq mshr miss latency 539system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33191.919192 # average ReadReq mshr miss latency 540system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33191.919192 # average overall mshr miss latency 541system.cpu.icache.demand_avg_mshr_miss_latency::total 33191.919192 # average overall mshr miss latency 542system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33191.919192 # average overall mshr miss latency 543system.cpu.icache.overall_avg_mshr_miss_latency::total 33191.919192 # average overall mshr miss latency |
| 386system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 544system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 387system.cpu.dcache.replacements 2071944 # number of replacements 388system.cpu.dcache.tagsinuse 4071.467534 # Cycle average of tags in use 389system.cpu.dcache.total_refs 74936342 # Total number of references to valid blocks. 390system.cpu.dcache.sampled_refs 2076040 # Sample count of references to valid blocks. 391system.cpu.dcache.avg_refs 36.095808 # Average number of references to valid blocks. 392system.cpu.dcache.warmup_cycle 21468323000 # Cycle when the warmup percentage was hit. 393system.cpu.dcache.occ_blocks::cpu.data 4071.467534 # Average occupied blocks per requestor 394system.cpu.dcache.occ_percent::cpu.data 0.994011 # Average percentage of cache occupancy 395system.cpu.dcache.occ_percent::total 0.994011 # Average percentage of cache occupancy 396system.cpu.dcache.ReadReq_hits::cpu.data 43578741 # number of ReadReq hits 397system.cpu.dcache.ReadReq_hits::total 43578741 # number of ReadReq hits 398system.cpu.dcache.WriteReq_hits::cpu.data 31357591 # number of WriteReq hits 399system.cpu.dcache.WriteReq_hits::total 31357591 # number of WriteReq hits 400system.cpu.dcache.demand_hits::cpu.data 74936332 # number of demand (read+write) hits 401system.cpu.dcache.demand_hits::total 74936332 # number of demand (read+write) hits 402system.cpu.dcache.overall_hits::cpu.data 74936332 # number of overall hits 403system.cpu.dcache.overall_hits::total 74936332 # number of overall hits 404system.cpu.dcache.ReadReq_misses::cpu.data 2256554 # number of ReadReq misses 405system.cpu.dcache.ReadReq_misses::total 2256554 # number of ReadReq misses 406system.cpu.dcache.WriteReq_misses::cpu.data 82160 # number of WriteReq misses 407system.cpu.dcache.WriteReq_misses::total 82160 # number of WriteReq misses 408system.cpu.dcache.demand_misses::cpu.data 2338714 # number of demand (read+write) misses 409system.cpu.dcache.demand_misses::total 2338714 # number of demand (read+write) misses 410system.cpu.dcache.overall_misses::cpu.data 2338714 # number of overall misses 411system.cpu.dcache.overall_misses::total 2338714 # number of overall misses 412system.cpu.dcache.ReadReq_miss_latency::cpu.data 9114703500 # number of ReadReq miss cycles 413system.cpu.dcache.ReadReq_miss_latency::total 9114703500 # number of ReadReq miss cycles 414system.cpu.dcache.WriteReq_miss_latency::cpu.data 1290980000 # number of WriteReq miss cycles 415system.cpu.dcache.WriteReq_miss_latency::total 1290980000 # number of WriteReq miss cycles 416system.cpu.dcache.demand_miss_latency::cpu.data 10405683500 # number of demand (read+write) miss cycles 417system.cpu.dcache.demand_miss_latency::total 10405683500 # number of demand (read+write) miss cycles 418system.cpu.dcache.overall_miss_latency::cpu.data 10405683500 # number of overall miss cycles 419system.cpu.dcache.overall_miss_latency::total 10405683500 # number of overall miss cycles 420system.cpu.dcache.ReadReq_accesses::cpu.data 45835295 # number of ReadReq accesses(hits+misses) 421system.cpu.dcache.ReadReq_accesses::total 45835295 # number of ReadReq accesses(hits+misses) | 545system.cpu.dcache.replacements 2071993 # number of replacements 546system.cpu.dcache.tagsinuse 4071.813370 # Cycle average of tags in use 547system.cpu.dcache.total_refs 74974075 # Total number of references to valid blocks. 548system.cpu.dcache.sampled_refs 2076089 # Sample count of references to valid blocks. 549system.cpu.dcache.avg_refs 36.113131 # Average number of references to valid blocks. 550system.cpu.dcache.warmup_cycle 21436010000 # Cycle when the warmup percentage was hit. 551system.cpu.dcache.occ_blocks::cpu.data 4071.813370 # Average occupied blocks per requestor 552system.cpu.dcache.occ_percent::cpu.data 0.994095 # Average percentage of cache occupancy 553system.cpu.dcache.occ_percent::total 0.994095 # Average percentage of cache occupancy 554system.cpu.dcache.ReadReq_hits::cpu.data 43616503 # number of ReadReq hits 555system.cpu.dcache.ReadReq_hits::total 43616503 # number of ReadReq hits 556system.cpu.dcache.WriteReq_hits::cpu.data 31357567 # number of WriteReq hits 557system.cpu.dcache.WriteReq_hits::total 31357567 # number of WriteReq hits 558system.cpu.dcache.demand_hits::cpu.data 74974070 # number of demand (read+write) hits 559system.cpu.dcache.demand_hits::total 74974070 # number of demand (read+write) hits 560system.cpu.dcache.overall_hits::cpu.data 74974070 # number of overall hits 561system.cpu.dcache.overall_hits::total 74974070 # number of overall hits 562system.cpu.dcache.ReadReq_misses::cpu.data 2256459 # number of ReadReq misses 563system.cpu.dcache.ReadReq_misses::total 2256459 # number of ReadReq misses 564system.cpu.dcache.WriteReq_misses::cpu.data 82184 # number of WriteReq misses 565system.cpu.dcache.WriteReq_misses::total 82184 # number of WriteReq misses 566system.cpu.dcache.demand_misses::cpu.data 2338643 # number of demand (read+write) misses 567system.cpu.dcache.demand_misses::total 2338643 # number of demand (read+write) misses 568system.cpu.dcache.overall_misses::cpu.data 2338643 # number of overall misses 569system.cpu.dcache.overall_misses::total 2338643 # number of overall misses 570system.cpu.dcache.ReadReq_miss_latency::cpu.data 9093612500 # number of ReadReq miss cycles 571system.cpu.dcache.ReadReq_miss_latency::total 9093612500 # number of ReadReq miss cycles 572system.cpu.dcache.WriteReq_miss_latency::cpu.data 977800000 # number of WriteReq miss cycles 573system.cpu.dcache.WriteReq_miss_latency::total 977800000 # number of WriteReq miss cycles 574system.cpu.dcache.demand_miss_latency::cpu.data 10071412500 # number of demand (read+write) miss cycles 575system.cpu.dcache.demand_miss_latency::total 10071412500 # number of demand (read+write) miss cycles 576system.cpu.dcache.overall_miss_latency::cpu.data 10071412500 # number of overall miss cycles 577system.cpu.dcache.overall_miss_latency::total 10071412500 # number of overall miss cycles 578system.cpu.dcache.ReadReq_accesses::cpu.data 45872962 # number of ReadReq accesses(hits+misses) 579system.cpu.dcache.ReadReq_accesses::total 45872962 # number of ReadReq accesses(hits+misses) |
| 422system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) | 580system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) 581system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) |
| 424system.cpu.dcache.demand_accesses::cpu.data 77275046 # number of demand (read+write) accesses 425system.cpu.dcache.demand_accesses::total 77275046 # number of demand (read+write) accesses 426system.cpu.dcache.overall_accesses::cpu.data 77275046 # number of overall (read+write) accesses 427system.cpu.dcache.overall_accesses::total 77275046 # number of overall (read+write) accesses 428system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049232 # miss rate for ReadReq accesses 429system.cpu.dcache.ReadReq_miss_rate::total 0.049232 # miss rate for ReadReq accesses 430system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002613 # miss rate for WriteReq accesses 431system.cpu.dcache.WriteReq_miss_rate::total 0.002613 # miss rate for WriteReq accesses 432system.cpu.dcache.demand_miss_rate::cpu.data 0.030265 # miss rate for demand accesses 433system.cpu.dcache.demand_miss_rate::total 0.030265 # miss rate for demand accesses 434system.cpu.dcache.overall_miss_rate::cpu.data 0.030265 # miss rate for overall accesses 435system.cpu.dcache.overall_miss_rate::total 0.030265 # miss rate for overall accesses 436system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4039.213553 # average ReadReq miss latency 437system.cpu.dcache.ReadReq_avg_miss_latency::total 4039.213553 # average ReadReq miss latency 438system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15712.999026 # average WriteReq miss latency 439system.cpu.dcache.WriteReq_avg_miss_latency::total 15712.999026 # average WriteReq miss latency 440system.cpu.dcache.demand_avg_miss_latency::cpu.data 4449.318514 # average overall miss latency 441system.cpu.dcache.demand_avg_miss_latency::total 4449.318514 # average overall miss latency 442system.cpu.dcache.overall_avg_miss_latency::cpu.data 4449.318514 # average overall miss latency 443system.cpu.dcache.overall_avg_miss_latency::total 4449.318514 # average overall miss latency | 582system.cpu.dcache.demand_accesses::cpu.data 77312713 # number of demand (read+write) accesses 583system.cpu.dcache.demand_accesses::total 77312713 # number of demand (read+write) accesses 584system.cpu.dcache.overall_accesses::cpu.data 77312713 # number of overall (read+write) accesses 585system.cpu.dcache.overall_accesses::total 77312713 # number of overall (read+write) accesses 586system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049189 # miss rate for ReadReq accesses 587system.cpu.dcache.ReadReq_miss_rate::total 0.049189 # miss rate for ReadReq accesses 588system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002614 # miss rate for WriteReq accesses 589system.cpu.dcache.WriteReq_miss_rate::total 0.002614 # miss rate for WriteReq accesses 590system.cpu.dcache.demand_miss_rate::cpu.data 0.030249 # miss rate for demand accesses 591system.cpu.dcache.demand_miss_rate::total 0.030249 # miss rate for demand accesses 592system.cpu.dcache.overall_miss_rate::cpu.data 0.030249 # miss rate for overall accesses 593system.cpu.dcache.overall_miss_rate::total 0.030249 # miss rate for overall accesses 594system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4030.036664 # average ReadReq miss latency 595system.cpu.dcache.ReadReq_avg_miss_latency::total 4030.036664 # average ReadReq miss latency 596system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11897.692982 # average WriteReq miss latency 597system.cpu.dcache.WriteReq_avg_miss_latency::total 11897.692982 # average WriteReq miss latency 598system.cpu.dcache.demand_avg_miss_latency::cpu.data 4306.519849 # average overall miss latency 599system.cpu.dcache.demand_avg_miss_latency::total 4306.519849 # average overall miss latency 600system.cpu.dcache.overall_avg_miss_latency::cpu.data 4306.519849 # average overall miss latency 601system.cpu.dcache.overall_avg_miss_latency::total 4306.519849 # average overall miss latency |
| 444system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 445system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 446system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 447system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 448system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 449system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 450system.cpu.dcache.fast_writes 0 # number of fast writes performed 451system.cpu.dcache.cache_copies 0 # number of cache copies performed | 602system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 603system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 604system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 605system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 606system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 607system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 608system.cpu.dcache.fast_writes 0 # number of fast writes performed 609system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 452system.cpu.dcache.writebacks::writebacks 2064785 # number of writebacks 453system.cpu.dcache.writebacks::total 2064785 # number of writebacks 454system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262571 # number of ReadReq MSHR hits 455system.cpu.dcache.ReadReq_mshr_hits::total 262571 # number of ReadReq MSHR hits 456system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99 # number of WriteReq MSHR hits 457system.cpu.dcache.WriteReq_mshr_hits::total 99 # number of WriteReq MSHR hits 458system.cpu.dcache.demand_mshr_hits::cpu.data 262670 # number of demand (read+write) MSHR hits 459system.cpu.dcache.demand_mshr_hits::total 262670 # number of demand (read+write) MSHR hits 460system.cpu.dcache.overall_mshr_hits::cpu.data 262670 # number of overall MSHR hits 461system.cpu.dcache.overall_mshr_hits::total 262670 # number of overall MSHR hits 462system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1993983 # number of ReadReq MSHR misses 463system.cpu.dcache.ReadReq_mshr_misses::total 1993983 # number of ReadReq MSHR misses 464system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82061 # number of WriteReq MSHR misses 465system.cpu.dcache.WriteReq_mshr_misses::total 82061 # number of WriteReq MSHR misses 466system.cpu.dcache.demand_mshr_misses::cpu.data 2076044 # number of demand (read+write) MSHR misses 467system.cpu.dcache.demand_mshr_misses::total 2076044 # number of demand (read+write) MSHR misses 468system.cpu.dcache.overall_mshr_misses::cpu.data 2076044 # number of overall MSHR misses 469system.cpu.dcache.overall_mshr_misses::total 2076044 # number of overall MSHR misses 470system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4061724500 # number of ReadReq MSHR miss cycles 471system.cpu.dcache.ReadReq_mshr_miss_latency::total 4061724500 # number of ReadReq MSHR miss cycles 472system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125939500 # number of WriteReq MSHR miss cycles 473system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125939500 # number of WriteReq MSHR miss cycles 474system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5187664000 # number of demand (read+write) MSHR miss cycles 475system.cpu.dcache.demand_mshr_miss_latency::total 5187664000 # number of demand (read+write) MSHR miss cycles 476system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5187664000 # number of overall MSHR miss cycles 477system.cpu.dcache.overall_mshr_miss_latency::total 5187664000 # number of overall MSHR miss cycles 478system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043503 # mshr miss rate for ReadReq accesses 479system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043503 # mshr miss rate for ReadReq accesses 480system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses 481system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses 482system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026866 # mshr miss rate for demand accesses 483system.cpu.dcache.demand_mshr_miss_rate::total 0.026866 # mshr miss rate for demand accesses 484system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026866 # mshr miss rate for overall accesses 485system.cpu.dcache.overall_mshr_miss_rate::total 0.026866 # mshr miss rate for overall accesses 486system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2036.990536 # average ReadReq mshr miss latency 487system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2036.990536 # average ReadReq mshr miss latency 488system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13720.762603 # average WriteReq mshr miss latency 489system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13720.762603 # average WriteReq mshr miss latency 490system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2498.821798 # average overall mshr miss latency 491system.cpu.dcache.demand_avg_mshr_miss_latency::total 2498.821798 # average overall mshr miss latency 492system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2498.821798 # average overall mshr miss latency 493system.cpu.dcache.overall_avg_mshr_miss_latency::total 2498.821798 # average overall mshr miss latency | 610system.cpu.dcache.writebacks::writebacks 2064741 # number of writebacks 611system.cpu.dcache.writebacks::total 2064741 # number of writebacks 612system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262443 # number of ReadReq MSHR hits 613system.cpu.dcache.ReadReq_mshr_hits::total 262443 # number of ReadReq MSHR hits 614system.cpu.dcache.WriteReq_mshr_hits::cpu.data 102 # number of WriteReq MSHR hits 615system.cpu.dcache.WriteReq_mshr_hits::total 102 # number of WriteReq MSHR hits 616system.cpu.dcache.demand_mshr_hits::cpu.data 262545 # number of demand (read+write) MSHR hits 617system.cpu.dcache.demand_mshr_hits::total 262545 # number of demand (read+write) MSHR hits 618system.cpu.dcache.overall_mshr_hits::cpu.data 262545 # number of overall MSHR hits 619system.cpu.dcache.overall_mshr_hits::total 262545 # number of overall MSHR hits 620system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994016 # number of ReadReq MSHR misses 621system.cpu.dcache.ReadReq_mshr_misses::total 1994016 # number of ReadReq MSHR misses 622system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82082 # number of WriteReq MSHR misses 623system.cpu.dcache.WriteReq_mshr_misses::total 82082 # number of WriteReq MSHR misses 624system.cpu.dcache.demand_mshr_misses::cpu.data 2076098 # number of demand (read+write) MSHR misses 625system.cpu.dcache.demand_mshr_misses::total 2076098 # number of demand (read+write) MSHR misses 626system.cpu.dcache.overall_mshr_misses::cpu.data 2076098 # number of overall MSHR misses 627system.cpu.dcache.overall_mshr_misses::total 2076098 # number of overall MSHR misses 628system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4062202500 # number of ReadReq MSHR miss cycles 629system.cpu.dcache.ReadReq_mshr_miss_latency::total 4062202500 # number of ReadReq MSHR miss cycles 630system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 812900500 # number of WriteReq MSHR miss cycles 631system.cpu.dcache.WriteReq_mshr_miss_latency::total 812900500 # number of WriteReq MSHR miss cycles 632system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4875103000 # number of demand (read+write) MSHR miss cycles 633system.cpu.dcache.demand_mshr_miss_latency::total 4875103000 # number of demand (read+write) MSHR miss cycles 634system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4875103000 # number of overall MSHR miss cycles 635system.cpu.dcache.overall_mshr_miss_latency::total 4875103000 # number of overall MSHR miss cycles 636system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043468 # mshr miss rate for ReadReq accesses 637system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043468 # mshr miss rate for ReadReq accesses 638system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses 639system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses 640system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026853 # mshr miss rate for demand accesses 641system.cpu.dcache.demand_mshr_miss_rate::total 0.026853 # mshr miss rate for demand accesses 642system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026853 # mshr miss rate for overall accesses 643system.cpu.dcache.overall_mshr_miss_rate::total 0.026853 # mshr miss rate for overall accesses 644system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2037.196542 # average ReadReq mshr miss latency 645system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2037.196542 # average ReadReq mshr miss latency 646system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9903.517214 # average WriteReq mshr miss latency 647system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9903.517214 # average WriteReq mshr miss latency 648system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2348.204661 # average overall mshr miss latency 649system.cpu.dcache.demand_avg_mshr_miss_latency::total 2348.204661 # average overall mshr miss latency 650system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2348.204661 # average overall mshr miss latency 651system.cpu.dcache.overall_avg_mshr_miss_latency::total 2348.204661 # average overall mshr miss latency |
| 494system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 652system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 495system.cpu.l2cache.replacements 1463 # number of replacements 496system.cpu.l2cache.tagsinuse 19632.807637 # Cycle average of tags in use 497system.cpu.l2cache.total_refs 4026981 # Total number of references to valid blocks. 498system.cpu.l2cache.sampled_refs 30627 # Sample count of references to valid blocks. 499system.cpu.l2cache.avg_refs 131.484670 # Average number of references to valid blocks. | 653system.cpu.l2cache.replacements 1477 # number of replacements 654system.cpu.l2cache.tagsinuse 19662.234768 # Cycle average of tags in use 655system.cpu.l2cache.total_refs 4026933 # Total number of references to valid blocks. 656system.cpu.l2cache.sampled_refs 30639 # Sample count of references to valid blocks. 657system.cpu.l2cache.avg_refs 131.431607 # Average number of references to valid blocks. |
| 500system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 658system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 501system.cpu.l2cache.occ_blocks::writebacks 19126.604204 # Average occupied blocks per requestor 502system.cpu.l2cache.occ_blocks::cpu.inst 278.184174 # Average occupied blocks per requestor 503system.cpu.l2cache.occ_blocks::cpu.data 228.019260 # Average occupied blocks per requestor 504system.cpu.l2cache.occ_percent::writebacks 0.583698 # Average percentage of cache occupancy 505system.cpu.l2cache.occ_percent::cpu.inst 0.008490 # Average percentage of cache occupancy 506system.cpu.l2cache.occ_percent::cpu.data 0.006959 # Average percentage of cache occupancy 507system.cpu.l2cache.occ_percent::total 0.599146 # Average percentage of cache occupancy 508system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits 509system.cpu.l2cache.ReadReq_hits::cpu.data 1993318 # number of ReadReq hits 510system.cpu.l2cache.ReadReq_hits::total 1993325 # number of ReadReq hits 511system.cpu.l2cache.Writeback_hits::writebacks 2064785 # number of Writeback hits 512system.cpu.l2cache.Writeback_hits::total 2064785 # number of Writeback hits 513system.cpu.l2cache.ReadExReq_hits::cpu.data 53145 # number of ReadExReq hits 514system.cpu.l2cache.ReadExReq_hits::total 53145 # number of ReadExReq hits 515system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits 516system.cpu.l2cache.demand_hits::cpu.data 2046463 # number of demand (read+write) hits 517system.cpu.l2cache.demand_hits::total 2046470 # number of demand (read+write) hits 518system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits 519system.cpu.l2cache.overall_hits::cpu.data 2046463 # number of overall hits 520system.cpu.l2cache.overall_hits::total 2046470 # number of overall hits 521system.cpu.l2cache.ReadReq_misses::cpu.inst 1068 # number of ReadReq misses 522system.cpu.l2cache.ReadReq_misses::cpu.data 586 # number of ReadReq misses 523system.cpu.l2cache.ReadReq_misses::total 1654 # number of ReadReq misses 524system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 525system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses | 659system.cpu.l2cache.occ_blocks::writebacks 19155.060613 # Average occupied blocks per requestor 660system.cpu.l2cache.occ_blocks::cpu.inst 278.346040 # Average occupied blocks per requestor 661system.cpu.l2cache.occ_blocks::cpu.data 228.828114 # Average occupied blocks per requestor 662system.cpu.l2cache.occ_percent::writebacks 0.584566 # Average percentage of cache occupancy 663system.cpu.l2cache.occ_percent::cpu.inst 0.008494 # Average percentage of cache occupancy 664system.cpu.l2cache.occ_percent::cpu.data 0.006983 # Average percentage of cache occupancy 665system.cpu.l2cache.occ_percent::total 0.600044 # Average percentage of cache occupancy 666system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits 667system.cpu.l2cache.ReadReq_hits::cpu.data 1993342 # number of ReadReq hits 668system.cpu.l2cache.ReadReq_hits::total 1993350 # number of ReadReq hits 669system.cpu.l2cache.Writeback_hits::writebacks 2064741 # number of Writeback hits 670system.cpu.l2cache.Writeback_hits::total 2064741 # number of Writeback hits 671system.cpu.l2cache.ReadExReq_hits::cpu.data 53165 # number of ReadExReq hits 672system.cpu.l2cache.ReadExReq_hits::total 53165 # number of ReadExReq hits 673system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits 674system.cpu.l2cache.demand_hits::cpu.data 2046507 # number of demand (read+write) hits 675system.cpu.l2cache.demand_hits::total 2046515 # number of demand (read+write) hits 676system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits 677system.cpu.l2cache.overall_hits::cpu.data 2046507 # number of overall hits 678system.cpu.l2cache.overall_hits::total 2046515 # number of overall hits 679system.cpu.l2cache.ReadReq_misses::cpu.inst 1076 # number of ReadReq misses 680system.cpu.l2cache.ReadReq_misses::cpu.data 593 # number of ReadReq misses 681system.cpu.l2cache.ReadReq_misses::total 1669 # number of ReadReq misses 682system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 683system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses |
| 526system.cpu.l2cache.ReadExReq_misses::cpu.data 28993 # number of ReadExReq misses 527system.cpu.l2cache.ReadExReq_misses::total 28993 # number of ReadExReq misses | 684system.cpu.l2cache.ReadExReq_misses::cpu.data 28993 # number of ReadExReq misses 685system.cpu.l2cache.ReadExReq_misses::total 28993 # number of ReadExReq misses |
| 528system.cpu.l2cache.demand_misses::cpu.inst 1068 # number of demand (read+write) misses 529system.cpu.l2cache.demand_misses::cpu.data 29579 # number of demand (read+write) misses 530system.cpu.l2cache.demand_misses::total 30647 # number of demand (read+write) misses 531system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses 532system.cpu.l2cache.overall_misses::cpu.data 29579 # number of overall misses 533system.cpu.l2cache.overall_misses::total 30647 # number of overall misses 534system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38066500 # number of ReadReq miss cycles 535system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21080500 # number of ReadReq miss cycles 536system.cpu.l2cache.ReadReq_miss_latency::total 59147000 # number of ReadReq miss cycles 537system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 989282000 # number of ReadExReq miss cycles 538system.cpu.l2cache.ReadExReq_miss_latency::total 989282000 # number of ReadExReq miss cycles 539system.cpu.l2cache.demand_miss_latency::cpu.inst 38066500 # number of demand (read+write) miss cycles 540system.cpu.l2cache.demand_miss_latency::cpu.data 1010362500 # number of demand (read+write) miss cycles 541system.cpu.l2cache.demand_miss_latency::total 1048429000 # number of demand (read+write) miss cycles 542system.cpu.l2cache.overall_miss_latency::cpu.inst 38066500 # number of overall miss cycles 543system.cpu.l2cache.overall_miss_latency::cpu.data 1010362500 # number of overall miss cycles 544system.cpu.l2cache.overall_miss_latency::total 1048429000 # number of overall miss cycles 545system.cpu.l2cache.ReadReq_accesses::cpu.inst 1075 # number of ReadReq accesses(hits+misses) 546system.cpu.l2cache.ReadReq_accesses::cpu.data 1993904 # number of ReadReq accesses(hits+misses) 547system.cpu.l2cache.ReadReq_accesses::total 1994979 # number of ReadReq accesses(hits+misses) 548system.cpu.l2cache.Writeback_accesses::writebacks 2064785 # number of Writeback accesses(hits+misses) 549system.cpu.l2cache.Writeback_accesses::total 2064785 # number of Writeback accesses(hits+misses) 550system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 551system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 552system.cpu.l2cache.ReadExReq_accesses::cpu.data 82138 # number of ReadExReq accesses(hits+misses) 553system.cpu.l2cache.ReadExReq_accesses::total 82138 # number of ReadExReq accesses(hits+misses) 554system.cpu.l2cache.demand_accesses::cpu.inst 1075 # number of demand (read+write) accesses 555system.cpu.l2cache.demand_accesses::cpu.data 2076042 # number of demand (read+write) accesses 556system.cpu.l2cache.demand_accesses::total 2077117 # number of demand (read+write) accesses 557system.cpu.l2cache.overall_accesses::cpu.inst 1075 # number of overall (read+write) accesses 558system.cpu.l2cache.overall_accesses::cpu.data 2076042 # number of overall (read+write) accesses 559system.cpu.l2cache.overall_accesses::total 2077117 # number of overall (read+write) accesses 560system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993488 # miss rate for ReadReq accesses 561system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000294 # miss rate for ReadReq accesses 562system.cpu.l2cache.ReadReq_miss_rate::total 0.000829 # miss rate for ReadReq accesses | 686system.cpu.l2cache.demand_misses::cpu.inst 1076 # number of demand (read+write) misses 687system.cpu.l2cache.demand_misses::cpu.data 29586 # number of demand (read+write) misses 688system.cpu.l2cache.demand_misses::total 30662 # number of demand (read+write) misses 689system.cpu.l2cache.overall_misses::cpu.inst 1076 # number of overall misses 690system.cpu.l2cache.overall_misses::cpu.data 29586 # number of overall misses 691system.cpu.l2cache.overall_misses::total 30662 # number of overall misses 692system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35032500 # number of ReadReq miss cycles 693system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20747500 # number of ReadReq miss cycles 694system.cpu.l2cache.ReadReq_miss_latency::total 55780000 # number of ReadReq miss cycles 695system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 676068000 # number of ReadExReq miss cycles 696system.cpu.l2cache.ReadExReq_miss_latency::total 676068000 # number of ReadExReq miss cycles 697system.cpu.l2cache.demand_miss_latency::cpu.inst 35032500 # number of demand (read+write) miss cycles 698system.cpu.l2cache.demand_miss_latency::cpu.data 696815500 # number of demand (read+write) miss cycles 699system.cpu.l2cache.demand_miss_latency::total 731848000 # number of demand (read+write) miss cycles 700system.cpu.l2cache.overall_miss_latency::cpu.inst 35032500 # number of overall miss cycles 701system.cpu.l2cache.overall_miss_latency::cpu.data 696815500 # number of overall miss cycles 702system.cpu.l2cache.overall_miss_latency::total 731848000 # number of overall miss cycles 703system.cpu.l2cache.ReadReq_accesses::cpu.inst 1084 # number of ReadReq accesses(hits+misses) 704system.cpu.l2cache.ReadReq_accesses::cpu.data 1993935 # number of ReadReq accesses(hits+misses) 705system.cpu.l2cache.ReadReq_accesses::total 1995019 # number of ReadReq accesses(hits+misses) 706system.cpu.l2cache.Writeback_accesses::writebacks 2064741 # number of Writeback accesses(hits+misses) 707system.cpu.l2cache.Writeback_accesses::total 2064741 # number of Writeback accesses(hits+misses) 708system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) 709system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) 710system.cpu.l2cache.ReadExReq_accesses::cpu.data 82158 # number of ReadExReq accesses(hits+misses) 711system.cpu.l2cache.ReadExReq_accesses::total 82158 # number of ReadExReq accesses(hits+misses) 712system.cpu.l2cache.demand_accesses::cpu.inst 1084 # number of demand (read+write) accesses 713system.cpu.l2cache.demand_accesses::cpu.data 2076093 # number of demand (read+write) accesses 714system.cpu.l2cache.demand_accesses::total 2077177 # number of demand (read+write) accesses 715system.cpu.l2cache.overall_accesses::cpu.inst 1084 # number of overall (read+write) accesses 716system.cpu.l2cache.overall_accesses::cpu.data 2076093 # number of overall (read+write) accesses 717system.cpu.l2cache.overall_accesses::total 2077177 # number of overall (read+write) accesses 718system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992620 # miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000297 # miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_miss_rate::total 0.000837 # miss rate for ReadReq accesses |
| 563system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 564system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 721system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 722system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 565system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352979 # miss rate for ReadExReq accesses 566system.cpu.l2cache.ReadExReq_miss_rate::total 0.352979 # miss rate for ReadExReq accesses 567system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993488 # miss rate for demand accesses 568system.cpu.l2cache.demand_miss_rate::cpu.data 0.014248 # miss rate for demand accesses 569system.cpu.l2cache.demand_miss_rate::total 0.014755 # miss rate for demand accesses 570system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993488 # miss rate for overall accesses 571system.cpu.l2cache.overall_miss_rate::cpu.data 0.014248 # miss rate for overall accesses 572system.cpu.l2cache.overall_miss_rate::total 0.014755 # miss rate for overall accesses 573system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35642.790262 # average ReadReq miss latency 574system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35973.549488 # average ReadReq miss latency 575system.cpu.l2cache.ReadReq_avg_miss_latency::total 35759.975816 # average ReadReq miss latency 576system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34121.408616 # average ReadExReq miss latency 577system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34121.408616 # average ReadExReq miss latency 578system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35642.790262 # average overall miss latency 579system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34158.102032 # average overall miss latency 580system.cpu.l2cache.demand_avg_miss_latency::total 34209.841094 # average overall miss latency 581system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35642.790262 # average overall miss latency 582system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34158.102032 # average overall miss latency 583system.cpu.l2cache.overall_avg_miss_latency::total 34209.841094 # average overall miss latency | 723system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352893 # miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_miss_rate::total 0.352893 # miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992620 # miss rate for demand accesses 726system.cpu.l2cache.demand_miss_rate::cpu.data 0.014251 # miss rate for demand accesses 727system.cpu.l2cache.demand_miss_rate::total 0.014761 # miss rate for demand accesses 728system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992620 # miss rate for overall accesses 729system.cpu.l2cache.overall_miss_rate::cpu.data 0.014251 # miss rate for overall accesses 730system.cpu.l2cache.overall_miss_rate::total 0.014761 # miss rate for overall accesses 731system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32558.085502 # average ReadReq miss latency 732system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34987.352445 # average ReadReq miss latency 733system.cpu.l2cache.ReadReq_avg_miss_latency::total 33421.210306 # average ReadReq miss latency 734system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 23318.318215 # average ReadExReq miss latency 735system.cpu.l2cache.ReadExReq_avg_miss_latency::total 23318.318215 # average ReadExReq miss latency 736system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32558.085502 # average overall miss latency 737system.cpu.l2cache.demand_avg_miss_latency::cpu.data 23552.203745 # average overall miss latency 738system.cpu.l2cache.demand_avg_miss_latency::total 23868.240819 # average overall miss latency 739system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32558.085502 # average overall miss latency 740system.cpu.l2cache.overall_avg_miss_latency::cpu.data 23552.203745 # average overall miss latency 741system.cpu.l2cache.overall_avg_miss_latency::total 23868.240819 # average overall miss latency |
| 584system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 585system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 586system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 587system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 588system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 589system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 590system.cpu.l2cache.fast_writes 0 # number of fast writes performed 591system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 742system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 743system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 744system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 745system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 746system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 747system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 748system.cpu.l2cache.fast_writes 0 # number of fast writes performed 749system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 592system.cpu.l2cache.writebacks::writebacks 317 # number of writebacks 593system.cpu.l2cache.writebacks::total 317 # number of writebacks 594system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses 595system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 586 # number of ReadReq MSHR misses 596system.cpu.l2cache.ReadReq_mshr_misses::total 1654 # number of ReadReq MSHR misses 597system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 598system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses | 750system.cpu.l2cache.writebacks::writebacks 322 # number of writebacks 751system.cpu.l2cache.writebacks::total 322 # number of writebacks 752system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses 753system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 593 # number of ReadReq MSHR misses 754system.cpu.l2cache.ReadReq_mshr_misses::total 1669 # number of ReadReq MSHR misses 755system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses 756system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses |
| 599system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses 600system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses | 757system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses 758system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses |
| 601system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses 602system.cpu.l2cache.demand_mshr_misses::cpu.data 29579 # number of demand (read+write) MSHR misses 603system.cpu.l2cache.demand_mshr_misses::total 30647 # number of demand (read+write) MSHR misses 604system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses 605system.cpu.l2cache.overall_mshr_misses::cpu.data 29579 # number of overall MSHR misses 606system.cpu.l2cache.overall_mshr_misses::total 30647 # number of overall MSHR misses 607system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34670500 # number of ReadReq MSHR miss cycles 608system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19225500 # number of ReadReq MSHR miss cycles 609system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53896000 # number of ReadReq MSHR miss cycles 610system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 62000 # number of UpgradeReq MSHR miss cycles 611system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 62000 # number of UpgradeReq MSHR miss cycles 612system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899128500 # number of ReadExReq MSHR miss cycles 613system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899128500 # number of ReadExReq MSHR miss cycles 614system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34670500 # number of demand (read+write) MSHR miss cycles 615system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918354000 # number of demand (read+write) MSHR miss cycles 616system.cpu.l2cache.demand_mshr_miss_latency::total 953024500 # number of demand (read+write) MSHR miss cycles 617system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34670500 # number of overall MSHR miss cycles 618system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918354000 # number of overall MSHR miss cycles 619system.cpu.l2cache.overall_mshr_miss_latency::total 953024500 # number of overall MSHR miss cycles 620system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for ReadReq accesses 621system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses 622system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000829 # mshr miss rate for ReadReq accesses | 759system.cpu.l2cache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses 760system.cpu.l2cache.demand_mshr_misses::cpu.data 29586 # number of demand (read+write) MSHR misses 761system.cpu.l2cache.demand_mshr_misses::total 30662 # number of demand (read+write) MSHR misses 762system.cpu.l2cache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses 763system.cpu.l2cache.overall_mshr_misses::cpu.data 29586 # number of overall MSHR misses 764system.cpu.l2cache.overall_mshr_misses::total 30662 # number of overall MSHR misses 765system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31175128 # number of ReadReq MSHR miss cycles 766system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18631896 # number of ReadReq MSHR miss cycles 767system.cpu.l2cache.ReadReq_mshr_miss_latency::total 49807024 # number of ReadReq MSHR miss cycles 768system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5005 # number of UpgradeReq MSHR miss cycles 769system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5005 # number of UpgradeReq MSHR miss cycles 770system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 566101870 # number of ReadExReq MSHR miss cycles 771system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 566101870 # number of ReadExReq MSHR miss cycles 772system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31175128 # number of demand (read+write) MSHR miss cycles 773system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 584733766 # number of demand (read+write) MSHR miss cycles 774system.cpu.l2cache.demand_mshr_miss_latency::total 615908894 # number of demand (read+write) MSHR miss cycles 775system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31175128 # number of overall MSHR miss cycles 776system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 584733766 # number of overall MSHR miss cycles 777system.cpu.l2cache.overall_mshr_miss_latency::total 615908894 # number of overall MSHR miss cycles 778system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992620 # mshr miss rate for ReadReq accesses 779system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses 780system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000837 # mshr miss rate for ReadReq accesses |
| 623system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 624system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 781system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 782system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 625system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352979 # mshr miss rate for ReadExReq accesses 626system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352979 # mshr miss rate for ReadExReq accesses 627system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for demand accesses 628system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses 629system.cpu.l2cache.demand_mshr_miss_rate::total 0.014755 # mshr miss rate for demand accesses 630system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for overall accesses 631system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses 632system.cpu.l2cache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses 633system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32463.014981 # average ReadReq mshr miss latency 634system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32808.020478 # average ReadReq mshr miss latency 635system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32585.247884 # average ReadReq mshr miss latency 636system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 637system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency 638system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.916670 # average ReadExReq mshr miss latency 639system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.916670 # average ReadExReq mshr miss latency 640system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency 641system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency 642system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency 643system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency 644system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency 645system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency | 783system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352893 # mshr miss rate for ReadExReq accesses 784system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352893 # mshr miss rate for ReadExReq accesses 785system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992620 # mshr miss rate for demand accesses 786system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014251 # mshr miss rate for demand accesses 787system.cpu.l2cache.demand_mshr_miss_rate::total 0.014761 # mshr miss rate for demand accesses 788system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992620 # mshr miss rate for overall accesses 789system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014251 # mshr miss rate for overall accesses 790system.cpu.l2cache.overall_mshr_miss_rate::total 0.014761 # mshr miss rate for overall accesses 791system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28973.167286 # average ReadReq mshr miss latency 792system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31419.723440 # average ReadReq mshr miss latency 793system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29842.434991 # average ReadReq mshr miss latency 794system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency 795system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency 796system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 19525.467182 # average ReadExReq mshr miss latency 797system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 19525.467182 # average ReadExReq mshr miss latency 798system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28973.167286 # average overall mshr miss latency 799system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 19763.866897 # average overall mshr miss latency 800system.cpu.l2cache.demand_avg_mshr_miss_latency::total 20087.042398 # average overall mshr miss latency 801system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28973.167286 # average overall mshr miss latency 802system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 19763.866897 # average overall mshr miss latency 803system.cpu.l2cache.overall_avg_mshr_miss_latency::total 20087.042398 # average overall mshr miss latency |
| 646system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 647 648---------- End Simulation Statistics ---------- | 804system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 805 806---------- End Simulation Statistics ---------- |